* [PATCHv7 0/3] Variscite DART-6UL SoM support
@ 2019-11-12 19:22 Oliver Graute
2019-11-12 19:22 ` [PATCHv7 1/3] ARM: dts: imx6ul: Add " Oliver Graute
` (2 more replies)
0 siblings, 3 replies; 16+ messages in thread
From: Oliver Graute @ 2019-11-12 19:22 UTC (permalink / raw)
To: shawnguo
Cc: oliver.graute, m.felsch, narmstrong, Rob Herring, Mark Rutland,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, devicetree, linux-arm-kernel, linux-kernel
This patch series adds support for the Variscite DART-6UL SoM
Product Page: https://www.variscite.com/product/evaluation-kits/dart-6ul-kits
Oliver Graute (3):
ARM: dts: imx6ul: Add Variscite DART-6UL SoM support
ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard
dt-bindings: arm64: fsl: Add Variscite i.MX6UL compatibles
Documentation/devicetree/bindings/arm/fsl.yaml | 1 +
arch/arm/boot/dts/Makefile | 1 +
.../boot/dts/imx6ul-imx6ull-var-dart-common.dtsi | 367 +++++++++++++++++++++
arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts | 221 +++++++++++++
4 files changed, 590 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi
create mode 100644 arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts
--
2.7.4
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCHv7 1/3] ARM: dts: imx6ul: Add Variscite DART-6UL SoM support 2019-11-12 19:22 [PATCHv7 0/3] Variscite DART-6UL SoM support Oliver Graute @ 2019-11-12 19:22 ` Oliver Graute 2019-11-13 7:39 ` Marco Felsch 2019-11-12 19:22 ` [PATCHv7 2/3] ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard Oliver Graute 2019-11-12 19:22 ` [PATCH 3/3] dt-bindings: arm64: fsl: Add Variscite i.MX6UL compatibles Oliver Graute 2 siblings, 1 reply; 16+ messages in thread From: Oliver Graute @ 2019-11-12 19:22 UTC (permalink / raw) To: shawnguo Cc: oliver.graute, m.felsch, narmstrong, Rob Herring, Mark Rutland, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, devicetree, linux-arm-kernel, linux-kernel This patch adds support for the i.MX6UL variant of the Variscite DART-6UL SoM Carrier-Board Signed-off-by: Oliver Graute <oliver.graute@gmail.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Marco Felsch <m.felsch@pengutronix.de> --- Changelog: v7: - removed cpu0 node - fixed phy problem v6: - renamed touch regulator - renamed rmii clock - moved some muxing to baseboard - added pinctrl for gpio key - added bus-width to usdhc1 - fixed missing subnode on partitions .../boot/dts/imx6ul-imx6ull-var-dart-common.dtsi | 376 +++++++++++++++++++++ 1 file changed, 376 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi diff --git a/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi b/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi new file mode 100644 index 00000000..b3cd928 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi @@ -0,0 +1,367 @@ +// SPDX-License-Identifier: (GPL-2.0) +/dts-v1/; + +#include "imx6ul.dtsi" +/ { + chosen { + stdout-path = &uart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + clk_rmii_ref: clock-rmii-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "rmii-ref"; + }; + + reg_touch_3v3: regulator-touch-3v3 { + compatible = "regulator-fixed"; + regulator-name = "touch_3v3_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_sd1_vmmc: regulator-sd1-vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_gpio_dvfs: regulator-gpio { + compatible = "regulator-gpio"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1400000>; + regulator-name = "gpio_dvfs"; + regulator-type = "voltage"; + gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + states = <1300000 0x1 1400000 0x0>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + phy-reset-gpios=<&gpio5 10 1>; + phy-reset-duration=<100>; + phy-reset-on-resume; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + micrel,rmii-reference-clock-select-25-mhz; + clocks = <&clk_rmii_ref>; + clock-names = "rmii-ref"; + reg = <1>; + }; + + ethphy1: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + micrel,rmii-reference-clock-select-25-mhz; + clocks = <&clk_rmii_ref>; + clock-names = "rmii-ref"; + reg = <3>; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; + + nand@0 { + + partition@0 { + label = "spl"; + reg = <0x00000000 0x00200000>; + }; + + partition@200000 { + label = "uboot"; + reg = <0x00200000 0x00200000>; + }; + + partition@400000 { + label = "uboot-env"; + reg = <0x00400000 0x00200000>; + }; + + partition@600000 { + label = "kernel"; + reg = <0x00600000 0x00800000>; + }; + + partition@e00000 { + label = "rootfs"; + reg = <0x00e00000 0x3f200000>; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, + <&clks IMX6UL_CLK_SAI2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&snvs_rtc { + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <4>; + no-1-8-v; + keep-power-in-suspend; + vmmc-supply = <®_sd1_vmmc>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x1b0b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp{ + fsl,pins = < + MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x17059 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x03029 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_lcdif: lcdif { + fsl,pins = < + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x1b0b1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x1b0b1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x1b0b1 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x78b0 + >; + }; +}; -- 2.7.4 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCHv7 1/3] ARM: dts: imx6ul: Add Variscite DART-6UL SoM support 2019-11-12 19:22 ` [PATCHv7 1/3] ARM: dts: imx6ul: Add " Oliver Graute @ 2019-11-13 7:39 ` Marco Felsch 0 siblings, 0 replies; 16+ messages in thread From: Marco Felsch @ 2019-11-13 7:39 UTC (permalink / raw) To: Oliver Graute Cc: shawnguo, narmstrong, Rob Herring, Mark Rutland, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, devicetree, linux-arm-kernel, linux-kernel Hi Oliver, thanks for the patch. I made my comments inline. On 19-11-12 20:22, Oliver Graute wrote: > This patch adds support for the i.MX6UL variant of the Variscite DART-6UL > SoM Carrier-Board > > Signed-off-by: Oliver Graute <oliver.graute@gmail.com> > Cc: Shawn Guo <shawnguo@kernel.org> > Cc: Neil Armstrong <narmstrong@baylibre.com> > Cc: Marco Felsch <m.felsch@pengutronix.de> > --- > Changelog: > > v7: > - removed cpu0 node > - fixed phy problem > > v6: > - renamed touch regulator > - renamed rmii clock > - moved some muxing to baseboard > - added pinctrl for gpio key > - added bus-width to usdhc1 > - fixed missing subnode on partitions > > .../boot/dts/imx6ul-imx6ull-var-dart-common.dtsi | 376 +++++++++++++++++++++ > 1 file changed, 376 insertions(+) > create mode 100644 arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi > > diff --git a/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi b/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi > new file mode 100644 > index 00000000..b3cd928 > --- /dev/null > +++ b/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi > @@ -0,0 +1,367 @@ > +// SPDX-License-Identifier: (GPL-2.0) > +/dts-v1/; > + > +#include "imx6ul.dtsi" > +/ { > + chosen { > + stdout-path = &uart1; > + }; > + > + memory@80000000 { > + device_type = "memory"; > + reg = <0x80000000 0x20000000>; > + }; > + > + clk_rmii_ref: clock-rmii-ref { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <25000000>; > + clock-output-names = "rmii-ref"; > + }; > + > + reg_touch_3v3: regulator-touch-3v3 { > + compatible = "regulator-fixed"; > + regulator-name = "touch_3v3_supply"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + }; Where is this regulator used? > + > + reg_sd1_vmmc: regulator-sd1-vmmc { > + compatible = "regulator-fixed"; > + regulator-name = "VSD_3V3"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + }; > + > + reg_gpio_dvfs: regulator-gpio { > + compatible = "regulator-gpio"; > + regulator-min-microvolt = <1300000>; > + regulator-max-microvolt = <1400000>; > + regulator-name = "gpio_dvfs"; > + regulator-type = "voltage"; > + gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; Please add a dedicated pinctrl for this regultor. > + enable-active-high; > + states = <1300000 0x1 1400000 0x0>; > + }; Can you alphabetical order the regultor-* nodes? > +}; > + > +&fec1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_enet1>; > + phy-mode = "rmii"; > + phy-handle = <ðphy0>; > + phy-reset-gpios=<&gpio5 10 1>; Where happens this mux? > + phy-reset-duration=<100>; > + phy-reset-on-resume; > + > + mdio { > + #address-cells = <1>; > + #size-cells = <0>; > + > + ethphy0: ethernet-phy@1 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + micrel,rmii-reference-clock-select-25-mhz; > + clocks = <&clk_rmii_ref>; > + clock-names = "rmii-ref"; > + reg = <1>; > + }; > + > + ethphy1: ethernet-phy@3 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + micrel,rmii-reference-clock-select-25-mhz; > + clocks = <&clk_rmii_ref>; > + clock-names = "rmii-ref"; > + reg = <3>; > + }; > + }; > +}; > + > +&gpmi { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_gpmi_nand>; > + status = "okay"; > + > + nand@0 { I never saw this notation. Please check the Documentation/devicetree/bindings/mtd/partition.txt. > + partition@0 { > + label = "spl"; > + reg = <0x00000000 0x00200000>; > + }; > + > + partition@200000 { > + label = "uboot"; > + reg = <0x00200000 0x00200000>; > + }; > + > + partition@400000 { > + label = "uboot-env"; > + reg = <0x00400000 0x00200000>; > + }; > + > + partition@600000 { > + label = "kernel"; > + reg = <0x00600000 0x00800000>; > + }; > + > + partition@e00000 { > + label = "rootfs"; > + reg = <0x00e00000 0x3f200000>; > + }; > + }; > +}; > + > +&i2c1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c1>; > +}; Please sort it alphabetical. > + > +&sai2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_sai2>; > + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, > + <&clks IMX6UL_CLK_SAI2>; > + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; > + assigned-clock-rates = <0>, <12288000>; > + fsl,sai-mclk-direction-output; > + status = "okay"; > +}; > + > +&snvs_poweroff { > + status = "okay"; > +}; > + > +&snvs_rtc { > + status = "disabled"; > +}; > + > +&uart2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart2>; > + uart-has-rtscts; > +}; > + > +&usdhc1 { > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > + pinctrl-0 = <&pinctrl_usdhc1>; > + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; > + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; > + bus-width = <4>; > + no-1-8-v; HS200 mode only works with 1.8V or 1.2V. Can you verify the HS200 state? Regards, Marco > + keep-power-in-suspend; > + vmmc-supply = <®_sd1_vmmc>; > + non-removable; > + status = "okay"; > +}; > + > +&wdog1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_wdog>; > + fsl,ext-reset-output; > +}; > + > +&iomuxc { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_hog>; > + > + pinctrl_enet1: enet1grp { > + fsl,pins = < > + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 > + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 > + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 > + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 > + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 > + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 > + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 > + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 > + >; > + }; > + > + pinctrl_enet2: enet2grp { > + fsl,pins = < > + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 > + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 > + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 > + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 > + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 > + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 > + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 > + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 > + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x1b0b0 > + >; > + }; > + > + pinctrl_flexcan1: flexcan1grp{ > + fsl,pins = < > + MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x1b020 > + MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x1b020 > + >; > + }; > + > + pinctrl_flexcan2: flexcan2grp{ > + fsl,pins = < > + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 > + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 > + >; > + }; > + > + pinctrl_gpio_keys: gpio_keysgrp { > + fsl,pins = < > + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x17059 > + >; > + }; > + > + pinctrl_gpio_leds: gpioledsgrp { > + fsl,pins = < > + MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x1b0b0 > + >; > + }; > + > + pinctrl_gpmi_nand: gpminandgrp { > + fsl,pins = < > + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 > + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 > + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 > + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 > + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 > + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 > + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 > + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 > + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 > + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 > + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 > + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 > + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 > + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 > + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 > + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 > + >; > + }; > + > + pinctrl_hog: hoggrp { > + fsl,pins = < > + MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x03029 > + >; > + }; > + > + pinctrl_i2c1: i2c1grp { > + fsl,pins = < > + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 > + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 > + >; > + }; > + > + pinctrl_i2c2: i2c2grp { > + fsl,pins = < > + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 > + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 > + >; > + }; > + > + pinctrl_lcdif: lcdif { > + fsl,pins = < > + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 > + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 > + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 > + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 > + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 > + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 > + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 > + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 > + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 > + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 > + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 > + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 > + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 > + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 > + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 > + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 > + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 > + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 > + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 > + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 > + >; > + }; > + > + pinctrl_pwm1: pwm1grp { > + fsl,pins = < > + MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x110b0 > + >; > + }; > + > + pinctrl_sai2: sai2grp { > + fsl,pins = < > + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 > + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 > + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 > + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 > + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 > + >; > + }; > + > + pinctrl_uart1: uart1grp { > + fsl,pins = < > + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 > + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 > + >; > + }; > + > + pinctrl_uart2: uart2grp { > + fsl,pins = < > + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 > + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 > + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 > + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 > + >; > + }; > + > + pinctrl_uart3: uart3grp { > + fsl,pins = < > + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 > + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 > + MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1 > + MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 > + >; > + }; > + > + pinctrl_usdhc1: usdhc1grp { > + fsl,pins = < > + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 > + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 > + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 > + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 > + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 > + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 > + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x1b0b1 > + >; > + }; > + > + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { > + fsl,pins = < > + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 > + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 > + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 > + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 > + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 > + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 > + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x1b0b1 > + >; > + }; > + > + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { > + fsl,pins = < > + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 > + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 > + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 > + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 > + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 > + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 > + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x1b0b1 > + >; > + }; > + > + pinctrl_wdog: wdoggrp { > + fsl,pins = < > + MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x78b0 > + >; > + }; > +}; > -- > 2.7.4 > > -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCHv7 2/3] ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard 2019-11-12 19:22 [PATCHv7 0/3] Variscite DART-6UL SoM support Oliver Graute 2019-11-12 19:22 ` [PATCHv7 1/3] ARM: dts: imx6ul: Add " Oliver Graute @ 2019-11-12 19:22 ` Oliver Graute 2019-11-12 23:17 ` Fabio Estevam 2019-11-13 7:52 ` Marco Felsch 2019-11-12 19:22 ` [PATCH 3/3] dt-bindings: arm64: fsl: Add Variscite i.MX6UL compatibles Oliver Graute 2 siblings, 2 replies; 16+ messages in thread From: Oliver Graute @ 2019-11-12 19:22 UTC (permalink / raw) To: shawnguo Cc: oliver.graute, m.felsch, narmstrong, Rob Herring, Mark Rutland, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, devicetree, linux-kernel, linux-arm-kernel This patch adds DeviceTree Source for the i.MX6 UltraLite DART NAND/WIFI Signed-off-by: Oliver Graute <oliver.graute@gmail.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Marco Felsch <m.felsch@pengutronix.de> --- Changelog: v7 - fixed wakeup-source v6: - added some muxing - added codec in sound node - added adc1 node arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts | 221 ++++++++++++++++++++++++ 2 files changed, 222 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index df2e1f2..65fac53 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -583,6 +583,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-tx6ul-0010.dtb \ imx6ul-tx6ul-0011.dtb \ imx6ul-tx6ul-mainboard.dtb \ + imx6ul-var-6ulcustomboard.dtb \ imx6ull-14x14-evk.dtb \ imx6ull-colibri-eval-v3.dtb \ imx6ull-colibri-wifi-eval-v3.dtb \ diff --git a/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts b/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts new file mode 100644 index 00000000..5b88aad --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts @@ -0,0 +1,221 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * Support for Variscite DART-6UL Module + * + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright (C) 2015-2016 Variscite Ltd. - http://www.variscite.com + * Copyright (C) 2018-2019 Oliver Graute <oliver.graute@gmail.com> + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include "imx6ul-imx6ull-var-dart-common.dtsi" + +/ { + model = "Variscite i.MX6 UltraLite Carrier-board"; + compatible = "variscite,6ulcustomboard", "fsl,imx6ul"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 20000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + user { + gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + linux,code = <KEY_BACK>; + wakeup-source; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + d16-led { + gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "wm8731audio"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line Jack", + "Microphone", "Mic Jack"; + simple-audio-card,routing = + "Headphone Jack", "RHPOUT", + "Headphone Jack", "LHPOUT", + "LLINEIN", "Line Jack", + "RLINEIN", "Line Jack", + "MICIN", "Mic Bias", + "Mic Bias", "Mic Jack"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,frame-master = <&codec_dai>; + + cpu_dai: simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8731>; + system-clock-frequency = <12288000>; + }; + }; +}; + +&adc1 { + vref-supply = <®_touch_3v3>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + wm8731: audio-codec@1a { + compatible = "wlf,wm8731"; + reg = <0x1a>; + #sound-dai-cells = <0>; + clocks = <&clks IMX6UL_CLK_SAI2>; + clock-names = "mclk"; + }; + + touchscreen@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + interrupt-parent = <&gpio3>; + interrupts = <4 IRQ_TYPE_NONE>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + wakeup-source; + }; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-parent = <&gpio5>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency =<35000000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <40>; + hback-porch = <40>; + hsync-len = <48>; + vback-porch = <29>; + vfront-porch = <13>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +&usbotg2 { + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +&iomuxc { + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 + >; + }; +}; -- 2.7.4 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCHv7 2/3] ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard 2019-11-12 19:22 ` [PATCHv7 2/3] ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard Oliver Graute @ 2019-11-12 23:17 ` Fabio Estevam 2019-11-13 7:41 ` Marco Felsch 2020-07-08 10:38 ` Oliver Graute 2019-11-13 7:52 ` Marco Felsch 1 sibling, 2 replies; 16+ messages in thread From: Fabio Estevam @ 2019-11-12 23:17 UTC (permalink / raw) To: Oliver Graute Cc: Shawn Guo, Marco Felsch, Neil Armstrong, Rob Herring, Mark Rutland, Sascha Hauer, Pengutronix Kernel Team, NXP Linux Team, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-kernel, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE Hi Oliver, On Tue, Nov 12, 2019 at 4:22 PM Oliver Graute <oliver.graute@gmail.com> wrote: > +&lcdif { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_lcdif>; > + display = <&display0>; > + status = "okay"; > + > + display0: display0 { > + bits-per-pixel = <16>; > + bus-width = <24>; > + > + display-timings { > + native-mode = <&timing0>; > + timing0: timing0 { > + clock-frequency =<35000000>; > + hactive = <800>; > + vactive = <480>; > + hfront-porch = <40>; > + hback-porch = <40>; > + hsync-len = <48>; > + vback-porch = <29>; > + vfront-porch = <13>; > + vsync-len = <3>; > + hsync-active = <0>; > + vsync-active = <0>; > + de-active = <1>; > + pixelclk-active = <0>; > + }; > + }; > + }; > +}; You are using the deprecated bindings. Please switch to the DRM bindings as stated at Documentation/devicetree/bindings/display/mxsfb.txt You should also add your panel to the simple panel driver. ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCHv7 2/3] ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard 2019-11-12 23:17 ` Fabio Estevam @ 2019-11-13 7:41 ` Marco Felsch 2020-07-08 10:38 ` Oliver Graute 1 sibling, 0 replies; 16+ messages in thread From: Marco Felsch @ 2019-11-13 7:41 UTC (permalink / raw) To: Fabio Estevam Cc: Oliver Graute, Shawn Guo, Neil Armstrong, Rob Herring, Mark Rutland, Sascha Hauer, Pengutronix Kernel Team, NXP Linux Team, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-kernel, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE On 19-11-12 20:17, Fabio Estevam wrote: > Hi Oliver, > > On Tue, Nov 12, 2019 at 4:22 PM Oliver Graute <oliver.graute@gmail.com> wrote: > > > +&lcdif { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_lcdif>; > > + display = <&display0>; > > + status = "okay"; > > + > > + display0: display0 { > > + bits-per-pixel = <16>; > > + bus-width = <24>; > > + > > + display-timings { > > + native-mode = <&timing0>; > > + timing0: timing0 { > > + clock-frequency =<35000000>; > > + hactive = <800>; > > + vactive = <480>; > > + hfront-porch = <40>; > > + hback-porch = <40>; > > + hsync-len = <48>; > > + vback-porch = <29>; > > + vfront-porch = <13>; > > + vsync-len = <3>; > > + hsync-active = <0>; > > + vsync-active = <0>; > > + de-active = <1>; > > + pixelclk-active = <0>; > > + }; > > + }; > > + }; > > +}; > > You are using the deprecated bindings. > > Please switch to the DRM bindings as stated at > Documentation/devicetree/bindings/display/mxsfb.txt > > You should also add your panel to the simple panel driver. That would be the best solution :) Regards, Marco ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCHv7 2/3] ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard 2019-11-12 23:17 ` Fabio Estevam 2019-11-13 7:41 ` Marco Felsch @ 2020-07-08 10:38 ` Oliver Graute 2020-07-08 13:31 ` Fabio Estevam 1 sibling, 1 reply; 16+ messages in thread From: Oliver Graute @ 2020-07-08 10:38 UTC (permalink / raw) To: Fabio Estevam Cc: Shawn Guo, Marco Felsch, Neil Armstrong, Rob Herring, Mark Rutland, Sascha Hauer, Pengutronix Kernel Team, NXP Linux Team, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-kernel, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE On 12/11/19, Fabio Estevam wrote: > Hi Oliver, > > On Tue, Nov 12, 2019 at 4:22 PM Oliver Graute <oliver.graute@gmail.com> wrote: > > > +&lcdif { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_lcdif>; > > + display = <&display0>; > > + status = "okay"; > > + > > + display0: display0 { > > + bits-per-pixel = <16>; > > + bus-width = <24>; > > + > > + display-timings { > > + native-mode = <&timing0>; > > + timing0: timing0 { > > + clock-frequency =<35000000>; > > + hactive = <800>; > > + vactive = <480>; > > + hfront-porch = <40>; > > + hback-porch = <40>; > > + hsync-len = <48>; > > + vback-porch = <29>; > > + vfront-porch = <13>; > > + vsync-len = <3>; > > + hsync-active = <0>; > > + vsync-active = <0>; > > + de-active = <1>; > > + pixelclk-active = <0>; > > + }; > > + }; > > + }; > > +}; > > You are using the deprecated bindings. > > Please switch to the DRM bindings as stated at > Documentation/devicetree/bindings/display/mxsfb.txt > > You should also add your panel to the simple panel driver. ok thx for you comments, coming back to this. I now added this to panel-simple.c. Is this the way to go? Best Regards, Oliver diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index c1374be..c2f20ac 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -3139,6 +3139,29 @@ static const struct panel_desc satoz_sat050at40h12r2 = { .connector_type = DRM_MODE_CONNECTOR_LVDS, }; +static const struct display_timing sgd_gktw70sdad1sd_timing = { + .pixelclock = {35000000, 35000000, 35000000}, + .hactive = { 800, 800, 800}, + .hfront_porch = {39, 39, 39}, + .hback_porch = {39, 39, 39}, + .hsync_len = {48, 48, 48}, + .vactive = {480, 480, 480}, + .vfront_porch = {13, 13, 13}, + .vback_porch = {29, 29, 29}, + .vsync_len = {3, 3, 3}, +}; + +static const struct panel_desc sgd_gktw70sdad1sd = { + .timings = &sgd_gktw70sdad1sd_timing, + .num_timings = 1, + .bpc = 8, + .size = { + .width = 153, + .height = 86, + }, + .connector_type = DRM_MODE_CONNECTOR_DPI, +}; + static const struct drm_display_mode sharp_ld_d5116z01b_mode = { .clock = 168480, .hdisplay = 1920, @@ -3999,6 +4022,9 @@ static const struct of_device_id platform_of_match[] = { .compatible = "satoz,sat050at40h12r2", .data = &satoz_sat050at40h12r2, }, { + .compatible = "sgd,gktw70sdad1sd", + .data = &sgd_gktw70sdad1sd, + }, { .compatible = "sharp,ld-d5116z01b", ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCHv7 2/3] ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard 2020-07-08 10:38 ` Oliver Graute @ 2020-07-08 13:31 ` Fabio Estevam 0 siblings, 0 replies; 16+ messages in thread From: Fabio Estevam @ 2020-07-08 13:31 UTC (permalink / raw) To: Oliver Graute Cc: Shawn Guo, Marco Felsch, Neil Armstrong, Rob Herring, Mark Rutland, Sascha Hauer, Pengutronix Kernel Team, NXP Linux Team, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-kernel, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE Hi Oliver, On Wed, Jul 8, 2020 at 10:12 AM Oliver Graute <oliver.graute@gmail.com> wrote: > ok thx for you comments, coming back to this. I now added this to > panel-simple.c. Is this the way to go? Yes, please submit it as a formal patch to the drm folks. ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCHv7 2/3] ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard 2019-11-12 19:22 ` [PATCHv7 2/3] ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard Oliver Graute 2019-11-12 23:17 ` Fabio Estevam @ 2019-11-13 7:52 ` Marco Felsch 1 sibling, 0 replies; 16+ messages in thread From: Marco Felsch @ 2019-11-13 7:52 UTC (permalink / raw) To: Oliver Graute Cc: shawnguo, narmstrong, Rob Herring, Mark Rutland, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, devicetree, linux-kernel, linux-arm-kernel Hi Oliver, I made my comments inline. On 19-11-12 20:22, Oliver Graute wrote: > This patch adds DeviceTree Source for the i.MX6 UltraLite DART NAND/WIFI > > Signed-off-by: Oliver Graute <oliver.graute@gmail.com> > Cc: Shawn Guo <shawnguo@kernel.org> > Cc: Neil Armstrong <narmstrong@baylibre.com> > Cc: Marco Felsch <m.felsch@pengutronix.de> > --- > Changelog: > > v7 > - fixed wakeup-source > > v6: > - added some muxing > - added codec in sound node > - added adc1 node > > arch/arm/boot/dts/Makefile | 1 + > arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts | 221 ++++++++++++++++++++++++ > 2 files changed, 222 insertions(+) > create mode 100644 arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index df2e1f2..65fac53 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -583,6 +583,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ > imx6ul-tx6ul-0010.dtb \ > imx6ul-tx6ul-0011.dtb \ > imx6ul-tx6ul-mainboard.dtb \ > + imx6ul-var-6ulcustomboard.dtb \ > imx6ull-14x14-evk.dtb \ > imx6ull-colibri-eval-v3.dtb \ > imx6ull-colibri-wifi-eval-v3.dtb \ > diff --git a/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts b/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts > new file mode 100644 > index 00000000..5b88aad > --- /dev/null > +++ b/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts > @@ -0,0 +1,221 @@ > +// SPDX-License-Identifier: (GPL-2.0) > +/* > + * Support for Variscite DART-6UL Module > + * > + * Copyright (C) 2015 Freescale Semiconductor, Inc. > + * Copyright (C) 2015-2016 Variscite Ltd. - http://www.variscite.com > + * Copyright (C) 2018-2019 Oliver Graute <oliver.graute@gmail.com> > + */ > + > +/dts-v1/; > + > +#include <dt-bindings/input/input.h> > +#include "imx6ul-imx6ull-var-dart-common.dtsi" > + > +/ { > + model = "Variscite i.MX6 UltraLite Carrier-board"; > + compatible = "variscite,6ulcustomboard", "fsl,imx6ul"; > + > + backlight { > + compatible = "pwm-backlight"; > + pwms = <&pwm1 0 20000>; > + brightness-levels = <0 4 8 16 32 64 128 255>; > + default-brightness-level = <6>; > + status = "okay"; The status line can be dropped. > + }; > + > + gpio-keys { > + compatible = "gpio-keys"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_gpio_keys>; Where is the phandle? > + > + user { > + gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; > + linux,code = <KEY_BACK>; > + wakeup-source; > + }; > + }; > + > + gpio-leds { > + compatible = "gpio-leds"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_gpio_leds>; Also this phandle.. I saw this a few times within this dts. Please make sure that your dts(i) files are self-contained so move the muxing to this dts. This happens a few time, I don't list all phandles. > + > + d16-led { > + gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; > + linux,default-trigger = "heartbeat"; > + }; > + }; > + > + sound { > + compatible = "simple-audio-card"; > + simple-audio-card,name = "wm8731audio"; > + simple-audio-card,widgets = > + "Headphone", "Headphone Jack", > + "Line", "Line Jack", > + "Microphone", "Mic Jack"; > + simple-audio-card,routing = > + "Headphone Jack", "RHPOUT", > + "Headphone Jack", "LHPOUT", > + "LLINEIN", "Line Jack", > + "RLINEIN", "Line Jack", > + "MICIN", "Mic Bias", > + "Mic Bias", "Mic Jack"; > + simple-audio-card,format = "i2s"; > + simple-audio-card,bitclock-master = <&codec_dai>; > + simple-audio-card,frame-master = <&codec_dai>; > + > + cpu_dai: simple-audio-card,cpu { Do you need the cpu_dai phandle? > + sound-dai = <&sai2>; > + }; > + > + codec_dai: simple-audio-card,codec { > + sound-dai = <&wm8731>; > + system-clock-frequency = <12288000>; > + }; > + }; > +}; > + > +&adc1 { > + vref-supply = <®_touch_3v3>; This is the only place where you use this regulator so can we move the regulator to this dts instead of the common dtsi? > + status = "okay"; > +}; > + > +&can1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_flexcan1>; > + status = "okay"; > +}; > + > +&can2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_flexcan2>; > + status = "okay"; > +}; > + > +&fec1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_enet1>; > + status = "okay"; > +}; > + > +&fec2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_enet2>; > + status = "okay"; > +}; > + > +&i2c1 { > + clock-frequency = <400000>; Can this go to the common dtsi file? > + status = "okay"; > +}; > + > +&i2c2 { > + clock_frequency = <100000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c2>; > + status = "okay"; > + > + wm8731: audio-codec@1a { > + compatible = "wlf,wm8731"; > + reg = <0x1a>; > + #sound-dai-cells = <0>; > + clocks = <&clks IMX6UL_CLK_SAI2>; > + clock-names = "mclk"; > + }; > + > + touchscreen@38 { > + compatible = "edt,edt-ft5x06"; > + reg = <0x38>; > + interrupt-parent = <&gpio3>; > + interrupts = <4 IRQ_TYPE_NONE>; > + touchscreen-size-x = <800>; > + touchscreen-size-y = <480>; > + touchscreen-inverted-x; > + touchscreen-inverted-y; > + wakeup-source; > + }; > + > + rtc@68 { > + compatible = "dallas,ds1337"; > + reg = <0x68>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_rtc>; > + interrupt-parent = <&gpio5>; > + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; > + }; > +}; > + > +&lcdif { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_lcdif>; > + display = <&display0>; > + status = "okay"; > + > + display0: display0 { > + bits-per-pixel = <16>; > + bus-width = <24>; > + > + display-timings { > + native-mode = <&timing0>; > + timing0: timing0 { > + clock-frequency =<35000000>; > + hactive = <800>; > + vactive = <480>; > + hfront-porch = <40>; > + hback-porch = <40>; > + hsync-len = <48>; > + vback-porch = <29>; > + vfront-porch = <13>; > + vsync-len = <3>; > + hsync-active = <0>; > + vsync-active = <0>; > + de-active = <1>; > + pixelclk-active = <0>; > + }; > + }; > + }; > +}; > + > +&pwm1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pwm1>; Where goes this phandle? > + status = "okay"; > +}; > + > +&uart1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart1>; > + status = "okay"; > +}; > + > +&uart2 { > + status = "okay"; > +}; > + > +&uart3 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart3>; > + uart-has-rtscts; > + status = "okay"; > +}; > + > +&usbotg1 { > + disable-over-current; > + dr_mode = "host"; > + status = "okay"; > +}; > + > +&usbotg2 { > + disable-over-current; > + dr_mode = "host"; > + status = "okay"; > +}; > + > +&iomuxc { > + pinctrl_rtc: rtcgrp { > + fsl,pins = < > + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 > + >; > + }; > +}; > -- > 2.7.4 > > -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 3/3] dt-bindings: arm64: fsl: Add Variscite i.MX6UL compatibles 2019-11-12 19:22 [PATCHv7 0/3] Variscite DART-6UL SoM support Oliver Graute 2019-11-12 19:22 ` [PATCHv7 1/3] ARM: dts: imx6ul: Add " Oliver Graute 2019-11-12 19:22 ` [PATCHv7 2/3] ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard Oliver Graute @ 2019-11-12 19:22 ` Oliver Graute 2019-11-12 20:29 ` Fabio Estevam 2019-11-12 21:24 ` [PATCH v2 3/3] dt-bindings: arm: " Oliver Graute 2 siblings, 2 replies; 16+ messages in thread From: Oliver Graute @ 2019-11-12 19:22 UTC (permalink / raw) To: shawnguo Cc: oliver.graute, m.felsch, narmstrong, Rob Herring, Mark Rutland, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Andrey Smirnov, Manivannan Sadhasivam, Anson Huang, Marcel Ziswiler, Sébastien Szymanski, devicetree, linux-kernel, linux-arm-kernel Add the compatibles for Variscite i.MX6UL compatibles --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index f79683a..d0c7e60 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -182,6 +182,7 @@ properties: - fsl,imx6ul-14x14-evk # i.MX6 UltraLite 14x14 EVK Board - kontron,imx6ul-n6310-som # Kontron N6310 SOM - kontron,imx6ul-n6311-som # Kontron N6311 SOM + - variscite,6ulcustomboard" # i.MX UltraLite Carrier-board - const: fsl,imx6ul - description: Kontron N6310 S Board -- 2.7.4 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 3/3] dt-bindings: arm64: fsl: Add Variscite i.MX6UL compatibles 2019-11-12 19:22 ` [PATCH 3/3] dt-bindings: arm64: fsl: Add Variscite i.MX6UL compatibles Oliver Graute @ 2019-11-12 20:29 ` Fabio Estevam 2019-11-12 21:11 ` Oliver Graute 2019-11-12 21:24 ` [PATCH v2 3/3] dt-bindings: arm: " Oliver Graute 1 sibling, 1 reply; 16+ messages in thread From: Fabio Estevam @ 2019-11-12 20:29 UTC (permalink / raw) To: Oliver Graute Cc: Shawn Guo, Marco Felsch, Neil Armstrong, Rob Herring, Mark Rutland, Sascha Hauer, Pengutronix Kernel Team, NXP Linux Team, Andrey Smirnov, Manivannan Sadhasivam, Anson Huang, Marcel Ziswiler, Sébastien Szymanski, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-kernel, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE Hi Oliver On Tue, Nov 12, 2019 at 4:22 PM Oliver Graute <oliver.graute@gmail.com> wrote: > > Add the compatibles for Variscite i.MX6UL compatibles You missed your Signed-off-by tag. Also, you should remove arm64 from the Subject line as this is a 32-bit SoC :-) ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 3/3] dt-bindings: arm64: fsl: Add Variscite i.MX6UL compatibles 2019-11-12 20:29 ` Fabio Estevam @ 2019-11-12 21:11 ` Oliver Graute 0 siblings, 0 replies; 16+ messages in thread From: Oliver Graute @ 2019-11-12 21:11 UTC (permalink / raw) To: Fabio Estevam Cc: Shawn Guo, Marco Felsch, Neil Armstrong, Rob Herring, Mark Rutland, Sascha Hauer, Pengutronix Kernel Team, NXP Linux Team, Andrey Smirnov, Manivannan Sadhasivam, Anson Huang, Marcel Ziswiler, Sébastien Szymanski, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-kernel, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE On 12/11/19, Fabio Estevam wrote: > Hi Oliver > > On Tue, Nov 12, 2019 at 4:22 PM Oliver Graute <oliver.graute@gmail.com> wrote: > > > > Add the compatibles for Variscite i.MX6UL compatibles > > You missed your Signed-off-by tag. > > Also, you should remove arm64 from the Subject line as this is a 32-bit SoC :-) thx, you are right I messed thinks up. Because I also working with another 64-bit SoC in parallel. I'll fix it soon Best regards, Oliver ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 3/3] dt-bindings: arm: fsl: Add Variscite i.MX6UL compatibles 2019-11-12 19:22 ` [PATCH 3/3] dt-bindings: arm64: fsl: Add Variscite i.MX6UL compatibles Oliver Graute 2019-11-12 20:29 ` Fabio Estevam @ 2019-11-12 21:24 ` Oliver Graute 2019-11-12 23:19 ` Fabio Estevam 1 sibling, 1 reply; 16+ messages in thread From: Oliver Graute @ 2019-11-12 21:24 UTC (permalink / raw) To: shawnguo Cc: oliver.graute, m.felsch, narmstrong, Rob Herring, Mark Rutland, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Manivannan Sadhasivam, Andrey Smirnov, Aisheng Dong, Marcel Ziswiler, Anson Huang, Sébastien Szymanski, devicetree, linux-kernel, linux-arm-kernel Add the compatibles for Variscite i.MX6UL compatibles Signed-off-by: Oliver Graute <oliver.graute@gmail.com> --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index f79683a..d0c7e60 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -182,6 +182,7 @@ properties: - fsl,imx6ul-14x14-evk # i.MX6 UltraLite 14x14 EVK Board - kontron,imx6ul-n6310-som # Kontron N6310 SOM - kontron,imx6ul-n6311-som # Kontron N6311 SOM + - variscite,6ulcustomboard" # i.MX UltraLite Carrier-board - const: fsl,imx6ul - description: Kontron N6310 S Board -- 2.7.4 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v2 3/3] dt-bindings: arm: fsl: Add Variscite i.MX6UL compatibles 2019-11-12 21:24 ` [PATCH v2 3/3] dt-bindings: arm: " Oliver Graute @ 2019-11-12 23:19 ` Fabio Estevam 2019-11-18 21:29 ` Rob Herring 0 siblings, 1 reply; 16+ messages in thread From: Fabio Estevam @ 2019-11-12 23:19 UTC (permalink / raw) To: Oliver Graute Cc: Shawn Guo, Marco Felsch, Neil Armstrong, Rob Herring, Mark Rutland, Sascha Hauer, Pengutronix Kernel Team, NXP Linux Team, Manivannan Sadhasivam, Andrey Smirnov, Aisheng Dong, Marcel Ziswiler, Anson Huang, Sébastien Szymanski, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-kernel, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE On Tue, Nov 12, 2019 at 6:25 PM Oliver Graute <oliver.graute@gmail.com> wrote: > > Add the compatibles for Variscite i.MX6UL compatibles > > Signed-off-by: Oliver Graute <oliver.graute@gmail.com> > --- > Documentation/devicetree/bindings/arm/fsl.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml > index f79683a..d0c7e60 100644 > --- a/Documentation/devicetree/bindings/arm/fsl.yaml > +++ b/Documentation/devicetree/bindings/arm/fsl.yaml > @@ -182,6 +182,7 @@ properties: > - fsl,imx6ul-14x14-evk # i.MX6 UltraLite 14x14 EVK Board > - kontron,imx6ul-n6310-som # Kontron N6310 SOM > - kontron,imx6ul-n6311-som # Kontron N6311 SOM > + - variscite,6ulcustomboard" # i.MX UltraLite Carrier-board I guess what you mean is: variscite,imx6ul-var-6ulcustomboard # i.MX6 UltraLite Carrier-board ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 3/3] dt-bindings: arm: fsl: Add Variscite i.MX6UL compatibles 2019-11-12 23:19 ` Fabio Estevam @ 2019-11-18 21:29 ` Rob Herring 2019-11-19 2:37 ` Fabio Estevam 0 siblings, 1 reply; 16+ messages in thread From: Rob Herring @ 2019-11-18 21:29 UTC (permalink / raw) To: Fabio Estevam Cc: Oliver Graute, Shawn Guo, Marco Felsch, Neil Armstrong, Mark Rutland, Sascha Hauer, Pengutronix Kernel Team, NXP Linux Team, Manivannan Sadhasivam, Andrey Smirnov, Aisheng Dong, Marcel Ziswiler, Anson Huang, Sébastien Szymanski, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-kernel, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE On Tue, Nov 12, 2019 at 08:19:44PM -0300, Fabio Estevam wrote: > On Tue, Nov 12, 2019 at 6:25 PM Oliver Graute <oliver.graute@gmail.com> wrote: > > > > Add the compatibles for Variscite i.MX6UL compatibles > > > > Signed-off-by: Oliver Graute <oliver.graute@gmail.com> > > --- > > Documentation/devicetree/bindings/arm/fsl.yaml | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml > > index f79683a..d0c7e60 100644 > > --- a/Documentation/devicetree/bindings/arm/fsl.yaml > > +++ b/Documentation/devicetree/bindings/arm/fsl.yaml > > @@ -182,6 +182,7 @@ properties: > > - fsl,imx6ul-14x14-evk # i.MX6 UltraLite 14x14 EVK Board > > - kontron,imx6ul-n6310-som # Kontron N6310 SOM > > - kontron,imx6ul-n6311-som # Kontron N6311 SOM > > + - variscite,6ulcustomboard" # i.MX UltraLite Carrier-board > > I guess what you mean is: > > variscite,imx6ul-var-6ulcustomboard # i.MX6 UltraLite Carrier-board It matched the .dts file. However the '"' in there is an error. Make sure 'make dt_binding_check' passes. Rob ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 3/3] dt-bindings: arm: fsl: Add Variscite i.MX6UL compatibles 2019-11-18 21:29 ` Rob Herring @ 2019-11-19 2:37 ` Fabio Estevam 0 siblings, 0 replies; 16+ messages in thread From: Fabio Estevam @ 2019-11-19 2:37 UTC (permalink / raw) To: Rob Herring Cc: Oliver Graute, Shawn Guo, Marco Felsch, Neil Armstrong, Mark Rutland, Sascha Hauer, Pengutronix Kernel Team, NXP Linux Team, Manivannan Sadhasivam, Andrey Smirnov, Aisheng Dong, Marcel Ziswiler, Anson Huang, Sébastien Szymanski, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-kernel, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE On Mon, Nov 18, 2019 at 6:29 PM Rob Herring <robh@kernel.org> wrote: > > I guess what you mean is: > > > > variscite,imx6ul-var-6ulcustomboard # i.MX6 UltraLite Carrier-board > > It matched the .dts file. However the '"' in there is an error. Make > sure 'make dt_binding_check' passes. The dts is called imx6ul-var-6ulcustomboard.dts, so it is not matching the dts name. ^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2020-07-08 13:32 UTC | newest] Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-11-12 19:22 [PATCHv7 0/3] Variscite DART-6UL SoM support Oliver Graute 2019-11-12 19:22 ` [PATCHv7 1/3] ARM: dts: imx6ul: Add " Oliver Graute 2019-11-13 7:39 ` Marco Felsch 2019-11-12 19:22 ` [PATCHv7 2/3] ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard Oliver Graute 2019-11-12 23:17 ` Fabio Estevam 2019-11-13 7:41 ` Marco Felsch 2020-07-08 10:38 ` Oliver Graute 2020-07-08 13:31 ` Fabio Estevam 2019-11-13 7:52 ` Marco Felsch 2019-11-12 19:22 ` [PATCH 3/3] dt-bindings: arm64: fsl: Add Variscite i.MX6UL compatibles Oliver Graute 2019-11-12 20:29 ` Fabio Estevam 2019-11-12 21:11 ` Oliver Graute 2019-11-12 21:24 ` [PATCH v2 3/3] dt-bindings: arm: " Oliver Graute 2019-11-12 23:19 ` Fabio Estevam 2019-11-18 21:29 ` Rob Herring 2019-11-19 2:37 ` Fabio Estevam
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