From: Billy Tsai <billy_tsai@aspeedtech.com>
To: "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>
Cc: "lee.jones@linaro.org" <lee.jones@linaro.org>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"joel@jms.id.au" <joel@jms.id.au>,
"andrew@aj.id.au" <andrew@aj.id.au>,
"thierry.reding@gmail.com" <thierry.reding@gmail.com>,
"p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-aspeed@lists.ozlabs.org" <linux-aspeed@lists.ozlabs.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-pwm@vger.kernel.org" <linux-pwm@vger.kernel.org>,
BMC-SW <BMC-SW@aspeedtech.com>
Subject: Re: [v9 2/2] pwm: Add Aspeed ast2600 PWM support
Date: Fri, 16 Jul 2021 09:22:22 +0000 [thread overview]
Message-ID: <DD5590B4-11BC-411B-95BF-03AC26C078E4@aspeedtech.com> (raw)
In-Reply-To: <20210716070943.ayxkz2irkwhgincz@pengutronix.de>
Hello Uwe,
On 2021/7/16, 3:10 PM, "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de> wrote:
Hello Billy,
On Fri, Jul 16, 2021 at 01:48:20AM +0000, Billy Tsai wrote:
>> On 2021/7/15, 11:06 PM, "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>> wrote:
>> > Another is: The PWM doesn't support duty_cycle 0, on such a request the
>> > PWM is disabled which results in a constant inactive level.
>>
>> > (This is correct, is it? Or does it yield a constant 0 level?)
>>
>> Our pwm can support duty_cycle 0 by unset CLK_ENABLE.
> This has a slightly different semantic though. Some consumer might
> expect that the following sequence:
> pwm_apply(mypwm, { .period = 10000, .duty_cycle = 10000, .enabled = true })
> pwm_apply(mypwm, { .period = 10000, .duty_cycle = 0, .enabled = true })
> pwm_apply(mypwm, { .period = 10000, .duty_cycle = 10000, .enabled = true })
> results in the output being low for an integer multiple of 10 µs. This
> isn't given with setting CLK_ENABLE to zero, is it? (I didn't recheck,
> if the PWM doesn't complete periods on reconfiguration this doesn't
> matter much though.)
Thanks for the explanation.
Our hardware actually can only support duty from 1/256 to 256/256.
For this situation I can do possible solution:
We can though change polarity to meet this requirement. Inverse the pin and use
duty_cycle 100.
But I think this is not a good solution for this problem right?
next prev parent reply other threads:[~2021-07-16 9:22 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-09 6:52 [v9 0/2] Support pwm driver for aspeed ast26xx Billy Tsai
2021-07-09 6:52 ` [v9 1/2] dt-bindings: Add bindings for aspeed pwm-tach Billy Tsai
2021-07-13 22:14 ` Rob Herring
2021-07-14 4:02 ` Billy Tsai
2021-10-04 1:46 ` Billy Tsai
2021-07-09 6:52 ` [v9 2/2] pwm: Add Aspeed ast2600 PWM support Billy Tsai
2021-07-15 15:05 ` Uwe Kleine-König
2021-07-16 1:48 ` Billy Tsai
2021-07-16 7:09 ` Uwe Kleine-König
2021-07-16 9:22 ` Billy Tsai [this message]
2021-07-16 10:13 ` Uwe Kleine-König
2021-07-16 10:56 ` Billy Tsai
2021-07-21 10:52 ` Billy Tsai
2021-07-21 12:48 ` Uwe Kleine-König
2021-07-23 4:23 ` Billy Tsai
2021-07-23 20:12 ` Uwe Kleine-König
2021-07-26 5:14 ` Billy Tsai
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