[PATCH v2 0/5] add NXP imx8mp usb support

[PATCH v2 0/5] add NXP imx8mp usb support

[Li Jun]

NXP imx8MPlus integrates 2 indentical dwc3 3.30b IP with additional wakeup
logic to support low power, this wakeup logic has a separated interrupt
which can generate events with suspend clock(32K); due to SoC integration
limitation, a few quriks required, instead of create new properties flags,
introduce platform data and pass it from glue layer to dwc3 core, those xhci
private data can further pass to xhci-plat.

Changes for v2:
- Drop the 2 patches for new property("snps,xhci-dis-64bit-support-quirk")
  introduction, as suggested, imply by SoC compatible string, this is done
  by introduce dwc3 core platform data and pass the xhci_plat_priv to
  xhci-plat for those xhci quirks, so a new patch added:
  [1/5] usb: dwc3: add platform data to dwc3 core device to pass data.
  this patch is based on Peter's one patch which is also in review:
  https://patchwork.kernel.org/patch/11640945/
- dts change, use the USB power function of TRL logic instead of a always-on
  regulator to control vbus on/off.
- Some changes to address Peter's command on patch [2/5].

Li Jun (5):
  usb: dwc3: add platform data to dwc3 core device to pass data
  usb: dwc3: add imx8mp dwc3 glue layer driver
  arm64: dtsi: imx8mp: add usb nodes
  arm64: dts: imx8mp-evk: enable usb1 as host mode
  dt-bindings: usb: dwc3-imx8mp: add imx8mp dwc3 glue bindings

 .../devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml   |  87 +++++
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts       |  21 ++
 arch/arm64/boot/dts/freescale/imx8mp.dtsi          |  77 +++++
 drivers/usb/dwc3/Kconfig                           |  10 +
 drivers/usb/dwc3/Makefile                          |   1 +
 drivers/usb/dwc3/core.h                            |   5 +
 drivers/usb/dwc3/dwc3-imx8mp.c                     | 374 +++++++++++++++++++++
 drivers/usb/dwc3/host.c                            |   9 +
 8 files changed, 584 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml
 create mode 100644 drivers/usb/dwc3/dwc3-imx8mp.c

-- 
2.7.4

[PATCH v2 1/5] usb: dwc3: add platform data to dwc3 core device to pass data

[Li Jun]

In case dwc3 has SoC specific customizations, dwc3 glue driver can base on
compatible string and pass it via platform data to dwc3 core driver; and
pass xhci private data further to xhci-plat like quirks.

Signed-off-by: Li Jun <jun.li@nxp.com>
---
 drivers/usb/dwc3/core.h | 5 +++++
 drivers/usb/dwc3/host.c | 9 +++++++++
 2 files changed, 14 insertions(+)

diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 0b8ea8c..3146697 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -29,6 +29,7 @@
 #include <linux/ulpi/interface.h>
 
 #include <linux/phy/phy.h>
+#include "../host/xhci-plat.h"
 
 #define DWC3_MSG_MAX	500
 
@@ -924,6 +925,10 @@ struct dwc3_scratchpad_array {
 	__le64	dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
 };
 
+struct dwc3_platform_data {
+	struct xhci_plat_priv *xhci_priv;
+};
+
 /**
  * struct dwc3 - representation of our controller
  * @drd_work: workqueue used for role swapping
diff --git a/drivers/usb/dwc3/host.c b/drivers/usb/dwc3/host.c
index bef1c1a..4f8514a 100644
--- a/drivers/usb/dwc3/host.c
+++ b/drivers/usb/dwc3/host.c
@@ -46,6 +46,7 @@ int dwc3_host_init(struct dwc3 *dwc)
 {
 	struct property_entry	props[4];
 	struct platform_device	*xhci;
+	struct dwc3_platform_data *dwc3_pdata;
 	int			ret, irq;
 	struct resource		*res;
 	struct platform_device	*dwc3_pdev = to_platform_device(dwc->dev);
@@ -115,6 +116,14 @@ int dwc3_host_init(struct dwc3 *dwc)
 		}
 	}
 
+	dwc3_pdata = (struct dwc3_platform_data *)dev_get_platdata(dwc->dev);
+	if (dwc3_pdata && dwc3_pdata->xhci_priv) {
+		ret = platform_device_add_data(xhci, dwc3_pdata->xhci_priv,
+					       sizeof(struct xhci_plat_priv));
+		if (ret)
+			goto err;
+	}
+
 	ret = platform_device_add(xhci);
 	if (ret) {
 		dev_err(dwc->dev, "failed to register xHCI device\n");
-- 
2.7.4

[PATCH v2 2/5] usb: dwc3: add imx8mp dwc3 glue layer driver

[Li Jun]

imx8mp SoC integrate dwc3 3.30b IP and has some customizations to
support low power, which has a seprated wakeup irq and additional
logic to wakeup usb from low power mode both for host mode and
device mode.

Signed-off-by: Li Jun <jun.li@nxp.com>
---
 drivers/usb/dwc3/Kconfig       |  10 ++
 drivers/usb/dwc3/Makefile      |   1 +
 drivers/usb/dwc3/dwc3-imx8mp.c | 374 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 385 insertions(+)

diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
index 206caa0..7ef2339 100644
--- a/drivers/usb/dwc3/Kconfig
+++ b/drivers/usb/dwc3/Kconfig
@@ -138,4 +138,14 @@ config USB_DWC3_QCOM
 	  for peripheral mode support.
 	  Say 'Y' or 'M' if you have one such device.
 
+config USB_DWC3_IMX8MP
+	tristate "NXP iMX8MP Platform"
+	depends on OF && COMMON_CLK
+	depends on (ARCH_MXC && ARM64) || COMPILE_TEST
+	default USB_DWC3
+	help
+	  NXP iMX8M Plus SoC use DesignWare Core IP for USB2/3
+	  functionality.
+	  Say 'Y' or 'M' if you have one such device.
+
 endif
diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
index ae86da0..2259f88 100644
--- a/drivers/usb/dwc3/Makefile
+++ b/drivers/usb/dwc3/Makefile
@@ -51,3 +51,4 @@ obj-$(CONFIG_USB_DWC3_MESON_G12A)	+= dwc3-meson-g12a.o
 obj-$(CONFIG_USB_DWC3_OF_SIMPLE)	+= dwc3-of-simple.o
 obj-$(CONFIG_USB_DWC3_ST)		+= dwc3-st.o
 obj-$(CONFIG_USB_DWC3_QCOM)		+= dwc3-qcom.o
+obj-$(CONFIG_USB_DWC3_IMX8MP)		+= dwc3-imx8mp.o
diff --git a/drivers/usb/dwc3/dwc3-imx8mp.c b/drivers/usb/dwc3/dwc3-imx8mp.c
new file mode 100644
index 0000000..e67d404
--- /dev/null
+++ b/drivers/usb/dwc3/dwc3-imx8mp.c
@@ -0,0 +1,374 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * dwc3-imx8mp.c - NXP imx8mp Specific Glue layer
+ *
+ * Copyright (c) 2020 NXP.
+ */
+
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/of_platform.h>
+#include <linux/pm_runtime.h>
+
+#include "core.h"
+
+/* USB wakeup registers */
+#define USB_WAKEUP_CTRL			0x00
+
+/* Global wakeup interrupt enable, also used to clear interrupt */
+#define USB_WAKEUP_EN			BIT(31)
+/* Wakeup from connect or disconnect, only for superspeed */
+#define USB_WAKEUP_SS_CONN		BIT(5)
+/* 0 select vbus_valid, 1 select sessvld */
+#define USB_WAKEUP_VBUS_SRC_SESS_VAL	BIT(4)
+/* Enable signal for wake up from u3 state */
+#define USB_WAKEUP_U3_EN		BIT(3)
+/* Enable signal for wake up from id change */
+#define USB_WAKEUP_ID_EN		BIT(2)
+/* Enable signal for wake up from vbus change */
+#define	USB_WAKEUP_VBUS_EN		BIT(1)
+/* Enable signal for wake up from dp/dm change */
+#define USB_WAKEUP_DPDM_EN		BIT(0)
+
+#define USB_WAKEUP_EN_MASK		GENMASK(5, 0)
+
+struct dwc3_imx8mp {
+	struct device			*dev;
+	struct platform_device		*dwc3;
+	void __iomem			*glue_base;
+	struct clk_bulk_data		*clks;
+	int				num_clks;
+	int				irq;
+	bool				pm_suspended;
+	bool				wakeup_pending;
+};
+
+static const struct clk_bulk_data dwc3_imx8mp_clks[] = {
+	{ .id = "hsio" },
+	{ .id = "bus" },
+	{ .id = "suspend" },
+};
+
+static void dwc3_imx8mp_wakeup_enable(struct dwc3_imx8mp *dwc3_imx)
+{
+	struct dwc3	*dwc3 = platform_get_drvdata(dwc3_imx->dwc3);
+	u32		val;
+
+	if (!dwc3)
+		return;
+
+	val = readl(dwc3_imx->glue_base + USB_WAKEUP_CTRL);
+
+	if ((dwc3->current_dr_role == DWC3_GCTL_PRTCAP_HOST) && dwc3->xhci)
+		val |= USB_WAKEUP_EN | USB_WAKEUP_SS_CONN |
+		       USB_WAKEUP_U3_EN | USB_WAKEUP_DPDM_EN;
+	else if (dwc3->current_dr_role == DWC3_GCTL_PRTCAP_DEVICE)
+		val |= USB_WAKEUP_EN | USB_WAKEUP_VBUS_EN |
+		       USB_WAKEUP_VBUS_SRC_SESS_VAL;
+
+	writel(val, dwc3_imx->glue_base + USB_WAKEUP_CTRL);
+}
+
+static void dwc3_imx8mp_wakeup_disable(struct dwc3_imx8mp *dwc3_imx)
+{
+	u32 val;
+
+	val = readl(dwc3_imx->glue_base + USB_WAKEUP_CTRL);
+	val &= ~(USB_WAKEUP_EN | USB_WAKEUP_EN_MASK);
+	writel(val, dwc3_imx->glue_base + USB_WAKEUP_CTRL);
+}
+
+static irqreturn_t dwc3_imx8mp_interrupt(int irq, void *_dwc3_imx)
+{
+	struct dwc3_imx8mp	*dwc3_imx = _dwc3_imx;
+	struct dwc3		*dwc = platform_get_drvdata(dwc3_imx->dwc3);
+
+	if (!dwc3_imx->pm_suspended)
+		return IRQ_HANDLED;
+
+	disable_irq_nosync(dwc3_imx->irq);
+	dwc3_imx->wakeup_pending = true;
+
+	if ((dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) && dwc->xhci)
+		pm_runtime_resume(&dwc->xhci->dev);
+	else if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_DEVICE)
+		pm_runtime_get(dwc->dev);
+
+	return IRQ_HANDLED;
+}
+
+static struct xhci_plat_priv dwc3_imx8mp_xhci_priv = {
+	.quirks = XHCI_NO_64BIT_SUPPORT |
+		  XHCI_MISSING_CAS,
+};
+
+static struct dwc3_platform_data dwc3_imx8mp_pdata = {
+	.xhci_priv = &dwc3_imx8mp_xhci_priv,
+};
+
+static struct of_dev_auxdata dwc3_imx8mp_auxdata[] = {
+	{
+	.compatible = "snps,dwc3",
+	.platform_data = &dwc3_imx8mp_pdata,
+	},
+	{},
+};
+
+static int dwc3_imx8mp_probe(struct platform_device *pdev)
+{
+	struct device		*dev = &pdev->dev;
+	struct device_node	*dwc3_np, *node = dev->of_node;
+	struct dwc3_imx8mp	*dwc3_imx;
+	int			err, irq;
+
+	if (!node) {
+		dev_err(dev, "device node not found\n");
+		return -EINVAL;
+	}
+
+	dwc3_imx = devm_kzalloc(dev, sizeof(*dwc3_imx), GFP_KERNEL);
+	if (!dwc3_imx)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, dwc3_imx);
+
+	dwc3_imx->dev = dev;
+
+	dwc3_imx->glue_base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(dwc3_imx->glue_base))
+		return PTR_ERR(dwc3_imx->glue_base);
+
+	dwc3_imx->clks = devm_kmemdup(dev, dwc3_imx8mp_clks,
+			sizeof(dwc3_imx8mp_clks), GFP_KERNEL);
+	if (!dwc3_imx->clks)
+		return -ENOMEM;
+
+	dwc3_imx->num_clks = ARRAY_SIZE(dwc3_imx8mp_clks);
+	err = devm_clk_bulk_get(dev, dwc3_imx->num_clks, dwc3_imx->clks);
+	if (err) {
+		dev_err(dev, "Failed to request all necessary clocks\n");
+		return err;
+	}
+
+	err = clk_bulk_prepare_enable(dwc3_imx->num_clks, dwc3_imx->clks);
+	if (err)
+		return err;
+
+	/* Double enable suspend clk to keep it always on  */
+	err = clk_prepare_enable(dwc3_imx->clks[dwc3_imx->num_clks-1].clk);
+	if (err)
+		goto disable_bulk_clk;
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		err = irq;
+		goto disable_clks;
+	}
+	dwc3_imx->irq = irq;
+
+	err = devm_request_threaded_irq(dev, irq, NULL, dwc3_imx8mp_interrupt,
+					IRQF_ONESHOT, dev_name(dev), dwc3_imx);
+	if (err) {
+		dev_err(dev, "failed to request IRQ #%d --> %d\n", irq, err);
+		goto disable_clks;
+	}
+
+	pm_runtime_set_active(dev);
+	pm_runtime_enable(dev);
+	err = pm_runtime_get_sync(dev);
+	if (err < 0)
+		goto disable_rpm;
+
+	dwc3_np = of_get_child_by_name(node, "dwc3");
+	if (!dwc3_np) {
+		dev_err(dev, "failed to find dwc3 core child\n");
+		goto disable_rpm;
+	}
+
+	err = of_platform_populate(node, NULL, dwc3_imx8mp_auxdata, dev);
+	if (err) {
+		dev_err(&pdev->dev, "failed to create dwc3 core\n");
+		goto err_node_put;
+	}
+
+	dwc3_imx->dwc3 = of_find_device_by_node(dwc3_np);
+	if (!dwc3_imx->dwc3) {
+		dev_err(dev, "failed to get dwc3 platform device\n");
+		err = -ENODEV;
+		goto depopulate;
+	}
+	of_node_put(dwc3_np);
+
+	device_set_wakeup_capable(dev, true);
+	pm_runtime_put(dev);
+
+	return 0;
+
+depopulate:
+	of_platform_depopulate(dev);
+err_node_put:
+	of_node_put(dwc3_np);
+disable_rpm:
+	pm_runtime_disable(dev);
+	pm_runtime_put_noidle(dev);
+disable_clks:
+	clk_disable_unprepare(dwc3_imx->clks[dwc3_imx->num_clks-1].clk);
+disable_bulk_clk:
+	clk_bulk_disable_unprepare(dwc3_imx->num_clks, dwc3_imx->clks);
+
+	return err;
+}
+
+static int dwc3_imx8mp_remove(struct platform_device *pdev)
+{
+	struct dwc3_imx8mp *dwc3_imx = platform_get_drvdata(pdev);
+	struct device *dev = &pdev->dev;
+
+	pm_runtime_get_sync(dev);
+	of_platform_depopulate(dev);
+
+	clk_bulk_disable_unprepare(dwc3_imx->num_clks, dwc3_imx->clks);
+	clk_disable_unprepare(dwc3_imx->clks[dwc3_imx->num_clks-1].clk);
+
+	pm_runtime_disable(dev);
+	pm_runtime_put_noidle(dev);
+	platform_set_drvdata(pdev, NULL);
+
+	return 0;
+}
+
+static int __maybe_unused dwc3_imx8mp_suspend(struct dwc3_imx8mp *dwc3_imx,
+					      pm_message_t msg)
+{
+	if (dwc3_imx->pm_suspended)
+		return 0;
+
+	/* Wakeup enable */
+	if (PMSG_IS_AUTO(msg) || device_may_wakeup(dwc3_imx->dev))
+		dwc3_imx8mp_wakeup_enable(dwc3_imx);
+
+	clk_bulk_disable_unprepare(dwc3_imx->num_clks, dwc3_imx->clks);
+	dwc3_imx->pm_suspended = true;
+
+	return 0;
+}
+
+static int __maybe_unused dwc3_imx8mp_resume(struct dwc3_imx8mp *dwc3_imx,
+					     pm_message_t msg)
+{
+	struct dwc3	*dwc = platform_get_drvdata(dwc3_imx->dwc3);
+	int ret = 0;
+
+	if (!dwc3_imx->pm_suspended)
+		return 0;
+
+	ret = clk_bulk_prepare_enable(dwc3_imx->num_clks, dwc3_imx->clks);
+	if (ret)
+		return ret;
+
+	/* Wakeup disable */
+	dwc3_imx8mp_wakeup_disable(dwc3_imx);
+	dwc3_imx->pm_suspended = false;
+
+	if (dwc3_imx->wakeup_pending) {
+		dwc3_imx->wakeup_pending = false;
+		if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_DEVICE) {
+			pm_runtime_mark_last_busy(dwc->dev);
+			pm_runtime_put_autosuspend(dwc->dev);
+		} else {
+			/*
+			 * Add wait for xhci switch from suspend
+			 * clock to normal clock to detect connection.
+			 */
+			usleep_range(9000, 10000);
+		}
+		enable_irq(dwc3_imx->irq);
+	}
+
+	return ret;
+}
+
+static int __maybe_unused dwc3_imx8mp_pm_suspend(struct device *dev)
+{
+	struct dwc3_imx8mp *dwc3_imx = dev_get_drvdata(dev);
+	int ret;
+
+	ret = dwc3_imx8mp_suspend(dwc3_imx, PMSG_SUSPEND);
+
+	if (device_may_wakeup(dwc3_imx->dev))
+		enable_irq_wake(dwc3_imx->irq);
+
+	dev_dbg(dev, "dwc3 imx8mp pm suspend.\n");
+
+	return ret;
+}
+
+static int __maybe_unused dwc3_imx8mp_pm_resume(struct device *dev)
+{
+	struct dwc3_imx8mp *dwc3_imx = dev_get_drvdata(dev);
+	int ret;
+
+	if (device_may_wakeup(dwc3_imx->dev))
+		disable_irq_wake(dwc3_imx->irq);
+
+	ret = dwc3_imx8mp_resume(dwc3_imx, PMSG_RESUME);
+
+	pm_runtime_disable(dev);
+	pm_runtime_set_active(dev);
+	pm_runtime_enable(dev);
+
+	dev_dbg(dev, "dwc3 imx8mp pm resume.\n");
+
+	return ret;
+}
+
+static int __maybe_unused dwc3_imx8mp_runtime_suspend(struct device *dev)
+{
+	struct dwc3_imx8mp *dwc3_imx = dev_get_drvdata(dev);
+
+	dev_dbg(dev, "dwc3 imx8mp runtime suspend.\n");
+
+	return dwc3_imx8mp_suspend(dwc3_imx, PMSG_AUTO_SUSPEND);
+}
+
+static int __maybe_unused dwc3_imx8mp_runtime_resume(struct device *dev)
+{
+	struct dwc3_imx8mp *dwc3_imx = dev_get_drvdata(dev);
+
+	dev_dbg(dev, "dwc3 imx8mp runtime resume.\n");
+
+	return dwc3_imx8mp_resume(dwc3_imx, PMSG_AUTO_RESUME);
+}
+
+static const struct dev_pm_ops dwc3_imx8mp_dev_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(dwc3_imx8mp_pm_suspend, dwc3_imx8mp_pm_resume)
+	SET_RUNTIME_PM_OPS(dwc3_imx8mp_runtime_suspend,
+			   dwc3_imx8mp_runtime_resume, NULL)
+};
+
+static const struct of_device_id dwc3_imx8mp_of_match[] = {
+	{ .compatible = "fsl,imx8mp-dwc3", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, dwc3_imx8mp_of_match);
+
+static struct platform_driver dwc3_imx8mp_driver = {
+	.probe		= dwc3_imx8mp_probe,
+	.remove		= dwc3_imx8mp_remove,
+	.driver		= {
+		.name	= "imx8mp-dwc3",
+		.pm	= &dwc3_imx8mp_dev_pm_ops,
+		.of_match_table	= dwc3_imx8mp_of_match,
+	},
+};
+
+module_platform_driver(dwc3_imx8mp_driver);
+
+MODULE_ALIAS("platform:imx8mp-dwc3");
+MODULE_AUTHOR("jun.li@nxp.com");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("DesignWare USB3 imx8mp Glue Layer");
-- 
2.7.4

[PATCH v2 3/5] arm64: dtsi: imx8mp: add usb nodes

[Li Jun]

imx8mp integrates 2 identical dwc3 based USB3 controllers and
Synopsys phys, each instance has additional wakeup logic to
support low powe mode, so the glue layer need a node with dwc3
core sub node.

Signed-off-by: Li Jun <jun.li@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 77 +++++++++++++++++++++++++++++++
 1 file changed, 77 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 9b1616e..f3d671f5 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -650,5 +650,82 @@
 			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-parent = <&gic>;
 		};
+
+		usb3_phy0: usb-phy@381f0040 {
+			compatible = "fsl,imx8mp-usb-phy";
+			reg = <0x381f0040 0x40>;
+			clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
+			clock-names = "phy";
+			assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
+			assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
+		usb3_0: usb@32f10100 {
+			compatible = "fsl,imx8mp-dwc3";
+			reg = <0x32f10100 0x8>;
+			clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+				 <&clk IMX8MP_CLK_HSIO_AXI_DIV>,
+				 <&clk IMX8MP_CLK_USB_ROOT>;
+			clock-names = "hsio", "bus", "suspend";
+			assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>;
+			assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
+			assigned-clock-rates = <500000000>;
+			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			status = "disabled";
+
+			usb_dwc3_0: dwc3@38100000 {
+				compatible = "snps,dwc3";
+				reg = <0x38100000 0x10000>;
+				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+				phys = <&usb3_phy0>, <&usb3_phy0>;
+				phy-names = "usb2-phy", "usb3-phy";
+				snps,dis-u2-freeclk-exists-quirk;
+				status = "disabled";
+			};
+
+		};
+
+		usb3_phy1: usb-phy@382f0040 {
+			compatible = "fsl,imx8mp-usb-phy";
+			reg = <0x382f0040 0x40>;
+			clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
+			clock-names = "phy";
+			assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
+			assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
+		usb3_1: usb@32f10108 {
+			compatible = "fsl,imx8mp-dwc3";
+			reg = <0x32f10108 0x8>;
+			clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+				 <&clk IMX8MP_CLK_HSIO_AXI_DIV>,
+				 <&clk IMX8MP_CLK_USB_ROOT>;
+			clock-names = "hsio", "bus", "suspend";
+			assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>;
+			assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
+			assigned-clock-rates = <500000000>;
+			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			status = "disabled";
+
+			usb_dwc3_1: dwc3@38200000 {
+				compatible = "snps,dwc3";
+				reg = <0x38200000 0x10000>;
+				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+				phys = <&usb3_phy1>, <&usb3_phy1>;
+				phy-names = "usb2-phy", "usb3-phy";
+				snps,dis-u2-freeclk-exists-quirk;
+				status = "disabled";
+			};
+		};
 	};
 };
-- 
2.7.4

[PATCH v2 4/5] arm64: dts: imx8mp-evk: enable usb1 as host mode

[Li Jun]

Enable usb host port with type-A connector on imx8mp-evk board.

Signed-off-by: Li Jun <jun.li@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 3da1fff..c7cacf2 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -91,6 +91,21 @@
 	status = "okay";
 };
 
+&usb3_phy1 {
+	status = "okay";
+};
+
+&usb3_1 {
+	status = "okay";
+};
+
+&usb_dwc3_1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb1_vbus>;
+	dr_mode = "host";
+	status = "okay";
+};
+
 &usdhc2 {
 	assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
 	assigned-clock-rates = <400000000>;
@@ -172,6 +187,12 @@
 		>;
 	};
 
+	pinctrl_usb1_vbus: usb1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO14__HSIOMIX_usb2_OTG_PWR	0x19
+		>;
+	};
+
 	pinctrl_usdhc2: usdhc2grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190
-- 
2.7.4

[PATCH v2 5/5] dt-bindings: usb: dwc3-imx8mp: add imx8mp dwc3 glue bindings

[Li Jun]

NXP imx8mp integrates 2 dwc3 3.30b IP and add some wakeup logic
to support low power mode, the glue layer is for this wakeup
functionality, which has a separated interrupt, can support
wakeup from U3 and connect events for host, and vbus wakeup for
device.

Signed-off-by: Li Jun <jun.li@nxp.com>
---
 .../devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml   | 87 ++++++++++++++++++++++
 1 file changed, 87 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml b/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml
new file mode 100644
index 0000000..823db058
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 NXP
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/fsl,imx8mp-dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP iMX8MP Soc USB Controller
+
+maintainers:
+  - Li Jun <jun.li@nxp.com>
+
+properties:
+  compatible:
+    items:
+    - const: fsl,imx8mp-dwc3
+
+  reg:
+    maxItems: 1
+    description: Address and length of the register set for the wrapper of
+      dwc3 core on the SOC.
+
+  "#address-cells":
+    enum: [ 1, 2 ]
+
+  "#size-cells":
+    enum: [ 1, 2 ]
+
+  interrupts:
+    maxItems: 1
+    description: The interrupt that is asserted when a wakeup event is
+      received.
+
+  clocks:
+    description:
+      A list of phandle and clock-specifier pairs for the clocks
+      listed in clock-names.
+    items:
+      - description: system hsio root clock.
+      - description: system bus AXI clock.
+      - description: suspend clock, used for wakeup logic.
+
+  clock-names:
+    items:
+      - const: hsio
+      - const: bus
+      - const: suspend
+
+# Required child node:
+
+  dwc3:
+    description: This is the node representing the DWC3 controller instance
+      Documentation/devicetree/bindings/usb/dwc3.txt
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8mp-clock.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    usb3_0: usb@32f10100 {
+      compatible = "fsl,imx8mp-dwc3";
+      reg = <0x32f10100 0x8>;
+      clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+               <&clk IMX8MP_CLK_HSIO_AXI_DIV>,
+               <&clk IMX8MP_CLK_USB_ROOT>;
+      clock-names = "hsio", "bus", "suspend";
+      assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>;
+      assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
+      assigned-clock-rates = <500000000>;
+      interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+      #address-cells = <1>;
+      #size-cells = <1>;
+      ranges;
+
+      dwc3@38100000 {
+        compatible = "snps,dwc3";
+        reg = <0x38100000 0x10000>;
+        interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+        phys = <&usb3_phy0>, <&usb3_phy0>;
+        phy-names = "usb2-phy", "usb3-phy";
+      };
+    };
-- 
2.7.4

Re: [PATCH v2 5/5] dt-bindings: usb: dwc3-imx8mp: add imx8mp dwc3 glue bindings

[Rob Herring]

On Mon, Jul 06, 2020 at 05:44:59PM +0800, Li Jun wrote:
> NXP imx8mp integrates 2 dwc3 3.30b IP and add some wakeup logic
> to support low power mode, the glue layer is for this wakeup
> functionality, which has a separated interrupt, can support
> wakeup from U3 and connect events for host, and vbus wakeup for
> device.
> 
> Signed-off-by: Li Jun <jun.li@nxp.com>
> ---
>  .../devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml   | 87 ++++++++++++++++++++++
>  1 file changed, 87 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml b/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml
> new file mode 100644
> index 0000000..823db058
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml
> @@ -0,0 +1,87 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2020 NXP
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/usb/fsl,imx8mp-dwc3.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP iMX8MP Soc USB Controller
> +
> +maintainers:
> +  - Li Jun <jun.li@nxp.com>
> +
> +properties:
> +  compatible:
> +    items:
> +    - const: fsl,imx8mp-dwc3
> +
> +  reg:
> +    maxItems: 1
> +    description: Address and length of the register set for the wrapper of
> +      dwc3 core on the SOC.
> +
> +  "#address-cells":
> +    enum: [ 1, 2 ]
> +
> +  "#size-cells":
> +    enum: [ 1, 2 ]
> +
> +  interrupts:
> +    maxItems: 1
> +    description: The interrupt that is asserted when a wakeup event is
> +      received.
> +
> +  clocks:
> +    description:
> +      A list of phandle and clock-specifier pairs for the clocks
> +      listed in clock-names.
> +    items:
> +      - description: system hsio root clock.
> +      - description: system bus AXI clock.
> +      - description: suspend clock, used for wakeup logic.
> +
> +  clock-names:
> +    items:
> +      - const: hsio
> +      - const: bus
> +      - const: suspend
> +
> +# Required child node:
> +
> +  dwc3:

Needs to be a pattern with the unit-address.

> +    description: This is the node representing the DWC3 controller instance
> +      Documentation/devicetree/bindings/usb/dwc3.txt
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - clocks

Pretty sure you need a few more properties here...

Add:

additionalProperties: false

> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/imx8mp-clock.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    usb3_0: usb@32f10100 {
> +      compatible = "fsl,imx8mp-dwc3";
> +      reg = <0x32f10100 0x8>;
> +      clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
> +               <&clk IMX8MP_CLK_HSIO_AXI_DIV>,
> +               <&clk IMX8MP_CLK_USB_ROOT>;
> +      clock-names = "hsio", "bus", "suspend";
> +      assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>;
> +      assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
> +      assigned-clock-rates = <500000000>;
> +      interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> +      #address-cells = <1>;
> +      #size-cells = <1>;
> +      ranges;
> +
> +      dwc3@38100000 {
> +        compatible = "snps,dwc3";
> +        reg = <0x38100000 0x10000>;
> +        interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
> +        phys = <&usb3_phy0>, <&usb3_phy0>;
> +        phy-names = "usb2-phy", "usb3-phy";
> +      };
> +    };
> -- 
> 2.7.4
> 

RE: [PATCH v2 1/5] usb: dwc3: add platform data to dwc3 core device to pass data

[Jun Li]

> -----Original Message-----
> From: Jun Li <jun.li@nxp.com>
> Sent: Monday, July 6, 2020 5:45 PM
> To: balbi@kernel.org; shawnguo@kernel.org; robh+dt@kernel.org
> Cc: gregkh@linuxfoundation.org; s.hauer@pengutronix.de; kernel@pengutronix.de;
> festevam@gmail.com; dl-linux-imx <linux-imx@nxp.com>; linux-usb@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org; Peter Chen
> <peter.chen@nxp.com>; Anson Huang <anson.huang@nxp.com>; Peng Fan
> <peng.fan@nxp.com>; Horia Geanta <horia.geanta@nxp.com>
> Subject: [PATCH v2 1/5] usb: dwc3: add platform data to dwc3 core device to pass
> data
> 
> In case dwc3 has SoC specific customizations, dwc3 glue driver can base on compatible
> string and pass it via platform data to dwc3 core driver; and pass xhci private
> data further to xhci-plat like quirks.
> 
> Signed-off-by: Li Jun <jun.li@nxp.com>
> ---
>  drivers/usb/dwc3/core.h | 5 +++++
>  drivers/usb/dwc3/host.c | 9 +++++++++
>  2 files changed, 14 insertions(+)
> 
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index
> 0b8ea8c..3146697 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -29,6 +29,7 @@
>  #include <linux/ulpi/interface.h>
> 
>  #include <linux/phy/phy.h>
> +#include "../host/xhci-plat.h"
> 
>  #define DWC3_MSG_MAX	500
> 
> @@ -924,6 +925,10 @@ struct dwc3_scratchpad_array {
>  	__le64	dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
>  };
> 
> +struct dwc3_platform_data {
> +	struct xhci_plat_priv *xhci_priv;
> +};
> +
>  /**
>   * struct dwc3 - representation of our controller
>   * @drd_work: workqueue used for role swapping diff --git a/drivers/usb/dwc3/host.c
> b/drivers/usb/dwc3/host.c index bef1c1a..4f8514a 100644
> --- a/drivers/usb/dwc3/host.c
> +++ b/drivers/usb/dwc3/host.c
> @@ -46,6 +46,7 @@ int dwc3_host_init(struct dwc3 *dwc)  {
>  	struct property_entry	props[4];
>  	struct platform_device	*xhci;
> +	struct dwc3_platform_data *dwc3_pdata;
>  	int			ret, irq;
>  	struct resource		*res;
>  	struct platform_device	*dwc3_pdev = to_platform_device(dwc->dev);
> @@ -115,6 +116,14 @@ int dwc3_host_init(struct dwc3 *dwc)
>  		}
>  	}
> 
> +	dwc3_pdata = (struct dwc3_platform_data *)dev_get_platdata(dwc->dev);
> +	if (dwc3_pdata && dwc3_pdata->xhci_priv) {
> +		ret = platform_device_add_data(xhci, dwc3_pdata->xhci_priv,
> +					       sizeof(struct xhci_plat_priv));
> +		if (ret)
> +			goto err;
> +	}
> +
>  	ret = platform_device_add(xhci);
>  	if (ret) {
>  		dev_err(dwc->dev, "failed to register xHCI device\n");
> --
> 2.7.4

A gentle ping...

Thanks
Li Jun

Re: [PATCH v2 1/5] usb: dwc3: add platform data to dwc3 core device to pass data

[Felipe Balbi]

[-- Attachment #1: Type: text/plain, Size: 1013 bytes --]


Hi,

Li Jun <jun.li@nxp.com> writes:
> In case dwc3 has SoC specific customizations, dwc3 glue driver can base on
> compatible string and pass it via platform data to dwc3 core driver; and
> pass xhci private data further to xhci-plat like quirks.
>
> Signed-off-by: Li Jun <jun.li@nxp.com>
> ---
>  drivers/usb/dwc3/core.h | 5 +++++
>  drivers/usb/dwc3/host.c | 9 +++++++++
>  2 files changed, 14 insertions(+)
>
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index 0b8ea8c..3146697 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -29,6 +29,7 @@
>  #include <linux/ulpi/interface.h>
>  
>  #include <linux/phy/phy.h>
> +#include "../host/xhci-plat.h"
>  
>  #define DWC3_MSG_MAX	500
>  
> @@ -924,6 +925,10 @@ struct dwc3_scratchpad_array {
>  	__le64	dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
>  };
>  
> +struct dwc3_platform_data {
> +	struct xhci_plat_priv *xhci_priv;
> +};

why? We should rely on properties, no?

-- 
balbi

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 832 bytes --]

RE: [PATCH v2 1/5] usb: dwc3: add platform data to dwc3 core device to pass data

[Jun Li]

> -----Original Message-----
> From: Felipe Balbi <balbif@gmail.com> On Behalf Of Felipe Balbi
> Sent: Thursday, July 23, 2020 5:22 PM
> To: Jun Li <jun.li@nxp.com>; shawnguo@kernel.org; robh+dt@kernel.org
> Cc: gregkh@linuxfoundation.org; s.hauer@pengutronix.de; kernel@pengutronix.de;
> festevam@gmail.com; dl-linux-imx <linux-imx@nxp.com>; linux-usb@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org; Peter Chen
> <peter.chen@nxp.com>; Anson Huang <anson.huang@nxp.com>; Peng Fan
> <peng.fan@nxp.com>; Horia Geanta <horia.geanta@nxp.com>
> Subject: Re: [PATCH v2 1/5] usb: dwc3: add platform data to dwc3 core device to
> pass data
> 
> 
> Hi,
> 
> Li Jun <jun.li@nxp.com> writes:
> > In case dwc3 has SoC specific customizations, dwc3 glue driver can
> > base on compatible string and pass it via platform data to dwc3 core
> > driver; and pass xhci private data further to xhci-plat like quirks.
> >
> > Signed-off-by: Li Jun <jun.li@nxp.com>
> > ---
> >  drivers/usb/dwc3/core.h | 5 +++++
> >  drivers/usb/dwc3/host.c | 9 +++++++++
> >  2 files changed, 14 insertions(+)
> >
> > diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index
> > 0b8ea8c..3146697 100644
> > --- a/drivers/usb/dwc3/core.h
> > +++ b/drivers/usb/dwc3/core.h
> > @@ -29,6 +29,7 @@
> >  #include <linux/ulpi/interface.h>
> >
> >  #include <linux/phy/phy.h>
> > +#include "../host/xhci-plat.h"
> >
> >  #define DWC3_MSG_MAX	500
> >
> > @@ -924,6 +925,10 @@ struct dwc3_scratchpad_array {
> >  	__le64	dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
> >  };
> >
> > +struct dwc3_platform_data {
> > +	struct xhci_plat_priv *xhci_priv;
> > +};
> 
> why? We should rely on properties, no?

My v1 patch was adding new property directly, considering Rob has objection
on that way if I understand correctly, also there is suggestion on use
compatible string to set quirks, I changed to add platform data to pass
SoC level quirks, I think this also can be used to extend other special
handling for glue layer driver, so should I go back to use properties? 
Hope an agreement can be made on adding new properties/quirks. 

Thanks
Li Jun
 
> 
> --
> balbi

RE: [PATCH v2 1/5] usb: dwc3: add platform data to dwc3 core device to pass data

[Jun Li]

> -----Original Message-----
> From: Jun Li
> Sent: Thursday, July 23, 2020 5:58 PM
> To: Felipe Balbi <balbi@kernel.org>; shawnguo@kernel.org; robh+dt@kernel.org
> Cc: gregkh@linuxfoundation.org; s.hauer@pengutronix.de; kernel@pengutronix.de;
> festevam@gmail.com; dl-linux-imx <linux-imx@nxp.com>; linux-usb@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org; Peter Chen
> <peter.chen@nxp.com>; Anson Huang <anson.huang@nxp.com>; Peng Fan
> <peng.fan@nxp.com>; Horia Geanta <horia.geanta@nxp.com>
> Subject: RE: [PATCH v2 1/5] usb: dwc3: add platform data to dwc3 core device to
> pass data
> 
> 
> 
> > -----Original Message-----
> > From: Felipe Balbi <balbif@gmail.com> On Behalf Of Felipe Balbi
> > Sent: Thursday, July 23, 2020 5:22 PM
> > To: Jun Li <jun.li@nxp.com>; shawnguo@kernel.org; robh+dt@kernel.org
> > Cc: gregkh@linuxfoundation.org; s.hauer@pengutronix.de;
> > kernel@pengutronix.de; festevam@gmail.com; dl-linux-imx
> > <linux-imx@nxp.com>; linux-usb@vger.kernel.org;
> > linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org;
> > Peter Chen <peter.chen@nxp.com>; Anson Huang <anson.huang@nxp.com>;
> > Peng Fan <peng.fan@nxp.com>; Horia Geanta <horia.geanta@nxp.com>
> > Subject: Re: [PATCH v2 1/5] usb: dwc3: add platform data to dwc3 core
> > device to pass data
> >
> >
> > Hi,
> >
> > Li Jun <jun.li@nxp.com> writes:
> > > In case dwc3 has SoC specific customizations, dwc3 glue driver can
> > > base on compatible string and pass it via platform data to dwc3 core
> > > driver; and pass xhci private data further to xhci-plat like quirks.
> > >
> > > Signed-off-by: Li Jun <jun.li@nxp.com>
> > > ---
> > >  drivers/usb/dwc3/core.h | 5 +++++
> > >  drivers/usb/dwc3/host.c | 9 +++++++++
> > >  2 files changed, 14 insertions(+)
> > >
> > > diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index
> > > 0b8ea8c..3146697 100644
> > > --- a/drivers/usb/dwc3/core.h
> > > +++ b/drivers/usb/dwc3/core.h
> > > @@ -29,6 +29,7 @@
> > >  #include <linux/ulpi/interface.h>
> > >
> > >  #include <linux/phy/phy.h>
> > > +#include "../host/xhci-plat.h"
> > >
> > >  #define DWC3_MSG_MAX	500
> > >
> > > @@ -924,6 +925,10 @@ struct dwc3_scratchpad_array {
> > >  	__le64	dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
> > >  };
> > >
> > > +struct dwc3_platform_data {
> > > +	struct xhci_plat_priv *xhci_priv;
> > > +};
> >
> > why? We should rely on properties, no?
> 
> My v1 patch was adding new property directly, considering Rob has objection on that
> way if I understand correctly, also there is suggestion on use compatible string
> to set quirks, I changed to add platform data to pass SoC level quirks, I think
> this also can be used to extend other special handling for glue layer driver, so
> should I go back to use properties?
> Hope an agreement can be made on adding new properties/quirks.
'
Hi Felipe,

Could you please point me how I can move forward on this, thanks a lot.

Li Jun
> 
> Thanks
> Li Jun
> 
> >
> > --
> > balbi