* [PATCH v5 2/6] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings
[not found] <20210727185527.19907-1-biju.das.jz@bp.renesas.com>
@ 2021-07-27 18:55 ` Biju Das
2021-08-02 20:55 ` Rob Herring
` (2 more replies)
2021-07-27 18:55 ` [PATCH v5 4/6] arm64: dts: renesas: r9a07g044: Add USB2.0 phy and host support Biju Das
` (2 subsequent siblings)
3 siblings, 3 replies; 11+ messages in thread
From: Biju Das @ 2021-07-27 18:55 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Kishon Vijay Abraham I, Vinod Koul, Yoshihiro Shimoda,
linux-phy, devicetree, Geert Uytterhoeven, Chris Paterson,
Biju Das, Prabhakar Mahadev Lad, linux-renesas-soc
Document USB phy bindings for RZ/G2L SoC.
RZ/G2L USB2.0 phy uses line ctrl register for OTG_ID pin changes. It uses
a different OTG-BC interrupt bit for device recognition. Apart from this,
the PHY reset is controlled by USBPHY control IP and Document reset is a
required property.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v4->v5:
* Removed 'properties' and just used 'required' for RZ/G2L SoC.
v3->v4:
* Removed second reset
* Added family specific compatible string.
v2->v3
* Created a new compatible for RZ/G2L as per Geert's suggestion.
* Added resets required properties for RZ/G2L SoC.
---
.../devicetree/bindings/phy/renesas,usb2-phy.yaml | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
index d5dc5a3cdceb..3a6e1165419c 100644
--- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
@@ -30,6 +30,11 @@ properties:
- renesas,usb2-phy-r8a77995 # R-Car D3
- const: renesas,rcar-gen3-usb2-phy
+ - items:
+ - enum:
+ - renesas,usb2-phy-r9a07g044 # RZ/G2{L,LC}
+ - const: renesas,rzg2l-usb2-phy # RZ/G2L family
+
reg:
maxItems: 1
@@ -91,6 +96,16 @@ required:
- clocks
- '#phy-cells'
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,rzg2l-usb2-phy
+ then:
+ required:
+ - resets
+
additionalProperties: false
examples:
--
2.17.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v5 4/6] arm64: dts: renesas: r9a07g044: Add USB2.0 phy and host support
[not found] <20210727185527.19907-1-biju.das.jz@bp.renesas.com>
2021-07-27 18:55 ` [PATCH v5 2/6] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings Biju Das
@ 2021-07-27 18:55 ` Biju Das
2021-08-10 10:19 ` Geert Uytterhoeven
2021-07-27 18:55 ` [PATCH v5 5/6] dt-bindings: usb: renesas,usbhs: Document RZ/G2L bindings Biju Das
2021-07-27 18:55 ` [PATCH v5 6/6] arm64: dts: renesas: r9a07g044: Add USB2.0 device support Biju Das
3 siblings, 1 reply; 11+ messages in thread
From: Biju Das @ 2021-07-27 18:55 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add USB2.0 phy and host support to SoC DT.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v4->v5:
* No change.
V3->v4:
* Removed second reset from phy node.
V3:
* Added reset entries
* Updated compatible, phy and reset entries.
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 94 ++++++++++++++++++++++
1 file changed, 94 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 9a7489dc70d1..f0dcd086ba20 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -200,6 +200,100 @@
<0x0 0x11940000 0 0x60000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
+
+ phyrst: usbphy-ctrl@11c40000 {
+ compatible = "renesas,r9a07g044-usbphy-ctrl",
+ "renesas,rzg2l-usbphy-ctrl";
+ reg = <0 0x11c40000 0 0x10000>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
+ resets = <&cpg R9A07G044_USB_PRESETN>;
+ power-domains = <&cpg>;
+ #reset-cells = <1>;
+ };
+
+ ohci0: usb@11c50000 {
+ compatible = "generic-ohci";
+ reg = <0 0x11c50000 0 0x100>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
+ resets = <&phyrst 0>,
+ <&cpg R9A07G044_USB_U2H0_HRESETN>;
+ phys = <&usb2_phy0 1>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ohci1: usb@11c70000 {
+ compatible = "generic-ohci";
+ reg = <0 0x11c70000 0 0x100>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
+ resets = <&phyrst 1>,
+ <&cpg R9A07G044_USB_U2H1_HRESETN>;
+ phys = <&usb2_phy1 1>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ehci0: usb@11c50100 {
+ compatible = "generic-ehci";
+ reg = <0 0x11c50100 0 0x100>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
+ resets = <&phyrst 0>,
+ <&cpg R9A07G044_USB_U2H0_HRESETN>;
+ phys = <&usb2_phy0 2>;
+ phy-names = "usb";
+ companion = <&ohci0>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ehci1: usb@11c70100 {
+ compatible = "generic-ehci";
+ reg = <0 0x11c70100 0 0x100>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
+ resets = <&phyrst 1>,
+ <&cpg R9A07G044_USB_U2H1_HRESETN>;
+ phys = <&usb2_phy1 2>;
+ phy-names = "usb";
+ companion = <&ohci1>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ usb2_phy0: usb-phy@11c50200 {
+ compatible = "renesas,usb2-phy-r9a07g044",
+ "renesas,rzg2l-usb2-phy";
+ reg = <0 0x11c50200 0 0x700>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
+ resets = <&phyrst 0>;
+ #phy-cells = <1>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ usb2_phy1: usb-phy@11c70200 {
+ compatible = "renesas,usb2-phy-r9a07g044",
+ "renesas,rzg2l-usb2-phy";
+ reg = <0 0x11c70200 0 0x700>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
+ resets = <&phyrst 1>;
+ #phy-cells = <1>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
};
timer {
--
2.17.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v5 5/6] dt-bindings: usb: renesas,usbhs: Document RZ/G2L bindings
[not found] <20210727185527.19907-1-biju.das.jz@bp.renesas.com>
2021-07-27 18:55 ` [PATCH v5 2/6] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings Biju Das
2021-07-27 18:55 ` [PATCH v5 4/6] arm64: dts: renesas: r9a07g044: Add USB2.0 phy and host support Biju Das
@ 2021-07-27 18:55 ` Biju Das
2021-08-02 20:56 ` Rob Herring
2021-07-27 18:55 ` [PATCH v5 6/6] arm64: dts: renesas: r9a07g044: Add USB2.0 device support Biju Das
3 siblings, 1 reply; 11+ messages in thread
From: Biju Das @ 2021-07-27 18:55 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Greg Kroah-Hartman, Yoshihiro Shimoda, linux-usb,
devicetree, Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
Document RZ/G2L (R9A07G044L) SoC bindings.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v4->v5:
* Added interrupts maxitems=1 for SoC's other than RZ/G2L.
v3->v4:
* Added maxitems in interrupt property as per Rob's suggestion.
v3:
* Updated the bindings as per the USBPHY control IP.
---
.../bindings/usb/renesas,usbhs.yaml | 26 +++++++++++++++++--
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
index ad73339ffe1d..012fe80a7611 100644
--- a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
+++ b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
@@ -17,7 +17,9 @@ properties:
- const: renesas,rza1-usbhs
- items:
- - const: renesas,usbhs-r7s9210 # RZ/A2
+ - enum:
+ - renesas,usbhs-r7s9210 # RZ/A2
+ - renesas,usbhs-r9a07g044 # RZ/G2{L,LC}
- const: renesas,rza2-usbhs
- items:
@@ -59,7 +61,8 @@ properties:
- description: USB 2.0 clock selector
interrupts:
- maxItems: 1
+ minItems: 1
+ maxItems: 4
renesas,buswait:
$ref: /schemas/types.yaml#/definitions/uint32
@@ -108,6 +111,25 @@ required:
- clocks
- interrupts
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,usbhs-r9a07g044
+ then:
+ properties:
+ interrupts:
+ items:
+ - description: U2P_IXL_INT
+ - description: U2P_INT_DMA[0]
+ - description: U2P_INT_DMA[1]
+ - description: U2P_INT_DMAERR
+ else:
+ properties:
+ interrupts:
+ maxItems: 1
+
additionalProperties: false
examples:
--
2.17.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v5 6/6] arm64: dts: renesas: r9a07g044: Add USB2.0 device support
[not found] <20210727185527.19907-1-biju.das.jz@bp.renesas.com>
` (2 preceding siblings ...)
2021-07-27 18:55 ` [PATCH v5 5/6] dt-bindings: usb: renesas,usbhs: Document RZ/G2L bindings Biju Das
@ 2021-07-27 18:55 ` Biju Das
2021-08-10 10:20 ` Geert Uytterhoeven
3 siblings, 1 reply; 11+ messages in thread
From: Biju Das @ 2021-07-27 18:55 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add USB2.0 device support to RZ/G2L SoC DT.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v4->v5:
* No change.
v3->v4:
* No change.
V3:
* Updated reset entries.
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index f0dcd086ba20..39ad13fb4c8c 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -294,6 +294,25 @@
power-domains = <&cpg>;
status = "disabled";
};
+
+ hsusb: usb@11c60000 {
+ compatible = "renesas,usbhs-r9a07g044",
+ "renesas,rza2-usbhs";
+ reg = <0 0x11c60000 0 0x10000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2P_EXR_CPUCLK>;
+ resets = <&phyrst 0>,
+ <&cpg R9A07G044_USB_U2P_EXL_SYSRST>;
+ renesas,buswait = <7>;
+ phys = <&usb2_phy0 3>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
};
timer {
--
2.17.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v5 2/6] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings
2021-07-27 18:55 ` [PATCH v5 2/6] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings Biju Das
@ 2021-08-02 20:55 ` Rob Herring
2021-08-04 9:38 ` Yoshihiro Shimoda
2021-08-06 12:42 ` Vinod Koul
2 siblings, 0 replies; 11+ messages in thread
From: Rob Herring @ 2021-08-02 20:55 UTC (permalink / raw)
To: Biju Das
Cc: Kishon Vijay Abraham I, linux-renesas-soc, linux-phy,
Rob Herring, Geert Uytterhoeven, Chris Paterson, Vinod Koul,
devicetree, Biju Das, Yoshihiro Shimoda, Prabhakar Mahadev Lad
On Tue, 27 Jul 2021 19:55:23 +0100, Biju Das wrote:
> Document USB phy bindings for RZ/G2L SoC.
>
> RZ/G2L USB2.0 phy uses line ctrl register for OTG_ID pin changes. It uses
> a different OTG-BC interrupt bit for device recognition. Apart from this,
> the PHY reset is controlled by USBPHY control IP and Document reset is a
> required property.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v4->v5:
> * Removed 'properties' and just used 'required' for RZ/G2L SoC.
> v3->v4:
> * Removed second reset
> * Added family specific compatible string.
> v2->v3
> * Created a new compatible for RZ/G2L as per Geert's suggestion.
> * Added resets required properties for RZ/G2L SoC.
> ---
> .../devicetree/bindings/phy/renesas,usb2-phy.yaml | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v5 5/6] dt-bindings: usb: renesas,usbhs: Document RZ/G2L bindings
2021-07-27 18:55 ` [PATCH v5 5/6] dt-bindings: usb: renesas,usbhs: Document RZ/G2L bindings Biju Das
@ 2021-08-02 20:56 ` Rob Herring
0 siblings, 0 replies; 11+ messages in thread
From: Rob Herring @ 2021-08-02 20:56 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, linux-usb, Prabhakar Mahadev Lad, linux-renesas-soc,
devicetree, Greg Kroah-Hartman, Biju Das, Chris Paterson,
Geert Uytterhoeven, Yoshihiro Shimoda
On Tue, 27 Jul 2021 19:55:26 +0100, Biju Das wrote:
> Document RZ/G2L (R9A07G044L) SoC bindings.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v4->v5:
> * Added interrupts maxitems=1 for SoC's other than RZ/G2L.
> v3->v4:
> * Added maxitems in interrupt property as per Rob's suggestion.
> v3:
> * Updated the bindings as per the USBPHY control IP.
> ---
> .../bindings/usb/renesas,usbhs.yaml | 26 +++++++++++++++++--
> 1 file changed, 24 insertions(+), 2 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH v5 2/6] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings
2021-07-27 18:55 ` [PATCH v5 2/6] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings Biju Das
2021-08-02 20:55 ` Rob Herring
@ 2021-08-04 9:38 ` Yoshihiro Shimoda
2021-08-06 12:42 ` Vinod Koul
2 siblings, 0 replies; 11+ messages in thread
From: Yoshihiro Shimoda @ 2021-08-04 9:38 UTC (permalink / raw)
To: Biju Das, Rob Herring
Cc: Biju Das, Kishon Vijay Abraham I, Vinod Koul, linux-phy,
devicetree, Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
Hi Biju-san,
> From: Biju Das, Sent: Wednesday, July 28, 2021 3:55 AM
>
> Document USB phy bindings for RZ/G2L SoC.
>
> RZ/G2L USB2.0 phy uses line ctrl register for OTG_ID pin changes. It uses
> a different OTG-BC interrupt bit for device recognition. Apart from this,
> the PHY reset is controlled by USBPHY control IP and Document reset is a
> required property.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Thank you for the patch!
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Best regards,
Yoshihiro Shimoda
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v5 2/6] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings
2021-07-27 18:55 ` [PATCH v5 2/6] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings Biju Das
2021-08-02 20:55 ` Rob Herring
2021-08-04 9:38 ` Yoshihiro Shimoda
@ 2021-08-06 12:42 ` Vinod Koul
2 siblings, 0 replies; 11+ messages in thread
From: Vinod Koul @ 2021-08-06 12:42 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Kishon Vijay Abraham I, Yoshihiro Shimoda,
linux-phy, devicetree, Geert Uytterhoeven, Chris Paterson,
Biju Das, Prabhakar Mahadev Lad, linux-renesas-soc
On 27-07-21, 19:55, Biju Das wrote:
> Document USB phy bindings for RZ/G2L SoC.
>
> RZ/G2L USB2.0 phy uses line ctrl register for OTG_ID pin changes. It uses
> a different OTG-BC interrupt bit for device recognition. Apart from this,
> the PHY reset is controlled by USBPHY control IP and Document reset is a
> required property.
Applied, thanks
--
~Vinod
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v5 4/6] arm64: dts: renesas: r9a07g044: Add USB2.0 phy and host support
2021-07-27 18:55 ` [PATCH v5 4/6] arm64: dts: renesas: r9a07g044: Add USB2.0 phy and host support Biju Das
@ 2021-08-10 10:19 ` Geert Uytterhoeven
2021-08-12 7:17 ` Biju Das
0 siblings, 1 reply; 11+ messages in thread
From: Geert Uytterhoeven @ 2021-08-10 10:19 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Geert Uytterhoeven, Magnus Damm, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Hi Biju,
On Tue, Jul 27, 2021 at 8:55 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add USB2.0 phy and host support to SoC DT.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Thanks for your patch!
> --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> @@ -200,6 +200,100 @@
> <0x0 0x11940000 0 0x60000>;
> interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
> };
> +
> + phyrst: usbphy-ctrl@11c40000 {
> + compatible = "renesas,r9a07g044-usbphy-ctrl",
> + "renesas,rzg2l-usbphy-ctrl";
> + reg = <0 0x11c40000 0 0x10000>;
> + clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
> + resets = <&cpg R9A07G044_USB_PRESETN>;
> + power-domains = <&cpg>;
> + #reset-cells = <1>;
Should there be a status = "disabled"?
> + };
The rest looks good to me, so with the above clarified:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v5 6/6] arm64: dts: renesas: r9a07g044: Add USB2.0 device support
2021-07-27 18:55 ` [PATCH v5 6/6] arm64: dts: renesas: r9a07g044: Add USB2.0 device support Biju Das
@ 2021-08-10 10:20 ` Geert Uytterhoeven
0 siblings, 0 replies; 11+ messages in thread
From: Geert Uytterhoeven @ 2021-08-10 10:20 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Magnus Damm, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
On Tue, Jul 27, 2021 at 8:55 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add USB2.0 device support to RZ/G2L SoC DT.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH v5 4/6] arm64: dts: renesas: r9a07g044: Add USB2.0 phy and host support
2021-08-10 10:19 ` Geert Uytterhoeven
@ 2021-08-12 7:17 ` Biju Das
0 siblings, 0 replies; 11+ messages in thread
From: Biju Das @ 2021-08-12 7:17 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Rob Herring, Geert Uytterhoeven, Magnus Damm, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH v5 4/6] arm64: dts: renesas: r9a07g044: Add USB2.0 phy
> and host support
>
> Hi Biju,
>
> On Tue, Jul 27, 2021 at 8:55 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > Add USB2.0 phy and host support to SoC DT.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > @@ -200,6 +200,100 @@
> > <0x0 0x11940000 0 0x60000>;
> > interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
> > };
> > +
> > + phyrst: usbphy-ctrl@11c40000 {
> > + compatible = "renesas,r9a07g044-usbphy-ctrl",
> > + "renesas,rzg2l-usbphy-ctrl";
> > + reg = <0 0x11c40000 0 0x10000>;
> > + clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
> > + resets = <&cpg R9A07G044_USB_PRESETN>;
> > + power-domains = <&cpg>;
> > + #reset-cells = <1>;
>
> Should there be a status = "disabled"?
OK, will add it in SoC dtsi, since all RZ/G2L based boards have USB support.
In future, if there is a requirement for handling of permanently unused pin
as mentioned in section "34.4.2. Handling of permanently unused pin"
then we need to enable this driver in SoC dtsi. with dt-binding and driver probe
changes for handling the same.
Cheers,
Biju
>
> > + };
>
> The rest looks good to me, so with the above clarified:
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
>
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2021-08-12 7:17 UTC | newest]
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[not found] <20210727185527.19907-1-biju.das.jz@bp.renesas.com>
2021-07-27 18:55 ` [PATCH v5 2/6] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings Biju Das
2021-08-02 20:55 ` Rob Herring
2021-08-04 9:38 ` Yoshihiro Shimoda
2021-08-06 12:42 ` Vinod Koul
2021-07-27 18:55 ` [PATCH v5 4/6] arm64: dts: renesas: r9a07g044: Add USB2.0 phy and host support Biju Das
2021-08-10 10:19 ` Geert Uytterhoeven
2021-08-12 7:17 ` Biju Das
2021-07-27 18:55 ` [PATCH v5 5/6] dt-bindings: usb: renesas,usbhs: Document RZ/G2L bindings Biju Das
2021-08-02 20:56 ` Rob Herring
2021-07-27 18:55 ` [PATCH v5 6/6] arm64: dts: renesas: r9a07g044: Add USB2.0 device support Biju Das
2021-08-10 10:20 ` Geert Uytterhoeven
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