[PATCH 0/4] spi: cadence-quadspi: Add Xilinx Versal OSPI support

[PATCH 0/4] spi: cadence-quadspi: Add Xilinx Versal OSPI support

[Sai Krishna Potthuri]

Add Octal SPI(OSPI) controller support for Xilinx Versal SoC.
Update the binding to add Xilinx Versal compatible string, also add
'power-domains' property and made as required for Xilinx Versal SoCs.
Add API in xilinx firmware for configuring OSPI Mux, which is
required to change the interface to OSPI. Xilinx Versal SoC
has external DMA support, so by using the OSPI MUX selection, interface
to the OSPI will be selected (either DMA interface or AXI slave interface).
Xilinx Versal OSPI external DMA:
Xilinx Versal OSPI DMA module is integrated to the Cadence OSPI Controller
with the DMA write channel. Cadence OSPI Controller which reads the data
from the Flash and stores in its internal SRAM and Xilinx Versal OSPI DMA
which reads the data from the SRAM in the Cadence OSPI Controller using
the DMA SRC channel and then the DMA DST channel initiates a write DMA
transfer into the destined address location.

Sai Krishna Potthuri (4):
  firmware: xilinx: Add OSPI Mux selection support
  dt-bindings: spi: cadence-quadspi: Add support for Xilinx Versal OSPI
  spi: cadence-quadspi: Add OSPI support for Xilinx Versal SoC
  spi: cadence-quadspi: Add Xilinx Versal external DMA support

 .../bindings/spi/cdns,qspi-nor.yaml           |  12 +
 drivers/firmware/xilinx/zynqmp.c              |  17 ++
 drivers/spi/spi-cadence-quadspi.c             | 214 ++++++++++++++++++
 include/linux/firmware/xlnx-zynqmp.h          |  12 +
 4 files changed, 255 insertions(+)

-- 
2.17.1

[PATCH 1/4] firmware: xilinx: Add OSPI Mux selection support

[Sai Krishna Potthuri]

Add OSPI Mux selection API support to select the AXI interface to OSPI.

Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
---
 drivers/firmware/xilinx/zynqmp.c     | 17 +++++++++++++++++
 include/linux/firmware/xlnx-zynqmp.h | 12 ++++++++++++
 2 files changed, 29 insertions(+)

diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 15b138326ecc..43c3b5a9eef7 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -647,6 +647,23 @@ int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type)
 }
 EXPORT_SYMBOL_GPL(zynqmp_pm_sd_dll_reset);
 
+/**
+ * zynqmp_pm_ospi_mux_select() - OSPI Mux selection
+ *
+ * @dev_id:	Device Id of the OSPI device.
+ * @select:	OSPI Mux select value.
+ *
+ * This function select the OSPI Mux.
+ *
+ * Return:	Returns status, either success or error+reason
+ */
+int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select)
+{
+	return zynqmp_pm_invoke_fn(PM_IOCTL, dev_id, IOCTL_OSPI_MUX_SELECT,
+				   select, 0, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_ospi_mux_select);
+
 /**
  * zynqmp_pm_write_ggs() - PM API for writing global general storage (ggs)
  * @index:	GGS register index
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index 9d1a5c175065..6979a79f553a 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -119,6 +119,7 @@ enum pm_ioctl_id {
 	IOCTL_READ_PGGS = 15,
 	/* Set healthy bit value */
 	IOCTL_SET_BOOT_HEALTH_STATUS = 17,
+	IOCTL_OSPI_MUX_SELECT = 21,
 };
 
 enum pm_query_id {
@@ -347,6 +348,11 @@ enum zynqmp_pm_shutdown_subtype {
 	ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM = 2,
 };
 
+enum ospi_mux_select_type {
+	PM_OSPI_MUX_SEL_DMA = 0,
+	PM_OSPI_MUX_SEL_LINEAR = 1,
+};
+
 /**
  * struct zynqmp_pm_query_data - PM query data
  * @qid:	query ID
@@ -383,6 +389,7 @@ int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data);
 int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data);
 int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value);
 int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type);
+int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select);
 int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
 			   const enum zynqmp_pm_reset_action assert_flag);
 int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status);
@@ -503,6 +510,11 @@ static inline int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type)
 	return -ENODEV;
 }
 
+static inline int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select)
+{
+	return -ENODEV;
+}
+
 static inline int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
 					 const enum zynqmp_pm_reset_action assert_flag)
 {
-- 
2.17.1

Re: [PATCH 1/4] firmware: xilinx: Add OSPI Mux selection support

[Greg Kroah-Hartman]

On Fri, Sep 24, 2021 at 03:37:08PM +0530, Sai Krishna Potthuri wrote:
> Add OSPI Mux selection API support to select the AXI interface to OSPI.
> 
> Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
> ---
>  drivers/firmware/xilinx/zynqmp.c     | 17 +++++++++++++++++
>  include/linux/firmware/xlnx-zynqmp.h | 12 ++++++++++++
>  2 files changed, 29 insertions(+)
> 
> diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
> index 15b138326ecc..43c3b5a9eef7 100644
> --- a/drivers/firmware/xilinx/zynqmp.c
> +++ b/drivers/firmware/xilinx/zynqmp.c
> @@ -647,6 +647,23 @@ int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type)
>  }
>  EXPORT_SYMBOL_GPL(zynqmp_pm_sd_dll_reset);
>  
> +/**
> + * zynqmp_pm_ospi_mux_select() - OSPI Mux selection
> + *
> + * @dev_id:	Device Id of the OSPI device.
> + * @select:	OSPI Mux select value.
> + *
> + * This function select the OSPI Mux.
> + *
> + * Return:	Returns status, either success or error+reason
> + */
> +int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select)
> +{
> +	return zynqmp_pm_invoke_fn(PM_IOCTL, dev_id, IOCTL_OSPI_MUX_SELECT,
> +				   select, 0, NULL);
> +}
> +EXPORT_SYMBOL_GPL(zynqmp_pm_ospi_mux_select);
> +
>  /**
>   * zynqmp_pm_write_ggs() - PM API for writing global general storage (ggs)
>   * @index:	GGS register index
> diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
> index 9d1a5c175065..6979a79f553a 100644
> --- a/include/linux/firmware/xlnx-zynqmp.h
> +++ b/include/linux/firmware/xlnx-zynqmp.h
> @@ -119,6 +119,7 @@ enum pm_ioctl_id {
>  	IOCTL_READ_PGGS = 15,
>  	/* Set healthy bit value */
>  	IOCTL_SET_BOOT_HEALTH_STATUS = 17,
> +	IOCTL_OSPI_MUX_SELECT = 21,

Why the gap?  What are the commands in the middle for?

thanks,

greg k-h

Re: [PATCH 1/4] firmware: xilinx: Add OSPI Mux selection support

[Michal Simek]

On 9/24/21 1:36 PM, Greg Kroah-Hartman wrote:
> On Fri, Sep 24, 2021 at 03:37:08PM +0530, Sai Krishna Potthuri wrote:
>> Add OSPI Mux selection API support to select the AXI interface to OSPI.
>>
>> Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
>> ---
>>  drivers/firmware/xilinx/zynqmp.c     | 17 +++++++++++++++++
>>  include/linux/firmware/xlnx-zynqmp.h | 12 ++++++++++++
>>  2 files changed, 29 insertions(+)
>>
>> diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
>> index 15b138326ecc..43c3b5a9eef7 100644
>> --- a/drivers/firmware/xilinx/zynqmp.c
>> +++ b/drivers/firmware/xilinx/zynqmp.c
>> @@ -647,6 +647,23 @@ int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type)
>>  }
>>  EXPORT_SYMBOL_GPL(zynqmp_pm_sd_dll_reset);
>>  
>> +/**
>> + * zynqmp_pm_ospi_mux_select() - OSPI Mux selection
>> + *
>> + * @dev_id:	Device Id of the OSPI device.
>> + * @select:	OSPI Mux select value.
>> + *
>> + * This function select the OSPI Mux.
>> + *
>> + * Return:	Returns status, either success or error+reason
>> + */
>> +int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select)
>> +{
>> +	return zynqmp_pm_invoke_fn(PM_IOCTL, dev_id, IOCTL_OSPI_MUX_SELECT,
>> +				   select, 0, NULL);
>> +}
>> +EXPORT_SYMBOL_GPL(zynqmp_pm_ospi_mux_select);
>> +
>>  /**
>>   * zynqmp_pm_write_ggs() - PM API for writing global general storage (ggs)
>>   * @index:	GGS register index
>> diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
>> index 9d1a5c175065..6979a79f553a 100644
>> --- a/include/linux/firmware/xlnx-zynqmp.h
>> +++ b/include/linux/firmware/xlnx-zynqmp.h
>> @@ -119,6 +119,7 @@ enum pm_ioctl_id {
>>  	IOCTL_READ_PGGS = 15,
>>  	/* Set healthy bit value */
>>  	IOCTL_SET_BOOT_HEALTH_STATUS = 17,
>> +	IOCTL_OSPI_MUX_SELECT = 21,
> 
> Why the gap?  What are the commands in the middle for?

Below is the full list. Not everything has been upstream yet. There was
an attempt on AFI which one colleague is working on and should send new
version soon. I don't think anybody has started with upstreaming probe
counters.
Every part has different owner with unfortunately own upstreaming plan.

Thanks,
Michal

enum pm_ioctl_id {
	IOCTL_GET_RPU_OPER_MODE = 0,
	IOCTL_SET_RPU_OPER_MODE = 1,
	IOCTL_RPU_BOOT_ADDR_CONFIG = 2,
	IOCTL_TCM_COMB_CONFIG = 3,
	IOCTL_SET_TAPDELAY_BYPASS = 4,
	IOCTL_SET_SGMII_MODE = 5,
	IOCTL_SD_DLL_RESET = 6,
	IOCTL_SET_SD_TAPDELAY = 7,
	IOCTL_SET_PLL_FRAC_MODE = 8,
	IOCTL_GET_PLL_FRAC_MODE = 9,
	IOCTL_SET_PLL_FRAC_DATA = 10,
	IOCTL_GET_PLL_FRAC_DATA = 11,
	IOCTL_WRITE_GGS = 12,
	IOCTL_READ_GGS = 13,
	IOCTL_WRITE_PGGS = 14,
	IOCTL_READ_PGGS = 15,
	/* IOCTL for ULPI reset */
	IOCTL_ULPI_RESET = 16,
	/* Set healthy bit value */
	IOCTL_SET_BOOT_HEALTH_STATUS = 17,
	IOCTL_AFI = 18,
	/* Probe counter read/write */
	IOCTL_PROBE_COUNTER_READ = 19,
	IOCTL_PROBE_COUNTER_WRITE = 20,
	IOCTL_OSPI_MUX_SELECT = 21,
	/* IOCTL for USB power request */
	IOCTL_USB_SET_STATE = 22,
	/* IOCTL to get last reset reason */
	IOCTL_GET_LAST_RESET_REASON = 23,
	/* AI engine NPI ISR clear */
	IOCTL_AIE_ISR_CLEAR = 24,
	/* Register SGI to ATF */
	IOCTL_REGISTER_SGI = 25,
	/* Runtime feature configuration */
	IOCTL_SET_FEATURE_CONFIG = 26,
	IOCTL_GET_FEATURE_CONFIG = 27,
};

Re: [PATCH 1/4] firmware: xilinx: Add OSPI Mux selection support

[Greg Kroah-Hartman]

On Fri, Sep 24, 2021 at 02:12:55PM +0200, Michal Simek wrote:
> 
> 
> On 9/24/21 1:36 PM, Greg Kroah-Hartman wrote:
> > On Fri, Sep 24, 2021 at 03:37:08PM +0530, Sai Krishna Potthuri wrote:
> >> Add OSPI Mux selection API support to select the AXI interface to OSPI.
> >>
> >> Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
> >> ---
> >>  drivers/firmware/xilinx/zynqmp.c     | 17 +++++++++++++++++
> >>  include/linux/firmware/xlnx-zynqmp.h | 12 ++++++++++++
> >>  2 files changed, 29 insertions(+)
> >>
> >> diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
> >> index 15b138326ecc..43c3b5a9eef7 100644
> >> --- a/drivers/firmware/xilinx/zynqmp.c
> >> +++ b/drivers/firmware/xilinx/zynqmp.c
> >> @@ -647,6 +647,23 @@ int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type)
> >>  }
> >>  EXPORT_SYMBOL_GPL(zynqmp_pm_sd_dll_reset);
> >>  
> >> +/**
> >> + * zynqmp_pm_ospi_mux_select() - OSPI Mux selection
> >> + *
> >> + * @dev_id:	Device Id of the OSPI device.
> >> + * @select:	OSPI Mux select value.
> >> + *
> >> + * This function select the OSPI Mux.
> >> + *
> >> + * Return:	Returns status, either success or error+reason
> >> + */
> >> +int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select)
> >> +{
> >> +	return zynqmp_pm_invoke_fn(PM_IOCTL, dev_id, IOCTL_OSPI_MUX_SELECT,
> >> +				   select, 0, NULL);
> >> +}
> >> +EXPORT_SYMBOL_GPL(zynqmp_pm_ospi_mux_select);
> >> +
> >>  /**
> >>   * zynqmp_pm_write_ggs() - PM API for writing global general storage (ggs)
> >>   * @index:	GGS register index
> >> diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
> >> index 9d1a5c175065..6979a79f553a 100644
> >> --- a/include/linux/firmware/xlnx-zynqmp.h
> >> +++ b/include/linux/firmware/xlnx-zynqmp.h
> >> @@ -119,6 +119,7 @@ enum pm_ioctl_id {
> >>  	IOCTL_READ_PGGS = 15,
> >>  	/* Set healthy bit value */
> >>  	IOCTL_SET_BOOT_HEALTH_STATUS = 17,
> >> +	IOCTL_OSPI_MUX_SELECT = 21,
> > 
> > Why the gap?  What are the commands in the middle for?
> 
> Below is the full list. Not everything has been upstream yet. There was
> an attempt on AFI which one colleague is working on and should send new
> version soon. I don't think anybody has started with upstreaming probe
> counters.
> Every part has different owner with unfortunately own upstreaming plan.
> 
> Thanks,
> Michal
> 
> enum pm_ioctl_id {
> 	IOCTL_GET_RPU_OPER_MODE = 0,
> 	IOCTL_SET_RPU_OPER_MODE = 1,
> 	IOCTL_RPU_BOOT_ADDR_CONFIG = 2,
> 	IOCTL_TCM_COMB_CONFIG = 3,
> 	IOCTL_SET_TAPDELAY_BYPASS = 4,
> 	IOCTL_SET_SGMII_MODE = 5,
> 	IOCTL_SD_DLL_RESET = 6,
> 	IOCTL_SET_SD_TAPDELAY = 7,
> 	IOCTL_SET_PLL_FRAC_MODE = 8,
> 	IOCTL_GET_PLL_FRAC_MODE = 9,
> 	IOCTL_SET_PLL_FRAC_DATA = 10,
> 	IOCTL_GET_PLL_FRAC_DATA = 11,
> 	IOCTL_WRITE_GGS = 12,
> 	IOCTL_READ_GGS = 13,
> 	IOCTL_WRITE_PGGS = 14,
> 	IOCTL_READ_PGGS = 15,
> 	/* IOCTL for ULPI reset */
> 	IOCTL_ULPI_RESET = 16,
> 	/* Set healthy bit value */
> 	IOCTL_SET_BOOT_HEALTH_STATUS = 17,
> 	IOCTL_AFI = 18,
> 	/* Probe counter read/write */
> 	IOCTL_PROBE_COUNTER_READ = 19,
> 	IOCTL_PROBE_COUNTER_WRITE = 20,
> 	IOCTL_OSPI_MUX_SELECT = 21,
> 	/* IOCTL for USB power request */
> 	IOCTL_USB_SET_STATE = 22,
> 	/* IOCTL to get last reset reason */
> 	IOCTL_GET_LAST_RESET_REASON = 23,
> 	/* AI engine NPI ISR clear */
> 	IOCTL_AIE_ISR_CLEAR = 24,
> 	/* Register SGI to ATF */
> 	IOCTL_REGISTER_SGI = 25,
> 	/* Runtime feature configuration */
> 	IOCTL_SET_FEATURE_CONFIG = 26,
> 	IOCTL_GET_FEATURE_CONFIG = 27,
> };

Odd mix of comments and no comments...

Anyway, that's fine, just curious as to why there was a gap.  No real
reason why you can't just add them all now right?

thanks,

greg k-h

Re: [PATCH 1/4] firmware: xilinx: Add OSPI Mux selection support

[Michal Simek]

On 9/24/21 2:22 PM, Greg Kroah-Hartman wrote:
> On Fri, Sep 24, 2021 at 02:12:55PM +0200, Michal Simek wrote:
>>
>>
>> On 9/24/21 1:36 PM, Greg Kroah-Hartman wrote:
>>> On Fri, Sep 24, 2021 at 03:37:08PM +0530, Sai Krishna Potthuri wrote:
>>>> Add OSPI Mux selection API support to select the AXI interface to OSPI.
>>>>
>>>> Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
>>>> ---
>>>>  drivers/firmware/xilinx/zynqmp.c     | 17 +++++++++++++++++
>>>>  include/linux/firmware/xlnx-zynqmp.h | 12 ++++++++++++
>>>>  2 files changed, 29 insertions(+)
>>>>
>>>> diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
>>>> index 15b138326ecc..43c3b5a9eef7 100644
>>>> --- a/drivers/firmware/xilinx/zynqmp.c
>>>> +++ b/drivers/firmware/xilinx/zynqmp.c
>>>> @@ -647,6 +647,23 @@ int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type)
>>>>  }
>>>>  EXPORT_SYMBOL_GPL(zynqmp_pm_sd_dll_reset);
>>>>  
>>>> +/**
>>>> + * zynqmp_pm_ospi_mux_select() - OSPI Mux selection
>>>> + *
>>>> + * @dev_id:	Device Id of the OSPI device.
>>>> + * @select:	OSPI Mux select value.
>>>> + *
>>>> + * This function select the OSPI Mux.
>>>> + *
>>>> + * Return:	Returns status, either success or error+reason
>>>> + */
>>>> +int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select)
>>>> +{
>>>> +	return zynqmp_pm_invoke_fn(PM_IOCTL, dev_id, IOCTL_OSPI_MUX_SELECT,
>>>> +				   select, 0, NULL);
>>>> +}
>>>> +EXPORT_SYMBOL_GPL(zynqmp_pm_ospi_mux_select);
>>>> +
>>>>  /**
>>>>   * zynqmp_pm_write_ggs() - PM API for writing global general storage (ggs)
>>>>   * @index:	GGS register index
>>>> diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
>>>> index 9d1a5c175065..6979a79f553a 100644
>>>> --- a/include/linux/firmware/xlnx-zynqmp.h
>>>> +++ b/include/linux/firmware/xlnx-zynqmp.h
>>>> @@ -119,6 +119,7 @@ enum pm_ioctl_id {
>>>>  	IOCTL_READ_PGGS = 15,
>>>>  	/* Set healthy bit value */
>>>>  	IOCTL_SET_BOOT_HEALTH_STATUS = 17,
>>>> +	IOCTL_OSPI_MUX_SELECT = 21,
>>>
>>> Why the gap?  What are the commands in the middle for?
>>
>> Below is the full list. Not everything has been upstream yet. There was
>> an attempt on AFI which one colleague is working on and should send new
>> version soon. I don't think anybody has started with upstreaming probe
>> counters.
>> Every part has different owner with unfortunately own upstreaming plan.
>>
>> Thanks,
>> Michal
>>
>> enum pm_ioctl_id {
>> 	IOCTL_GET_RPU_OPER_MODE = 0,
>> 	IOCTL_SET_RPU_OPER_MODE = 1,
>> 	IOCTL_RPU_BOOT_ADDR_CONFIG = 2,
>> 	IOCTL_TCM_COMB_CONFIG = 3,
>> 	IOCTL_SET_TAPDELAY_BYPASS = 4,
>> 	IOCTL_SET_SGMII_MODE = 5,
>> 	IOCTL_SD_DLL_RESET = 6,
>> 	IOCTL_SET_SD_TAPDELAY = 7,
>> 	IOCTL_SET_PLL_FRAC_MODE = 8,
>> 	IOCTL_GET_PLL_FRAC_MODE = 9,
>> 	IOCTL_SET_PLL_FRAC_DATA = 10,
>> 	IOCTL_GET_PLL_FRAC_DATA = 11,
>> 	IOCTL_WRITE_GGS = 12,
>> 	IOCTL_READ_GGS = 13,
>> 	IOCTL_WRITE_PGGS = 14,
>> 	IOCTL_READ_PGGS = 15,
>> 	/* IOCTL for ULPI reset */
>> 	IOCTL_ULPI_RESET = 16,
>> 	/* Set healthy bit value */
>> 	IOCTL_SET_BOOT_HEALTH_STATUS = 17,
>> 	IOCTL_AFI = 18,
>> 	/* Probe counter read/write */
>> 	IOCTL_PROBE_COUNTER_READ = 19,
>> 	IOCTL_PROBE_COUNTER_WRITE = 20,
>> 	IOCTL_OSPI_MUX_SELECT = 21,
>> 	/* IOCTL for USB power request */
>> 	IOCTL_USB_SET_STATE = 22,
>> 	/* IOCTL to get last reset reason */
>> 	IOCTL_GET_LAST_RESET_REASON = 23,
>> 	/* AI engine NPI ISR clear */
>> 	IOCTL_AIE_ISR_CLEAR = 24,
>> 	/* Register SGI to ATF */
>> 	IOCTL_REGISTER_SGI = 25,
>> 	/* Runtime feature configuration */
>> 	IOCTL_SET_FEATURE_CONFIG = 26,
>> 	IOCTL_GET_FEATURE_CONFIG = 27,
>> };
> 
> Odd mix of comments and no comments...
> 
> Anyway, that's fine, just curious as to why there was a gap.  No real
> reason why you can't just add them all now right?

Code is firstly integrated to soc tree and then upstream. I would love
to see this happen vise versa but still marketing wants to deliver
features first to customers. On the other hand customers care about
getting features on the first place and they are fine with not having
upstream solution first.
Back to your comment. It can also happen while upstreaming that some
numbers are simply not used because design is changed. That's why that
numbers can be skipped because it was just temporary solution or not
proper design.
It doesn't mean that these numbers can't be listed but on the other hand
why they should be listed if they shouldn't/can't be used.
That's why over time we are just adding number which are used by that
patchset.
I can't see any problem to send all of them if that's fine for you.

Thanks,
Michal

Re: [PATCH 1/4] firmware: xilinx: Add OSPI Mux selection support

[Greg Kroah-Hartman]

On Fri, Sep 24, 2021 at 02:49:09PM +0200, Michal Simek wrote:
> 
> 
> On 9/24/21 2:22 PM, Greg Kroah-Hartman wrote:
> > On Fri, Sep 24, 2021 at 02:12:55PM +0200, Michal Simek wrote:
> >>
> >>
> >> On 9/24/21 1:36 PM, Greg Kroah-Hartman wrote:
> >>> On Fri, Sep 24, 2021 at 03:37:08PM +0530, Sai Krishna Potthuri wrote:
> >>>> Add OSPI Mux selection API support to select the AXI interface to OSPI.
> >>>>
> >>>> Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
> >>>> ---
> >>>>  drivers/firmware/xilinx/zynqmp.c     | 17 +++++++++++++++++
> >>>>  include/linux/firmware/xlnx-zynqmp.h | 12 ++++++++++++
> >>>>  2 files changed, 29 insertions(+)
> >>>>
> >>>> diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
> >>>> index 15b138326ecc..43c3b5a9eef7 100644
> >>>> --- a/drivers/firmware/xilinx/zynqmp.c
> >>>> +++ b/drivers/firmware/xilinx/zynqmp.c
> >>>> @@ -647,6 +647,23 @@ int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type)
> >>>>  }
> >>>>  EXPORT_SYMBOL_GPL(zynqmp_pm_sd_dll_reset);
> >>>>  
> >>>> +/**
> >>>> + * zynqmp_pm_ospi_mux_select() - OSPI Mux selection
> >>>> + *
> >>>> + * @dev_id:	Device Id of the OSPI device.
> >>>> + * @select:	OSPI Mux select value.
> >>>> + *
> >>>> + * This function select the OSPI Mux.
> >>>> + *
> >>>> + * Return:	Returns status, either success or error+reason
> >>>> + */
> >>>> +int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select)
> >>>> +{
> >>>> +	return zynqmp_pm_invoke_fn(PM_IOCTL, dev_id, IOCTL_OSPI_MUX_SELECT,
> >>>> +				   select, 0, NULL);
> >>>> +}
> >>>> +EXPORT_SYMBOL_GPL(zynqmp_pm_ospi_mux_select);
> >>>> +
> >>>>  /**
> >>>>   * zynqmp_pm_write_ggs() - PM API for writing global general storage (ggs)
> >>>>   * @index:	GGS register index
> >>>> diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
> >>>> index 9d1a5c175065..6979a79f553a 100644
> >>>> --- a/include/linux/firmware/xlnx-zynqmp.h
> >>>> +++ b/include/linux/firmware/xlnx-zynqmp.h
> >>>> @@ -119,6 +119,7 @@ enum pm_ioctl_id {
> >>>>  	IOCTL_READ_PGGS = 15,
> >>>>  	/* Set healthy bit value */
> >>>>  	IOCTL_SET_BOOT_HEALTH_STATUS = 17,
> >>>> +	IOCTL_OSPI_MUX_SELECT = 21,
> >>>
> >>> Why the gap?  What are the commands in the middle for?
> >>
> >> Below is the full list. Not everything has been upstream yet. There was
> >> an attempt on AFI which one colleague is working on and should send new
> >> version soon. I don't think anybody has started with upstreaming probe
> >> counters.
> >> Every part has different owner with unfortunately own upstreaming plan.
> >>
> >> Thanks,
> >> Michal
> >>
> >> enum pm_ioctl_id {
> >> 	IOCTL_GET_RPU_OPER_MODE = 0,
> >> 	IOCTL_SET_RPU_OPER_MODE = 1,
> >> 	IOCTL_RPU_BOOT_ADDR_CONFIG = 2,
> >> 	IOCTL_TCM_COMB_CONFIG = 3,
> >> 	IOCTL_SET_TAPDELAY_BYPASS = 4,
> >> 	IOCTL_SET_SGMII_MODE = 5,
> >> 	IOCTL_SD_DLL_RESET = 6,
> >> 	IOCTL_SET_SD_TAPDELAY = 7,
> >> 	IOCTL_SET_PLL_FRAC_MODE = 8,
> >> 	IOCTL_GET_PLL_FRAC_MODE = 9,
> >> 	IOCTL_SET_PLL_FRAC_DATA = 10,
> >> 	IOCTL_GET_PLL_FRAC_DATA = 11,
> >> 	IOCTL_WRITE_GGS = 12,
> >> 	IOCTL_READ_GGS = 13,
> >> 	IOCTL_WRITE_PGGS = 14,
> >> 	IOCTL_READ_PGGS = 15,
> >> 	/* IOCTL for ULPI reset */
> >> 	IOCTL_ULPI_RESET = 16,
> >> 	/* Set healthy bit value */
> >> 	IOCTL_SET_BOOT_HEALTH_STATUS = 17,
> >> 	IOCTL_AFI = 18,
> >> 	/* Probe counter read/write */
> >> 	IOCTL_PROBE_COUNTER_READ = 19,
> >> 	IOCTL_PROBE_COUNTER_WRITE = 20,
> >> 	IOCTL_OSPI_MUX_SELECT = 21,
> >> 	/* IOCTL for USB power request */
> >> 	IOCTL_USB_SET_STATE = 22,
> >> 	/* IOCTL to get last reset reason */
> >> 	IOCTL_GET_LAST_RESET_REASON = 23,
> >> 	/* AI engine NPI ISR clear */
> >> 	IOCTL_AIE_ISR_CLEAR = 24,
> >> 	/* Register SGI to ATF */
> >> 	IOCTL_REGISTER_SGI = 25,
> >> 	/* Runtime feature configuration */
> >> 	IOCTL_SET_FEATURE_CONFIG = 26,
> >> 	IOCTL_GET_FEATURE_CONFIG = 27,
> >> };
> > 
> > Odd mix of comments and no comments...
> > 
> > Anyway, that's fine, just curious as to why there was a gap.  No real
> > reason why you can't just add them all now right?
> 
> Code is firstly integrated to soc tree and then upstream. I would love
> to see this happen vise versa but still marketing wants to deliver
> features first to customers. On the other hand customers care about
> getting features on the first place and they are fine with not having
> upstream solution first.
> Back to your comment. It can also happen while upstreaming that some
> numbers are simply not used because design is changed. That's why that
> numbers can be skipped because it was just temporary solution or not
> proper design.
> It doesn't mean that these numbers can't be listed but on the other hand
> why they should be listed if they shouldn't/can't be used.
> That's why over time we are just adding number which are used by that
> patchset.

Ok, that makes sense to keep this in sync with the newly added features,
that way you don't have the "temporary number" problem.

thanks,

greg k-h

[PATCH 2/4] dt-bindings: spi: cadence-quadspi: Add support for Xilinx Versal OSPI

[Sai Krishna Potthuri]

Add new compatible to support Cadence Octal SPI(OSPI) controller on
Xilinx Versal SoCs, also add power-domains property to the properties
list and marked as required for Xilinx Versal OSPI compatible.

Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
---
 .../devicetree/bindings/spi/cdns,qspi-nor.yaml       | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
index 0e7087cc8bf9..ca155abbda7a 100644
--- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
+++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
@@ -11,6 +11,14 @@ maintainers:
 
 allOf:
   - $ref: spi-controller.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: xlnx,versal-ospi-1.0
+    then:
+      required:
+        - power-domains
 
 properties:
   compatible:
@@ -20,6 +28,7 @@ properties:
               - ti,k2g-qspi
               - ti,am654-ospi
               - intel,lgm-qspi
+              - xlnx,versal-ospi-1.0
           - const: cdns,qspi-nor
       - const: cdns,qspi-nor
 
@@ -65,6 +74,9 @@ properties:
       data rather than the QSPI clock. Make sure that QSPI return clock
       is populated on the board before using this property.
 
+  power-domains:
+    maxItems: 1
+
   resets:
     maxItems: 2
 
-- 
2.17.1

Re: [PATCH 2/4] dt-bindings: spi: cadence-quadspi: Add support for Xilinx Versal OSPI

[Rob Herring]

On Fri, 24 Sep 2021 15:37:09 +0530, Sai Krishna Potthuri wrote:
> Add new compatible to support Cadence Octal SPI(OSPI) controller on
> Xilinx Versal SoCs, also add power-domains property to the properties
> list and marked as required for Xilinx Versal OSPI compatible.
> 
> Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
> ---
>  .../devicetree/bindings/spi/cdns,qspi-nor.yaml       | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 

Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.

Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.

Full log is available here: https://patchwork.ozlabs.org/patch/1532183


spi@ff705000: resets: [[6, 37]] is too short
	arch/arm/boot/dts/socfpga_arria5_socdk.dt.yaml
	arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dt.yaml
	arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dt.yaml
	arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dt.yaml
	arch/arm/boot/dts/socfpga_cyclone5_socdk.dt.yaml
	arch/arm/boot/dts/socfpga_cyclone5_sockit.dt.yaml
	arch/arm/boot/dts/socfpga_cyclone5_socrates.dt.yaml
	arch/arm/boot/dts/socfpga_cyclone5_sodia.dt.yaml
	arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dt.yaml
	arch/arm/boot/dts/socfpga_vt.dt.yaml

Re: [PATCH 2/4] dt-bindings: spi: cadence-quadspi: Add support for Xilinx Versal OSPI

[Rob Herring]

On Fri, 24 Sep 2021 15:37:09 +0530, Sai Krishna Potthuri wrote:
> Add new compatible to support Cadence Octal SPI(OSPI) controller on
> Xilinx Versal SoCs, also add power-domains property to the properties
> list and marked as required for Xilinx Versal OSPI compatible.
> 
> Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
> ---
>  .../devicetree/bindings/spi/cdns,qspi-nor.yaml       | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

[PATCH 3/4] spi: cadence-quadspi: Add OSPI support for Xilinx Versal SoC

[Sai Krishna Potthuri]

Add OSPI support for Xilinx Versal SoCs.
Disable the Direct Access Controller for Xilinx Versal OSPI.
On Xilinx Versal platform, AXI interface need to be selected as Linear
mode (driven from interconnect rather than external DMA) to use
Software triggered 'indirect' mode of operation. This will be achieved
by calling Xilinx firmware API.

Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
---
 drivers/spi/spi-cadence-quadspi.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 101cc71bffa7..32cba7830b58 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -13,6 +13,7 @@
 #include <linux/dmaengine.h>
 #include <linux/err.h>
 #include <linux/errno.h>
+#include <linux/firmware/xlnx-zynqmp.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/iopoll.h>
@@ -82,6 +83,7 @@ struct cqspi_st {
 	u32			wr_delay;
 	bool			use_direct_mode;
 	struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
+	u32			pd_dev_id;
 };
 
 struct cqspi_driver_platdata {
@@ -1299,6 +1301,7 @@ static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
 {
 	struct device *dev = &cqspi->pdev->dev;
 	struct device_node *np = dev->of_node;
+	u32 id[2];
 
 	cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
 
@@ -1323,6 +1326,10 @@ static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
 
 	cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
 
+	if (!of_property_read_u32_array(np, "power-domains", id,
+					ARRAY_SIZE(id)))
+		cqspi->pd_dev_id = id[1];
+
 	return 0;
 }
 
@@ -1548,6 +1555,15 @@ static int cqspi_probe(struct platform_device *pdev)
 			master->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL;
 		if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE))
 			cqspi->use_direct_mode = true;
+		if (of_device_is_compatible(pdev->dev.of_node,
+					    "xlnx,versal-ospi-1.0")) {
+			ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id,
+							PM_OSPI_MUX_SEL_LINEAR);
+			if (ret) {
+				dev_err(dev, "failed to select OSPI Mux.\n");
+				goto probe_reset_failed;
+			}
+		}
 	}
 
 	ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
@@ -1656,6 +1672,11 @@ static const struct cqspi_driver_platdata intel_lgm_qspi = {
 	.quirks = CQSPI_DISABLE_DAC_MODE,
 };
 
+static const struct cqspi_driver_platdata versal_ospi = {
+	.hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
+	.quirks = CQSPI_DISABLE_DAC_MODE,
+};
+
 static const struct of_device_id cqspi_dt_ids[] = {
 	{
 		.compatible = "cdns,qspi-nor",
@@ -1673,6 +1694,10 @@ static const struct of_device_id cqspi_dt_ids[] = {
 		.compatible = "intel,lgm-qspi",
 		.data = &intel_lgm_qspi,
 	},
+	{
+		.compatible = "xlnx,versal-ospi-1.0",
+		.data = (void *)&versal_ospi,
+	},
 	{ /* end of table */ }
 };
 
-- 
2.17.1

[PATCH 4/4] spi: cadence-quadspi: Add Xilinx Versal external DMA support

[Sai Krishna Potthuri]

Add support to read the data from the flash using external DMA.
Cadence Octal SPI Flash Controller has optional DMA peripheral interface
to communicate indirect mode of operations with external DMA.
Xilinx Versal OSPI has external DMA enabled, this will automatically
request the external DMA to fetch the data from SRAM. It supports only
reading the data from SRAM (DMA read) and doesn't support writing the
data to SRAM (DMA write).
Xilinx Versal OSPI read the data from the flash device using external DMA
and write the data to the flash device using software triggered
indirect mode.

Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
---
 drivers/spi/spi-cadence-quadspi.c | 207 ++++++++++++++++++++++++++++--
 1 file changed, 198 insertions(+), 9 deletions(-)

diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 32cba7830b58..5bdb1bae5c99 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -36,6 +36,7 @@
 /* Quirks */
 #define CQSPI_NEEDS_WR_DELAY		BIT(0)
 #define CQSPI_DISABLE_DAC_MODE		BIT(1)
+#define CQSPI_SUPPORT_EXTERNAL_DMA	BIT(2)
 
 /* Capabilities */
 #define CQSPI_SUPPORTS_OCTAL		BIT(0)
@@ -83,12 +84,16 @@ struct cqspi_st {
 	u32			wr_delay;
 	bool			use_direct_mode;
 	struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
+	bool			use_dma_read;
 	u32			pd_dev_id;
 };
 
 struct cqspi_driver_platdata {
 	u32 hwcaps_mask;
 	u8 quirks;
+	int (*indirect_read_dma)(struct cqspi_flash_pdata *f_pdata,
+				 u_char *rxbuf, loff_t from_addr, size_t n_rx);
+	u32 (*get_dma_status)(struct cqspi_st *cqspi);
 };
 
 /* Operation timeout value */
@@ -219,6 +224,8 @@ struct cqspi_driver_platdata {
 #define CQSPI_REG_INDIRECTWRSTARTADDR		0x78
 #define CQSPI_REG_INDIRECTWRBYTES		0x7C
 
+#define CQSPI_REG_INDTRIG_ADDRRANGE		0x80
+
 #define CQSPI_REG_CMDADDRESS			0x94
 #define CQSPI_REG_CMDREADDATALOWER		0xA0
 #define CQSPI_REG_CMDREADDATAUPPER		0xA4
@@ -233,6 +240,23 @@ struct cqspi_driver_platdata {
 #define CQSPI_REG_OP_EXT_WRITE_LSB		16
 #define CQSPI_REG_OP_EXT_STIG_LSB		0
 
+#define CQSPI_REG_VERSAL_DMA_SRC_ADDR		0x1000
+
+#define CQSPI_REG_VERSAL_DMA_DST_ADDR		0x1800
+#define CQSPI_REG_VERSAL_DMA_DST_SIZE		0x1804
+
+#define CQSPI_REG_VERSAL_DMA_DST_CTRL		0x180C
+
+#define CQSPI_REG_VERSAL_DMA_DST_I_STS		0x1814
+#define CQSPI_REG_VERSAL_DMA_DST_I_EN		0x1818
+#define CQSPI_REG_VERSAL_DMA_DST_I_DIS		0x181C
+#define CQSPI_REG_VERSAL_DMA_DST_DONE_MASK	BIT(1)
+
+#define CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB	0x1828
+
+#define CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL	0xF43FFA00
+#define CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL	0x6
+
 /* Interrupt status bits */
 #define CQSPI_REG_IRQ_MODE_ERR			BIT(0)
 #define CQSPI_REG_IRQ_UNDERFLOW			BIT(1)
@@ -252,6 +276,9 @@ struct cqspi_driver_platdata {
 					 CQSPI_REG_IRQ_UNDERFLOW)
 
 #define CQSPI_IRQ_STATUS_MASK		0x1FFFF
+#define CQSPI_DMA_UNALIGN		0x3
+
+#define CQSPI_REG_VERSAL_DMA_VAL		0x602
 
 static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr)
 {
@@ -277,10 +304,26 @@ static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
 	return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
 }
 
+static u32 cqspi_get_versal_dma_status(struct cqspi_st *cqspi)
+{
+	u32 dma_status;
+
+	dma_status = readl(cqspi->iobase +
+					   CQSPI_REG_VERSAL_DMA_DST_I_STS);
+	writel(dma_status, cqspi->iobase +
+		   CQSPI_REG_VERSAL_DMA_DST_I_STS);
+
+	return dma_status & CQSPI_REG_VERSAL_DMA_DST_DONE_MASK;
+}
+
 static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
 {
 	struct cqspi_st *cqspi = dev;
 	unsigned int irq_status;
+	struct device *device = &cqspi->pdev->dev;
+	const struct cqspi_driver_platdata *ddata;
+
+	ddata = of_device_get_match_data(device);
 
 	/* Read interrupt status */
 	irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
@@ -288,6 +331,13 @@ static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
 	/* Clear interrupt */
 	writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
 
+	if (cqspi->use_dma_read && ddata && ddata->get_dma_status) {
+		if (ddata->get_dma_status(cqspi)) {
+			complete(&cqspi->transfer_complete);
+			return IRQ_HANDLED;
+		}
+	}
+
 	irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
 
 	if (irq_status)
@@ -783,6 +833,131 @@ static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata,
 	return ret;
 }
 
+static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata,
+					  u_char *rxbuf, loff_t from_addr,
+					  size_t n_rx)
+{
+	struct cqspi_st *cqspi = f_pdata->cqspi;
+	struct device *dev = &cqspi->pdev->dev;
+	void __iomem *reg_base = cqspi->iobase;
+	u32 reg, bytes_to_dma;
+	loff_t addr = from_addr;
+	void *buf = rxbuf;
+	dma_addr_t dma_addr;
+	u8 bytes_rem;
+	int ret = 0;
+
+	bytes_rem = n_rx % 4;
+	bytes_to_dma = (n_rx - bytes_rem);
+
+	if (!bytes_to_dma)
+		goto nondmard;
+
+	ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_DMA);
+	if (ret)
+		return ret;
+
+	reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
+	reg |= CQSPI_REG_CONFIG_DMA_MASK;
+	writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
+
+	dma_addr = dma_map_single(dev, rxbuf, bytes_to_dma, DMA_FROM_DEVICE);
+	if (dma_mapping_error(dev, dma_addr)) {
+		dev_err(dev, "dma mapping failed\n");
+		return -ENOMEM;
+	}
+
+	writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
+	writel(bytes_to_dma, reg_base + CQSPI_REG_INDIRECTRDBYTES);
+	writel(CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL,
+	       reg_base + CQSPI_REG_INDTRIG_ADDRRANGE);
+
+	/* Clear all interrupts. */
+	writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
+
+	/* Enable DMA done interrupt */
+	writel(CQSPI_REG_VERSAL_DMA_DST_DONE_MASK,
+	       reg_base + CQSPI_REG_VERSAL_DMA_DST_I_EN);
+
+	/* Default DMA periph configuration */
+	writel(CQSPI_REG_VERSAL_DMA_VAL, reg_base + CQSPI_REG_DMA);
+
+	/* Configure DMA Dst address */
+	writel(lower_32_bits(dma_addr),
+	       reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR);
+	writel(upper_32_bits(dma_addr),
+	       reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB);
+
+	/* Configure DMA Src address */
+	writel(cqspi->trigger_address, reg_base +
+	       CQSPI_REG_VERSAL_DMA_SRC_ADDR);
+
+	/* Set DMA destination size */
+	writel(bytes_to_dma, reg_base + CQSPI_REG_VERSAL_DMA_DST_SIZE);
+
+	/* Set DMA destination control */
+	writel(CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL,
+	       reg_base + CQSPI_REG_VERSAL_DMA_DST_CTRL);
+
+	writel(CQSPI_REG_INDIRECTRD_START_MASK,
+	       reg_base + CQSPI_REG_INDIRECTRD);
+
+	reinit_completion(&cqspi->transfer_complete);
+
+	if (!wait_for_completion_timeout(&cqspi->transfer_complete,
+					 msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) {
+		ret = -ETIMEDOUT;
+		goto failrd;
+	}
+
+	/* Disable DMA interrupt */
+	writel(0x0, cqspi->iobase + CQSPI_REG_VERSAL_DMA_DST_I_DIS);
+
+	/* Clear indirect completion status */
+	writel(CQSPI_REG_INDIRECTRD_DONE_MASK,
+	       cqspi->iobase + CQSPI_REG_INDIRECTRD);
+	dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE);
+
+	reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
+	reg &= ~CQSPI_REG_CONFIG_DMA_MASK;
+	writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
+
+	ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id,
+					PM_OSPI_MUX_SEL_LINEAR);
+	if (ret)
+		return ret;
+
+nondmard:
+	if (bytes_rem) {
+		addr += bytes_to_dma;
+		buf += bytes_to_dma;
+		ret = cqspi_indirect_read_execute(f_pdata, buf, addr,
+						  bytes_rem);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+
+failrd:
+	/* Disable DMA interrupt */
+	writel(0x0, reg_base + CQSPI_REG_VERSAL_DMA_DST_I_DIS);
+
+	/* Cancel the indirect read */
+	writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
+	       reg_base + CQSPI_REG_INDIRECTRD);
+
+	dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_DEV_TO_MEM);
+
+	reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
+	reg &= ~CQSPI_REG_CONFIG_DMA_MASK;
+	writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
+
+	zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_LINEAR);
+
+	return ret;
+}
+
 static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata,
 			     const struct spi_mem_op *op)
 {
@@ -1182,11 +1357,15 @@ static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata,
 			  const struct spi_mem_op *op)
 {
 	struct cqspi_st *cqspi = f_pdata->cqspi;
+	struct device *dev = &cqspi->pdev->dev;
+	const struct cqspi_driver_platdata *ddata;
 	loff_t from = op->addr.val;
 	size_t len = op->data.nbytes;
 	u_char *buf = op->data.buf.in;
+	u64 dma_align = (u64)(uintptr_t)buf;
 	int ret;
 
+	ddata = of_device_get_match_data(dev);
 	ret = cqspi_set_protocol(f_pdata, op);
 	if (ret)
 		return ret;
@@ -1198,6 +1377,10 @@ static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata,
 	if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size))
 		return cqspi_direct_read_execute(f_pdata, buf, from, len);
 
+	if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma &&
+	    virt_addr_valid(buf) && ((dma_align & CQSPI_DMA_UNALIGN) == 0))
+		return ddata->indirect_read_dma(f_pdata, buf, from, len);
+
 	return cqspi_indirect_read_execute(f_pdata, buf, from, len);
 }
 
@@ -1366,6 +1549,13 @@ static void cqspi_controller_init(struct cqspi_st *cqspi)
 		writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
 	}
 
+	/* Enable DMA interface */
+	if (cqspi->use_dma_read) {
+		reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
+		reg |= CQSPI_REG_CONFIG_DMA_MASK;
+		writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
+	}
+
 	cqspi_controller_enable(cqspi, 1);
 }
 
@@ -1555,15 +1745,12 @@ static int cqspi_probe(struct platform_device *pdev)
 			master->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL;
 		if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE))
 			cqspi->use_direct_mode = true;
+		if (ddata->quirks & CQSPI_SUPPORT_EXTERNAL_DMA)
+			cqspi->use_dma_read = true;
+
 		if (of_device_is_compatible(pdev->dev.of_node,
-					    "xlnx,versal-ospi-1.0")) {
-			ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id,
-							PM_OSPI_MUX_SEL_LINEAR);
-			if (ret) {
-				dev_err(dev, "failed to select OSPI Mux.\n");
-				goto probe_reset_failed;
-			}
-		}
+					    "xlnx,versal-ospi-1.0"))
+			dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
 	}
 
 	ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
@@ -1674,7 +1861,9 @@ static const struct cqspi_driver_platdata intel_lgm_qspi = {
 
 static const struct cqspi_driver_platdata versal_ospi = {
 	.hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
-	.quirks = CQSPI_DISABLE_DAC_MODE,
+	.quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA,
+	.indirect_read_dma = cqspi_versal_indirect_read_dma,
+	.get_dma_status = cqspi_get_versal_dma_status,
 };
 
 static const struct of_device_id cqspi_dt_ids[] = {
-- 
2.17.1

Re: [PATCH 0/4] spi: cadence-quadspi: Add Xilinx Versal OSPI support

[Mark Brown]

On Fri, 24 Sep 2021 15:37:07 +0530, Sai Krishna Potthuri wrote:
> Add Octal SPI(OSPI) controller support for Xilinx Versal SoC.
> Update the binding to add Xilinx Versal compatible string, also add
> 'power-domains' property and made as required for Xilinx Versal SoCs.
> Add API in xilinx firmware for configuring OSPI Mux, which is
> required to change the interface to OSPI. Xilinx Versal SoC
> has external DMA support, so by using the OSPI MUX selection, interface
> to the OSPI will be selected (either DMA interface or AXI slave interface).
> Xilinx Versal OSPI external DMA:
> Xilinx Versal OSPI DMA module is integrated to the Cadence OSPI Controller
> with the DMA write channel. Cadence OSPI Controller which reads the data
> from the Flash and stores in its internal SRAM and Xilinx Versal OSPI DMA
> which reads the data from the SRAM in the Cadence OSPI Controller using
> the DMA SRC channel and then the DMA DST channel initiates a write DMA
> transfer into the destined address location.
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next

Thanks!

[1/4] firmware: xilinx: Add OSPI Mux selection support
      commit: 74e78adc6ccf6c3b53939788cf0c49f54db70731
[2/4] dt-bindings: spi: cadence-quadspi: Add support for Xilinx Versal OSPI
      commit: 8db76cfae1004f5476d9c35670f0a0f084c6b73f
[3/4] spi: cadence-quadspi: Add OSPI support for Xilinx Versal SoC
      commit: 09e393e3f13970f194f7ed9a93140a8601225b46
[4/4] spi: cadence-quadspi: Add Xilinx Versal external DMA support
      commit: 1a6f854f7daab100ff0a94d31f35a387b462b4d1

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark