* [PATCH v2 01/16] dt-bindings: misc: Convert Tegra MISC to json-schema
2021-11-19 14:38 [PATCH v2 00/16] dt-bindings: Convert Tegra DT bindings to json-schema Thierry Reding
@ 2021-11-19 14:38 ` Thierry Reding
2021-11-30 1:29 ` Rob Herring
2021-11-19 14:38 ` [PATCH v2 02/16] dt-bindings: mmc: tegra: Convert " Thierry Reding
` (15 subsequent siblings)
16 siblings, 1 reply; 42+ messages in thread
From: Thierry Reding @ 2021-11-19 14:38 UTC (permalink / raw)
To: Thierry Reding, Rob Herring; +Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Convert the device tree bindings for the MISC register block found on
NVIDIA Tegra SoCs from plain text to json-schema format.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
.../bindings/misc/nvidia,tegra186-misc.txt | 14 -----
.../bindings/misc/nvidia,tegra186-misc.yaml | 43 ++++++++++++++++
.../bindings/misc/nvidia,tegra20-apbmisc.txt | 17 -------
.../bindings/misc/nvidia,tegra20-apbmisc.yaml | 51 +++++++++++++++++++
4 files changed, 94 insertions(+), 31 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt
create mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml
delete mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt
create mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.yaml
diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt
deleted file mode 100644
index 43d777ed8316..000000000000
--- a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-NVIDIA Tegra186 (and later) MISC register block
-
-The MISC register block found on Tegra186 and later SoCs contains registers
-that can be used to identify a given chip and various strapping options.
-
-Required properties:
-- compatible: Must be:
- - Tegra186: "nvidia,tegra186-misc"
- - Tegra194: "nvidia,tegra194-misc"
- - Tegra234: "nvidia,tegra234-misc"
-- reg: Should contain 2 entries: The first entry gives the physical address
- and length of the register region which contains revision and debug
- features. The second entry specifies the physical address and length
- of the register region indicating the strapping options.
diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml
new file mode 100644
index 000000000000..cacb845868f4
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/nvidia,tegra186-misc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra186 (and later) MISC register block
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+
+description: The MISC register block found on Tegra186 and later SoCs contains
+ registers that can be used to identify a given chip and various strapping
+ options.
+
+properties:
+ compatible:
+ enum:
+ - nvidia,tegra186-misc
+ - nvidia,tegra194-misc
+ - nvidia,tegra234-misc
+
+ reg:
+ items:
+ - description: physical address and length of the registers which
+ contain revision and debug features
+ - description: physical address and length of the registers which
+ indicate strapping options
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ misc@100000 {
+ compatible = "nvidia,tegra186-misc";
+ reg = <0x00100000 0xf000>,
+ <0x0010f000 0x1000>;
+ };
diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt
deleted file mode 100644
index 83f6a251ba3e..000000000000
--- a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-NVIDIA Tegra APBMISC block
-
-Required properties:
-- compatible: Must be:
- - Tegra20: "nvidia,tegra20-apbmisc"
- - Tegra30: "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"
- - Tegra114: "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc"
- - Tegra124: "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"
- - Tegra132: "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"
- - Tegra210: "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"
-- reg: Should contain 2 entries: the first entry gives the physical address
- and length of the registers which contain revision and debug features.
- The second entry gives the physical address and length of the
- registers indicating the strapping options.
-
-Optional properties:
-- nvidia,long-ram-code: If present, the RAM code is long (4 bit). If not, short (2 bit).
diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.yaml
new file mode 100644
index 000000000000..6f504fa74007
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/nvidia,tegra20-apbmisc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra APBMISC block
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - nvidia,tegra210-apbmisc
+ - nvidia,tegra124-apbmisc
+ - nvidia,tegra114-apbmisc
+ - nvidia,tegra30-apbmisc
+ - const: nvidia,tegra20-apbmisc
+
+ - items:
+ - const: nvidia,tegra20-apbmisc
+
+ reg:
+ items:
+ - description: physical address and length of the registers which
+ contain revision and debug features
+ - description: physical address and length of the registers which
+ indicate strapping options
+
+ nvidia,long-ram-code:
+ description: If present, the RAM code is long (4 bit). If not, short
+ (2 bit).
+ type: boolean
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ apbmisc@70000800 {
+ compatible = "nvidia,tegra20-apbmisc";
+ reg = <0x70000800 0x64>, /* Chip revision */
+ <0x70000008 0x04>; /* Strapping options */
+ };
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH v2 01/16] dt-bindings: misc: Convert Tegra MISC to json-schema
2021-11-19 14:38 ` [PATCH v2 01/16] dt-bindings: misc: Convert Tegra MISC " Thierry Reding
@ 2021-11-30 1:29 ` Rob Herring
0 siblings, 0 replies; 42+ messages in thread
From: Rob Herring @ 2021-11-30 1:29 UTC (permalink / raw)
To: Thierry Reding; +Cc: linux-tegra, Jon Hunter, devicetree, Rob Herring
On Fri, 19 Nov 2021 15:38:24 +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Convert the device tree bindings for the MISC register block found on
> NVIDIA Tegra SoCs from plain text to json-schema format.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> .../bindings/misc/nvidia,tegra186-misc.txt | 14 -----
> .../bindings/misc/nvidia,tegra186-misc.yaml | 43 ++++++++++++++++
> .../bindings/misc/nvidia,tegra20-apbmisc.txt | 17 -------
> .../bindings/misc/nvidia,tegra20-apbmisc.yaml | 51 +++++++++++++++++++
> 4 files changed, 94 insertions(+), 31 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt
> create mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml
> delete mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt
> create mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v2 02/16] dt-bindings: mmc: tegra: Convert to json-schema
2021-11-19 14:38 [PATCH v2 00/16] dt-bindings: Convert Tegra DT bindings to json-schema Thierry Reding
2021-11-19 14:38 ` [PATCH v2 01/16] dt-bindings: misc: Convert Tegra MISC " Thierry Reding
@ 2021-11-19 14:38 ` Thierry Reding
2021-11-30 1:31 ` Rob Herring
2021-11-19 14:38 ` [PATCH v2 03/16] dt-bindings: mailbox: " Thierry Reding
` (14 subsequent siblings)
16 siblings, 1 reply; 42+ messages in thread
From: Thierry Reding @ 2021-11-19 14:38 UTC (permalink / raw)
To: Thierry Reding, Rob Herring; +Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Convert the NVIDIA Tegra SDHCI bindings from the free-form text format
to json-schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v2:
- drop redundant $ref properties, add missing maxItems
.../bindings/mmc/nvidia,tegra20-sdhci.txt | 143 ---------
.../bindings/mmc/nvidia,tegra20-sdhci.yaml | 294 ++++++++++++++++++
2 files changed, 294 insertions(+), 143 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
create mode 100644 Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
deleted file mode 100644
index 96c0b1440c9c..000000000000
--- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
+++ /dev/null
@@ -1,143 +0,0 @@
-* NVIDIA Tegra Secure Digital Host Controller
-
-This controller on Tegra family SoCs provides an interface for MMC, SD,
-and SDIO types of memory cards.
-
-This file documents differences between the core properties described
-by mmc.txt and the properties used by the sdhci-tegra driver.
-
-Required properties:
-- compatible : should be one of:
- - "nvidia,tegra20-sdhci": for Tegra20
- - "nvidia,tegra30-sdhci": for Tegra30
- - "nvidia,tegra114-sdhci": for Tegra114
- - "nvidia,tegra124-sdhci": for Tegra124 and Tegra132
- - "nvidia,tegra210-sdhci": for Tegra210
- - "nvidia,tegra186-sdhci": for Tegra186
- - "nvidia,tegra194-sdhci": for Tegra194
-- clocks: For Tegra210, Tegra186 and Tegra194 must contain two entries.
- One for the module clock and one for the timeout clock.
- For all other Tegra devices, must contain a single entry for
- the module clock. See ../clocks/clock-bindings.txt for details.
-- clock-names: For Tegra210, Tegra186 and Tegra194 must contain the
- strings 'sdhci' and 'tmclk' to represent the module and
- the timeout clocks, respectively.
- For all other Tegra devices must contain the string 'sdhci'
- to represent the module clock.
-- resets : Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
-- reset-names : Must include the following entries:
- - sdhci
-
-Optional properties:
-- power-gpios : Specify GPIOs for power control
-
-Example:
-
-sdhci@c8000200 {
- compatible = "nvidia,tegra20-sdhci";
- reg = <0xc8000200 0x200>;
- interrupts = <47>;
- clocks = <&tegra_car 14>;
- resets = <&tegra_car 14>;
- reset-names = "sdhci";
- cd-gpios = <&gpio 69 0>; /* gpio PI5 */
- wp-gpios = <&gpio 57 0>; /* gpio PH1 */
- power-gpios = <&gpio 155 0>; /* gpio PT3 */
- bus-width = <8>;
-};
-
-Optional properties for Tegra210, Tegra186 and Tegra194:
-- pinctrl-names, pinctrl-0, pinctrl-1 : Specify pad voltage
- configurations. Valid pinctrl-names are "sdmmc-3v3" and "sdmmc-1v8"
- for controllers supporting multiple voltage levels. The order of names
- should correspond to the pin configuration states in pinctrl-0 and
- pinctrl-1.
-- pinctrl-names : "sdmmc-3v3-drv" and "sdmmc-1v8-drv" are applicable for
- Tegra210 where pad config registers are in the pinmux register domain
- for pull-up-strength and pull-down-strength values configuration when
- using pads at 3V3 and 1V8 levels.
-- nvidia,only-1-8-v : The presence of this property indicates that the
- controller operates at a 1.8 V fixed I/O voltage.
-- nvidia,pad-autocal-pull-up-offset-3v3,
- nvidia,pad-autocal-pull-down-offset-3v3 : Specify drive strength
- calibration offsets for 3.3 V signaling modes.
-- nvidia,pad-autocal-pull-up-offset-1v8,
- nvidia,pad-autocal-pull-down-offset-1v8 : Specify drive strength
- calibration offsets for 1.8 V signaling modes.
-- nvidia,pad-autocal-pull-up-offset-3v3-timeout,
- nvidia,pad-autocal-pull-down-offset-3v3-timeout : Specify drive
- strength used as a fallback in case the automatic calibration times
- out on a 3.3 V signaling mode.
-- nvidia,pad-autocal-pull-up-offset-1v8-timeout,
- nvidia,pad-autocal-pull-down-offset-1v8-timeout : Specify drive
- strength used as a fallback in case the automatic calibration times
- out on a 1.8 V signaling mode.
-- nvidia,pad-autocal-pull-up-offset-sdr104,
- nvidia,pad-autocal-pull-down-offset-sdr104 : Specify drive strength
- calibration offsets for SDR104 mode.
-- nvidia,pad-autocal-pull-up-offset-hs400,
- nvidia,pad-autocal-pull-down-offset-hs400 : Specify drive strength
- calibration offsets for HS400 mode.
-- nvidia,default-tap : Specify the default inbound sampling clock
- trimmer value for non-tunable modes.
-- nvidia,default-trim : Specify the default outbound clock trimmer
- value.
-- nvidia,dqs-trim : Specify DQS trim value for HS400 timing
-
- Notes on the pad calibration pull up and pulldown offset values:
- - The property values are drive codes which are programmed into the
- PD_OFFSET and PU_OFFSET sections of the
- SDHCI_TEGRA_AUTO_CAL_CONFIG register.
- - A higher value corresponds to higher drive strength. Please refer
- to the reference manual of the SoC for correct values.
- - The SDR104 and HS400 timing specific values are used in
- corresponding modes if specified.
-
- Notes on tap and trim values:
- - The values are used for compensating trace length differences
- by adjusting the sampling point.
- - The values are programmed to the Vendor Clock Control Register.
- Please refer to the reference manual of the SoC for correct
- values.
- - The DQS trim values are only used on controllers which support
- HS400 timing. Only SDMMC4 on Tegra210 and Tegra 186 supports
- HS400.
-
-Example:
-sdhci@700b0000 {
- compatible = "nvidia,tegra124-sdhci";
- reg = <0x0 0x700b0000 0x0 0x200>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
- clock-names = "sdhci";
- resets = <&tegra_car 14>;
- reset-names = "sdhci";
- pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
- pinctrl-0 = <&sdmmc1_3v3>;
- pinctrl-1 = <&sdmmc1_1v8>;
- nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
- nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
- nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
- nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
- status = "disabled";
-};
-
-sdhci@700b0000 {
- compatible = "nvidia,tegra210-sdhci";
- reg = <0x0 0x700b0000 0x0 0x200>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
- <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
- clock-names = "sdhci", "tmclk";
- resets = <&tegra_car 14>;
- reset-names = "sdhci";
- pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
- pinctrl-0 = <&sdmmc1_3v3>;
- pinctrl-1 = <&sdmmc1_1v8>;
- nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
- nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
- nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
- nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
- status = "disabled";
-};
diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
new file mode 100644
index 000000000000..1c3b9bbea6b4
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
@@ -0,0 +1,294 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/nvidia,tegra20-sdhci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Secure Digital Host Controller
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+
+description: |
+ This controller on Tegra family SoCs provides an interface for MMC, SD, and
+ SDIO types of memory cards.
+
+ This file documents differences between the core properties described by
+ mmc-controller.yaml and the properties for the Tegra SDHCI controller.
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - nvidia,tegra20-sdhci
+ - nvidia,tegra30-sdhci
+ - nvidia,tegra114-sdhci
+ - nvidia,tegra124-sdhci
+ - nvidia,tegra210-sdhci
+ - nvidia,tegra186-sdhci
+ - nvidia,tegra194-sdhci
+
+ - items:
+ - const: nvidia,tegra132-sdhci
+ - const: nvidia,tegra124-sdhci
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ assigned-clocks: true
+ assigned-clock-parents: true
+ assigned-clock-rates: true
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ minItems: 1
+ maxItems: 2
+
+ resets:
+ items:
+ - description: module reset
+
+ reset-names:
+ items:
+ - const: sdhci
+
+ power-gpios:
+ description: specify GPIOs for power control
+ maxItems: 1
+
+ iommus:
+ maxItems: 1
+
+ nvidia,default-tap:
+ description: Specify the default inbound sampling clock trimmer value for
+ non-tunable modes.
+
+ The values are used for compensating trace length differences by
+ adjusting the sampling point. The values are programmed to the Vendor
+ Clock Control Register. Please refer to the reference manual of the SoC
+ for correct values.
+
+ The DQS trim values are only used on controllers which support HS400
+ timing. Only SDMMC4 on Tegra210 and Tegra186 supports HS400.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+
+ nvidia,default-trim:
+ description: Specify the default outbound clock trimmer value.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+
+ nvidia,dqs-trim:
+ description: Specify DQS trim value for HS400 timing.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+
+ nvidia,pad-autocal-pull-down-offset-1v8:
+ description: Specify drive strength calibration offsets for 1.8 V
+ signaling modes.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+
+ nvidia,pad-autocal-pull-down-offset-1v8-timeout:
+ description: Specify drive strength used as a fallback in case the
+ automatic calibration times out on a 1.8 V signaling mode.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+
+ nvidia,pad-autocal-pull-down-offset-3v3:
+ description: Specify drive strength calibration offsets for 3.3 V
+ signaling modes.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+
+ nvidia,pad-autocal-pull-down-offset-3v3-timeout:
+ description: Specify drive strength used as a fallback in case the
+ automatic calibration times out on a 3.3 V signaling mode.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+
+ nvidia,pad-autocal-pull-down-offset-sdr104:
+ description: Specify drive strength calibration offsets for SDR104 mode.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+
+ nvidia,pad-autocal-pull-down-offset-hs400:
+ description: Specify drive strength calibration offsets for HS400 mode.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+
+ nvidia,pad-autocal-pull-up-offset-1v8:
+ description: Specify drive strength calibration offsets for 1.8 V
+ signaling modes.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+
+ nvidia,pad-autocal-pull-up-offset-1v8-timeout:
+ description: Specify drive strength used as a fallback in case the
+ automatic calibration times out on a 1.8 V signaling mode.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+
+ nvidia,pad-autocal-pull-up-offset-3v3:
+ description: Specify drive strength calibration offsets for 3.3 V
+ signaling modes.
+
+ The property values are drive codes which are programmed into the
+ PD_OFFSET and PU_OFFSET sections of the SDHCI_TEGRA_AUTO_CAL_CONFIG
+ register. A higher value corresponds to higher drive strength. Please
+ refer to the reference manual of the SoC for correct values. The SDR104
+ and HS400 timing specific values are used in corresponding modes if
+ specified.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+
+ nvidia,pad-autocal-pull-up-offset-3v3-timeout:
+ description: Specify drive strength used as a fallback in case the
+ automatic calibration times out on a 3.3 V signaling mode.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+
+ nvidia,pad-autocal-pull-up-offset-sdr104:
+ description: Specify drive strength calibration offsets for SDR104 mode.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+
+ nvidia,pad-autocal-pull-up-offset-hs400:
+ description: Specify drive strength calibration offsets for HS400 mode.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+
+ nvidia,only-1-8v:
+ description: The presence of this property indicates that the controller
+ operates at a 1.8 V fixed I/O voltage.
+ $ref: "/schemas/types.yaml#/definitions/flag"
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - resets
+ - reset-names
+
+allOf:
+ - $ref: "mmc-controller.yaml"
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nvidia,tegra20-sdhci
+ - nvidia,tegra30-sdhci
+ - nvidia,tegra114-sdhci
+ - nvidia,tegra124-sdhci
+ clocks:
+ items:
+ - description: module clock
+ minItems: 1
+ maxItems: 1
+ else:
+ properties:
+ clocks:
+ items:
+ - description: module clock
+ - description: timeout clock
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: sdhci
+ - const: tmclk
+ minItems: 2
+ maxItems: 2
+ required:
+ - clock-names
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: nvidia,tegra210-sdhci
+ then:
+ properties:
+ pinctrl-names:
+ oneOf:
+ - items:
+ - const: sdmmc-3v3
+ description: pad configuration for 3.3 V
+ - const: sdmmc-1v8
+ description: pad configuration for 1.8 V
+ - const: sdmmc-3v3-drv
+ description: pull-up/down configuration for 3.3 V
+ - const: sdmmc-1v8-drv
+ description: pull-up/down configuration for 1.8 V
+ - items:
+ - const: sdmmc-3v3-drv
+ description: pull-up/down configuration for 3.3 V
+ - const: sdmmc-1v8-drv
+ description: pull-up/down configuration for 1.8 V
+ - items:
+ - const: sdmmc-1v8-drv
+ description: pull-up/down configuration for 1.8 V
+ required:
+ - clock-names
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nvidia,tegra186-sdhci
+ - nvidia,tegra194-sdhci
+ then:
+ properties:
+ pinctrl-names:
+ items:
+ - const: sdmmc-3v3
+ description: pad configuration for 3.3 V
+ - const: sdmmc-1v8
+ description: pad configuration for 1.8 V
+ required:
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ mmc@c8000200 {
+ compatible = "nvidia,tegra20-sdhci";
+ reg = <0xc8000200 0x200>;
+ interrupts = <47>;
+ clocks = <&tegra_car 14>;
+ resets = <&tegra_car 14>;
+ reset-names = "sdhci";
+ cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+ wp-gpios = <&gpio 57 0>; /* gpio PH1 */
+ power-gpios = <&gpio 155 0>; /* gpio PT3 */
+ bus-width = <8>;
+ };
+
+ - |
+ #include <dt-bindings/clock/tegra210-car.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ mmc@700b0000 {
+ compatible = "nvidia,tegra210-sdhci";
+ reg = <0x700b0000 0x200>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
+ <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
+ clock-names = "sdhci", "tmclk";
+ resets = <&tegra_car 14>;
+ reset-names = "sdhci";
+ pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
+ "sdmmc-3v3-drv", "sdmmc-1v8-drv";
+ pinctrl-0 = <&sdmmc1_3v3>;
+ pinctrl-1 = <&sdmmc1_1v8>;
+ pinctrl-2 = <&sdmmc1_3v3_drv>;
+ pinctrl-3 = <&sdmmc1_1v8_drv>;
+ nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
+ nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
+ nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
+ nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
+ nvidia,default-tap = <0x2>;
+ nvidia,default-trim = <0x4>;
+ assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
+ <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
+ <&tegra_car TEGRA210_CLK_PLL_C4>;
+ assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
+ assigned-clock-rates = <200000000>, <1000000000>, <1000000000>;
+ };
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH v2 02/16] dt-bindings: mmc: tegra: Convert to json-schema
2021-11-19 14:38 ` [PATCH v2 02/16] dt-bindings: mmc: tegra: Convert " Thierry Reding
@ 2021-11-30 1:31 ` Rob Herring
0 siblings, 0 replies; 42+ messages in thread
From: Rob Herring @ 2021-11-30 1:31 UTC (permalink / raw)
To: Thierry Reding; +Cc: Rob Herring, devicetree, linux-tegra, Jon Hunter
On Fri, 19 Nov 2021 15:38:25 +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Convert the NVIDIA Tegra SDHCI bindings from the free-form text format
> to json-schema.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> Changes in v2:
> - drop redundant $ref properties, add missing maxItems
>
> .../bindings/mmc/nvidia,tegra20-sdhci.txt | 143 ---------
> .../bindings/mmc/nvidia,tegra20-sdhci.yaml | 294 ++++++++++++++++++
> 2 files changed, 294 insertions(+), 143 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> create mode 100644 Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v2 03/16] dt-bindings: mailbox: tegra: Convert to json-schema
2021-11-19 14:38 [PATCH v2 00/16] dt-bindings: Convert Tegra DT bindings to json-schema Thierry Reding
2021-11-19 14:38 ` [PATCH v2 01/16] dt-bindings: misc: Convert Tegra MISC " Thierry Reding
2021-11-19 14:38 ` [PATCH v2 02/16] dt-bindings: mmc: tegra: Convert " Thierry Reding
@ 2021-11-19 14:38 ` Thierry Reding
2021-11-30 1:32 ` Rob Herring
2021-11-19 14:38 ` [PATCH v2 04/16] dt-bindings: mailbox: tegra: Document Tegra234 HSP Thierry Reding
` (13 subsequent siblings)
16 siblings, 1 reply; 42+ messages in thread
From: Thierry Reding @ 2021-11-19 14:38 UTC (permalink / raw)
To: Thierry Reding, Rob Herring; +Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Convert the NVIDIA Tegra HSP bindings from the free-form text format to
json-schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v2:
- add missing additionalProperties: false
.../bindings/mailbox/nvidia,tegra186-hsp.txt | 72 ------------
.../bindings/mailbox/nvidia,tegra186-hsp.yaml | 111 ++++++++++++++++++
2 files changed, 111 insertions(+), 72 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt
create mode 100644 Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt
deleted file mode 100644
index ff3eafc5a882..000000000000
--- a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt
+++ /dev/null
@@ -1,72 +0,0 @@
-NVIDIA Tegra Hardware Synchronization Primitives (HSP)
-
-The HSP modules are used for the processors to share resources and communicate
-together. It provides a set of hardware synchronization primitives for
-interprocessor communication. So the interprocessor communication (IPC)
-protocols can use hardware synchronization primitives, when operating between
-two processors not in an SMP relationship.
-
-The features that HSP supported are shared mailboxes, shared semaphores,
-arbitrated semaphores and doorbells.
-
-Required properties:
-- name : Should be hsp
-- compatible
- Array of strings.
- one of:
- - "nvidia,tegra186-hsp"
- - "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"
-- reg : Offset and length of the register set for the device.
-- interrupt-names
- Array of strings.
- Contains a list of names for the interrupts described by the interrupt
- property. May contain the following entries, in any order:
- - "doorbell"
- - "sharedN", where 'N' is a number from zero up to the number of
- external interrupts supported by the HSP instance minus one.
- Users of this binding MUST look up entries in the interrupt property
- by name, using this interrupt-names property to do so.
-- interrupts
- Array of interrupt specifiers.
- Must contain one entry per entry in the interrupt-names property,
- in a matching order.
-- #mbox-cells : Should be 2.
-
-The mbox specifier of the "mboxes" property in the client node should contain
-two cells. The first cell determines the HSP type and the second cell is used
-to identify the mailbox that the client is going to use.
-
-For doorbells, the second cell specifies the index of the doorbell to use.
-
-For shared mailboxes, the second cell is composed of two fields:
-- bits 31..24:
- A bit mask of flags that further specify how the shared mailbox will be
- used. Valid flags are:
- - bit 31:
- Defines the direction of the mailbox. If set, the mailbox will be used
- as a producer (i.e. used to send data). If cleared, the mailbox is the
- consumer of data sent by a producer.
-
-- bits 23.. 0:
- The index of the shared mailbox to use. The number of available mailboxes
- may vary by instance of the HSP block and SoC generation.
-
-The following file contains definitions that can be used to construct mailbox
-specifiers:
-
- <dt-bindings/mailbox/tegra186-hsp.h>
-
-Example:
-
-hsp_top0: hsp@3c00000 {
- compatible = "nvidia,tegra186-hsp";
- reg = <0x0 0x03c00000 0x0 0xa0000>;
- interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "doorbell";
- #mbox-cells = <2>;
-};
-
-client {
- ...
- mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_XXX>;
-};
diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
new file mode 100644
index 000000000000..c43fc4c56f77
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
@@ -0,0 +1,111 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mailbox/nvidia,tegra186-hsp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Hardware Synchronization Primitives (HSP)
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+
+description: |
+ The HSP modules are used for the processors to share resources and
+ communicate together. It provides a set of hardware synchronization
+ primitives for interprocessor communication. So the interprocessor
+ communication (IPC) protocols can use hardware synchronization
+ primitives, when operating between two processors not in an SMP
+ relationship.
+
+ The features that HSP supported are shared mailboxes, shared
+ semaphores, arbitrated semaphores and doorbells.
+
+ The mbox specifier of the "mboxes" property in the client node should
+ contain two cells. The first cell determines the HSP type and the
+ second cell is used to identify the mailbox that the client is going
+ to use.
+
+ For doorbells, the second cell specifies the index of the doorbell to
+ use.
+
+ For shared mailboxes, the second cell is composed of two fields:
+ - bits 31..24:
+ A bit mask of flags that further specify how the shared mailbox
+ will be used. Valid flags are:
+ - bit 31:
+ Defines the direction of the mailbox. If set, the mailbox
+ will be used as a producer (i.e. used to send data). If
+ cleared, the mailbox is the consumer of data sent by a
+ producer.
+
+ - bits 23..0:
+ The index of the shared mailbox to use. The number of available
+ mailboxes may vary by instance of the HSP block and SoC
+ generation.
+
+ The following file contains definitions that can be used to
+ construct mailbox specifiers:
+
+ <dt-bindings/mailbox/tegra186-hsp.h>
+
+properties:
+ $nodename:
+ pattern: "^hsp@[0-9a-f]+$"
+
+ compatible:
+ oneOf:
+ - const: nvidia,tegra186-hsp
+ - const: nvidia,tegra194-hsp
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 1
+ maxItems: 9
+
+ interrupt-names:
+ oneOf:
+ # shared interrupts are optional
+ - items:
+ - const: doorbell
+
+ - items:
+ - const: doorbell
+ - pattern: "^shared[0-7]$"
+ - pattern: "^shared[0-7]$"
+ - pattern: "^shared[0-7]$"
+ - pattern: "^shared[0-7]$"
+ - pattern: "^shared[0-7]$"
+ - pattern: "^shared[0-7]$"
+ - pattern: "^shared[0-7]$"
+ - pattern: "^shared[0-7]$"
+
+ - items:
+ - pattern: "^shared[0-7]$"
+ - pattern: "^shared[0-7]$"
+ - pattern: "^shared[0-7]$"
+ - pattern: "^shared[0-7]$"
+
+ "#mbox-cells":
+ const: 2
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/mailbox/tegra186-hsp.h>
+
+ hsp_top0: hsp@3c00000 {
+ compatible = "nvidia,tegra186-hsp";
+ reg = <0x03c00000 0xa0000>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "doorbell";
+ #mbox-cells = <2>;
+ };
+
+ client {
+ mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_CCPLEX>;
+ };
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH v2 03/16] dt-bindings: mailbox: tegra: Convert to json-schema
2021-11-19 14:38 ` [PATCH v2 03/16] dt-bindings: mailbox: " Thierry Reding
@ 2021-11-30 1:32 ` Rob Herring
0 siblings, 0 replies; 42+ messages in thread
From: Rob Herring @ 2021-11-30 1:32 UTC (permalink / raw)
To: Thierry Reding; +Cc: devicetree, linux-tegra, Rob Herring, Jon Hunter
On Fri, 19 Nov 2021 15:38:26 +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Convert the NVIDIA Tegra HSP bindings from the free-form text format to
> json-schema.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> Changes in v2:
> - add missing additionalProperties: false
>
> .../bindings/mailbox/nvidia,tegra186-hsp.txt | 72 ------------
> .../bindings/mailbox/nvidia,tegra186-hsp.yaml | 111 ++++++++++++++++++
> 2 files changed, 111 insertions(+), 72 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt
> create mode 100644 Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v2 04/16] dt-bindings: mailbox: tegra: Document Tegra234 HSP
2021-11-19 14:38 [PATCH v2 00/16] dt-bindings: Convert Tegra DT bindings to json-schema Thierry Reding
` (2 preceding siblings ...)
2021-11-19 14:38 ` [PATCH v2 03/16] dt-bindings: mailbox: " Thierry Reding
@ 2021-11-19 14:38 ` Thierry Reding
2021-11-30 1:32 ` Rob Herring
2021-11-19 14:38 ` [PATCH v2 05/16] dt-bindings: rtc: tegra: Convert to json-schema Thierry Reding
` (12 subsequent siblings)
16 siblings, 1 reply; 42+ messages in thread
From: Thierry Reding @ 2021-11-19 14:38 UTC (permalink / raw)
To: Thierry Reding, Rob Herring; +Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Add the compatible string for the HSP block found on the Tegra234 SoC.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
.../devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
index c43fc4c56f77..9f7a7296b57f 100644
--- a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
+++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
@@ -57,6 +57,9 @@ properties:
oneOf:
- const: nvidia,tegra186-hsp
- const: nvidia,tegra194-hsp
+ - items:
+ - const: nvidia,tegra234-hsp
+ - const: nvidia,tegra194-hsp
reg:
maxItems: 1
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH v2 05/16] dt-bindings: rtc: tegra: Convert to json-schema
2021-11-19 14:38 [PATCH v2 00/16] dt-bindings: Convert Tegra DT bindings to json-schema Thierry Reding
` (3 preceding siblings ...)
2021-11-19 14:38 ` [PATCH v2 04/16] dt-bindings: mailbox: tegra: Document Tegra234 HSP Thierry Reding
@ 2021-11-19 14:38 ` Thierry Reding
2021-11-30 1:33 ` Rob Herring
2021-11-19 14:38 ` [PATCH v2 06/16] dt-bindings: rtc: tegra: Document Tegra234 RTC Thierry Reding
` (11 subsequent siblings)
16 siblings, 1 reply; 42+ messages in thread
From: Thierry Reding @ 2021-11-19 14:38 UTC (permalink / raw)
To: Thierry Reding, Rob Herring; +Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Convert the NVIDIA Tegra RTC bindings from the free-form text format to
json-schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v2:
- document clock-names property and add additionalProperties: false
.../bindings/rtc/nvidia,tegra20-rtc.txt | 24 --------
.../bindings/rtc/nvidia,tegra20-rtc.yaml | 60 +++++++++++++++++++
2 files changed, 60 insertions(+), 24 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
create mode 100644 Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml
diff --git a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
deleted file mode 100644
index b7d98ed3e098..000000000000
--- a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-NVIDIA Tegra20 real-time clock
-
-The Tegra RTC maintains seconds and milliseconds counters, and five alarm
-registers. The alarms and other interrupts may wake the system from low-power
-state.
-
-Required properties:
-
-- compatible : For Tegra20, must contain "nvidia,tegra20-rtc". Otherwise,
- must contain '"nvidia,<chip>-rtc", "nvidia,tegra20-rtc"', where <chip>
- can be tegra30, tegra114, tegra124, or tegra132.
-- reg : Specifies base physical address and size of the registers.
-- interrupts : A single interrupt specifier.
-- clocks : Must contain one entry, for the module clock.
- See ../clocks/clock-bindings.txt for details.
-
-Example:
-
-timer {
- compatible = "nvidia,tegra20-rtc";
- reg = <0x7000e000 0x100>;
- interrupts = <0 2 0x04>;
- clocks = <&tegra_car 4>;
-};
diff --git a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml
new file mode 100644
index 000000000000..94266de73cb9
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/nvidia,tegra20-rtc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra real-time clock
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+
+description: |
+ The Tegra RTC maintains seconds and milliseconds counters, and five
+ alarm registers. The alarms and other interrupts may wake the system
+ from low-power state.
+
+properties:
+ compatible:
+ oneOf:
+ - const: nvidia,tegra20-rtc
+ - items:
+ - enum:
+ - nvidia,tegra30-rtc
+ - nvidia,tegra114-rtc
+ - nvidia,tegra124-rtc
+ - nvidia,tegra210-rtc
+ - nvidia,tegra186-rtc
+ - nvidia,tegra194-rtc
+ - const: nvidia,tegra20-rtc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: rtc
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+examples:
+ - |
+ timer@7000e000 {
+ compatible = "nvidia,tegra20-rtc";
+ reg = <0x7000e000 0x100>;
+ interrupts = <0 2 0x04>;
+ clocks = <&tegra_car 4>;
+ };
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH v2 05/16] dt-bindings: rtc: tegra: Convert to json-schema
2021-11-19 14:38 ` [PATCH v2 05/16] dt-bindings: rtc: tegra: Convert to json-schema Thierry Reding
@ 2021-11-30 1:33 ` Rob Herring
0 siblings, 0 replies; 42+ messages in thread
From: Rob Herring @ 2021-11-30 1:33 UTC (permalink / raw)
To: Thierry Reding; +Cc: devicetree, Jon Hunter, Rob Herring, linux-tegra
On Fri, 19 Nov 2021 15:38:28 +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Convert the NVIDIA Tegra RTC bindings from the free-form text format to
> json-schema.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> Changes in v2:
> - document clock-names property and add additionalProperties: false
>
> .../bindings/rtc/nvidia,tegra20-rtc.txt | 24 --------
> .../bindings/rtc/nvidia,tegra20-rtc.yaml | 60 +++++++++++++++++++
> 2 files changed, 60 insertions(+), 24 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
> create mode 100644 Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v2 06/16] dt-bindings: rtc: tegra: Document Tegra234 RTC
2021-11-19 14:38 [PATCH v2 00/16] dt-bindings: Convert Tegra DT bindings to json-schema Thierry Reding
` (4 preceding siblings ...)
2021-11-19 14:38 ` [PATCH v2 05/16] dt-bindings: rtc: tegra: Convert to json-schema Thierry Reding
@ 2021-11-19 14:38 ` Thierry Reding
2021-11-30 1:33 ` Rob Herring
2021-11-19 14:38 ` [PATCH v2 07/16] dt-bindings: fuse: tegra: Convert to json-schema Thierry Reding
` (10 subsequent siblings)
16 siblings, 1 reply; 42+ messages in thread
From: Thierry Reding @ 2021-11-19 14:38 UTC (permalink / raw)
To: Thierry Reding, Rob Herring; +Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Add the compatible string for the RTC block found on the Tegra234 SoC.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml
index 94266de73cb9..17d6280e5515 100644
--- a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml
+++ b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml
@@ -27,6 +27,7 @@ properties:
- nvidia,tegra210-rtc
- nvidia,tegra186-rtc
- nvidia,tegra194-rtc
+ - nvidia,tegra234-rtc
- const: nvidia,tegra20-rtc
reg:
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH v2 07/16] dt-bindings: fuse: tegra: Convert to json-schema
2021-11-19 14:38 [PATCH v2 00/16] dt-bindings: Convert Tegra DT bindings to json-schema Thierry Reding
` (5 preceding siblings ...)
2021-11-19 14:38 ` [PATCH v2 06/16] dt-bindings: rtc: tegra: Document Tegra234 RTC Thierry Reding
@ 2021-11-19 14:38 ` Thierry Reding
2021-11-30 1:35 ` Rob Herring
2021-11-19 14:38 ` [PATCH v2 08/16] dt-bindings: fuse: tegra: Document Tegra234 FUSE Thierry Reding
` (9 subsequent siblings)
16 siblings, 1 reply; 42+ messages in thread
From: Thierry Reding @ 2021-11-19 14:38 UTC (permalink / raw)
To: Thierry Reding, Rob Herring; +Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Convert the NVIDIA Tegra FUSE bindings from the free-form text format to
json-schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v2:
- add missing additionalProperties: false
.../bindings/fuse/nvidia,tegra20-fuse.txt | 42 ----------
.../bindings/fuse/nvidia,tegra20-fuse.yaml | 81 +++++++++++++++++++
2 files changed, 81 insertions(+), 42 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt
create mode 100644 Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml
diff --git a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt
deleted file mode 100644
index b109911669e4..000000000000
--- a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block.
-
-Required properties:
-- compatible : For Tegra20, must contain "nvidia,tegra20-efuse". For Tegra30,
- must contain "nvidia,tegra30-efuse". For Tegra114, must contain
- "nvidia,tegra114-efuse". For Tegra124, must contain "nvidia,tegra124-efuse".
- For Tegra132 must contain "nvidia,tegra132-efuse", "nvidia,tegra124-efuse".
- For Tegra210 must contain "nvidia,tegra210-efuse". For Tegra186 must contain
- "nvidia,tegra186-efuse". For Tegra194 must contain "nvidia,tegra194-efuse".
- For Tegra234 must contain "nvidia,tegra234-efuse".
- Details:
- nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data
- due to a hardware bug. Tegra20 also lacks certain information which is
- available in later generations such as fab code, lot code, wafer id,..
- nvidia,tegra30-efuse, nvidia,tegra114-efuse and nvidia,tegra124-efuse:
- The differences between these SoCs are the size of the efuse array,
- the location of the spare (OEM programmable) bits and the location of
- the speedo data.
-- reg: Should contain 1 entry: the entry gives the physical address and length
- of the fuse registers.
-- clocks: Must contain an entry for each entry in clock-names.
- See ../clocks/clock-bindings.txt for details.
-- clock-names: Must include the following entries:
- - fuse
-- resets: Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
-- reset-names: Must include the following entries:
- - fuse
-
-Example:
-
- fuse@7000f800 {
- compatible = "nvidia,tegra20-efuse";
- reg = <0x7000f800 0x400>,
- <0x70000000 0x400>;
- clocks = <&tegra_car TEGRA20_CLK_FUSE>;
- clock-names = "fuse";
- resets = <&tegra_car 39>;
- reset-names = "fuse";
- };
-
-
diff --git a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml
new file mode 100644
index 000000000000..8d608e722ab2
--- /dev/null
+++ b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fuse/nvidia,tegra20-fuse.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra FUSE block
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - nvidia,tegra20-efuse
+ - nvidia,tegra30-efuse
+ - nvidia,tegra114-efuse
+ - nvidia,tegra124-efuse
+ - nvidia,tegra210-efuse
+ - nvidia,tegra186-efuse
+ - nvidia,tegra194-efuse
+
+ - items:
+ - const: nvidia,tegra132-efuse
+ - const: nvidia,tegra124-efuse
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: fuse
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: fuse
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nvidia,tegra20-efuse
+ - nvidia,tegra30-efuse
+ - nvidia,tegra114-efuse
+ - nvidia,tegra124-efuse
+ - nvidia,tegra132-efuse
+ - nvidia,tegra210-efuse
+then:
+ required:
+ - resets
+ - reset-names
+
+examples:
+ - |
+ #include <dt-bindings/clock/tegra20-car.h>
+
+ fuse@7000f800 {
+ compatible = "nvidia,tegra20-efuse";
+ reg = <0x7000f800 0x400>;
+ clocks = <&tegra_car TEGRA20_CLK_FUSE>;
+ clock-names = "fuse";
+ resets = <&tegra_car 39>;
+ reset-names = "fuse";
+ };
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH v2 07/16] dt-bindings: fuse: tegra: Convert to json-schema
2021-11-19 14:38 ` [PATCH v2 07/16] dt-bindings: fuse: tegra: Convert to json-schema Thierry Reding
@ 2021-11-30 1:35 ` Rob Herring
0 siblings, 0 replies; 42+ messages in thread
From: Rob Herring @ 2021-11-30 1:35 UTC (permalink / raw)
To: Thierry Reding; +Cc: Rob Herring, linux-tegra, devicetree, Jon Hunter
On Fri, 19 Nov 2021 15:38:30 +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Convert the NVIDIA Tegra FUSE bindings from the free-form text format to
> json-schema.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> Changes in v2:
> - add missing additionalProperties: false
>
> .../bindings/fuse/nvidia,tegra20-fuse.txt | 42 ----------
> .../bindings/fuse/nvidia,tegra20-fuse.yaml | 81 +++++++++++++++++++
> 2 files changed, 81 insertions(+), 42 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt
> create mode 100644 Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v2 08/16] dt-bindings: fuse: tegra: Document Tegra234 FUSE
2021-11-19 14:38 [PATCH v2 00/16] dt-bindings: Convert Tegra DT bindings to json-schema Thierry Reding
` (6 preceding siblings ...)
2021-11-19 14:38 ` [PATCH v2 07/16] dt-bindings: fuse: tegra: Convert to json-schema Thierry Reding
@ 2021-11-19 14:38 ` Thierry Reding
2021-11-30 1:35 ` Rob Herring
2021-11-19 14:38 ` [PATCH v2 09/16] dt-bindings: mmc: tegra: Document Tegra234 SDHCI Thierry Reding
` (8 subsequent siblings)
16 siblings, 1 reply; 42+ messages in thread
From: Thierry Reding @ 2021-11-19 14:38 UTC (permalink / raw)
To: Thierry Reding, Rob Herring; +Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Add the compatible string for the FUSE block found on the Tegra234 SoC.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml
index 8d608e722ab2..ce1056174778 100644
--- a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml
+++ b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml
@@ -21,6 +21,7 @@ properties:
- nvidia,tegra210-efuse
- nvidia,tegra186-efuse
- nvidia,tegra194-efuse
+ - nvidia,tegra234-efuse
- items:
- const: nvidia,tegra132-efuse
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH v2 09/16] dt-bindings: mmc: tegra: Document Tegra234 SDHCI
2021-11-19 14:38 [PATCH v2 00/16] dt-bindings: Convert Tegra DT bindings to json-schema Thierry Reding
` (7 preceding siblings ...)
2021-11-19 14:38 ` [PATCH v2 08/16] dt-bindings: fuse: tegra: Document Tegra234 FUSE Thierry Reding
@ 2021-11-19 14:38 ` Thierry Reding
2021-11-30 1:35 ` Rob Herring
2021-11-19 14:38 ` [PATCH v2 10/16] dt-bindings: serial: 8250: Document Tegra234 UART Thierry Reding
` (7 subsequent siblings)
16 siblings, 1 reply; 42+ messages in thread
From: Thierry Reding @ 2021-11-19 14:38 UTC (permalink / raw)
To: Thierry Reding, Rob Herring; +Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Add the compatible string for the SDHCI block found on the Tegra234 SoC.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
.../devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
index 1c3b9bbea6b4..a361896323d0 100644
--- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
+++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
@@ -33,6 +33,12 @@ properties:
- const: nvidia,tegra132-sdhci
- const: nvidia,tegra124-sdhci
+ - items:
+ - enum:
+ - nvidia,tegra194-sdhci
+ - nvidia,tegra234-sdhci
+ - const: nvidia,tegra186-sdhci
+
reg:
maxItems: 1
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH v2 10/16] dt-bindings: serial: 8250: Document Tegra234 UART
2021-11-19 14:38 [PATCH v2 00/16] dt-bindings: Convert Tegra DT bindings to json-schema Thierry Reding
` (8 preceding siblings ...)
2021-11-19 14:38 ` [PATCH v2 09/16] dt-bindings: mmc: tegra: Document Tegra234 SDHCI Thierry Reding
@ 2021-11-19 14:38 ` Thierry Reding
2021-11-30 1:36 ` Rob Herring
2021-11-19 14:38 ` [PATCH v2 11/16] dt-bindings: tegra: pmc: Convert to json-schema Thierry Reding
` (6 subsequent siblings)
16 siblings, 1 reply; 42+ messages in thread
From: Thierry Reding @ 2021-11-19 14:38 UTC (permalink / raw)
To: Thierry Reding, Rob Herring; +Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Add the compatible string for the UART found on the Tegra234 SoC.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Documentation/devicetree/bindings/serial/8250.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml
index fa767440f281..3bab2f27b970 100644
--- a/Documentation/devicetree/bindings/serial/8250.yaml
+++ b/Documentation/devicetree/bindings/serial/8250.yaml
@@ -113,9 +113,10 @@ properties:
- nvidia,tegra30-uart
- nvidia,tegra114-uart
- nvidia,tegra124-uart
+ - nvidia,tegra210-uart
- nvidia,tegra186-uart
- nvidia,tegra194-uart
- - nvidia,tegra210-uart
+ - nvidia,tegra234-uart
- const: nvidia,tegra20-uart
reg:
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH v2 11/16] dt-bindings: tegra: pmc: Convert to json-schema
2021-11-19 14:38 [PATCH v2 00/16] dt-bindings: Convert Tegra DT bindings to json-schema Thierry Reding
` (9 preceding siblings ...)
2021-11-19 14:38 ` [PATCH v2 10/16] dt-bindings: serial: 8250: Document Tegra234 UART Thierry Reding
@ 2021-11-19 14:38 ` Thierry Reding
2021-11-30 1:41 ` Rob Herring
2021-11-19 14:38 ` [PATCH v2 12/16] dt-bindings: firmware: tegra: " Thierry Reding
` (5 subsequent siblings)
16 siblings, 1 reply; 42+ messages in thread
From: Thierry Reding @ 2021-11-19 14:38 UTC (permalink / raw)
To: Thierry Reding, Rob Herring; +Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Convert the NVIDIA Tegra186 (and later) PMC bindings from the free-form
text format to json-schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
.../arm/tegra/nvidia,tegra186-pmc.txt | 133 ------------
.../arm/tegra/nvidia,tegra186-pmc.yaml | 199 ++++++++++++++++++
2 files changed, 199 insertions(+), 133 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt
create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt
deleted file mode 100644
index 576462fae27f..000000000000
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt
+++ /dev/null
@@ -1,133 +0,0 @@
-NVIDIA Tegra Power Management Controller (PMC)
-
-Required properties:
-- compatible: Should contain one of the following:
- - "nvidia,tegra186-pmc": for Tegra186
- - "nvidia,tegra194-pmc": for Tegra194
- - "nvidia,tegra234-pmc": for Tegra234
-- reg: Must contain an (offset, length) pair of the register set for each
- entry in reg-names.
-- reg-names: Must include the following entries:
- - "pmc"
- - "wake"
- - "aotag"
- - "scratch"
- - "misc" (Only for Tegra194 and later)
-
-Optional properties:
-- nvidia,invert-interrupt: If present, inverts the PMU interrupt signal.
-- interrupt-controller: Identifies the node as an interrupt controller.
-- #interrupt-cells: Specifies the number of cells needed to encode an
- interrupt source. The value must be 2.
-
-Example:
-
-SoC DTSI:
-
- pmc@c3600000 {
- compatible = "nvidia,tegra186-pmc";
- reg = <0 0x0c360000 0 0x10000>,
- <0 0x0c370000 0 0x10000>,
- <0 0x0c380000 0 0x10000>,
- <0 0x0c390000 0 0x10000>;
- reg-names = "pmc", "wake", "aotag", "scratch";
- };
-
-Board DTS:
-
- pmc@c360000 {
- nvidia,invert-interrupt;
- };
-
-== Pad Control ==
-
-On Tegra SoCs a pad is a set of pins which are configured as a group.
-The pin grouping is a fixed attribute of the hardware. The PMC can be
-used to set pad power state and signaling voltage. A pad can be either
-in active or power down mode. The support for power state and signaling
-voltage configuration varies depending on the pad in question. 3.3 V and
-1.8 V signaling voltages are supported on pins where software
-controllable signaling voltage switching is available.
-
-Pad configurations are described with pin configuration nodes which
-are placed under the pmc node and they are referred to by the pinctrl
-client properties. For more information see
-Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
-
-The following pads are present on Tegra186:
-csia csib dsi mipi-bias
-pex-clk-bias pex-clk3 pex-clk2 pex-clk1
-usb0 usb1 usb2 usb-bias
-uart audio hsic dbg
-hdmi-dp0 hdmi-dp1 pex-cntrl sdmmc2-hv
-sdmmc4 cam dsib dsic
-dsid csic csid csie
-dsif spi ufs dmic-hv
-edp sdmmc1-hv sdmmc3-hv conn
-audio-hv ao-hv
-
-Required pin configuration properties:
- - pins: A list of strings, each of which contains the name of a pad
- to be configured.
-
-Optional pin configuration properties:
- - low-power-enable: Configure the pad into power down mode
- - low-power-disable: Configure the pad into active mode
- - power-source: Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
- TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
- The values are defined in
- include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
-
-Note: The power state can be configured on all of the above pads except
- for ao-hv. Following pads have software configurable signaling
- voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv, audio-hv,
- ao-hv.
-
-Pad configuration state example:
- pmc: pmc@7000e400 {
- compatible = "nvidia,tegra186-pmc";
- reg = <0 0x0c360000 0 0x10000>,
- <0 0x0c370000 0 0x10000>,
- <0 0x0c380000 0 0x10000>,
- <0 0x0c390000 0 0x10000>;
- reg-names = "pmc", "wake", "aotag", "scratch";
-
- ...
-
- sdmmc1_3v3: sdmmc1-3v3 {
- pins = "sdmmc1-hv";
- power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
- };
-
- sdmmc1_1v8: sdmmc1-1v8 {
- pins = "sdmmc1-hv";
- power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
- };
-
- hdmi_off: hdmi-off {
- pins = "hdmi";
- low-power-enable;
- }
-
- hdmi_on: hdmi-on {
- pins = "hdmi";
- low-power-disable;
- }
- };
-
-Pinctrl client example:
- sdmmc1: sdhci@3400000 {
- ...
- pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
- pinctrl-0 = <&sdmmc1_3v3>;
- pinctrl-1 = <&sdmmc1_1v8>;
- };
-
- ...
-
- sor0: sor@15540000 {
- ...
- pinctrl-0 = <&hdmi_off>;
- pinctrl-1 = <&hdmi_on>;
- pinctrl-names = "hdmi-on", "hdmi-off";
- };
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml
new file mode 100644
index 000000000000..6946df96ec81
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml
@@ -0,0 +1,199 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Power Management Controller (PMC)
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+ compatible:
+ enum:
+ - nvidia,tegra186-pmc
+ - nvidia,tegra194-pmc
+ - nvidia,tegra234-pmc
+
+ reg:
+ minItems: 4
+ maxItems: 5
+
+ reg-names:
+ minItems: 4
+ maxItems: 5
+ items:
+ - const: pmc
+ - const: wake
+ - const: aotag
+ - const: scratch
+ - const: misc
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ description: Specifies the number of cells needed to encode an
+ interrupt source. The value must be 2.
+ const: 2
+
+ nvidia,invert-interrupt:
+ description: If present, inverts the PMU interrupt signal.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+if:
+ properties:
+ compatible:
+ contains:
+ const: nvidia,tegra186-pmc
+then:
+ properties:
+ reg:
+ maxItems: 4
+
+ reg-names:
+ maxItems: 4
+else:
+ properties:
+ reg:
+ minItems: 5
+
+ reg-names:
+ minItems: 5
+
+patternProperties:
+ "^[a-z0-9]+-[a-z0-9]+$":
+ if:
+ type: object
+ then:
+ description: |
+ These are pad configuration nodes. On Tegra SoCs a pad is a set of
+ pins which are configured as a group. The pin grouping is a fixed
+ attribute of the hardware. The PMC can be used to set pad power
+ state and signaling voltage. A pad can be either in active or
+ power down mode. The support for power state and signaling voltage
+ configuration varies depending on the pad in question. 3.3 V and
+ 1.8 V signaling voltages are supported on pins where software
+ controllable signaling voltage switching is available.
+
+ Pad configurations are described with pin configuration nodes
+ which are placed under the pmc node and they are referred to by
+ the pinctrl client properties. For more information see
+
+ Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
+
+ The following pads are present on Tegra186:
+
+ csia, csib, dsi, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2,
+ pex-clk1, usb0, usb1, usb2, usb-bias, uart, audio, hsic, dbg,
+ hdmi-dp0, hdmi-dp1, pex-cntrl, sdmmc2-hv, sdmmc4, cam, dsib,
+ dsic, dsid, csic, csid, csie, dsif, spi, ufs, dmic-hv, edp,
+ sdmmc1-hv, sdmmc3-hv, conn, audio-hv, ao-hv
+
+ The following pads are present on Tegra194:
+
+ csia, csib, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2,
+ pex-clk1, eqos, pex-clk-2-bias, pex-clk-2, dap3, dap5, uart,
+ pwr-ctl, soc-gpio53, audio, gp-pwm2, gp-pwm3, soc-gpio12,
+ soc-gpio13, soc-gpio10, uart4, uart5, dbg, hdmi-dp3, hdmi-dp2,
+ hdmi-dp0, hdmi-dp1, pex-cntrl, pex-ctl2, pex-l0-rst,
+ pex-l1-rst, sdmmc4, pex-l5-rst, cam, csic, csid, csie, csif,
+ spi, ufs, csig, csih, edp, sdmmc1-hv, sdmmc3-hv, conn,
+ audio-hv, ao-hv
+
+ properties:
+ pins:
+ $ref: /schemas/types.yaml#/definitions/string
+ description: Must contain the name of the pad(s) to be
+ configured.
+
+ low-power-enable:
+ description: Configure the pad into power down mode.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ low-power-disable:
+ description: Configure the pad into active mode.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ power-source:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
+ TEGRA_IO_PAD_VOLTAGE_3V3 to select between signalling
+ voltages.
+
+ The values are defined in
+
+ include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h
+
+ The power state can be configured on all of the above pads
+ except for ao-hv. Following pads have software configurable
+ signaling voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv,
+ audio-hv, ao-hv.
+
+ phandle: true
+
+ required:
+ - pins
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - reg-names
+
+additionalProperties: false
+
+dependencies:
+ interrupt-controller: ['#interrupt-cells']
+ "#interrupt-cells":
+ required:
+ - interrupt-controller
+
+examples:
+ - |
+ #include <dt-bindings/clock/tegra186-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
+ #include <dt-bindings/memory/tegra186-mc.h>
+ #include <dt-bindings/reset/tegra186-reset.h>
+
+ pmc@c3600000 {
+ compatible = "nvidia,tegra186-pmc";
+ reg = <0x0c360000 0x10000>,
+ <0x0c370000 0x10000>,
+ <0x0c380000 0x10000>,
+ <0x0c390000 0x10000>;
+ reg-names = "pmc", "wake", "aotag", "scratch";
+ nvidia,invert-interrupt;
+
+ sdmmc1_3v3: sdmmc1-3v3 {
+ pins = "sdmmc1-hv";
+ power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
+ };
+
+ sdmmc1_1v8: sdmmc1-1v8 {
+ pins = "sdmmc1-hv";
+ power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
+ };
+ };
+
+ sdmmc1: mmc@3400000 {
+ compatible = "nvidia,tegra186-sdhci";
+ reg = <0x03400000 0x10000>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
+ <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
+ clock-names = "sdhci", "tmclk";
+ resets = <&bpmp TEGRA186_RESET_SDMMC1>;
+ reset-names = "sdhci";
+ interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA186_SID_SDMMC1>;
+ pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
+ pinctrl-0 = <&sdmmc1_3v3>;
+ pinctrl-1 = <&sdmmc1_1v8>;
+ };
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH v2 11/16] dt-bindings: tegra: pmc: Convert to json-schema
2021-11-19 14:38 ` [PATCH v2 11/16] dt-bindings: tegra: pmc: Convert to json-schema Thierry Reding
@ 2021-11-30 1:41 ` Rob Herring
0 siblings, 0 replies; 42+ messages in thread
From: Rob Herring @ 2021-11-30 1:41 UTC (permalink / raw)
To: Thierry Reding; +Cc: Jon Hunter, devicetree, linux-tegra
On Fri, Nov 19, 2021 at 03:38:34PM +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Convert the NVIDIA Tegra186 (and later) PMC bindings from the free-form
> text format to json-schema.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> .../arm/tegra/nvidia,tegra186-pmc.txt | 133 ------------
> .../arm/tegra/nvidia,tegra186-pmc.yaml | 199 ++++++++++++++++++
> 2 files changed, 199 insertions(+), 133 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt
> create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt
> deleted file mode 100644
> index 576462fae27f..000000000000
> --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt
> +++ /dev/null
> @@ -1,133 +0,0 @@
> -NVIDIA Tegra Power Management Controller (PMC)
> -
> -Required properties:
> -- compatible: Should contain one of the following:
> - - "nvidia,tegra186-pmc": for Tegra186
> - - "nvidia,tegra194-pmc": for Tegra194
> - - "nvidia,tegra234-pmc": for Tegra234
> -- reg: Must contain an (offset, length) pair of the register set for each
> - entry in reg-names.
> -- reg-names: Must include the following entries:
> - - "pmc"
> - - "wake"
> - - "aotag"
> - - "scratch"
> - - "misc" (Only for Tegra194 and later)
> -
> -Optional properties:
> -- nvidia,invert-interrupt: If present, inverts the PMU interrupt signal.
> -- interrupt-controller: Identifies the node as an interrupt controller.
> -- #interrupt-cells: Specifies the number of cells needed to encode an
> - interrupt source. The value must be 2.
> -
> -Example:
> -
> -SoC DTSI:
> -
> - pmc@c3600000 {
> - compatible = "nvidia,tegra186-pmc";
> - reg = <0 0x0c360000 0 0x10000>,
> - <0 0x0c370000 0 0x10000>,
> - <0 0x0c380000 0 0x10000>,
> - <0 0x0c390000 0 0x10000>;
> - reg-names = "pmc", "wake", "aotag", "scratch";
> - };
> -
> -Board DTS:
> -
> - pmc@c360000 {
> - nvidia,invert-interrupt;
> - };
> -
> -== Pad Control ==
> -
> -On Tegra SoCs a pad is a set of pins which are configured as a group.
> -The pin grouping is a fixed attribute of the hardware. The PMC can be
> -used to set pad power state and signaling voltage. A pad can be either
> -in active or power down mode. The support for power state and signaling
> -voltage configuration varies depending on the pad in question. 3.3 V and
> -1.8 V signaling voltages are supported on pins where software
> -controllable signaling voltage switching is available.
> -
> -Pad configurations are described with pin configuration nodes which
> -are placed under the pmc node and they are referred to by the pinctrl
> -client properties. For more information see
> -Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
> -
> -The following pads are present on Tegra186:
> -csia csib dsi mipi-bias
> -pex-clk-bias pex-clk3 pex-clk2 pex-clk1
> -usb0 usb1 usb2 usb-bias
> -uart audio hsic dbg
> -hdmi-dp0 hdmi-dp1 pex-cntrl sdmmc2-hv
> -sdmmc4 cam dsib dsic
> -dsid csic csid csie
> -dsif spi ufs dmic-hv
> -edp sdmmc1-hv sdmmc3-hv conn
> -audio-hv ao-hv
> -
> -Required pin configuration properties:
> - - pins: A list of strings, each of which contains the name of a pad
> - to be configured.
> -
> -Optional pin configuration properties:
> - - low-power-enable: Configure the pad into power down mode
> - - low-power-disable: Configure the pad into active mode
> - - power-source: Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
> - TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
> - The values are defined in
> - include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
> -
> -Note: The power state can be configured on all of the above pads except
> - for ao-hv. Following pads have software configurable signaling
> - voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv, audio-hv,
> - ao-hv.
> -
> -Pad configuration state example:
> - pmc: pmc@7000e400 {
> - compatible = "nvidia,tegra186-pmc";
> - reg = <0 0x0c360000 0 0x10000>,
> - <0 0x0c370000 0 0x10000>,
> - <0 0x0c380000 0 0x10000>,
> - <0 0x0c390000 0 0x10000>;
> - reg-names = "pmc", "wake", "aotag", "scratch";
> -
> - ...
> -
> - sdmmc1_3v3: sdmmc1-3v3 {
> - pins = "sdmmc1-hv";
> - power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
> - };
> -
> - sdmmc1_1v8: sdmmc1-1v8 {
> - pins = "sdmmc1-hv";
> - power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
> - };
> -
> - hdmi_off: hdmi-off {
> - pins = "hdmi";
> - low-power-enable;
> - }
> -
> - hdmi_on: hdmi-on {
> - pins = "hdmi";
> - low-power-disable;
> - }
> - };
> -
> -Pinctrl client example:
> - sdmmc1: sdhci@3400000 {
> - ...
> - pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
> - pinctrl-0 = <&sdmmc1_3v3>;
> - pinctrl-1 = <&sdmmc1_1v8>;
> - };
> -
> - ...
> -
> - sor0: sor@15540000 {
> - ...
> - pinctrl-0 = <&hdmi_off>;
> - pinctrl-1 = <&hdmi_on>;
> - pinctrl-names = "hdmi-on", "hdmi-off";
> - };
> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml
> new file mode 100644
> index 000000000000..6946df96ec81
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml
> @@ -0,0 +1,199 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NVIDIA Tegra Power Management Controller (PMC)
> +
> +maintainers:
> + - Thierry Reding <thierry.reding@gmail.com>
> + - Jon Hunter <jonathanh@nvidia.com>
> +
> +properties:
> + compatible:
> + enum:
> + - nvidia,tegra186-pmc
> + - nvidia,tegra194-pmc
> + - nvidia,tegra234-pmc
> +
> + reg:
> + minItems: 4
> + maxItems: 5
> +
> + reg-names:
> + minItems: 4
> + maxItems: 5
maxItems is not needed (and should warn now).
With that fixed,
Reviewed-by: Rob Herring <robh@kernel.org>
> + items:
> + - const: pmc
> + - const: wake
> + - const: aotag
> + - const: scratch
> + - const: misc
> +
> + interrupt-controller: true
> +
> + "#interrupt-cells":
> + description: Specifies the number of cells needed to encode an
> + interrupt source. The value must be 2.
> + const: 2
> +
> + nvidia,invert-interrupt:
> + description: If present, inverts the PMU interrupt signal.
> + $ref: /schemas/types.yaml#/definitions/flag
> +
> +if:
> + properties:
> + compatible:
> + contains:
> + const: nvidia,tegra186-pmc
> +then:
> + properties:
> + reg:
> + maxItems: 4
> +
> + reg-names:
> + maxItems: 4
> +else:
> + properties:
> + reg:
> + minItems: 5
> +
> + reg-names:
> + minItems: 5
> +
> +patternProperties:
> + "^[a-z0-9]+-[a-z0-9]+$":
> + if:
> + type: object
> + then:
> + description: |
> + These are pad configuration nodes. On Tegra SoCs a pad is a set of
> + pins which are configured as a group. The pin grouping is a fixed
> + attribute of the hardware. The PMC can be used to set pad power
> + state and signaling voltage. A pad can be either in active or
> + power down mode. The support for power state and signaling voltage
> + configuration varies depending on the pad in question. 3.3 V and
> + 1.8 V signaling voltages are supported on pins where software
> + controllable signaling voltage switching is available.
> +
> + Pad configurations are described with pin configuration nodes
> + which are placed under the pmc node and they are referred to by
> + the pinctrl client properties. For more information see
> +
> + Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
> +
> + The following pads are present on Tegra186:
> +
> + csia, csib, dsi, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2,
> + pex-clk1, usb0, usb1, usb2, usb-bias, uart, audio, hsic, dbg,
> + hdmi-dp0, hdmi-dp1, pex-cntrl, sdmmc2-hv, sdmmc4, cam, dsib,
> + dsic, dsid, csic, csid, csie, dsif, spi, ufs, dmic-hv, edp,
> + sdmmc1-hv, sdmmc3-hv, conn, audio-hv, ao-hv
> +
> + The following pads are present on Tegra194:
> +
> + csia, csib, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2,
> + pex-clk1, eqos, pex-clk-2-bias, pex-clk-2, dap3, dap5, uart,
> + pwr-ctl, soc-gpio53, audio, gp-pwm2, gp-pwm3, soc-gpio12,
> + soc-gpio13, soc-gpio10, uart4, uart5, dbg, hdmi-dp3, hdmi-dp2,
> + hdmi-dp0, hdmi-dp1, pex-cntrl, pex-ctl2, pex-l0-rst,
> + pex-l1-rst, sdmmc4, pex-l5-rst, cam, csic, csid, csie, csif,
> + spi, ufs, csig, csih, edp, sdmmc1-hv, sdmmc3-hv, conn,
> + audio-hv, ao-hv
> +
> + properties:
> + pins:
> + $ref: /schemas/types.yaml#/definitions/string
> + description: Must contain the name of the pad(s) to be
> + configured.
> +
> + low-power-enable:
> + description: Configure the pad into power down mode.
> + $ref: /schemas/types.yaml#/definitions/flag
> +
> + low-power-disable:
> + description: Configure the pad into active mode.
> + $ref: /schemas/types.yaml#/definitions/flag
> +
> + power-source:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
> + TEGRA_IO_PAD_VOLTAGE_3V3 to select between signalling
> + voltages.
> +
> + The values are defined in
> +
> + include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h
> +
> + The power state can be configured on all of the above pads
> + except for ao-hv. Following pads have software configurable
> + signaling voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv,
> + audio-hv, ao-hv.
> +
> + phandle: true
> +
> + required:
> + - pins
> +
> + additionalProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> +
> +additionalProperties: false
> +
> +dependencies:
> + interrupt-controller: ['#interrupt-cells']
> + "#interrupt-cells":
> + required:
> + - interrupt-controller
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/tegra186-clock.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
> + #include <dt-bindings/memory/tegra186-mc.h>
> + #include <dt-bindings/reset/tegra186-reset.h>
> +
> + pmc@c3600000 {
> + compatible = "nvidia,tegra186-pmc";
> + reg = <0x0c360000 0x10000>,
> + <0x0c370000 0x10000>,
> + <0x0c380000 0x10000>,
> + <0x0c390000 0x10000>;
> + reg-names = "pmc", "wake", "aotag", "scratch";
> + nvidia,invert-interrupt;
> +
> + sdmmc1_3v3: sdmmc1-3v3 {
> + pins = "sdmmc1-hv";
> + power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
> + };
> +
> + sdmmc1_1v8: sdmmc1-1v8 {
> + pins = "sdmmc1-hv";
> + power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
> + };
> + };
> +
> + sdmmc1: mmc@3400000 {
> + compatible = "nvidia,tegra186-sdhci";
> + reg = <0x03400000 0x10000>;
> + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
> + <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
> + clock-names = "sdhci", "tmclk";
> + resets = <&bpmp TEGRA186_RESET_SDMMC1>;
> + reset-names = "sdhci";
> + interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>,
> + <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>;
> + interconnect-names = "dma-mem", "write";
> + iommus = <&smmu TEGRA186_SID_SDMMC1>;
> + pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
> + pinctrl-0 = <&sdmmc1_3v3>;
> + pinctrl-1 = <&sdmmc1_1v8>;
> + };
> --
> 2.33.1
>
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v2 12/16] dt-bindings: firmware: tegra: Convert to json-schema
2021-11-19 14:38 [PATCH v2 00/16] dt-bindings: Convert Tegra DT bindings to json-schema Thierry Reding
` (10 preceding siblings ...)
2021-11-19 14:38 ` [PATCH v2 11/16] dt-bindings: tegra: pmc: Convert to json-schema Thierry Reding
@ 2021-11-19 14:38 ` Thierry Reding
2021-11-30 1:43 ` Rob Herring
2021-11-19 14:38 ` [PATCH v2 13/16] dt-bindings: i2c: tegra-bpmp: " Thierry Reding
` (4 subsequent siblings)
16 siblings, 1 reply; 42+ messages in thread
From: Thierry Reding @ 2021-11-19 14:38 UTC (permalink / raw)
To: Thierry Reding, Rob Herring; +Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Convert the NVIDIA Tegra186 (and later) BPMP bindings from the free-form
text format to json-schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v2:
- add some missing properties and set additionalProperties to false
.../firmware/nvidia,tegra186-bpmp.txt | 107 ----------
.../firmware/nvidia,tegra186-bpmp.yaml | 186 ++++++++++++++++++
2 files changed, 186 insertions(+), 107 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt
create mode 100644 Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml
diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt
deleted file mode 100644
index e44a13bc06ed..000000000000
--- a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt
+++ /dev/null
@@ -1,107 +0,0 @@
-NVIDIA Tegra Boot and Power Management Processor (BPMP)
-
-The BPMP is a specific processor in Tegra chip, which is designed for
-booting process handling and offloading the power management, clock
-management, and reset control tasks from the CPU. The binding document
-defines the resources that would be used by the BPMP firmware driver,
-which can create the interprocessor communication (IPC) between the CPU
-and BPMP.
-
-Required properties:
-- compatible
- Array of strings
- One of:
- - "nvidia,tegra186-bpmp"
-- mboxes : The phandle of mailbox controller and the mailbox specifier.
-- shmem : List of the phandle of the TX and RX shared memory area that
- the IPC between CPU and BPMP is based on.
-- #clock-cells : Should be 1.
-- #power-domain-cells : Should be 1.
-- #reset-cells : Should be 1.
-
-This node is a mailbox consumer. See the following files for details of
-the mailbox subsystem, and the specifiers implemented by the relevant
-provider(s):
-
-- .../mailbox/mailbox.txt
-- .../mailbox/nvidia,tegra186-hsp.txt
-
-This node is a clock, power domain, and reset provider. See the following
-files for general documentation of those features, and the specifiers
-implemented by this node:
-
-- .../clock/clock-bindings.txt
-- <dt-bindings/clock/tegra186-clock.h>
-- ../power/power-domain.yaml
-- <dt-bindings/power/tegra186-powergate.h>
-- .../reset/reset.txt
-- <dt-bindings/reset/tegra186-reset.h>
-
-The BPMP implements some services which must be represented by separate nodes.
-For example, it can provide access to certain I2C controllers, and the I2C
-bindings represent each I2C controller as a device tree node. Such nodes should
-be nested directly inside the main BPMP node.
-
-Software can determine whether a child node of the BPMP node represents a device
-by checking for a compatible property. Any node with a compatible property
-represents a device that can be instantiated. Nodes without a compatible
-property may be used to provide configuration information regarding the BPMP
-itself, although no such configuration nodes are currently defined by this
-binding.
-
-The BPMP firmware defines no single global name-/numbering-space for such
-services. Put another way, the numbering scheme for I2C buses is distinct from
-the numbering scheme for any other service the BPMP may provide (e.g. a future
-hypothetical SPI bus service). As such, child device nodes will have no reg
-property, and the BPMP node will have no #address-cells or #size-cells property.
-
-The shared memory bindings for BPMP
------------------------------------
-
-The shared memory area for the IPC TX and RX between CPU and BPMP are
-predefined and work on top of sysram, which is an SRAM inside the chip.
-
-See ".../sram/sram.txt" for the bindings.
-
-Example:
-
-hsp_top0: hsp@3c00000 {
- ...
- #mbox-cells = <2>;
-};
-
-sysram@30000000 {
- compatible = "nvidia,tegra186-sysram", "mmio-sram";
- reg = <0x0 0x30000000 0x0 0x50000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
-
- cpu_bpmp_tx: shmem@4e000 {
- compatible = "nvidia,tegra186-bpmp-shmem";
- reg = <0x0 0x4e000 0x0 0x1000>;
- label = "cpu-bpmp-tx";
- pool;
- };
-
- cpu_bpmp_rx: shmem@4f000 {
- compatible = "nvidia,tegra186-bpmp-shmem";
- reg = <0x0 0x4f000 0x0 0x1000>;
- label = "cpu-bpmp-rx";
- pool;
- };
-};
-
-bpmp {
- compatible = "nvidia,tegra186-bpmp";
- mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>;
- shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
- #clock-cells = <1>;
- #power-domain-cells = <1>;
- #reset-cells = <1>;
-
- i2c {
- compatible = "...";
- ...
- };
-};
diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml
new file mode 100644
index 000000000000..833c07f1685c
--- /dev/null
+++ b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml
@@ -0,0 +1,186 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Boot and Power Management Processor (BPMP)
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+
+description: |
+ The BPMP is a specific processor in Tegra chip, which is designed for
+ booting process handling and offloading the power management, clock
+ management, and reset control tasks from the CPU. The binding document
+ defines the resources that would be used by the BPMP firmware driver,
+ which can create the interprocessor communication (IPC) between the
+ CPU and BPMP.
+
+ This node is a mailbox consumer. See the following files for details
+ of the mailbox subsystem, and the specifiers implemented by the
+ relevant provider(s):
+
+ - .../mailbox/mailbox.txt
+ - .../mailbox/nvidia,tegra186-hsp.yaml
+
+ This node is a clock, power domain, and reset provider. See the
+ following files for general documentation of those features, and the
+ specifiers implemented by this node:
+
+ - .../clock/clock-bindings.txt
+ - <dt-bindings/clock/tegra186-clock.h>
+ - ../power/power-domain.yaml
+ - <dt-bindings/power/tegra186-powergate.h>
+ - .../reset/reset.txt
+ - <dt-bindings/reset/tegra186-reset.h>
+
+ The BPMP implements some services which must be represented by
+ separate nodes. For example, it can provide access to certain I2C
+ controllers, and the I2C bindings represent each I2C controller as a
+ device tree node. Such nodes should be nested directly inside the main
+ BPMP node.
+
+ Software can determine whether a child node of the BPMP node
+ represents a device by checking for a compatible property. Any node
+ with a compatible property represents a device that can be
+ instantiated. Nodes without a compatible property may be used to
+ provide configuration information regarding the BPMP itself, although
+ no such configuration nodes are currently defined by this binding.
+
+ The BPMP firmware defines no single global name-/numbering-space for
+ such services. Put another way, the numbering scheme for I2C buses is
+ distinct from the numbering scheme for any other service the BPMP may
+ provide (e.g. a future hypothetical SPI bus service). As such, child
+ device nodes will have no reg property, and the BPMP node will have no
+ "#address-cells" or "#size-cells" property.
+
+ The shared memory area for the IPC TX and RX between CPU and BPMP are
+ predefined and work on top of sysram, which is an SRAM inside the
+ chip. See ".../sram/sram.yaml" for the bindings.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - nvidia,tegra194-bpmp
+ - nvidia,tegra234-bpmp
+ - const: nvidia,tegra186-bpmp
+ - const: nvidia,tegra186-bpmp
+
+ mboxes:
+ description: A phandle and channel specifier for the mailbox used to
+ communicate with the BPMP.
+ maxItems: 1
+
+ shmem:
+ description: List of the phandle to the TX and RX shared memory area
+ that the IPC between CPU and BPMP is based on.
+ minItems: 2
+ maxItems: 2
+
+ "#clock-cells":
+ const: 1
+
+ "#power-domain-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+ interconnects:
+ items:
+ - description: memory read client
+ - description: memory write client
+ - description: DMA read client
+ - description: DMA write client
+
+ interconnect-names:
+ items:
+ - const: read
+ - const: write
+ - const: dma-mem # dma-read
+ - const: dma-write
+
+ iommus:
+ maxItems: 1
+
+ i2c:
+ type: object
+
+ thermal:
+ type: object
+
+additionalProperties: false
+
+required:
+ - compatible
+ - mboxes
+ - shmem
+ - "#clock-cells"
+ - "#power-domain-cells"
+ - "#reset-cells"
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/mailbox/tegra186-hsp.h>
+ #include <dt-bindings/memory/tegra186-mc.h>
+
+ hsp_top0: hsp@3c00000 {
+ compatible = "nvidia,tegra186-hsp";
+ reg = <0x03c00000 0xa0000>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "doorbell";
+ #mbox-cells = <2>;
+ };
+
+ sram@30000000 {
+ compatible = "nvidia,tegra186-sysram", "mmio-sram";
+ reg = <0x30000000 0x50000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x30000000 0x50000>;
+
+ cpu_bpmp_tx: sram@4e000 {
+ reg = <0x4e000 0x1000>;
+ label = "cpu-bpmp-tx";
+ pool;
+ };
+
+ cpu_bpmp_rx: sram@4f000 {
+ reg = <0x4f000 0x1000>;
+ label = "cpu-bpmp-rx";
+ pool;
+ };
+ };
+
+ bpmp {
+ compatible = "nvidia,tegra186-bpmp";
+ interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
+ interconnect-names = "read", "write", "dma-mem", "dma-write";
+ iommus = <&smmu TEGRA186_SID_BPMP>;
+ mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
+ TEGRA_HSP_DB_MASTER_BPMP>;
+ shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ #reset-cells = <1>;
+
+ i2c {
+ compatible = "nvidia,tegra186-bpmp-i2c";
+ nvidia,bpmp-bus-id = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ thermal {
+ compatible = "nvidia,tegra186-bpmp-thermal";
+ #thermal-sensor-cells = <1>;
+ };
+ };
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH v2 12/16] dt-bindings: firmware: tegra: Convert to json-schema
2021-11-19 14:38 ` [PATCH v2 12/16] dt-bindings: firmware: tegra: " Thierry Reding
@ 2021-11-30 1:43 ` Rob Herring
0 siblings, 0 replies; 42+ messages in thread
From: Rob Herring @ 2021-11-30 1:43 UTC (permalink / raw)
To: Thierry Reding; +Cc: devicetree, linux-tegra, Jon Hunter, Rob Herring
On Fri, 19 Nov 2021 15:38:35 +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Convert the NVIDIA Tegra186 (and later) BPMP bindings from the free-form
> text format to json-schema.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> Changes in v2:
> - add some missing properties and set additionalProperties to false
>
> .../firmware/nvidia,tegra186-bpmp.txt | 107 ----------
> .../firmware/nvidia,tegra186-bpmp.yaml | 186 ++++++++++++++++++
> 2 files changed, 186 insertions(+), 107 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt
> create mode 100644 Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v2 13/16] dt-bindings: i2c: tegra-bpmp: Convert to json-schema
2021-11-19 14:38 [PATCH v2 00/16] dt-bindings: Convert Tegra DT bindings to json-schema Thierry Reding
` (11 preceding siblings ...)
2021-11-19 14:38 ` [PATCH v2 12/16] dt-bindings: firmware: tegra: " Thierry Reding
@ 2021-11-19 14:38 ` Thierry Reding
2021-11-23 16:34 ` Rob Herring
2021-11-30 1:44 ` Rob Herring
2021-11-19 14:38 ` [PATCH v2 14/16] dt-bindings: thermal: tegra186-bpmp: " Thierry Reding
` (3 subsequent siblings)
16 siblings, 2 replies; 42+ messages in thread
From: Thierry Reding @ 2021-11-19 14:38 UTC (permalink / raw)
To: Thierry Reding, Rob Herring; +Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Convert the NVIDIA Tegra186 (and later) BPMP I2C bindings from the
free-form text format to json-schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v2:
- add missing additionalProperties: false
.../bindings/i2c/nvidia,tegra186-bpmp-i2c.txt | 42 -------------------
.../i2c/nvidia,tegra186-bpmp-i2c.yaml | 42 +++++++++++++++++++
2 files changed, 42 insertions(+), 42 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt
create mode 100644 Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml
diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt b/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt
deleted file mode 100644
index ab240e10debc..000000000000
--- a/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-NVIDIA Tegra186 BPMP I2C controller
-
-In Tegra186, the BPMP (Boot and Power Management Processor) owns certain HW
-devices, such as the I2C controller for the power management I2C bus. Software
-running on other CPUs must perform IPC to the BPMP in order to execute
-transactions on that I2C bus. This binding describes an I2C bus that is
-accessed in such a fashion.
-
-The BPMP I2C node must be located directly inside the main BPMP node. See
-../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding.
-
-This node represents an I2C controller. See ../i2c/i2c.txt for details of the
-core I2C binding.
-
-Required properties:
-- compatible:
- Array of strings.
- One of:
- - "nvidia,tegra186-bpmp-i2c".
-- #address-cells: Address cells for I2C device address.
- Single-cell integer.
- Must be <1>.
-- #size-cells:
- Single-cell integer.
- Must be <0>.
-- nvidia,bpmp-bus-id:
- Single-cell integer.
- Indicates the I2C bus number this DT node represent, as defined by the
- BPMP firmware.
-
-Example:
-
-bpmp {
- ...
-
- i2c {
- compatible = "nvidia,tegra186-bpmp-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- nvidia,bpmp-bus-id = <5>;
- };
-};
diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml b/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml
new file mode 100644
index 000000000000..351e12124959
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/nvidia,tegra186-bpmp-i2c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra186 (and later) BPMP I2C controller
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+
+description: |
+ In Tegra186 and later, the BPMP (Boot and Power Management Processor)
+ owns certain HW devices, such as the I2C controller for the power
+ management I2C bus. Software running on other CPUs must perform IPC to
+ the BPMP in order to execute transactions on that I2C bus. This
+ binding describes an I2C bus that is accessed in such a fashion.
+
+ The BPMP I2C node must be located directly inside the main BPMP node.
+ See ../firmware/nvidia,tegra186-bpmp.yaml for details of the BPMP
+ binding.
+
+ This node represents an I2C controller. See ../i2c/i2c.txt for details
+ of the core I2C binding.
+
+properties:
+ compatible:
+ const: nvidia,tegra186-bpmp-i2c
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ nvidia,bpmp-bus-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Indicates the I2C bus number this DT node represents,
+ as defined by the BPMP firmware.
+
+additionalProperties: false
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH v2 13/16] dt-bindings: i2c: tegra-bpmp: Convert to json-schema
2021-11-19 14:38 ` [PATCH v2 13/16] dt-bindings: i2c: tegra-bpmp: " Thierry Reding
@ 2021-11-23 16:34 ` Rob Herring
2021-11-30 1:44 ` Rob Herring
1 sibling, 0 replies; 42+ messages in thread
From: Rob Herring @ 2021-11-23 16:34 UTC (permalink / raw)
To: Thierry Reding; +Cc: devicetree, Jon Hunter, Rob Herring, linux-tegra
On Fri, 19 Nov 2021 15:38:36 +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Convert the NVIDIA Tegra186 (and later) BPMP I2C bindings from the
> free-form text format to json-schema.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> Changes in v2:
> - add missing additionalProperties: false
>
> .../bindings/i2c/nvidia,tegra186-bpmp-i2c.txt | 42 -------------------
> .../i2c/nvidia,tegra186-bpmp-i2c.yaml | 42 +++++++++++++++++++
> 2 files changed, 42 insertions(+), 42 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt
> create mode 100644 Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml
>
Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.
Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.
Full log is available here: https://patchwork.ozlabs.org/patch/1557177
i2c: 'pmic@3c' does not match any of the regexes: 'pinctrl-[0-9]+'
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dt.yaml
arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dt.yaml
arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dt.yaml
arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0001.dt.yaml
i2c: 'pmic@3c', 'temperature-sensor@4c' do not match any of the regexes: 'pinctrl-[0-9]+'
arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dt.yaml
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 13/16] dt-bindings: i2c: tegra-bpmp: Convert to json-schema
2021-11-19 14:38 ` [PATCH v2 13/16] dt-bindings: i2c: tegra-bpmp: " Thierry Reding
2021-11-23 16:34 ` Rob Herring
@ 2021-11-30 1:44 ` Rob Herring
2021-12-01 17:42 ` Thierry Reding
1 sibling, 1 reply; 42+ messages in thread
From: Rob Herring @ 2021-11-30 1:44 UTC (permalink / raw)
To: Thierry Reding; +Cc: Jon Hunter, devicetree, linux-tegra
On Fri, Nov 19, 2021 at 03:38:36PM +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Convert the NVIDIA Tegra186 (and later) BPMP I2C bindings from the
> free-form text format to json-schema.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> Changes in v2:
> - add missing additionalProperties: false
>
> .../bindings/i2c/nvidia,tegra186-bpmp-i2c.txt | 42 -------------------
> .../i2c/nvidia,tegra186-bpmp-i2c.yaml | 42 +++++++++++++++++++
> 2 files changed, 42 insertions(+), 42 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt
> create mode 100644 Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml
>
> diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt b/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt
> deleted file mode 100644
> index ab240e10debc..000000000000
> --- a/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt
> +++ /dev/null
> @@ -1,42 +0,0 @@
> -NVIDIA Tegra186 BPMP I2C controller
> -
> -In Tegra186, the BPMP (Boot and Power Management Processor) owns certain HW
> -devices, such as the I2C controller for the power management I2C bus. Software
> -running on other CPUs must perform IPC to the BPMP in order to execute
> -transactions on that I2C bus. This binding describes an I2C bus that is
> -accessed in such a fashion.
> -
> -The BPMP I2C node must be located directly inside the main BPMP node. See
> -../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding.
> -
> -This node represents an I2C controller. See ../i2c/i2c.txt for details of the
> -core I2C binding.
> -
> -Required properties:
> -- compatible:
> - Array of strings.
> - One of:
> - - "nvidia,tegra186-bpmp-i2c".
> -- #address-cells: Address cells for I2C device address.
> - Single-cell integer.
> - Must be <1>.
> -- #size-cells:
> - Single-cell integer.
> - Must be <0>.
> -- nvidia,bpmp-bus-id:
> - Single-cell integer.
> - Indicates the I2C bus number this DT node represent, as defined by the
> - BPMP firmware.
> -
> -Example:
> -
> -bpmp {
> - ...
> -
> - i2c {
> - compatible = "nvidia,tegra186-bpmp-i2c";
> - #address-cells = <1>;
> - #size-cells = <0>;
> - nvidia,bpmp-bus-id = <5>;
> - };
> -};
> diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml b/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml
> new file mode 100644
> index 000000000000..351e12124959
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml
> @@ -0,0 +1,42 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/i2c/nvidia,tegra186-bpmp-i2c.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NVIDIA Tegra186 (and later) BPMP I2C controller
> +
> +maintainers:
> + - Thierry Reding <thierry.reding@gmail.com>
> + - Jon Hunter <jonathanh@nvidia.com>
> +
> +description: |
> + In Tegra186 and later, the BPMP (Boot and Power Management Processor)
> + owns certain HW devices, such as the I2C controller for the power
> + management I2C bus. Software running on other CPUs must perform IPC to
> + the BPMP in order to execute transactions on that I2C bus. This
> + binding describes an I2C bus that is accessed in such a fashion.
> +
> + The BPMP I2C node must be located directly inside the main BPMP node.
> + See ../firmware/nvidia,tegra186-bpmp.yaml for details of the BPMP
> + binding.
> +
> + This node represents an I2C controller. See ../i2c/i2c.txt for details
> + of the core I2C binding.
> +
> +properties:
> + compatible:
> + const: nvidia,tegra186-bpmp-i2c
> +
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 0
Covered by i2c-controller.yaml. Add a reference and then use
unevaluatedProperties.
> +
> + nvidia,bpmp-bus-id:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: Indicates the I2C bus number this DT node represents,
> + as defined by the BPMP firmware.
> +
> +additionalProperties: false
> --
> 2.33.1
>
>
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v2 13/16] dt-bindings: i2c: tegra-bpmp: Convert to json-schema
2021-11-30 1:44 ` Rob Herring
@ 2021-12-01 17:42 ` Thierry Reding
2021-12-01 18:42 ` Rob Herring
0 siblings, 1 reply; 42+ messages in thread
From: Thierry Reding @ 2021-12-01 17:42 UTC (permalink / raw)
To: Rob Herring; +Cc: Jon Hunter, devicetree, linux-tegra
[-- Attachment #1: Type: text/plain, Size: 5389 bytes --]
On Mon, Nov 29, 2021 at 07:44:32PM -0600, Rob Herring wrote:
> On Fri, Nov 19, 2021 at 03:38:36PM +0100, Thierry Reding wrote:
> > From: Thierry Reding <treding@nvidia.com>
> >
> > Convert the NVIDIA Tegra186 (and later) BPMP I2C bindings from the
> > free-form text format to json-schema.
> >
> > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > ---
> > Changes in v2:
> > - add missing additionalProperties: false
> >
> > .../bindings/i2c/nvidia,tegra186-bpmp-i2c.txt | 42 -------------------
> > .../i2c/nvidia,tegra186-bpmp-i2c.yaml | 42 +++++++++++++++++++
> > 2 files changed, 42 insertions(+), 42 deletions(-)
> > delete mode 100644 Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt
> > create mode 100644 Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt b/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt
> > deleted file mode 100644
> > index ab240e10debc..000000000000
> > --- a/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt
> > +++ /dev/null
> > @@ -1,42 +0,0 @@
> > -NVIDIA Tegra186 BPMP I2C controller
> > -
> > -In Tegra186, the BPMP (Boot and Power Management Processor) owns certain HW
> > -devices, such as the I2C controller for the power management I2C bus. Software
> > -running on other CPUs must perform IPC to the BPMP in order to execute
> > -transactions on that I2C bus. This binding describes an I2C bus that is
> > -accessed in such a fashion.
> > -
> > -The BPMP I2C node must be located directly inside the main BPMP node. See
> > -../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding.
> > -
> > -This node represents an I2C controller. See ../i2c/i2c.txt for details of the
> > -core I2C binding.
> > -
> > -Required properties:
> > -- compatible:
> > - Array of strings.
> > - One of:
> > - - "nvidia,tegra186-bpmp-i2c".
> > -- #address-cells: Address cells for I2C device address.
> > - Single-cell integer.
> > - Must be <1>.
> > -- #size-cells:
> > - Single-cell integer.
> > - Must be <0>.
> > -- nvidia,bpmp-bus-id:
> > - Single-cell integer.
> > - Indicates the I2C bus number this DT node represent, as defined by the
> > - BPMP firmware.
> > -
> > -Example:
> > -
> > -bpmp {
> > - ...
> > -
> > - i2c {
> > - compatible = "nvidia,tegra186-bpmp-i2c";
> > - #address-cells = <1>;
> > - #size-cells = <0>;
> > - nvidia,bpmp-bus-id = <5>;
> > - };
> > -};
> > diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml b/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml
> > new file mode 100644
> > index 000000000000..351e12124959
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml
> > @@ -0,0 +1,42 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/i2c/nvidia,tegra186-bpmp-i2c.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: NVIDIA Tegra186 (and later) BPMP I2C controller
> > +
> > +maintainers:
> > + - Thierry Reding <thierry.reding@gmail.com>
> > + - Jon Hunter <jonathanh@nvidia.com>
> > +
> > +description: |
> > + In Tegra186 and later, the BPMP (Boot and Power Management Processor)
> > + owns certain HW devices, such as the I2C controller for the power
> > + management I2C bus. Software running on other CPUs must perform IPC to
> > + the BPMP in order to execute transactions on that I2C bus. This
> > + binding describes an I2C bus that is accessed in such a fashion.
> > +
> > + The BPMP I2C node must be located directly inside the main BPMP node.
> > + See ../firmware/nvidia,tegra186-bpmp.yaml for details of the BPMP
> > + binding.
> > +
> > + This node represents an I2C controller. See ../i2c/i2c.txt for details
> > + of the core I2C binding.
> > +
> > +properties:
> > + compatible:
> > + const: nvidia,tegra186-bpmp-i2c
> > +
>
> > + "#address-cells":
> > + const: 1
> > +
> > + "#size-cells":
> > + const: 0
>
> Covered by i2c-controller.yaml. Add a reference and then use
> unevaluatedProperties.
About that: I've recently noticed that this doesn't seem to work
properly. I'm using branch draft2020-12 from your github and my
understanding was that this should give us support for
unevaluatedProperties. And indeed, it no longer complains about
#address-cells and #size-cells if I remove them from this binding,
presumably because it gets them from i2c-controller.yaml.
However, a side-effect seems to be that now it also ignores any
properties that aren't defined anywhere. So for example if I touch
up the example in firmware/nvidia,tegra186-bpmp.yaml and add a bogus
"foo-bar = <0>;" property in the BPMP I2C node, then it'll blindly
accept that as valid.
The validation will flag if I set #address-cells = <2> in the BPMP
I2C node, so validation of the schema still seems to work, but for
some reason it won't flag any properties that haven't been specified
in the schema.
Do I misunderstand how this is supposed to work, or is there something
wrong with the current implementation of unevaluatedProperties?
Thierry
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^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v2 13/16] dt-bindings: i2c: tegra-bpmp: Convert to json-schema
2021-12-01 17:42 ` Thierry Reding
@ 2021-12-01 18:42 ` Rob Herring
2021-12-02 17:55 ` Thierry Reding
0 siblings, 1 reply; 42+ messages in thread
From: Rob Herring @ 2021-12-01 18:42 UTC (permalink / raw)
To: Thierry Reding; +Cc: Jon Hunter, devicetree, linux-tegra
On Wed, Dec 1, 2021 at 11:42 AM Thierry Reding <thierry.reding@gmail.com> wrote:
>
> On Mon, Nov 29, 2021 at 07:44:32PM -0600, Rob Herring wrote:
> > On Fri, Nov 19, 2021 at 03:38:36PM +0100, Thierry Reding wrote:
> > > From: Thierry Reding <treding@nvidia.com>
> > >
> > > Convert the NVIDIA Tegra186 (and later) BPMP I2C bindings from the
> > > free-form text format to json-schema.
> > >
> > > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > > ---
> > > Changes in v2:
> > > - add missing additionalProperties: false
> > >
> > > .../bindings/i2c/nvidia,tegra186-bpmp-i2c.txt | 42 -------------------
> > > .../i2c/nvidia,tegra186-bpmp-i2c.yaml | 42 +++++++++++++++++++
> > > 2 files changed, 42 insertions(+), 42 deletions(-)
> > > delete mode 100644 Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt
> > > create mode 100644 Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt b/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt
> > > deleted file mode 100644
> > > index ab240e10debc..000000000000
> > > --- a/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt
> > > +++ /dev/null
> > > @@ -1,42 +0,0 @@
> > > -NVIDIA Tegra186 BPMP I2C controller
> > > -
> > > -In Tegra186, the BPMP (Boot and Power Management Processor) owns certain HW
> > > -devices, such as the I2C controller for the power management I2C bus. Software
> > > -running on other CPUs must perform IPC to the BPMP in order to execute
> > > -transactions on that I2C bus. This binding describes an I2C bus that is
> > > -accessed in such a fashion.
> > > -
> > > -The BPMP I2C node must be located directly inside the main BPMP node. See
> > > -../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding.
> > > -
> > > -This node represents an I2C controller. See ../i2c/i2c.txt for details of the
> > > -core I2C binding.
> > > -
> > > -Required properties:
> > > -- compatible:
> > > - Array of strings.
> > > - One of:
> > > - - "nvidia,tegra186-bpmp-i2c".
> > > -- #address-cells: Address cells for I2C device address.
> > > - Single-cell integer.
> > > - Must be <1>.
> > > -- #size-cells:
> > > - Single-cell integer.
> > > - Must be <0>.
> > > -- nvidia,bpmp-bus-id:
> > > - Single-cell integer.
> > > - Indicates the I2C bus number this DT node represent, as defined by the
> > > - BPMP firmware.
> > > -
> > > -Example:
> > > -
> > > -bpmp {
> > > - ...
> > > -
> > > - i2c {
> > > - compatible = "nvidia,tegra186-bpmp-i2c";
> > > - #address-cells = <1>;
> > > - #size-cells = <0>;
> > > - nvidia,bpmp-bus-id = <5>;
> > > - };
> > > -};
> > > diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml b/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml
> > > new file mode 100644
> > > index 000000000000..351e12124959
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml
> > > @@ -0,0 +1,42 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/i2c/nvidia,tegra186-bpmp-i2c.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: NVIDIA Tegra186 (and later) BPMP I2C controller
> > > +
> > > +maintainers:
> > > + - Thierry Reding <thierry.reding@gmail.com>
> > > + - Jon Hunter <jonathanh@nvidia.com>
> > > +
> > > +description: |
> > > + In Tegra186 and later, the BPMP (Boot and Power Management Processor)
> > > + owns certain HW devices, such as the I2C controller for the power
> > > + management I2C bus. Software running on other CPUs must perform IPC to
> > > + the BPMP in order to execute transactions on that I2C bus. This
> > > + binding describes an I2C bus that is accessed in such a fashion.
> > > +
> > > + The BPMP I2C node must be located directly inside the main BPMP node.
> > > + See ../firmware/nvidia,tegra186-bpmp.yaml for details of the BPMP
> > > + binding.
> > > +
> > > + This node represents an I2C controller. See ../i2c/i2c.txt for details
> > > + of the core I2C binding.
> > > +
> > > +properties:
> > > + compatible:
> > > + const: nvidia,tegra186-bpmp-i2c
> > > +
> >
> > > + "#address-cells":
> > > + const: 1
> > > +
> > > + "#size-cells":
> > > + const: 0
> >
> > Covered by i2c-controller.yaml. Add a reference and then use
> > unevaluatedProperties.
>
> About that: I've recently noticed that this doesn't seem to work
> properly. I'm using branch draft2020-12 from your github and my
Use dtschema main/master branch. That branch is likely stale.
> understanding was that this should give us support for
> unevaluatedProperties. And indeed, it no longer complains about
> #address-cells and #size-cells if I remove them from this binding,
> presumably because it gets them from i2c-controller.yaml.
>
> However, a side-effect seems to be that now it also ignores any
> properties that aren't defined anywhere. So for example if I touch
> up the example in firmware/nvidia,tegra186-bpmp.yaml and add a bogus
> "foo-bar = <0>;" property in the BPMP I2C node, then it'll blindly
> accept that as valid.
Do you have unevaluatedProperties within the i2c node? It only applies
to 1 level, and you can't have a parent+child schema evaluated with
another child (or parent+child) schema. This is why the graph schema
is done the way it is and why we're splitting spi-controller.yaml
child node schema out to spi-peripheral.yaml.
> The validation will flag if I set #address-cells = <2> in the BPMP
> I2C node, so validation of the schema still seems to work, but for
> some reason it won't flag any properties that haven't been specified
> in the schema.
>
> Do I misunderstand how this is supposed to work, or is there something
> wrong with the current implementation of unevaluatedProperties?
>
> Thierry
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v2 13/16] dt-bindings: i2c: tegra-bpmp: Convert to json-schema
2021-12-01 18:42 ` Rob Herring
@ 2021-12-02 17:55 ` Thierry Reding
2021-12-02 21:08 ` Rob Herring
0 siblings, 1 reply; 42+ messages in thread
From: Thierry Reding @ 2021-12-02 17:55 UTC (permalink / raw)
To: Rob Herring; +Cc: Jon Hunter, devicetree, linux-tegra
[-- Attachment #1: Type: text/plain, Size: 7792 bytes --]
On Wed, Dec 01, 2021 at 12:42:07PM -0600, Rob Herring wrote:
> On Wed, Dec 1, 2021 at 11:42 AM Thierry Reding <thierry.reding@gmail.com> wrote:
> >
> > On Mon, Nov 29, 2021 at 07:44:32PM -0600, Rob Herring wrote:
> > > On Fri, Nov 19, 2021 at 03:38:36PM +0100, Thierry Reding wrote:
> > > > From: Thierry Reding <treding@nvidia.com>
> > > >
> > > > Convert the NVIDIA Tegra186 (and later) BPMP I2C bindings from the
> > > > free-form text format to json-schema.
> > > >
> > > > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > > > ---
> > > > Changes in v2:
> > > > - add missing additionalProperties: false
> > > >
> > > > .../bindings/i2c/nvidia,tegra186-bpmp-i2c.txt | 42 -------------------
> > > > .../i2c/nvidia,tegra186-bpmp-i2c.yaml | 42 +++++++++++++++++++
> > > > 2 files changed, 42 insertions(+), 42 deletions(-)
> > > > delete mode 100644 Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt
> > > > create mode 100644 Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt b/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt
> > > > deleted file mode 100644
> > > > index ab240e10debc..000000000000
> > > > --- a/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt
> > > > +++ /dev/null
> > > > @@ -1,42 +0,0 @@
> > > > -NVIDIA Tegra186 BPMP I2C controller
> > > > -
> > > > -In Tegra186, the BPMP (Boot and Power Management Processor) owns certain HW
> > > > -devices, such as the I2C controller for the power management I2C bus. Software
> > > > -running on other CPUs must perform IPC to the BPMP in order to execute
> > > > -transactions on that I2C bus. This binding describes an I2C bus that is
> > > > -accessed in such a fashion.
> > > > -
> > > > -The BPMP I2C node must be located directly inside the main BPMP node. See
> > > > -../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding.
> > > > -
> > > > -This node represents an I2C controller. See ../i2c/i2c.txt for details of the
> > > > -core I2C binding.
> > > > -
> > > > -Required properties:
> > > > -- compatible:
> > > > - Array of strings.
> > > > - One of:
> > > > - - "nvidia,tegra186-bpmp-i2c".
> > > > -- #address-cells: Address cells for I2C device address.
> > > > - Single-cell integer.
> > > > - Must be <1>.
> > > > -- #size-cells:
> > > > - Single-cell integer.
> > > > - Must be <0>.
> > > > -- nvidia,bpmp-bus-id:
> > > > - Single-cell integer.
> > > > - Indicates the I2C bus number this DT node represent, as defined by the
> > > > - BPMP firmware.
> > > > -
> > > > -Example:
> > > > -
> > > > -bpmp {
> > > > - ...
> > > > -
> > > > - i2c {
> > > > - compatible = "nvidia,tegra186-bpmp-i2c";
> > > > - #address-cells = <1>;
> > > > - #size-cells = <0>;
> > > > - nvidia,bpmp-bus-id = <5>;
> > > > - };
> > > > -};
> > > > diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml b/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml
> > > > new file mode 100644
> > > > index 000000000000..351e12124959
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml
> > > > @@ -0,0 +1,42 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > +%YAML 1.2
> > > > +---
> > > > +$id: http://devicetree.org/schemas/i2c/nvidia,tegra186-bpmp-i2c.yaml#
> > > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > > +
> > > > +title: NVIDIA Tegra186 (and later) BPMP I2C controller
> > > > +
> > > > +maintainers:
> > > > + - Thierry Reding <thierry.reding@gmail.com>
> > > > + - Jon Hunter <jonathanh@nvidia.com>
> > > > +
> > > > +description: |
> > > > + In Tegra186 and later, the BPMP (Boot and Power Management Processor)
> > > > + owns certain HW devices, such as the I2C controller for the power
> > > > + management I2C bus. Software running on other CPUs must perform IPC to
> > > > + the BPMP in order to execute transactions on that I2C bus. This
> > > > + binding describes an I2C bus that is accessed in such a fashion.
> > > > +
> > > > + The BPMP I2C node must be located directly inside the main BPMP node.
> > > > + See ../firmware/nvidia,tegra186-bpmp.yaml for details of the BPMP
> > > > + binding.
> > > > +
> > > > + This node represents an I2C controller. See ../i2c/i2c.txt for details
> > > > + of the core I2C binding.
> > > > +
> > > > +properties:
> > > > + compatible:
> > > > + const: nvidia,tegra186-bpmp-i2c
> > > > +
> > >
> > > > + "#address-cells":
> > > > + const: 1
> > > > +
> > > > + "#size-cells":
> > > > + const: 0
> > >
> > > Covered by i2c-controller.yaml. Add a reference and then use
> > > unevaluatedProperties.
> >
> > About that: I've recently noticed that this doesn't seem to work
> > properly. I'm using branch draft2020-12 from your github and my
>
> Use dtschema main/master branch. That branch is likely stale.
That seems to have helped somewhat. I do occasionally see warnings now
about unevaluated properties being unexpected. I can still reproduce the
issue, though, see below.
> > understanding was that this should give us support for
> > unevaluatedProperties. And indeed, it no longer complains about
> > #address-cells and #size-cells if I remove them from this binding,
> > presumably because it gets them from i2c-controller.yaml.
> >
> > However, a side-effect seems to be that now it also ignores any
> > properties that aren't defined anywhere. So for example if I touch
> > up the example in firmware/nvidia,tegra186-bpmp.yaml and add a bogus
> > "foo-bar = <0>;" property in the BPMP I2C node, then it'll blindly
> > accept that as valid.
>
> Do you have unevaluatedProperties within the i2c node? It only applies
> to 1 level, and you can't have a parent+child schema evaluated with
> another child (or parent+child) schema. This is why the graph schema
> is done the way it is and why we're splitting spi-controller.yaml
> child node schema out to spi-peripheral.yaml.
Let me give an example based on a schema that's already upstream. So
looking at this:
Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
it does include spi-controller.yaml via an allOf: [ $ref: ... ], so it
uses unevaluatedProperties to validate against any generic SPI
controller properties. For example, #address-cells and #size-cells are
validated based on the schema from spi-controller.yaml.
However, if I now apply the following patch to add an undocumented
property to the example, then validation doesn't fail as I would expect
it to.
--- >8 ---
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
index 35a8045b2c70..e9342faf5194 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
@@ -104,6 +104,7 @@ examples:
resets = <&tegra_car 211>;
dmas = <&apbdma 5>, <&apbdma 5>;
dma-names = "rx", "tx";
+ foo-something = <42>;
flash@0 {
compatible = "spi-nor";
--- >8 ---
I would expect the validation to fail for foo-something because it isn't
defined in any of the schemas.
Or is this one of the cases that you mentioned above. I must admit I did
not follow what exactly is expected to work and what isn't. The QSPI
controller example from above seems simple enough.
Thierry
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^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH v2 13/16] dt-bindings: i2c: tegra-bpmp: Convert to json-schema
2021-12-02 17:55 ` Thierry Reding
@ 2021-12-02 21:08 ` Rob Herring
2021-12-02 22:38 ` Rob Herring
0 siblings, 1 reply; 42+ messages in thread
From: Rob Herring @ 2021-12-02 21:08 UTC (permalink / raw)
To: Thierry Reding; +Cc: Jon Hunter, devicetree, linux-tegra
On Thu, Dec 2, 2021 at 11:55 AM Thierry Reding <thierry.reding@gmail.com> wrote:
>
> On Wed, Dec 01, 2021 at 12:42:07PM -0600, Rob Herring wrote:
> > On Wed, Dec 1, 2021 at 11:42 AM Thierry Reding <thierry.reding@gmail.com> wrote:
> > >
> > > On Mon, Nov 29, 2021 at 07:44:32PM -0600, Rob Herring wrote:
> > > > On Fri, Nov 19, 2021 at 03:38:36PM +0100, Thierry Reding wrote:
> > > > > From: Thierry Reding <treding@nvidia.com>
> > > > >
> > > > > Convert the NVIDIA Tegra186 (and later) BPMP I2C bindings from the
> > > > > free-form text format to json-schema.
> > > > >
> > > > > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > > > > ---
> > > > > Changes in v2:
> > > > > - add missing additionalProperties: false
> > > > >
> > > > > .../bindings/i2c/nvidia,tegra186-bpmp-i2c.txt | 42 -------------------
> > > > > .../i2c/nvidia,tegra186-bpmp-i2c.yaml | 42 +++++++++++++++++++
> > > > > 2 files changed, 42 insertions(+), 42 deletions(-)
> > > > > delete mode 100644 Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt
> > > > > create mode 100644 Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml
> > > > >
> > > > > diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt b/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt
> > > > > deleted file mode 100644
> > > > > index ab240e10debc..000000000000
> > > > > --- a/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt
> > > > > +++ /dev/null
> > > > > @@ -1,42 +0,0 @@
> > > > > -NVIDIA Tegra186 BPMP I2C controller
> > > > > -
> > > > > -In Tegra186, the BPMP (Boot and Power Management Processor) owns certain HW
> > > > > -devices, such as the I2C controller for the power management I2C bus. Software
> > > > > -running on other CPUs must perform IPC to the BPMP in order to execute
> > > > > -transactions on that I2C bus. This binding describes an I2C bus that is
> > > > > -accessed in such a fashion.
> > > > > -
> > > > > -The BPMP I2C node must be located directly inside the main BPMP node. See
> > > > > -../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding.
> > > > > -
> > > > > -This node represents an I2C controller. See ../i2c/i2c.txt for details of the
> > > > > -core I2C binding.
> > > > > -
> > > > > -Required properties:
> > > > > -- compatible:
> > > > > - Array of strings.
> > > > > - One of:
> > > > > - - "nvidia,tegra186-bpmp-i2c".
> > > > > -- #address-cells: Address cells for I2C device address.
> > > > > - Single-cell integer.
> > > > > - Must be <1>.
> > > > > -- #size-cells:
> > > > > - Single-cell integer.
> > > > > - Must be <0>.
> > > > > -- nvidia,bpmp-bus-id:
> > > > > - Single-cell integer.
> > > > > - Indicates the I2C bus number this DT node represent, as defined by the
> > > > > - BPMP firmware.
> > > > > -
> > > > > -Example:
> > > > > -
> > > > > -bpmp {
> > > > > - ...
> > > > > -
> > > > > - i2c {
> > > > > - compatible = "nvidia,tegra186-bpmp-i2c";
> > > > > - #address-cells = <1>;
> > > > > - #size-cells = <0>;
> > > > > - nvidia,bpmp-bus-id = <5>;
> > > > > - };
> > > > > -};
> > > > > diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml b/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml
> > > > > new file mode 100644
> > > > > index 000000000000..351e12124959
> > > > > --- /dev/null
> > > > > +++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml
> > > > > @@ -0,0 +1,42 @@
> > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > > +%YAML 1.2
> > > > > +---
> > > > > +$id: http://devicetree.org/schemas/i2c/nvidia,tegra186-bpmp-i2c.yaml#
> > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > > > +
> > > > > +title: NVIDIA Tegra186 (and later) BPMP I2C controller
> > > > > +
> > > > > +maintainers:
> > > > > + - Thierry Reding <thierry.reding@gmail.com>
> > > > > + - Jon Hunter <jonathanh@nvidia.com>
> > > > > +
> > > > > +description: |
> > > > > + In Tegra186 and later, the BPMP (Boot and Power Management Processor)
> > > > > + owns certain HW devices, such as the I2C controller for the power
> > > > > + management I2C bus. Software running on other CPUs must perform IPC to
> > > > > + the BPMP in order to execute transactions on that I2C bus. This
> > > > > + binding describes an I2C bus that is accessed in such a fashion.
> > > > > +
> > > > > + The BPMP I2C node must be located directly inside the main BPMP node.
> > > > > + See ../firmware/nvidia,tegra186-bpmp.yaml for details of the BPMP
> > > > > + binding.
> > > > > +
> > > > > + This node represents an I2C controller. See ../i2c/i2c.txt for details
> > > > > + of the core I2C binding.
> > > > > +
> > > > > +properties:
> > > > > + compatible:
> > > > > + const: nvidia,tegra186-bpmp-i2c
> > > > > +
> > > >
> > > > > + "#address-cells":
> > > > > + const: 1
> > > > > +
> > > > > + "#size-cells":
> > > > > + const: 0
> > > >
> > > > Covered by i2c-controller.yaml. Add a reference and then use
> > > > unevaluatedProperties.
> > >
> > > About that: I've recently noticed that this doesn't seem to work
> > > properly. I'm using branch draft2020-12 from your github and my
> >
> > Use dtschema main/master branch. That branch is likely stale.
>
> That seems to have helped somewhat. I do occasionally see warnings now
> about unevaluated properties being unexpected. I can still reproduce the
> issue, though, see below.
>
> > > understanding was that this should give us support for
> > > unevaluatedProperties. And indeed, it no longer complains about
> > > #address-cells and #size-cells if I remove them from this binding,
> > > presumably because it gets them from i2c-controller.yaml.
> > >
> > > However, a side-effect seems to be that now it also ignores any
> > > properties that aren't defined anywhere. So for example if I touch
> > > up the example in firmware/nvidia,tegra186-bpmp.yaml and add a bogus
> > > "foo-bar = <0>;" property in the BPMP I2C node, then it'll blindly
> > > accept that as valid.
> >
> > Do you have unevaluatedProperties within the i2c node? It only applies
> > to 1 level, and you can't have a parent+child schema evaluated with
> > another child (or parent+child) schema. This is why the graph schema
> > is done the way it is and why we're splitting spi-controller.yaml
> > child node schema out to spi-peripheral.yaml.
>
> Let me give an example based on a schema that's already upstream. So
> looking at this:
>
> Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
>
> it does include spi-controller.yaml via an allOf: [ $ref: ... ], so it
> uses unevaluatedProperties to validate against any generic SPI
> controller properties. For example, #address-cells and #size-cells are
> validated based on the schema from spi-controller.yaml.
>
> However, if I now apply the following patch to add an undocumented
> property to the example, then validation doesn't fail as I would expect
> it to.
Indeed you are right. The problem is 'additionalProperties: true' in
spi-controller.yaml makes everything evaluated. I thought
'additionalProperties: true' was equivalent to the default, but that's
not how it's working. Now to figure out if this is correct operation
or not. No wonder there were relatively few fixes when
'unevaluatedProperties' got implemented...
Rob
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v2 13/16] dt-bindings: i2c: tegra-bpmp: Convert to json-schema
2021-12-02 21:08 ` Rob Herring
@ 2021-12-02 22:38 ` Rob Herring
0 siblings, 0 replies; 42+ messages in thread
From: Rob Herring @ 2021-12-02 22:38 UTC (permalink / raw)
To: Thierry Reding; +Cc: Jon Hunter, devicetree, linux-tegra
On Thu, Dec 2, 2021 at 3:08 PM Rob Herring <robh@kernel.org> wrote:
>
> On Thu, Dec 2, 2021 at 11:55 AM Thierry Reding <thierry.reding@gmail.com> wrote:
> >
> > On Wed, Dec 01, 2021 at 12:42:07PM -0600, Rob Herring wrote:
> > > On Wed, Dec 1, 2021 at 11:42 AM Thierry Reding <thierry.reding@gmail.com> wrote:
> > > >
[...]
> > > > However, a side-effect seems to be that now it also ignores any
> > > > properties that aren't defined anywhere. So for example if I touch
> > > > up the example in firmware/nvidia,tegra186-bpmp.yaml and add a bogus
> > > > "foo-bar = <0>;" property in the BPMP I2C node, then it'll blindly
> > > > accept that as valid.
> > >
> > > Do you have unevaluatedProperties within the i2c node? It only applies
> > > to 1 level, and you can't have a parent+child schema evaluated with
> > > another child (or parent+child) schema. This is why the graph schema
> > > is done the way it is and why we're splitting spi-controller.yaml
> > > child node schema out to spi-peripheral.yaml.
> >
> > Let me give an example based on a schema that's already upstream. So
> > looking at this:
> >
> > Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
> >
> > it does include spi-controller.yaml via an allOf: [ $ref: ... ], so it
> > uses unevaluatedProperties to validate against any generic SPI
> > controller properties. For example, #address-cells and #size-cells are
> > validated based on the schema from spi-controller.yaml.
> >
> > However, if I now apply the following patch to add an undocumented
> > property to the example, then validation doesn't fail as I would expect
> > it to.
>
> Indeed you are right. The problem is 'additionalProperties: true' in
> spi-controller.yaml makes everything evaluated. I thought
> 'additionalProperties: true' was equivalent to the default, but that's
> not how it's working. Now to figure out if this is correct operation
> or not. No wonder there were relatively few fixes when
> 'unevaluatedProperties' got implemented...
Based on the json-schema test cases[1], it looks like the tool is
doing the right thing and our schemas are wrong.
It's a quick fixup in the tools though to just delete any
'additionalProperties: true':
index 3cc5e428b0eb..a0f22aab935a 100644
--- a/dtschema/lib.py
+++ b/dtschema/lib.py
@@ -367,6 +367,9 @@ def fixup_sub_schema(schema, is_prop):
if not isinstance(schema, dict):
return
+ if 'additionalProperties' in schema and
schema['additionalProperties'] == True:
+ schema.pop('additionalProperties', None)
+
schema.pop('description', None)
fixup_interrupts(schema)
if is_prop:
I'm leaning towards this route besides being easy because the whole
reason for the explicit 'additionalProperties: true' was so that
missing 'additionalProperties' is flagged as an error. The only other
way I've come up with handling this is making common schema use a
different meta-schema.
The result with the above is about 150 warnings. I quickly got this
down to 100 with only a couple of fixes, but the rest appear to be
individual schemas...
Rob
[1] https://github.com/json-schema-org/JSON-Schema-Test-Suite/blob/master/tests/draft2019-09/unevaluatedProperties.json#L230
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v2 14/16] dt-bindings: thermal: tegra186-bpmp: Convert to json-schema
2021-11-19 14:38 [PATCH v2 00/16] dt-bindings: Convert Tegra DT bindings to json-schema Thierry Reding
` (12 preceding siblings ...)
2021-11-19 14:38 ` [PATCH v2 13/16] dt-bindings: i2c: tegra-bpmp: " Thierry Reding
@ 2021-11-19 14:38 ` Thierry Reding
2021-11-30 1:44 ` Rob Herring
2021-11-19 14:38 ` [PATCH v2 15/16] dt-bindings: serial: tegra-tcu: " Thierry Reding
` (2 subsequent siblings)
16 siblings, 1 reply; 42+ messages in thread
From: Thierry Reding @ 2021-11-19 14:38 UTC (permalink / raw)
To: Thierry Reding, Rob Herring; +Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Convert the Tegra186 (and later) BPMP thermal device tree bindings from
the free-form text format to json-schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
.../thermal/nvidia,tegra186-bpmp-thermal.txt | 33 ---------------
.../thermal/nvidia,tegra186-bpmp-thermal.yaml | 42 +++++++++++++++++++
2 files changed, 42 insertions(+), 33 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt
create mode 100644 Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.yaml
diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt b/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt
deleted file mode 100644
index fc87f6aa1b8f..000000000000
--- a/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-NVIDIA Tegra186 BPMP thermal sensor
-
-In Tegra186, the BPMP (Boot and Power Management Processor) implements an
-interface that is used to read system temperatures, including CPU cluster
-and GPU temperatures. This binding describes the thermal sensor that is
-exposed by BPMP.
-
-The BPMP thermal node must be located directly inside the main BPMP node. See
-../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding.
-
-This node represents a thermal sensor. See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for details of the
-core thermal binding.
-
-Required properties:
-- compatible:
- Array of strings.
- One of:
- - "nvidia,tegra186-bpmp-thermal"
- - "nvidia,tegra194-bpmp-thermal"
-- #thermal-sensor-cells: Cell for sensor index.
- Single-cell integer.
- Must be <1>.
-
-Example:
-
-bpmp {
- ...
-
- bpmp_thermal: thermal {
- compatible = "nvidia,tegra186-bpmp-thermal";
- #thermal-sensor-cells = <1>;
- };
-};
diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.yaml b/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.yaml
new file mode 100644
index 000000000000..c91fd07e4061
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/thermal/nvidia,tegra186-bpmp-thermal.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra186 (and later) BPMP thermal sensor
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+
+description: |
+ In Tegra186, the BPMP (Boot and Power Management Processor) implements
+ an interface that is used to read system temperatures, including CPU
+ cluster and GPU temperatures. This binding describes the thermal
+ sensor that is exposed by BPMP.
+
+ The BPMP thermal node must be located directly inside the main BPMP
+ node. See ../firmware/nvidia,tegra186-bpmp.yaml for details of the
+ BPMP binding.
+
+ This node represents a thermal sensor. See
+
+ Documentation/devicetree/bindings/thermal/thermal-sensor.yaml
+
+ for details of the core thermal binding.
+
+properties:
+ compatible:
+ enum:
+ - nvidia,tegra186-bpmp-thermal
+ - nvidia,tegra194-bpmp-thermal
+
+ '#thermal-sensor-cells':
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Number of cells needed in the phandle specifier to
+ identify a given sensor. Must be 1 and the single cell specifies
+ the sensor index.
+ const: 1
+
+additionalProperties: false
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH v2 14/16] dt-bindings: thermal: tegra186-bpmp: Convert to json-schema
2021-11-19 14:38 ` [PATCH v2 14/16] dt-bindings: thermal: tegra186-bpmp: " Thierry Reding
@ 2021-11-30 1:44 ` Rob Herring
0 siblings, 0 replies; 42+ messages in thread
From: Rob Herring @ 2021-11-30 1:44 UTC (permalink / raw)
To: Thierry Reding; +Cc: devicetree, Jon Hunter, linux-tegra, Rob Herring
On Fri, 19 Nov 2021 15:38:37 +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Convert the Tegra186 (and later) BPMP thermal device tree bindings from
> the free-form text format to json-schema.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> .../thermal/nvidia,tegra186-bpmp-thermal.txt | 33 ---------------
> .../thermal/nvidia,tegra186-bpmp-thermal.yaml | 42 +++++++++++++++++++
> 2 files changed, 42 insertions(+), 33 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt
> create mode 100644 Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v2 15/16] dt-bindings: serial: tegra-tcu: Convert to json-schema
2021-11-19 14:38 [PATCH v2 00/16] dt-bindings: Convert Tegra DT bindings to json-schema Thierry Reding
` (13 preceding siblings ...)
2021-11-19 14:38 ` [PATCH v2 14/16] dt-bindings: thermal: tegra186-bpmp: " Thierry Reding
@ 2021-11-19 14:38 ` Thierry Reding
2021-11-23 16:34 ` Rob Herring
2021-11-30 1:45 ` Rob Herring
2021-11-19 14:38 ` [PATCH v2 16/16] dt-bindings: serial: Document Tegra234 TCU Thierry Reding
2021-12-09 17:05 ` [PATCH v2 00/16] dt-bindings: Convert Tegra DT bindings to json-schema Thierry Reding
16 siblings, 2 replies; 42+ messages in thread
From: Thierry Reding @ 2021-11-19 14:38 UTC (permalink / raw)
To: Thierry Reding, Rob Herring; +Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Convert the Tegra TCU device tree bindings to json-schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
.../bindings/serial/nvidia,tegra194-tcu.txt | 35 ------------
.../bindings/serial/nvidia,tegra194-tcu.yaml | 56 +++++++++++++++++++
2 files changed, 56 insertions(+), 35 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt
create mode 100644 Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml
diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt
deleted file mode 100644
index 085a8591accd..000000000000
--- a/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt
+++ /dev/null
@@ -1,35 +0,0 @@
-NVIDIA Tegra Combined UART (TCU)
-
-The TCU is a system for sharing a hardware UART instance among multiple
-systems within the Tegra SoC. It is implemented through a mailbox-
-based protocol where each "virtual UART" has a pair of mailboxes, one
-for transmitting and one for receiving, that is used to communicate
-with the hardware implementing the TCU.
-
-Required properties:
-- name : Should be tcu
-- compatible
- Array of strings
- One of:
- - "nvidia,tegra194-tcu"
-- mbox-names:
- "rx" - Mailbox for receiving data from hardware UART
- "tx" - Mailbox for transmitting data to hardware UART
-- mboxes: Mailboxes corresponding to the mbox-names.
-
-This node is a mailbox consumer. See the following files for details of
-the mailbox subsystem, and the specifiers implemented by the relevant
-provider(s):
-
-- .../mailbox/mailbox.txt
-- .../mailbox/nvidia,tegra186-hsp.txt
-
-Example bindings:
------------------
-
-tcu: tcu {
- compatible = "nvidia,tegra194-tcu";
- mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM 0>,
- <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM 1>;
- mbox-names = "rx", "tx";
-};
diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml
new file mode 100644
index 000000000000..7987eca0bb52
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/serial/nvidia,tegra194-tcu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Combined UART (TCU)
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jonathan Hunter <jonathanh@nvidia.com>
+
+description:
+ The TCU is a system for sharing a hardware UART instance among multiple
+ systems within the Tegra SoC. It is implemented through a mailbox-
+ based protocol where each "virtual UART" has a pair of mailboxes, one
+ for transmitting and one for receiving, that is used to communicate
+ with the hardware implementing the TCU.
+
+properties:
+ $nodename:
+ pattern: "^serial(@.*)?$"
+
+ compatible:
+ const: nvidia,tegra194-tcu
+
+ mbox-names:
+ items:
+ - const: rx
+ - const: tx
+
+ mboxes:
+ description: |
+ List of phandles to mailbox channels used for receiving and
+ transmitting data from and to the hardware UART.
+ items:
+ - description: mailbox for receiving data from hardware UART
+ - description: mailbox for transmitting data to hardware UART
+
+required:
+ - compatible
+ - mbox-names
+ - mboxes
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/mailbox/tegra186-hsp.h>
+
+ tcu: serial {
+ compatible = "nvidia,tegra194-tcu";
+ mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM 0>,
+ <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM 1>;
+ mbox-names = "rx", "tx";
+ };
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH v2 15/16] dt-bindings: serial: tegra-tcu: Convert to json-schema
2021-11-19 14:38 ` [PATCH v2 15/16] dt-bindings: serial: tegra-tcu: " Thierry Reding
@ 2021-11-23 16:34 ` Rob Herring
2021-11-30 1:45 ` Rob Herring
1 sibling, 0 replies; 42+ messages in thread
From: Rob Herring @ 2021-11-23 16:34 UTC (permalink / raw)
To: Thierry Reding; +Cc: linux-tegra, devicetree, Rob Herring, Jon Hunter
On Fri, 19 Nov 2021 15:38:38 +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Convert the Tegra TCU device tree bindings to json-schema.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> .../bindings/serial/nvidia,tegra194-tcu.txt | 35 ------------
> .../bindings/serial/nvidia,tegra194-tcu.yaml | 56 +++++++++++++++++++
> 2 files changed, 56 insertions(+), 35 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt
> create mode 100644 Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml
>
Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.
Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.
Full log is available here: https://patchwork.ozlabs.org/patch/1557181
tcu: $nodename:0: 'tcu' does not match '^serial(@.*)?$'
arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dt.yaml
arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dt.yaml
arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0001.dt.yaml
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 15/16] dt-bindings: serial: tegra-tcu: Convert to json-schema
2021-11-19 14:38 ` [PATCH v2 15/16] dt-bindings: serial: tegra-tcu: " Thierry Reding
2021-11-23 16:34 ` Rob Herring
@ 2021-11-30 1:45 ` Rob Herring
1 sibling, 0 replies; 42+ messages in thread
From: Rob Herring @ 2021-11-30 1:45 UTC (permalink / raw)
To: Thierry Reding; +Cc: linux-tegra, Jon Hunter, Rob Herring, devicetree
On Fri, 19 Nov 2021 15:38:38 +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Convert the Tegra TCU device tree bindings to json-schema.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> .../bindings/serial/nvidia,tegra194-tcu.txt | 35 ------------
> .../bindings/serial/nvidia,tegra194-tcu.yaml | 56 +++++++++++++++++++
> 2 files changed, 56 insertions(+), 35 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt
> create mode 100644 Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v2 16/16] dt-bindings: serial: Document Tegra234 TCU
2021-11-19 14:38 [PATCH v2 00/16] dt-bindings: Convert Tegra DT bindings to json-schema Thierry Reding
` (14 preceding siblings ...)
2021-11-19 14:38 ` [PATCH v2 15/16] dt-bindings: serial: tegra-tcu: " Thierry Reding
@ 2021-11-19 14:38 ` Thierry Reding
2021-11-23 16:34 ` Rob Herring
2021-11-30 1:45 ` Rob Herring
2021-12-09 17:05 ` [PATCH v2 00/16] dt-bindings: Convert Tegra DT bindings to json-schema Thierry Reding
16 siblings, 2 replies; 42+ messages in thread
From: Thierry Reding @ 2021-11-19 14:38 UTC (permalink / raw)
To: Thierry Reding, Rob Herring; +Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Add the compatible string for the TCU found on the Tegra234 SoC.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
.../devicetree/bindings/serial/nvidia,tegra194-tcu.yaml | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml
index 7987eca0bb52..e2d111b3e0b0 100644
--- a/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml
+++ b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml
@@ -22,7 +22,12 @@ properties:
pattern: "^serial(@.*)?$"
compatible:
- const: nvidia,tegra194-tcu
+ oneOf:
+ - const: nvidia,tegra194-tcu
+ - items:
+ - enum:
+ - nvidia,tegra234-tcu
+ - const: nvidia,tegra194-tcu
mbox-names:
items:
--
2.33.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH v2 16/16] dt-bindings: serial: Document Tegra234 TCU
2021-11-19 14:38 ` [PATCH v2 16/16] dt-bindings: serial: Document Tegra234 TCU Thierry Reding
@ 2021-11-23 16:34 ` Rob Herring
2021-11-30 1:45 ` Rob Herring
1 sibling, 0 replies; 42+ messages in thread
From: Rob Herring @ 2021-11-23 16:34 UTC (permalink / raw)
To: Thierry Reding; +Cc: Jon Hunter, devicetree, Rob Herring, linux-tegra
On Fri, 19 Nov 2021 15:38:39 +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Add the compatible string for the TCU found on the Tegra234 SoC.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> .../devicetree/bindings/serial/nvidia,tegra194-tcu.yaml | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.
Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.
Full log is available here: https://patchwork.ozlabs.org/patch/1557183
tcu: $nodename:0: 'tcu' does not match '^serial(@.*)?$'
arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dt.yaml
arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dt.yaml
arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0001.dt.yaml
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 16/16] dt-bindings: serial: Document Tegra234 TCU
2021-11-19 14:38 ` [PATCH v2 16/16] dt-bindings: serial: Document Tegra234 TCU Thierry Reding
2021-11-23 16:34 ` Rob Herring
@ 2021-11-30 1:45 ` Rob Herring
1 sibling, 0 replies; 42+ messages in thread
From: Rob Herring @ 2021-11-30 1:45 UTC (permalink / raw)
To: Thierry Reding; +Cc: linux-tegra, Jon Hunter, devicetree, Rob Herring
On Fri, 19 Nov 2021 15:38:39 +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Add the compatible string for the TCU found on the Tegra234 SoC.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> .../devicetree/bindings/serial/nvidia,tegra194-tcu.yaml | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 00/16] dt-bindings: Convert Tegra DT bindings to json-schema
2021-11-19 14:38 [PATCH v2 00/16] dt-bindings: Convert Tegra DT bindings to json-schema Thierry Reding
` (15 preceding siblings ...)
2021-11-19 14:38 ` [PATCH v2 16/16] dt-bindings: serial: Document Tegra234 TCU Thierry Reding
@ 2021-12-09 17:05 ` Thierry Reding
16 siblings, 0 replies; 42+ messages in thread
From: Thierry Reding @ 2021-12-09 17:05 UTC (permalink / raw)
To: Rob Herring; +Cc: Jon Hunter, devicetree, linux-tegra
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On Fri, Nov 19, 2021 at 03:38:23PM +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Hi,
>
> this set of patches converts some Tegra-specific DT bindings to
> json-schema and, where appropriate, adds Tegra234 compatible strings.
> The goal is to prepare existing schemas to allow validation of the
> existing Tegra234 device tree files.
>
> I've got a follow-up series that adds more Tegra234 support and will
> extend/convert bindings along the way to keep things validatable.
>
> Rob, since all of these are Tegra-specific and given that I have some
> follow-up work based on these, I think it'd be best if I picked these
> up into the Tegra tree once you're happy with them.
>
> Changes in v2:
> - address various linting and validation warnings
> - add patch for BPMP thermal bindings
>
> Thierry
>
> Thierry Reding (16):
> dt-bindings: misc: Convert Tegra MISC to json-schema
> dt-bindings: mmc: tegra: Convert to json-schema
> dt-bindings: mailbox: tegra: Convert to json-schema
> dt-bindings: mailbox: tegra: Document Tegra234 HSP
> dt-bindings: rtc: tegra: Convert to json-schema
> dt-bindings: rtc: tegra: Document Tegra234 RTC
> dt-bindings: fuse: tegra: Convert to json-schema
> dt-bindings: fuse: tegra: Document Tegra234 FUSE
> dt-bindings: mmc: tegra: Document Tegra234 SDHCI
> dt-bindings: serial: 8250: Document Tegra234 UART
> dt-bindings: tegra: pmc: Convert to json-schema
> dt-bindings: firmware: tegra: Convert to json-schema
> dt-bindings: i2c: tegra-bpmp: Convert to json-schema
> dt-bindings: thermal: tegra186-bpmp: Convert to json-schema
> dt-bindings: serial: tegra-tcu: Convert to json-schema
> dt-bindings: serial: Document Tegra234 TCU
Hi Rob,
you applied v3 of patch 13 in this series that I sent separately but had
reviewed or acked all the others. Do you want to pick these up yourself,
or should I take them in via the Tegra tree? If you'd rather pick them
up yourself I can resend the remainder of the series.
Sorry, splitting up the patches like that was probably more confusing
than it was worth it.
Thierry
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^ permalink raw reply [flat|nested] 42+ messages in thread