* [PATCH v7 0/4] Rx mode support for Cadence DPHY @ 2021-12-27 10:55 Pratyush Yadav 2021-12-27 10:55 ` [PATCH v7 1/4] phy: cadence: Add Cadence D-PHY Rx driver Pratyush Yadav ` (3 more replies) 0 siblings, 4 replies; 12+ messages in thread From: Pratyush Yadav @ 2021-12-27 10:55 UTC (permalink / raw) To: Vinod Koul Cc: Laurent Pinchart, Paul Kocialkowski, Tomi Valkeinen, Vignesh Raghavendra, Kishon Vijay Abraham I, Pratyush Yadav, Rob Herring, Swapnil Jakhade, devicetree, linux-kernel, linux-phy Hi, This series adds support for Cadence DPHY Rx driver. It has been split off from [0] to facilitate easier merging. I have still kept the version number to maintain continuity with the previous patches. The earlier version used the same binding for Tx and Rx DPHY. With the separate driver, I have added a separate binding. But I am still keeping the old conversion patch in this series since I have already done the work in converting the binding to yaml, might as well get it merged. Tested on TI's J721E with OV5640 sensor. [0] https://patchwork.linuxtv.org/project/linux-media/list/?series=5526&state=%2A&archive=both Changes in v7: - Add spaces after { and before } in the bands table. - Drop the wrapping around the for loop on cdns_dphy_rx_get_band_ctrl(). - Make cdns_dphy_rx_wait_for_bit() inline. - Print an error message if registering PHY provider fails. Changes in v6: - Add a new binding for DPHY Rx. - Move the DPHY Rx part to a separate driver. - Drop Rx specific changes from the cdns,dphy.yaml binding. Keep those in cdns,dphy-rx.yaml Changes in v5: - Use the new cdns_dphy_info to specify PHY ops. - Re-order include in alphabetical order. - Make bands const. - Drop num_bands. - Make i, lanes unsigned. - Drop the maximum check in cdns_dphy_rx_get_band_ctrl(). Let the loop complete and return -EOPNOTSUPP when we reach the end. - Drop the "rate < bands[i].min_rate" check since the bands are in ascending order. - Move data_lane_ctrl to start of function and make it static const. Changes in v4: - Drop the submode parts. Use a different compatible for the Rx ops. - Make bands and num_bands static. - Drop the submode patches. Use a different compatible for Rx mode DPHY instead. Changes in v3: - Use a table to select the band. - Use a table to poll the data lane ready bits. - Multiply the DPHY HS clock rate by 2 to get the bit rate since the clock is DDR. - Add Rob's R-by. Changes in v2: - Drop reg description. - Add a description for each DPHY clock. - Rename dphy@... to phy@... in example. - Add Laurent's R-by. - Re-order subject prefixes. - Add power-domain to the example. - Add Laurent's R-by. - Re-order subject prefixes. Pratyush Yadav (4): phy: cadence: Add Cadence D-PHY Rx driver phy: dt-bindings: Convert Cadence DPHY binding to YAML phy: dt-bindings: cdns,dphy: add power-domains property phy: dt-bindings: Add Cadence D-PHY Rx bindings .../devicetree/bindings/phy/cdns,dphy-rx.yaml | 42 +++ .../devicetree/bindings/phy/cdns,dphy.txt | 20 -- .../devicetree/bindings/phy/cdns,dphy.yaml | 56 ++++ drivers/phy/cadence/Kconfig | 8 + drivers/phy/cadence/Makefile | 1 + drivers/phy/cadence/cdns-dphy-rx.c | 255 ++++++++++++++++++ 6 files changed, 362 insertions(+), 20 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/cdns,dphy-rx.yaml delete mode 100644 Documentation/devicetree/bindings/phy/cdns,dphy.txt create mode 100644 Documentation/devicetree/bindings/phy/cdns,dphy.yaml create mode 100644 drivers/phy/cadence/cdns-dphy-rx.c -- 2.33.1.835.ge9e5ba39a7 ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v7 1/4] phy: cadence: Add Cadence D-PHY Rx driver 2021-12-27 10:55 [PATCH v7 0/4] Rx mode support for Cadence DPHY Pratyush Yadav @ 2021-12-27 10:55 ` Pratyush Yadav 2021-12-29 23:30 ` Laurent Pinchart ` (2 more replies) 2021-12-27 10:55 ` [PATCH v7 2/4] phy: dt-bindings: Convert Cadence DPHY binding to YAML Pratyush Yadav ` (2 subsequent siblings) 3 siblings, 3 replies; 12+ messages in thread From: Pratyush Yadav @ 2021-12-27 10:55 UTC (permalink / raw) To: Vinod Koul Cc: Pratyush Yadav, Laurent Pinchart, Paul Kocialkowski, Tomi Valkeinen, Vignesh Raghavendra, Kishon Vijay Abraham I, Rob Herring, Swapnil Jakhade, devicetree, linux-kernel, linux-phy The Cadence D-PHY can be configured in Tx (DSI) mode or Rx (CSI) mode. Both modes have a different programming sequence and share little among them. In addition, a PHY configured in Tx mode cannot be used in Rx mode and vice versa. For this reason, create a separate driver for the Rx mode to make it easier to read and maintain. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> --- Changes in v7: - Add spaces after { and before } in the bands table. - Drop the wrapping around the for loop on cdns_dphy_rx_get_band_ctrl(). - Make cdns_dphy_rx_wait_for_bit() inline. - Print an error message if registering PHY provider fails. Changes in v6: - Move to a separate driver. Changes in v5: - Use the new cdns_dphy_info to specify PHY ops. - Re-order include in alphabetical order. - Make bands const. - Drop num_bands. - Make i, lanes unsigned. - Drop the maximum check in cdns_dphy_rx_get_band_ctrl(). Let the loop complete and return -EOPNOTSUPP when we reach the end. - Drop the "rate < bands[i].min_rate" check since the bands are in ascending order. - Move data_lane_ctrl to start of function and make it static const. Changes in v4: - Drop the submode parts. Use a different compatible for the Rx ops. - Make bands and num_bands static. Changes in v3: - Use a table to select the band. - Use a table to poll the data lane ready bits. - Multiply the DPHY HS clock rate by 2 to get the bit rate since the clock is DDR. drivers/phy/cadence/Kconfig | 8 + drivers/phy/cadence/Makefile | 1 + drivers/phy/cadence/cdns-dphy-rx.c | 255 +++++++++++++++++++++++++++++ 3 files changed, 264 insertions(+) create mode 100644 drivers/phy/cadence/cdns-dphy-rx.c diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig index a62910ff5591..1adde2d99ae7 100644 --- a/drivers/phy/cadence/Kconfig +++ b/drivers/phy/cadence/Kconfig @@ -22,6 +22,14 @@ config PHY_CADENCE_DPHY system. If M is selected, the module will be called cdns-dphy. +config PHY_CADENCE_DPHY_RX + tristate "Cadence D-PHY Rx Support" + depends on HAS_IOMEM && OF + select GENERIC_PHY + select GENERIC_PHY_MIPI_DPHY + help + Support for Cadence D-PHY in Rx configuration. + config PHY_CADENCE_SIERRA tristate "Cadence Sierra PHY Driver" depends on OF && HAS_IOMEM && RESET_CONTROLLER diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile index 26e16bd34efe..e17f035ddece 100644 --- a/drivers/phy/cadence/Makefile +++ b/drivers/phy/cadence/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_PHY_CADENCE_TORRENT) += phy-cadence-torrent.o obj-$(CONFIG_PHY_CADENCE_DPHY) += cdns-dphy.o +obj-$(CONFIG_PHY_CADENCE_DPHY_RX) += cdns-dphy-rx.o obj-$(CONFIG_PHY_CADENCE_SIERRA) += phy-cadence-sierra.o obj-$(CONFIG_PHY_CADENCE_SALVO) += phy-cadence-salvo.o diff --git a/drivers/phy/cadence/cdns-dphy-rx.c b/drivers/phy/cadence/cdns-dphy-rx.c new file mode 100644 index 000000000000..47a5b67ded58 --- /dev/null +++ b/drivers/phy/cadence/cdns-dphy-rx.c @@ -0,0 +1,255 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include <linux/bitfield.h> +#include <linux/bitops.h> +#include <linux/io.h> +#include <linux/iopoll.h> +#include <linux/module.h> +#include <linux/phy/phy.h> +#include <linux/phy/phy-mipi-dphy.h> +#include <linux/platform_device.h> + +#define DPHY_PMA_CMN(reg) (reg) +#define DPHY_PCS(reg) (0xb00 + (reg)) +#define DPHY_ISO(reg) (0xc00 + (reg)) + +#define DPHY_CMN_SSM DPHY_PMA_CMN(0x20) +#define DPHY_CMN_RX_MODE_EN BIT(10) +#define DPHY_CMN_RX_BANDGAP_TIMER_MASK GENMASK(8, 1) +#define DPHY_CMN_SSM_EN BIT(0) + +#define DPHY_CMN_RX_BANDGAP_TIMER 0x14 + +#define DPHY_BAND_CFG DPHY_PCS(0x0) +#define DPHY_BAND_CFG_RIGHT_BAND GENMASK(9, 5) +#define DPHY_BAND_CFG_LEFT_BAND GENMASK(4, 0) + +#define DPHY_POWER_ISLAND_EN_DATA DPHY_PCS(0x8) +#define DPHY_POWER_ISLAND_EN_DATA_VAL 0xaaaaaaaa + +#define DPHY_POWER_ISLAND_EN_CLK DPHY_PCS(0xc) +#define DPHY_POWER_ISLAND_EN_CLK_VAL 0xaa + +#define DPHY_ISO_CL_CTRL_L DPHY_ISO(0x10) +#define DPHY_ISO_DL_CTRL_L0 DPHY_ISO(0x14) +#define DPHY_ISO_DL_CTRL_L1 DPHY_ISO(0x20) +#define DPHY_ISO_DL_CTRL_L2 DPHY_ISO(0x30) +#define DPHY_ISO_DL_CTRL_L3 DPHY_ISO(0x3c) + +#define DPHY_ISO_LANE_READY_BIT 0 +#define DPHY_ISO_LANE_READY_TIMEOUT_MS 100UL + +#define DPHY_LANES_MIN 1 +#define DPHY_LANES_MAX 4 + +struct cdns_dphy_rx { + void __iomem *regs; + struct device *dev; + struct phy *phy; +}; + +struct cdns_dphy_rx_band { + /* Rates are in Mbps. */ + unsigned int min_rate; + unsigned int max_rate; +}; + +/* Order of bands is important since the index is the band number. */ +static const struct cdns_dphy_rx_band bands[] = { + { 80, 100 }, { 100, 120 }, { 120, 160 }, { 160, 200 }, { 200, 240 }, + { 240, 280 }, { 280, 320 }, { 320, 360 }, { 360, 400 }, { 400, 480 }, + { 480, 560 }, { 560, 640 }, { 640, 720 }, { 720, 800 }, { 800, 880 }, + { 880, 1040 }, { 1040, 1200 }, { 1200, 1350 }, { 1350, 1500 }, + { 1500, 1750 }, { 1750, 2000 }, { 2000, 2250 }, { 2250, 2500 } +}; + +static int cdns_dphy_rx_power_on(struct phy *phy) +{ + struct cdns_dphy_rx *dphy = phy_get_drvdata(phy); + + /* Start RX state machine. */ + writel(DPHY_CMN_SSM_EN | DPHY_CMN_RX_MODE_EN | + FIELD_PREP(DPHY_CMN_RX_BANDGAP_TIMER_MASK, + DPHY_CMN_RX_BANDGAP_TIMER), + dphy->regs + DPHY_CMN_SSM); + + return 0; +} + +static int cdns_dphy_rx_power_off(struct phy *phy) +{ + struct cdns_dphy_rx *dphy = phy_get_drvdata(phy); + + writel(0, dphy->regs + DPHY_CMN_SSM); + + return 0; +} + +static int cdns_dphy_rx_get_band_ctrl(unsigned long hs_clk_rate) +{ + unsigned int rate, i; + + rate = hs_clk_rate / 1000000UL; + /* Since CSI-2 clock is DDR, the bit rate is twice the clock rate. */ + rate *= 2; + + if (rate < bands[0].min_rate) + return -EOPNOTSUPP; + + for (i = 0; i < ARRAY_SIZE(bands); i++) + if (rate < bands[i].max_rate) + return i; + + return -EOPNOTSUPP; +} + +static inline int cdns_dphy_rx_wait_for_bit(void __iomem *addr, + unsigned int bit) +{ + u32 val; + + return readl_relaxed_poll_timeout(addr, val, val & BIT(bit), 10, + DPHY_ISO_LANE_READY_TIMEOUT_MS * 1000); +} + +static int cdns_dphy_rx_wait_lane_ready(struct cdns_dphy_rx *dphy, + unsigned int lanes) +{ + static const u32 data_lane_ctrl[] = {DPHY_ISO_DL_CTRL_L0, + DPHY_ISO_DL_CTRL_L1, + DPHY_ISO_DL_CTRL_L2, + DPHY_ISO_DL_CTRL_L3}; + void __iomem *reg = dphy->regs; + unsigned int i; + int ret; + + /* Data lanes. Minimum one lane is mandatory. */ + if (lanes < DPHY_LANES_MIN || lanes > DPHY_LANES_MAX) + return -EINVAL; + + /* Clock lane */ + ret = cdns_dphy_rx_wait_for_bit(reg + DPHY_ISO_CL_CTRL_L, + DPHY_ISO_LANE_READY_BIT); + if (ret) + return ret; + + for (i = 0; i < lanes; i++) { + ret = cdns_dphy_rx_wait_for_bit(reg + data_lane_ctrl[i], + DPHY_ISO_LANE_READY_BIT); + if (ret) + return ret; + } + + return 0; +} + +static int cdns_dphy_rx_configure(struct phy *phy, + union phy_configure_opts *opts) +{ + struct cdns_dphy_rx *dphy = phy_get_drvdata(phy); + unsigned int reg; + int band_ctrl, ret; + + band_ctrl = cdns_dphy_rx_get_band_ctrl(opts->mipi_dphy.hs_clk_rate); + if (band_ctrl < 0) + return band_ctrl; + + reg = FIELD_PREP(DPHY_BAND_CFG_LEFT_BAND, band_ctrl) | + FIELD_PREP(DPHY_BAND_CFG_RIGHT_BAND, band_ctrl); + writel(reg, dphy->regs + DPHY_BAND_CFG); + + /* + * Set the required power island phase 2 time. This is mandated by DPHY + * specs. + */ + reg = DPHY_POWER_ISLAND_EN_DATA_VAL; + writel(reg, dphy->regs + DPHY_POWER_ISLAND_EN_DATA); + reg = DPHY_POWER_ISLAND_EN_CLK_VAL; + writel(reg, dphy->regs + DPHY_POWER_ISLAND_EN_CLK); + + ret = cdns_dphy_rx_wait_lane_ready(dphy, opts->mipi_dphy.lanes); + if (ret) { + dev_err(dphy->dev, "DPHY wait for lane ready timeout\n"); + return ret; + } + + return 0; +} + +static int cdns_dphy_rx_validate(struct phy *phy, enum phy_mode mode, + int submode, union phy_configure_opts *opts) +{ + int ret; + + if (mode != PHY_MODE_MIPI_DPHY) + return -EINVAL; + + ret = cdns_dphy_rx_get_band_ctrl(opts->mipi_dphy.hs_clk_rate); + if (ret < 0) + return ret; + + return phy_mipi_dphy_config_validate(&opts->mipi_dphy); +} + +static const struct phy_ops cdns_dphy_rx_ops = { + .power_on = cdns_dphy_rx_power_on, + .power_off = cdns_dphy_rx_power_off, + .configure = cdns_dphy_rx_configure, + .validate = cdns_dphy_rx_validate, +}; + +static int cdns_dphy_rx_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct phy_provider *provider; + struct cdns_dphy_rx *dphy; + + dphy = devm_kzalloc(dev, sizeof(*dphy), GFP_KERNEL); + if (!dphy) + return -ENOMEM; + + dev_set_drvdata(dev, dphy); + dphy->dev = dev; + + dphy->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(dphy->regs)) + return PTR_ERR(dphy->regs); + + dphy->phy = devm_phy_create(dev, NULL, &cdns_dphy_rx_ops); + if (IS_ERR(dphy->phy)) { + dev_err(dev, "Failed to create PHY: %d\n", PTR_ERR(dphy->phy)); + return PTR_ERR(dphy->phy); + } + + phy_set_drvdata(dphy->phy, dphy); + provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + if (IS_ERR(provider)) { + dev_err(dev, "Failed to register PHY provider: %d\n", + PTR_ERR(provider)); + return PTR_ERR(provider); + } + + return 0; +} + +static const struct of_device_id cdns_dphy_rx_of_match[] = { + { .compatible = "cdns,dphy-rx" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, cdns_dphy_rx_of_match); + +static struct platform_driver cdns_dphy_rx_platform_driver = { + .probe = cdns_dphy_rx_probe, + .driver = { + .name = "cdns-mipi-dphy-rx", + .of_match_table = cdns_dphy_rx_of_match, + }, +}; +module_platform_driver(cdns_dphy_rx_platform_driver); + +MODULE_AUTHOR("Pratyush Yadav <p.yadav@ti.com>"); +MODULE_DESCRIPTION("Cadence D-PHY Rx Driver"); +MODULE_LICENSE("GPL v2"); -- 2.33.1.835.ge9e5ba39a7 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v7 1/4] phy: cadence: Add Cadence D-PHY Rx driver 2021-12-27 10:55 ` [PATCH v7 1/4] phy: cadence: Add Cadence D-PHY Rx driver Pratyush Yadav @ 2021-12-29 23:30 ` Laurent Pinchart 2021-12-31 10:28 ` Pratyush Yadav 2022-01-04 11:11 ` kernel test robot 2022-01-05 5:27 ` kernel test robot 2 siblings, 1 reply; 12+ messages in thread From: Laurent Pinchart @ 2021-12-29 23:30 UTC (permalink / raw) To: Pratyush Yadav Cc: Vinod Koul, Paul Kocialkowski, Tomi Valkeinen, Vignesh Raghavendra, Kishon Vijay Abraham I, Rob Herring, Swapnil Jakhade, devicetree, linux-kernel, linux-phy Hi Pratyush, Thank you for the patch. On Mon, Dec 27, 2021 at 04:25:42PM +0530, Pratyush Yadav wrote: > The Cadence D-PHY can be configured in Tx (DSI) mode or Rx (CSI) mode. > Both modes have a different programming sequence and share little among > them. In addition, a PHY configured in Tx mode cannot be used in Rx mode > and vice versa. For this reason, create a separate driver for the Rx > mode to make it easier to read and maintain. > > Signed-off-by: Pratyush Yadav <p.yadav@ti.com> > > --- > > Changes in v7: > - Add spaces after { and before } in the bands table. > - Drop the wrapping around the for loop on cdns_dphy_rx_get_band_ctrl(). > - Make cdns_dphy_rx_wait_for_bit() inline. > - Print an error message if registering PHY provider fails. > > Changes in v6: > - Move to a separate driver. > > Changes in v5: > - Use the new cdns_dphy_info to specify PHY ops. > - Re-order include in alphabetical order. > - Make bands const. > - Drop num_bands. > - Make i, lanes unsigned. > - Drop the maximum check in cdns_dphy_rx_get_band_ctrl(). Let the loop > complete and return -EOPNOTSUPP when we reach the end. > - Drop the "rate < bands[i].min_rate" check since the bands are in > ascending order. > - Move data_lane_ctrl to start of function and make it static const. > > Changes in v4: > - Drop the submode parts. Use a different compatible for the Rx ops. > - Make bands and num_bands static. > > Changes in v3: > - Use a table to select the band. > - Use a table to poll the data lane ready bits. > - Multiply the DPHY HS clock rate by 2 to get the bit rate since the > clock is DDR. > > drivers/phy/cadence/Kconfig | 8 + > drivers/phy/cadence/Makefile | 1 + > drivers/phy/cadence/cdns-dphy-rx.c | 255 +++++++++++++++++++++++++++++ > 3 files changed, 264 insertions(+) > create mode 100644 drivers/phy/cadence/cdns-dphy-rx.c > > diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig > index a62910ff5591..1adde2d99ae7 100644 > --- a/drivers/phy/cadence/Kconfig > +++ b/drivers/phy/cadence/Kconfig > @@ -22,6 +22,14 @@ config PHY_CADENCE_DPHY > system. If M is selected, the module will be called > cdns-dphy. > > +config PHY_CADENCE_DPHY_RX > + tristate "Cadence D-PHY Rx Support" > + depends on HAS_IOMEM && OF > + select GENERIC_PHY > + select GENERIC_PHY_MIPI_DPHY > + help > + Support for Cadence D-PHY in Rx configuration. > + > config PHY_CADENCE_SIERRA > tristate "Cadence Sierra PHY Driver" > depends on OF && HAS_IOMEM && RESET_CONTROLLER > diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile > index 26e16bd34efe..e17f035ddece 100644 > --- a/drivers/phy/cadence/Makefile > +++ b/drivers/phy/cadence/Makefile > @@ -1,5 +1,6 @@ > # SPDX-License-Identifier: GPL-2.0-only > obj-$(CONFIG_PHY_CADENCE_TORRENT) += phy-cadence-torrent.o > obj-$(CONFIG_PHY_CADENCE_DPHY) += cdns-dphy.o > +obj-$(CONFIG_PHY_CADENCE_DPHY_RX) += cdns-dphy-rx.o > obj-$(CONFIG_PHY_CADENCE_SIERRA) += phy-cadence-sierra.o > obj-$(CONFIG_PHY_CADENCE_SALVO) += phy-cadence-salvo.o > diff --git a/drivers/phy/cadence/cdns-dphy-rx.c b/drivers/phy/cadence/cdns-dphy-rx.c > new file mode 100644 > index 000000000000..47a5b67ded58 > --- /dev/null > +++ b/drivers/phy/cadence/cdns-dphy-rx.c > @@ -0,0 +1,255 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ > + */ > + > +#include <linux/bitfield.h> > +#include <linux/bitops.h> > +#include <linux/io.h> > +#include <linux/iopoll.h> > +#include <linux/module.h> > +#include <linux/phy/phy.h> > +#include <linux/phy/phy-mipi-dphy.h> > +#include <linux/platform_device.h> > + > +#define DPHY_PMA_CMN(reg) (reg) > +#define DPHY_PCS(reg) (0xb00 + (reg)) > +#define DPHY_ISO(reg) (0xc00 + (reg)) > + > +#define DPHY_CMN_SSM DPHY_PMA_CMN(0x20) > +#define DPHY_CMN_RX_MODE_EN BIT(10) > +#define DPHY_CMN_RX_BANDGAP_TIMER_MASK GENMASK(8, 1) > +#define DPHY_CMN_SSM_EN BIT(0) > + > +#define DPHY_CMN_RX_BANDGAP_TIMER 0x14 > + > +#define DPHY_BAND_CFG DPHY_PCS(0x0) > +#define DPHY_BAND_CFG_RIGHT_BAND GENMASK(9, 5) > +#define DPHY_BAND_CFG_LEFT_BAND GENMASK(4, 0) > + > +#define DPHY_POWER_ISLAND_EN_DATA DPHY_PCS(0x8) > +#define DPHY_POWER_ISLAND_EN_DATA_VAL 0xaaaaaaaa > + > +#define DPHY_POWER_ISLAND_EN_CLK DPHY_PCS(0xc) > +#define DPHY_POWER_ISLAND_EN_CLK_VAL 0xaa > + > +#define DPHY_ISO_CL_CTRL_L DPHY_ISO(0x10) > +#define DPHY_ISO_DL_CTRL_L0 DPHY_ISO(0x14) > +#define DPHY_ISO_DL_CTRL_L1 DPHY_ISO(0x20) > +#define DPHY_ISO_DL_CTRL_L2 DPHY_ISO(0x30) > +#define DPHY_ISO_DL_CTRL_L3 DPHY_ISO(0x3c) > + > +#define DPHY_ISO_LANE_READY_BIT 0 > +#define DPHY_ISO_LANE_READY_TIMEOUT_MS 100UL > + > +#define DPHY_LANES_MIN 1 > +#define DPHY_LANES_MAX 4 > + > +struct cdns_dphy_rx { > + void __iomem *regs; > + struct device *dev; > + struct phy *phy; > +}; > + > +struct cdns_dphy_rx_band { > + /* Rates are in Mbps. */ > + unsigned int min_rate; > + unsigned int max_rate; > +}; > + > +/* Order of bands is important since the index is the band number. */ > +static const struct cdns_dphy_rx_band bands[] = { > + { 80, 100 }, { 100, 120 }, { 120, 160 }, { 160, 200 }, { 200, 240 }, > + { 240, 280 }, { 280, 320 }, { 320, 360 }, { 360, 400 }, { 400, 480 }, > + { 480, 560 }, { 560, 640 }, { 640, 720 }, { 720, 800 }, { 800, 880 }, > + { 880, 1040 }, { 1040, 1200 }, { 1200, 1350 }, { 1350, 1500 }, > + { 1500, 1750 }, { 1750, 2000 }, { 2000, 2250 }, { 2250, 2500 } It could be possible to store only the min or max rate, as bands[i].max_rate == bands[i+1].min_rate. Up to you. > +}; > + > +static int cdns_dphy_rx_power_on(struct phy *phy) > +{ > + struct cdns_dphy_rx *dphy = phy_get_drvdata(phy); > + > + /* Start RX state machine. */ > + writel(DPHY_CMN_SSM_EN | DPHY_CMN_RX_MODE_EN | > + FIELD_PREP(DPHY_CMN_RX_BANDGAP_TIMER_MASK, > + DPHY_CMN_RX_BANDGAP_TIMER), > + dphy->regs + DPHY_CMN_SSM); > + > + return 0; > +} > + > +static int cdns_dphy_rx_power_off(struct phy *phy) > +{ > + struct cdns_dphy_rx *dphy = phy_get_drvdata(phy); > + > + writel(0, dphy->regs + DPHY_CMN_SSM); > + > + return 0; > +} > + > +static int cdns_dphy_rx_get_band_ctrl(unsigned long hs_clk_rate) > +{ > + unsigned int rate, i; > + > + rate = hs_clk_rate / 1000000UL; > + /* Since CSI-2 clock is DDR, the bit rate is twice the clock rate. */ > + rate *= 2; > + > + if (rate < bands[0].min_rate) > + return -EOPNOTSUPP; > + > + for (i = 0; i < ARRAY_SIZE(bands); i++) > + if (rate < bands[i].max_rate) > + return i; > + > + return -EOPNOTSUPP; > +} > + > +static inline int cdns_dphy_rx_wait_for_bit(void __iomem *addr, > + unsigned int bit) > +{ > + u32 val; > + > + return readl_relaxed_poll_timeout(addr, val, val & BIT(bit), 10, > + DPHY_ISO_LANE_READY_TIMEOUT_MS * 1000); > +} > + > +static int cdns_dphy_rx_wait_lane_ready(struct cdns_dphy_rx *dphy, > + unsigned int lanes) > +{ > + static const u32 data_lane_ctrl[] = {DPHY_ISO_DL_CTRL_L0, > + DPHY_ISO_DL_CTRL_L1, > + DPHY_ISO_DL_CTRL_L2, > + DPHY_ISO_DL_CTRL_L3}; > + void __iomem *reg = dphy->regs; > + unsigned int i; > + int ret; > + > + /* Data lanes. Minimum one lane is mandatory. */ > + if (lanes < DPHY_LANES_MIN || lanes > DPHY_LANES_MAX) > + return -EINVAL; How about moving this at the beginning of cdns_dphy_rx_configure(), to avoid starting the configuration sequence if the parameter is wrong ? > + > + /* Clock lane */ > + ret = cdns_dphy_rx_wait_for_bit(reg + DPHY_ISO_CL_CTRL_L, > + DPHY_ISO_LANE_READY_BIT); > + if (ret) > + return ret; > + > + for (i = 0; i < lanes; i++) { > + ret = cdns_dphy_rx_wait_for_bit(reg + data_lane_ctrl[i], > + DPHY_ISO_LANE_READY_BIT); > + if (ret) > + return ret; > + } > + > + return 0; > +} > + > +static int cdns_dphy_rx_configure(struct phy *phy, > + union phy_configure_opts *opts) > +{ > + struct cdns_dphy_rx *dphy = phy_get_drvdata(phy); > + unsigned int reg; > + int band_ctrl, ret; > + > + band_ctrl = cdns_dphy_rx_get_band_ctrl(opts->mipi_dphy.hs_clk_rate); > + if (band_ctrl < 0) > + return band_ctrl; > + > + reg = FIELD_PREP(DPHY_BAND_CFG_LEFT_BAND, band_ctrl) | > + FIELD_PREP(DPHY_BAND_CFG_RIGHT_BAND, band_ctrl); > + writel(reg, dphy->regs + DPHY_BAND_CFG); > + > + /* > + * Set the required power island phase 2 time. This is mandated by DPHY > + * specs. > + */ > + reg = DPHY_POWER_ISLAND_EN_DATA_VAL; > + writel(reg, dphy->regs + DPHY_POWER_ISLAND_EN_DATA); > + reg = DPHY_POWER_ISLAND_EN_CLK_VAL; > + writel(reg, dphy->regs + DPHY_POWER_ISLAND_EN_CLK); > + > + ret = cdns_dphy_rx_wait_lane_ready(dphy, opts->mipi_dphy.lanes); > + if (ret) { > + dev_err(dphy->dev, "DPHY wait for lane ready timeout\n"); > + return ret; > + } > + > + return 0; > +} > + > +static int cdns_dphy_rx_validate(struct phy *phy, enum phy_mode mode, > + int submode, union phy_configure_opts *opts) > +{ > + int ret; > + > + if (mode != PHY_MODE_MIPI_DPHY) > + return -EINVAL; > + > + ret = cdns_dphy_rx_get_band_ctrl(opts->mipi_dphy.hs_clk_rate); > + if (ret < 0) > + return ret; > + > + return phy_mipi_dphy_config_validate(&opts->mipi_dphy); > +} > + > +static const struct phy_ops cdns_dphy_rx_ops = { > + .power_on = cdns_dphy_rx_power_on, > + .power_off = cdns_dphy_rx_power_off, > + .configure = cdns_dphy_rx_configure, > + .validate = cdns_dphy_rx_validate, > +}; > + > +static int cdns_dphy_rx_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct phy_provider *provider; > + struct cdns_dphy_rx *dphy; > + > + dphy = devm_kzalloc(dev, sizeof(*dphy), GFP_KERNEL); > + if (!dphy) > + return -ENOMEM; > + > + dev_set_drvdata(dev, dphy); > + dphy->dev = dev; > + > + dphy->regs = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(dphy->regs)) > + return PTR_ERR(dphy->regs); > + > + dphy->phy = devm_phy_create(dev, NULL, &cdns_dphy_rx_ops); > + if (IS_ERR(dphy->phy)) { > + dev_err(dev, "Failed to create PHY: %d\n", PTR_ERR(dphy->phy)); > + return PTR_ERR(dphy->phy); > + } > + > + phy_set_drvdata(dphy->phy, dphy); > + provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); > + if (IS_ERR(provider)) { > + dev_err(dev, "Failed to register PHY provider: %d\n", > + PTR_ERR(provider)); > + return PTR_ERR(provider); > + } > + > + return 0; > +} > + > +static const struct of_device_id cdns_dphy_rx_of_match[] = { > + { .compatible = "cdns,dphy-rx" }, > + { /* sentinel */ }, > +}; > +MODULE_DEVICE_TABLE(of, cdns_dphy_rx_of_match); > + > +static struct platform_driver cdns_dphy_rx_platform_driver = { > + .probe = cdns_dphy_rx_probe, > + .driver = { > + .name = "cdns-mipi-dphy-rx", > + .of_match_table = cdns_dphy_rx_of_match, > + }, > +}; > +module_platform_driver(cdns_dphy_rx_platform_driver); > + > +MODULE_AUTHOR("Pratyush Yadav <p.yadav@ti.com>"); > +MODULE_DESCRIPTION("Cadence D-PHY Rx Driver"); > +MODULE_LICENSE("GPL v2"); This should be "GPL". "GPL v2" exists for historical reasons (see Documentation/process/license-rules.rst). Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> -- Regards, Laurent Pinchart ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v7 1/4] phy: cadence: Add Cadence D-PHY Rx driver 2021-12-29 23:30 ` Laurent Pinchart @ 2021-12-31 10:28 ` Pratyush Yadav 0 siblings, 0 replies; 12+ messages in thread From: Pratyush Yadav @ 2021-12-31 10:28 UTC (permalink / raw) To: Laurent Pinchart Cc: Vinod Koul, Paul Kocialkowski, Tomi Valkeinen, Vignesh Raghavendra, Kishon Vijay Abraham I, Rob Herring, Swapnil Jakhade, devicetree, linux-kernel, linux-phy On 30/12/21 01:30AM, Laurent Pinchart wrote: > Hi Pratyush, > > Thank you for the patch. > > On Mon, Dec 27, 2021 at 04:25:42PM +0530, Pratyush Yadav wrote: > > The Cadence D-PHY can be configured in Tx (DSI) mode or Rx (CSI) mode. > > Both modes have a different programming sequence and share little among > > them. In addition, a PHY configured in Tx mode cannot be used in Rx mode > > and vice versa. For this reason, create a separate driver for the Rx > > mode to make it easier to read and maintain. > > > > Signed-off-by: Pratyush Yadav <p.yadav@ti.com> > > > > --- > > > > Changes in v7: > > - Add spaces after { and before } in the bands table. > > - Drop the wrapping around the for loop on cdns_dphy_rx_get_band_ctrl(). > > - Make cdns_dphy_rx_wait_for_bit() inline. > > - Print an error message if registering PHY provider fails. > > > > Changes in v6: > > - Move to a separate driver. > > > > Changes in v5: > > - Use the new cdns_dphy_info to specify PHY ops. > > - Re-order include in alphabetical order. > > - Make bands const. > > - Drop num_bands. > > - Make i, lanes unsigned. > > - Drop the maximum check in cdns_dphy_rx_get_band_ctrl(). Let the loop > > complete and return -EOPNOTSUPP when we reach the end. > > - Drop the "rate < bands[i].min_rate" check since the bands are in > > ascending order. > > - Move data_lane_ctrl to start of function and make it static const. > > > > Changes in v4: > > - Drop the submode parts. Use a different compatible for the Rx ops. > > - Make bands and num_bands static. > > > > Changes in v3: > > - Use a table to select the band. > > - Use a table to poll the data lane ready bits. > > - Multiply the DPHY HS clock rate by 2 to get the bit rate since the > > clock is DDR. > > > > drivers/phy/cadence/Kconfig | 8 + > > drivers/phy/cadence/Makefile | 1 + > > drivers/phy/cadence/cdns-dphy-rx.c | 255 +++++++++++++++++++++++++++++ > > 3 files changed, 264 insertions(+) > > create mode 100644 drivers/phy/cadence/cdns-dphy-rx.c > > > > diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig > > index a62910ff5591..1adde2d99ae7 100644 > > --- a/drivers/phy/cadence/Kconfig > > +++ b/drivers/phy/cadence/Kconfig > > @@ -22,6 +22,14 @@ config PHY_CADENCE_DPHY > > system. If M is selected, the module will be called > > cdns-dphy. > > > > +config PHY_CADENCE_DPHY_RX > > + tristate "Cadence D-PHY Rx Support" > > + depends on HAS_IOMEM && OF > > + select GENERIC_PHY > > + select GENERIC_PHY_MIPI_DPHY > > + help > > + Support for Cadence D-PHY in Rx configuration. > > + > > config PHY_CADENCE_SIERRA > > tristate "Cadence Sierra PHY Driver" > > depends on OF && HAS_IOMEM && RESET_CONTROLLER > > diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile > > index 26e16bd34efe..e17f035ddece 100644 > > --- a/drivers/phy/cadence/Makefile > > +++ b/drivers/phy/cadence/Makefile > > @@ -1,5 +1,6 @@ > > # SPDX-License-Identifier: GPL-2.0-only > > obj-$(CONFIG_PHY_CADENCE_TORRENT) += phy-cadence-torrent.o > > obj-$(CONFIG_PHY_CADENCE_DPHY) += cdns-dphy.o > > +obj-$(CONFIG_PHY_CADENCE_DPHY_RX) += cdns-dphy-rx.o > > obj-$(CONFIG_PHY_CADENCE_SIERRA) += phy-cadence-sierra.o > > obj-$(CONFIG_PHY_CADENCE_SALVO) += phy-cadence-salvo.o > > diff --git a/drivers/phy/cadence/cdns-dphy-rx.c b/drivers/phy/cadence/cdns-dphy-rx.c > > new file mode 100644 > > index 000000000000..47a5b67ded58 > > --- /dev/null > > +++ b/drivers/phy/cadence/cdns-dphy-rx.c > > @@ -0,0 +1,255 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ > > + */ > > + > > +#include <linux/bitfield.h> > > +#include <linux/bitops.h> > > +#include <linux/io.h> > > +#include <linux/iopoll.h> > > +#include <linux/module.h> > > +#include <linux/phy/phy.h> > > +#include <linux/phy/phy-mipi-dphy.h> > > +#include <linux/platform_device.h> > > + > > +#define DPHY_PMA_CMN(reg) (reg) > > +#define DPHY_PCS(reg) (0xb00 + (reg)) > > +#define DPHY_ISO(reg) (0xc00 + (reg)) > > + > > +#define DPHY_CMN_SSM DPHY_PMA_CMN(0x20) > > +#define DPHY_CMN_RX_MODE_EN BIT(10) > > +#define DPHY_CMN_RX_BANDGAP_TIMER_MASK GENMASK(8, 1) > > +#define DPHY_CMN_SSM_EN BIT(0) > > + > > +#define DPHY_CMN_RX_BANDGAP_TIMER 0x14 > > + > > +#define DPHY_BAND_CFG DPHY_PCS(0x0) > > +#define DPHY_BAND_CFG_RIGHT_BAND GENMASK(9, 5) > > +#define DPHY_BAND_CFG_LEFT_BAND GENMASK(4, 0) > > + > > +#define DPHY_POWER_ISLAND_EN_DATA DPHY_PCS(0x8) > > +#define DPHY_POWER_ISLAND_EN_DATA_VAL 0xaaaaaaaa > > + > > +#define DPHY_POWER_ISLAND_EN_CLK DPHY_PCS(0xc) > > +#define DPHY_POWER_ISLAND_EN_CLK_VAL 0xaa > > + > > +#define DPHY_ISO_CL_CTRL_L DPHY_ISO(0x10) > > +#define DPHY_ISO_DL_CTRL_L0 DPHY_ISO(0x14) > > +#define DPHY_ISO_DL_CTRL_L1 DPHY_ISO(0x20) > > +#define DPHY_ISO_DL_CTRL_L2 DPHY_ISO(0x30) > > +#define DPHY_ISO_DL_CTRL_L3 DPHY_ISO(0x3c) > > + > > +#define DPHY_ISO_LANE_READY_BIT 0 > > +#define DPHY_ISO_LANE_READY_TIMEOUT_MS 100UL > > + > > +#define DPHY_LANES_MIN 1 > > +#define DPHY_LANES_MAX 4 > > + > > +struct cdns_dphy_rx { > > + void __iomem *regs; > > + struct device *dev; > > + struct phy *phy; > > +}; > > + > > +struct cdns_dphy_rx_band { > > + /* Rates are in Mbps. */ > > + unsigned int min_rate; > > + unsigned int max_rate; > > +}; > > + > > +/* Order of bands is important since the index is the band number. */ > > +static const struct cdns_dphy_rx_band bands[] = { > > + { 80, 100 }, { 100, 120 }, { 120, 160 }, { 160, 200 }, { 200, 240 }, > > + { 240, 280 }, { 280, 320 }, { 320, 360 }, { 360, 400 }, { 400, 480 }, > > + { 480, 560 }, { 560, 640 }, { 640, 720 }, { 720, 800 }, { 800, 880 }, > > + { 880, 1040 }, { 1040, 1200 }, { 1200, 1350 }, { 1350, 1500 }, > > + { 1500, 1750 }, { 1750, 2000 }, { 2000, 2250 }, { 2250, 2500 } > > It could be possible to store only the min or max rate, as > bands[i].max_rate == bands[i+1].min_rate. Up to you. I don't have a strong preference. I think this looks a bit nicer and is easier to understand at first glance. > > > +}; > > + > > +static int cdns_dphy_rx_power_on(struct phy *phy) > > +{ > > + struct cdns_dphy_rx *dphy = phy_get_drvdata(phy); > > + > > + /* Start RX state machine. */ > > + writel(DPHY_CMN_SSM_EN | DPHY_CMN_RX_MODE_EN | > > + FIELD_PREP(DPHY_CMN_RX_BANDGAP_TIMER_MASK, > > + DPHY_CMN_RX_BANDGAP_TIMER), > > + dphy->regs + DPHY_CMN_SSM); > > + > > + return 0; > > +} > > + > > +static int cdns_dphy_rx_power_off(struct phy *phy) > > +{ > > + struct cdns_dphy_rx *dphy = phy_get_drvdata(phy); > > + > > + writel(0, dphy->regs + DPHY_CMN_SSM); > > + > > + return 0; > > +} > > + > > +static int cdns_dphy_rx_get_band_ctrl(unsigned long hs_clk_rate) > > +{ > > + unsigned int rate, i; > > + > > + rate = hs_clk_rate / 1000000UL; > > + /* Since CSI-2 clock is DDR, the bit rate is twice the clock rate. */ > > + rate *= 2; > > + > > + if (rate < bands[0].min_rate) > > + return -EOPNOTSUPP; > > + > > + for (i = 0; i < ARRAY_SIZE(bands); i++) > > + if (rate < bands[i].max_rate) > > + return i; > > + > > + return -EOPNOTSUPP; > > +} > > + > > +static inline int cdns_dphy_rx_wait_for_bit(void __iomem *addr, > > + unsigned int bit) > > +{ > > + u32 val; > > + > > + return readl_relaxed_poll_timeout(addr, val, val & BIT(bit), 10, > > + DPHY_ISO_LANE_READY_TIMEOUT_MS * 1000); > > +} > > + > > +static int cdns_dphy_rx_wait_lane_ready(struct cdns_dphy_rx *dphy, > > + unsigned int lanes) > > +{ > > + static const u32 data_lane_ctrl[] = {DPHY_ISO_DL_CTRL_L0, > > + DPHY_ISO_DL_CTRL_L1, > > + DPHY_ISO_DL_CTRL_L2, > > + DPHY_ISO_DL_CTRL_L3}; > > + void __iomem *reg = dphy->regs; > > + unsigned int i; > > + int ret; > > + > > + /* Data lanes. Minimum one lane is mandatory. */ > > + if (lanes < DPHY_LANES_MIN || lanes > DPHY_LANES_MAX) > > + return -EINVAL; > > How about moving this at the beginning of cdns_dphy_rx_configure(), to > avoid starting the configuration sequence if the parameter is wrong ? Ok. > > > + > > + /* Clock lane */ > > + ret = cdns_dphy_rx_wait_for_bit(reg + DPHY_ISO_CL_CTRL_L, > > + DPHY_ISO_LANE_READY_BIT); > > + if (ret) > > + return ret; > > + > > + for (i = 0; i < lanes; i++) { > > + ret = cdns_dphy_rx_wait_for_bit(reg + data_lane_ctrl[i], > > + DPHY_ISO_LANE_READY_BIT); > > + if (ret) > > + return ret; > > + } > > + > > + return 0; > > +} > > + > > +static int cdns_dphy_rx_configure(struct phy *phy, > > + union phy_configure_opts *opts) > > +{ > > + struct cdns_dphy_rx *dphy = phy_get_drvdata(phy); > > + unsigned int reg; > > + int band_ctrl, ret; > > + > > + band_ctrl = cdns_dphy_rx_get_band_ctrl(opts->mipi_dphy.hs_clk_rate); > > + if (band_ctrl < 0) > > + return band_ctrl; > > + > > + reg = FIELD_PREP(DPHY_BAND_CFG_LEFT_BAND, band_ctrl) | > > + FIELD_PREP(DPHY_BAND_CFG_RIGHT_BAND, band_ctrl); > > + writel(reg, dphy->regs + DPHY_BAND_CFG); > > + > > + /* > > + * Set the required power island phase 2 time. This is mandated by DPHY > > + * specs. > > + */ > > + reg = DPHY_POWER_ISLAND_EN_DATA_VAL; > > + writel(reg, dphy->regs + DPHY_POWER_ISLAND_EN_DATA); > > + reg = DPHY_POWER_ISLAND_EN_CLK_VAL; > > + writel(reg, dphy->regs + DPHY_POWER_ISLAND_EN_CLK); > > + > > + ret = cdns_dphy_rx_wait_lane_ready(dphy, opts->mipi_dphy.lanes); > > + if (ret) { > > + dev_err(dphy->dev, "DPHY wait for lane ready timeout\n"); > > + return ret; > > + } > > + > > + return 0; > > +} > > + > > +static int cdns_dphy_rx_validate(struct phy *phy, enum phy_mode mode, > > + int submode, union phy_configure_opts *opts) > > +{ > > + int ret; > > + > > + if (mode != PHY_MODE_MIPI_DPHY) > > + return -EINVAL; > > + > > + ret = cdns_dphy_rx_get_band_ctrl(opts->mipi_dphy.hs_clk_rate); > > + if (ret < 0) > > + return ret; > > + > > + return phy_mipi_dphy_config_validate(&opts->mipi_dphy); > > +} > > + > > +static const struct phy_ops cdns_dphy_rx_ops = { > > + .power_on = cdns_dphy_rx_power_on, > > + .power_off = cdns_dphy_rx_power_off, > > + .configure = cdns_dphy_rx_configure, > > + .validate = cdns_dphy_rx_validate, > > +}; > > + > > +static int cdns_dphy_rx_probe(struct platform_device *pdev) > > +{ > > + struct device *dev = &pdev->dev; > > + struct phy_provider *provider; > > + struct cdns_dphy_rx *dphy; > > + > > + dphy = devm_kzalloc(dev, sizeof(*dphy), GFP_KERNEL); > > + if (!dphy) > > + return -ENOMEM; > > + > > + dev_set_drvdata(dev, dphy); > > + dphy->dev = dev; > > + > > + dphy->regs = devm_platform_ioremap_resource(pdev, 0); > > + if (IS_ERR(dphy->regs)) > > + return PTR_ERR(dphy->regs); > > + > > + dphy->phy = devm_phy_create(dev, NULL, &cdns_dphy_rx_ops); > > + if (IS_ERR(dphy->phy)) { > > + dev_err(dev, "Failed to create PHY: %d\n", PTR_ERR(dphy->phy)); > > + return PTR_ERR(dphy->phy); > > + } > > + > > + phy_set_drvdata(dphy->phy, dphy); > > + provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); > > + if (IS_ERR(provider)) { > > + dev_err(dev, "Failed to register PHY provider: %d\n", > > + PTR_ERR(provider)); > > + return PTR_ERR(provider); > > + } > > + > > + return 0; > > +} > > + > > +static const struct of_device_id cdns_dphy_rx_of_match[] = { > > + { .compatible = "cdns,dphy-rx" }, > > + { /* sentinel */ }, > > +}; > > +MODULE_DEVICE_TABLE(of, cdns_dphy_rx_of_match); > > + > > +static struct platform_driver cdns_dphy_rx_platform_driver = { > > + .probe = cdns_dphy_rx_probe, > > + .driver = { > > + .name = "cdns-mipi-dphy-rx", > > + .of_match_table = cdns_dphy_rx_of_match, > > + }, > > +}; > > +module_platform_driver(cdns_dphy_rx_platform_driver); > > + > > +MODULE_AUTHOR("Pratyush Yadav <p.yadav@ti.com>"); > > +MODULE_DESCRIPTION("Cadence D-PHY Rx Driver"); > > +MODULE_LICENSE("GPL v2"); > > This should be "GPL". "GPL v2" exists for historical reasons (see > Documentation/process/license-rules.rst). Ok. > > Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Thanks. -- Regards, Pratyush Yadav Texas Instruments Inc. ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v7 1/4] phy: cadence: Add Cadence D-PHY Rx driver 2021-12-27 10:55 ` [PATCH v7 1/4] phy: cadence: Add Cadence D-PHY Rx driver Pratyush Yadav 2021-12-29 23:30 ` Laurent Pinchart @ 2022-01-04 11:11 ` kernel test robot 2022-01-05 5:27 ` kernel test robot 2 siblings, 0 replies; 12+ messages in thread From: kernel test robot @ 2022-01-04 11:11 UTC (permalink / raw) To: Pratyush Yadav, Vinod Koul Cc: kbuild-all, Pratyush Yadav, Laurent Pinchart, Paul Kocialkowski, Tomi Valkeinen, Vignesh Raghavendra, Kishon Vijay Abraham I, Rob Herring, Swapnil Jakhade, devicetree Hi Pratyush, I love your patch! Perhaps something to improve: [auto build test WARNING on robh/for-next] [also build test WARNING on linus/master v5.16-rc8 next-20211224] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Pratyush-Yadav/Rx-mode-support-for-Cadence-DPHY/20211227-185749 base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next config: csky-allyesconfig (https://download.01.org/0day-ci/archive/20220104/202201041908.dB4f5BTe-lkp@intel.com/config) compiler: csky-linux-gcc (GCC) 11.2.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/0day-ci/linux/commit/266027120669b8824f07fa9c2f7a59b7bc12648c git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Pratyush-Yadav/Rx-mode-support-for-Cadence-DPHY/20211227-185749 git checkout 266027120669b8824f07fa9c2f7a59b7bc12648c # save the config file to linux build tree mkdir build_dir COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=csky SHELL=/bin/bash drivers/phy/cadence/ drivers/thermal/ If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp@intel.com> All warnings (new ones prefixed by >>): In file included from include/linux/device.h:15, from include/linux/phy/phy.h:15, from drivers/phy/cadence/cdns-dphy-rx.c:11: drivers/phy/cadence/cdns-dphy-rx.c: In function 'cdns_dphy_rx_probe': >> drivers/phy/cadence/cdns-dphy-rx.c:223:30: warning: format '%d' expects argument of type 'int', but argument 3 has type 'long int' [-Wformat=] 223 | dev_err(dev, "Failed to create PHY: %d\n", PTR_ERR(dphy->phy)); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ include/linux/dev_printk.h:110:30: note: in definition of macro 'dev_printk_index_wrap' 110 | _p_func(dev, fmt, ##__VA_ARGS__); \ | ^~~ include/linux/dev_printk.h:144:56: note: in expansion of macro 'dev_fmt' 144 | dev_printk_index_wrap(_dev_err, KERN_ERR, dev, dev_fmt(fmt), ##__VA_ARGS__) | ^~~~~~~ drivers/phy/cadence/cdns-dphy-rx.c:223:17: note: in expansion of macro 'dev_err' 223 | dev_err(dev, "Failed to create PHY: %d\n", PTR_ERR(dphy->phy)); | ^~~~~~~ drivers/phy/cadence/cdns-dphy-rx.c:223:54: note: format string is defined here 223 | dev_err(dev, "Failed to create PHY: %d\n", PTR_ERR(dphy->phy)); | ~^ | | | int | %ld In file included from include/linux/device.h:15, from include/linux/phy/phy.h:15, from drivers/phy/cadence/cdns-dphy-rx.c:11: drivers/phy/cadence/cdns-dphy-rx.c:230:30: warning: format '%d' expects argument of type 'int', but argument 3 has type 'long int' [-Wformat=] 230 | dev_err(dev, "Failed to register PHY provider: %d\n", | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ include/linux/dev_printk.h:110:30: note: in definition of macro 'dev_printk_index_wrap' 110 | _p_func(dev, fmt, ##__VA_ARGS__); \ | ^~~ include/linux/dev_printk.h:144:56: note: in expansion of macro 'dev_fmt' 144 | dev_printk_index_wrap(_dev_err, KERN_ERR, dev, dev_fmt(fmt), ##__VA_ARGS__) | ^~~~~~~ drivers/phy/cadence/cdns-dphy-rx.c:230:17: note: in expansion of macro 'dev_err' 230 | dev_err(dev, "Failed to register PHY provider: %d\n", | ^~~~~~~ drivers/phy/cadence/cdns-dphy-rx.c:230:65: note: format string is defined here 230 | dev_err(dev, "Failed to register PHY provider: %d\n", | ~^ | | | int | %ld vim +223 drivers/phy/cadence/cdns-dphy-rx.c 203 204 static int cdns_dphy_rx_probe(struct platform_device *pdev) 205 { 206 struct device *dev = &pdev->dev; 207 struct phy_provider *provider; 208 struct cdns_dphy_rx *dphy; 209 210 dphy = devm_kzalloc(dev, sizeof(*dphy), GFP_KERNEL); 211 if (!dphy) 212 return -ENOMEM; 213 214 dev_set_drvdata(dev, dphy); 215 dphy->dev = dev; 216 217 dphy->regs = devm_platform_ioremap_resource(pdev, 0); 218 if (IS_ERR(dphy->regs)) 219 return PTR_ERR(dphy->regs); 220 221 dphy->phy = devm_phy_create(dev, NULL, &cdns_dphy_rx_ops); 222 if (IS_ERR(dphy->phy)) { > 223 dev_err(dev, "Failed to create PHY: %d\n", PTR_ERR(dphy->phy)); 224 return PTR_ERR(dphy->phy); 225 } 226 227 phy_set_drvdata(dphy->phy, dphy); 228 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 229 if (IS_ERR(provider)) { 230 dev_err(dev, "Failed to register PHY provider: %d\n", 231 PTR_ERR(provider)); 232 return PTR_ERR(provider); 233 } 234 235 return 0; 236 } 237 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v7 1/4] phy: cadence: Add Cadence D-PHY Rx driver 2021-12-27 10:55 ` [PATCH v7 1/4] phy: cadence: Add Cadence D-PHY Rx driver Pratyush Yadav 2021-12-29 23:30 ` Laurent Pinchart 2022-01-04 11:11 ` kernel test robot @ 2022-01-05 5:27 ` kernel test robot 2 siblings, 0 replies; 12+ messages in thread From: kernel test robot @ 2022-01-05 5:27 UTC (permalink / raw) To: Pratyush Yadav, Vinod Koul Cc: llvm, kbuild-all, Pratyush Yadav, Laurent Pinchart, Paul Kocialkowski, Tomi Valkeinen, Vignesh Raghavendra, Kishon Vijay Abraham I, Rob Herring, Swapnil Jakhade, devicetree Hi Pratyush, I love your patch! Perhaps something to improve: [auto build test WARNING on robh/for-next] [also build test WARNING on linus/master v5.16-rc8 next-20220104] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Pratyush-Yadav/Rx-mode-support-for-Cadence-DPHY/20211227-185749 base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next config: riscv-randconfig-r013-20220105 (https://download.01.org/0day-ci/archive/20220105/202201051328.31W7Semj-lkp@intel.com/config) compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project d5b6e30ed3acad794dd0aec400e617daffc6cc3d) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install riscv cross compiling tool for clang build # apt-get install binutils-riscv64-linux-gnu # https://github.com/0day-ci/linux/commit/266027120669b8824f07fa9c2f7a59b7bc12648c git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Pratyush-Yadav/Rx-mode-support-for-Cadence-DPHY/20211227-185749 git checkout 266027120669b8824f07fa9c2f7a59b7bc12648c # save the config file to linux build tree mkdir build_dir COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=riscv SHELL=/bin/bash drivers/phy/cadence/ If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp@intel.com> All warnings (new ones prefixed by >>): >> drivers/phy/cadence/cdns-dphy-rx.c:223:46: warning: format specifies type 'int' but the argument has type 'long' [-Wformat] dev_err(dev, "Failed to create PHY: %d\n", PTR_ERR(dphy->phy)); ~~ ^~~~~~~~~~~~~~~~~~ %ld include/linux/dev_printk.h:144:65: note: expanded from macro 'dev_err' dev_printk_index_wrap(_dev_err, KERN_ERR, dev, dev_fmt(fmt), ##__VA_ARGS__) ~~~ ^~~~~~~~~~~ include/linux/dev_printk.h:110:23: note: expanded from macro 'dev_printk_index_wrap' _p_func(dev, fmt, ##__VA_ARGS__); \ ~~~ ^~~~~~~~~~~ drivers/phy/cadence/cdns-dphy-rx.c:231:4: warning: format specifies type 'int' but the argument has type 'long' [-Wformat] PTR_ERR(provider)); ^~~~~~~~~~~~~~~~~ include/linux/dev_printk.h:144:65: note: expanded from macro 'dev_err' dev_printk_index_wrap(_dev_err, KERN_ERR, dev, dev_fmt(fmt), ##__VA_ARGS__) ~~~ ^~~~~~~~~~~ include/linux/dev_printk.h:110:23: note: expanded from macro 'dev_printk_index_wrap' _p_func(dev, fmt, ##__VA_ARGS__); \ ~~~ ^~~~~~~~~~~ 2 warnings generated. vim +223 drivers/phy/cadence/cdns-dphy-rx.c 203 204 static int cdns_dphy_rx_probe(struct platform_device *pdev) 205 { 206 struct device *dev = &pdev->dev; 207 struct phy_provider *provider; 208 struct cdns_dphy_rx *dphy; 209 210 dphy = devm_kzalloc(dev, sizeof(*dphy), GFP_KERNEL); 211 if (!dphy) 212 return -ENOMEM; 213 214 dev_set_drvdata(dev, dphy); 215 dphy->dev = dev; 216 217 dphy->regs = devm_platform_ioremap_resource(pdev, 0); 218 if (IS_ERR(dphy->regs)) 219 return PTR_ERR(dphy->regs); 220 221 dphy->phy = devm_phy_create(dev, NULL, &cdns_dphy_rx_ops); 222 if (IS_ERR(dphy->phy)) { > 223 dev_err(dev, "Failed to create PHY: %d\n", PTR_ERR(dphy->phy)); 224 return PTR_ERR(dphy->phy); 225 } 226 227 phy_set_drvdata(dphy->phy, dphy); 228 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 229 if (IS_ERR(provider)) { 230 dev_err(dev, "Failed to register PHY provider: %d\n", 231 PTR_ERR(provider)); 232 return PTR_ERR(provider); 233 } 234 235 return 0; 236 } 237 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v7 2/4] phy: dt-bindings: Convert Cadence DPHY binding to YAML 2021-12-27 10:55 [PATCH v7 0/4] Rx mode support for Cadence DPHY Pratyush Yadav 2021-12-27 10:55 ` [PATCH v7 1/4] phy: cadence: Add Cadence D-PHY Rx driver Pratyush Yadav @ 2021-12-27 10:55 ` Pratyush Yadav 2021-12-27 10:55 ` [PATCH v7 3/4] phy: dt-bindings: cdns,dphy: add power-domains property Pratyush Yadav 2021-12-27 10:55 ` [PATCH v7 4/4] phy: dt-bindings: Add Cadence D-PHY Rx bindings Pratyush Yadav 3 siblings, 0 replies; 12+ messages in thread From: Pratyush Yadav @ 2021-12-27 10:55 UTC (permalink / raw) To: Vinod Koul Cc: Pratyush Yadav, Laurent Pinchart, Paul Kocialkowski, Tomi Valkeinen, Vignesh Raghavendra, Kishon Vijay Abraham I, Rob Herring, Swapnil Jakhade, devicetree, linux-kernel, linux-phy Convert Cadence DPHY binding to YAML. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Rob Herring <robh@kernel.org> --- (no changes since v3) Changes in v3: - Add Rob's R-by. Changes in v2: - Drop reg description. - Add a description for each DPHY clock. - Rename dphy@... to phy@... in example. - Add Laurent's R-by. - Re-order subject prefixes. .../devicetree/bindings/phy/cdns,dphy.txt | 20 -------- .../devicetree/bindings/phy/cdns,dphy.yaml | 51 +++++++++++++++++++ 2 files changed, 51 insertions(+), 20 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/cdns,dphy.txt create mode 100644 Documentation/devicetree/bindings/phy/cdns,dphy.yaml diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.txt b/Documentation/devicetree/bindings/phy/cdns,dphy.txt deleted file mode 100644 index 1095bc4e72d9..000000000000 --- a/Documentation/devicetree/bindings/phy/cdns,dphy.txt +++ /dev/null @@ -1,20 +0,0 @@ -Cadence DPHY -============ - -Cadence DPHY block. - -Required properties: -- compatible: should be set to "cdns,dphy". -- reg: physical base address and length of the DPHY registers. -- clocks: DPHY reference clocks. -- clock-names: must contain "psm" and "pll_ref". -- #phy-cells: must be set to 0. - -Example: - dphy0: dphy@fd0e0000{ - compatible = "cdns,dphy"; - reg = <0x0 0xfd0e0000 0x0 0x1000>; - clocks = <&psm_clk>, <&pll_ref_clk>; - clock-names = "psm", "pll_ref"; - #phy-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml new file mode 100644 index 000000000000..b90a58773bf2 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/cdns,dphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence DPHY Device Tree Bindings + +maintainers: + - Pratyush Yadav <p.yadav@ti.com> + +properties: + compatible: + items: + - const: cdns,dphy + + reg: + maxItems: 1 + + clocks: + items: + - description: PMA state machine clock + - description: PLL reference clock + + clock-names: + items: + - const: psm + - const: pll_ref + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + + dphy0: phy@fd0e0000{ + compatible = "cdns,dphy"; + reg = <0xfd0e0000 0x1000>; + clocks = <&psm_clk>, <&pll_ref_clk>; + clock-names = "psm", "pll_ref"; + #phy-cells = <0>; + }; -- 2.33.1.835.ge9e5ba39a7 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v7 3/4] phy: dt-bindings: cdns,dphy: add power-domains property 2021-12-27 10:55 [PATCH v7 0/4] Rx mode support for Cadence DPHY Pratyush Yadav 2021-12-27 10:55 ` [PATCH v7 1/4] phy: cadence: Add Cadence D-PHY Rx driver Pratyush Yadav 2021-12-27 10:55 ` [PATCH v7 2/4] phy: dt-bindings: Convert Cadence DPHY binding to YAML Pratyush Yadav @ 2021-12-27 10:55 ` Pratyush Yadav 2021-12-27 10:55 ` [PATCH v7 4/4] phy: dt-bindings: Add Cadence D-PHY Rx bindings Pratyush Yadav 3 siblings, 0 replies; 12+ messages in thread From: Pratyush Yadav @ 2021-12-27 10:55 UTC (permalink / raw) To: Vinod Koul Cc: Pratyush Yadav, Laurent Pinchart, Paul Kocialkowski, Tomi Valkeinen, Vignesh Raghavendra, Kishon Vijay Abraham I, Rob Herring, Swapnil Jakhade, devicetree, linux-kernel, linux-phy This property is needed on TI platforms to enable the PD of the DPHY before it can be used. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Rob Herring <robh@kernel.org> --- (no changes since v3) Changes in v3: - Add Rob's Ack. Changes in v2: - Add power-domain to the example. - Add Laurent's R-by. - Re-order subject prefixes. Documentation/devicetree/bindings/phy/cdns,dphy.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml index b90a58773bf2..c50629bd1b51 100644 --- a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml +++ b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml @@ -30,6 +30,9 @@ properties: "#phy-cells": const: 0 + power-domains: + maxItems: 1 + required: - compatible - reg @@ -41,11 +44,13 @@ additionalProperties: false examples: - | + #include <dt-bindings/soc/ti,sci_pm_domain.h> dphy0: phy@fd0e0000{ compatible = "cdns,dphy"; reg = <0xfd0e0000 0x1000>; clocks = <&psm_clk>, <&pll_ref_clk>; clock-names = "psm", "pll_ref"; + power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; #phy-cells = <0>; }; -- 2.33.1.835.ge9e5ba39a7 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v7 4/4] phy: dt-bindings: Add Cadence D-PHY Rx bindings 2021-12-27 10:55 [PATCH v7 0/4] Rx mode support for Cadence DPHY Pratyush Yadav ` (2 preceding siblings ...) 2021-12-27 10:55 ` [PATCH v7 3/4] phy: dt-bindings: cdns,dphy: add power-domains property Pratyush Yadav @ 2021-12-27 10:55 ` Pratyush Yadav 2021-12-27 16:57 ` Rob Herring 2021-12-29 23:14 ` Laurent Pinchart 3 siblings, 2 replies; 12+ messages in thread From: Pratyush Yadav @ 2021-12-27 10:55 UTC (permalink / raw) To: Vinod Koul Cc: Pratyush Yadav, Laurent Pinchart, Paul Kocialkowski, Tomi Valkeinen, Vignesh Raghavendra, Kishon Vijay Abraham I, Rob Herring, Swapnil Jakhade, devicetree, linux-kernel, linux-phy The Rx mode DPHY is different from Tx mode DPHY. Add a separate binding for it. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> --- (no changes since v6) Changes in v6: - Add a new binding for DPHY Rx. .../devicetree/bindings/phy/cdns,dphy-rx.yaml | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/cdns,dphy-rx.yaml diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy-rx.yaml b/Documentation/devicetree/bindings/phy/cdns,dphy-rx.yaml new file mode 100644 index 000000000000..07be031d82e6 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/cdns,dphy-rx.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/cdns,dphy-rx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence DPHY Rx Device Tree Bindings + +maintainers: + - Pratyush Yadav <p.yadav@ti.com> + +properties: + compatible: + items: + - const: cdns,dphy-rx + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/soc/ti,sci_pm_domain.h> + + dphy0: phy@4580000 { + compatible = "cdns,dphy-rx"; + reg = <0x4580000 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; + }; -- 2.33.1.835.ge9e5ba39a7 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v7 4/4] phy: dt-bindings: Add Cadence D-PHY Rx bindings 2021-12-27 10:55 ` [PATCH v7 4/4] phy: dt-bindings: Add Cadence D-PHY Rx bindings Pratyush Yadav @ 2021-12-27 16:57 ` Rob Herring 2021-12-27 20:48 ` Pratyush Yadav 2021-12-29 23:14 ` Laurent Pinchart 1 sibling, 1 reply; 12+ messages in thread From: Rob Herring @ 2021-12-27 16:57 UTC (permalink / raw) To: Pratyush Yadav Cc: linux-kernel, linux-phy, Vinod Koul, Rob Herring, Swapnil Jakhade, Laurent Pinchart, devicetree, Kishon Vijay Abraham I, Tomi Valkeinen, Paul Kocialkowski, Vignesh Raghavendra On Mon, 27 Dec 2021 16:25:45 +0530, Pratyush Yadav wrote: > The Rx mode DPHY is different from Tx mode DPHY. Add a separate binding > for it. > > Signed-off-by: Pratyush Yadav <p.yadav@ti.com> > > --- > > (no changes since v6) > > Changes in v6: > - Add a new binding for DPHY Rx. > > .../devicetree/bindings/phy/cdns,dphy-rx.yaml | 42 +++++++++++++++++++ > 1 file changed, 42 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/cdns,dphy-rx.yaml > Please add Acked-by/Reviewed-by tags when posting new versions. However, there's no need to repost patches *only* to add the tags. The upstream maintainer will do that for acks received on the version they apply. If a tag was not added on purpose, please state why and what changed. ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v7 4/4] phy: dt-bindings: Add Cadence D-PHY Rx bindings 2021-12-27 16:57 ` Rob Herring @ 2021-12-27 20:48 ` Pratyush Yadav 0 siblings, 0 replies; 12+ messages in thread From: Pratyush Yadav @ 2021-12-27 20:48 UTC (permalink / raw) To: Rob Herring Cc: linux-kernel, linux-phy, Vinod Koul, Rob Herring, Swapnil Jakhade, Laurent Pinchart, devicetree, Kishon Vijay Abraham I, Tomi Valkeinen, Paul Kocialkowski, Vignesh Raghavendra Hi Rob, On 27/12/21 12:57PM, Rob Herring wrote: > On Mon, 27 Dec 2021 16:25:45 +0530, Pratyush Yadav wrote: > > The Rx mode DPHY is different from Tx mode DPHY. Add a separate binding > > for it. > > > > Signed-off-by: Pratyush Yadav <p.yadav@ti.com> > > > > --- > > > > (no changes since v6) > > > > Changes in v6: > > - Add a new binding for DPHY Rx. > > > > .../devicetree/bindings/phy/cdns,dphy-rx.yaml | 42 +++++++++++++++++++ > > 1 file changed, 42 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/phy/cdns,dphy-rx.yaml > > > > > Please add Acked-by/Reviewed-by tags when posting new versions. However, > there's no need to repost patches *only* to add the tags. The upstream > maintainer will do that for acks received on the version they apply. > > If a tag was not added on purpose, please state why and what changed. Sorry. I missed adding your R-by. It was by mistake, since this patch has not changed since. -- Regards, Pratyush Yadav Texas Instruments Inc. ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v7 4/4] phy: dt-bindings: Add Cadence D-PHY Rx bindings 2021-12-27 10:55 ` [PATCH v7 4/4] phy: dt-bindings: Add Cadence D-PHY Rx bindings Pratyush Yadav 2021-12-27 16:57 ` Rob Herring @ 2021-12-29 23:14 ` Laurent Pinchart 1 sibling, 0 replies; 12+ messages in thread From: Laurent Pinchart @ 2021-12-29 23:14 UTC (permalink / raw) To: Pratyush Yadav Cc: Vinod Koul, Paul Kocialkowski, Tomi Valkeinen, Vignesh Raghavendra, Kishon Vijay Abraham I, Rob Herring, Swapnil Jakhade, devicetree, linux-kernel, linux-phy Hi Pratyush, Thank you for the patch. On Mon, Dec 27, 2021 at 04:25:45PM +0530, Pratyush Yadav wrote: > The Rx mode DPHY is different from Tx mode DPHY. Add a separate binding > for it. > > Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > --- > > (no changes since v6) > > Changes in v6: > - Add a new binding for DPHY Rx. > > .../devicetree/bindings/phy/cdns,dphy-rx.yaml | 42 +++++++++++++++++++ > 1 file changed, 42 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/cdns,dphy-rx.yaml > > diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy-rx.yaml b/Documentation/devicetree/bindings/phy/cdns,dphy-rx.yaml > new file mode 100644 > index 000000000000..07be031d82e6 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/cdns,dphy-rx.yaml > @@ -0,0 +1,42 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/cdns,dphy-rx.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Cadence DPHY Rx Device Tree Bindings > + > +maintainers: > + - Pratyush Yadav <p.yadav@ti.com> > + > +properties: > + compatible: > + items: > + - const: cdns,dphy-rx > + > + reg: > + maxItems: 1 > + > + "#phy-cells": > + const: 0 > + > + power-domains: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - "#phy-cells" > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/soc/ti,sci_pm_domain.h> > + > + dphy0: phy@4580000 { > + compatible = "cdns,dphy-rx"; > + reg = <0x4580000 0x1100>; > + #phy-cells = <0>; > + power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; > + }; -- Regards, Laurent Pinchart ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2022-01-05 5:27 UTC | newest] Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-12-27 10:55 [PATCH v7 0/4] Rx mode support for Cadence DPHY Pratyush Yadav 2021-12-27 10:55 ` [PATCH v7 1/4] phy: cadence: Add Cadence D-PHY Rx driver Pratyush Yadav 2021-12-29 23:30 ` Laurent Pinchart 2021-12-31 10:28 ` Pratyush Yadav 2022-01-04 11:11 ` kernel test robot 2022-01-05 5:27 ` kernel test robot 2021-12-27 10:55 ` [PATCH v7 2/4] phy: dt-bindings: Convert Cadence DPHY binding to YAML Pratyush Yadav 2021-12-27 10:55 ` [PATCH v7 3/4] phy: dt-bindings: cdns,dphy: add power-domains property Pratyush Yadav 2021-12-27 10:55 ` [PATCH v7 4/4] phy: dt-bindings: Add Cadence D-PHY Rx bindings Pratyush Yadav 2021-12-27 16:57 ` Rob Herring 2021-12-27 20:48 ` Pratyush Yadav 2021-12-29 23:14 ` Laurent Pinchart
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