[PATCH v2 1/5] dt-bindings: pwrap: mediatek: add pwrap support for MT6797

[PATCH v2 1/5] dt-bindings: pwrap: mediatek: add pwrap support for MT6797

[argus.lin]

[-- Attachment #1.1: Type: text/html, Size: 1845 bytes --]

[-- Attachment #1.2: Type: text/plain, Size: 863 bytes --]

From: Argus Lin <argus.lin@mediatek.com>

We add pwrap support for MT6797 SoCs.

Signed-off-by: Argus Lin <argus.lin@mediatek.com>
---
 Documentation/devicetree/bindings/soc/mediatek/pwrap.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
index bf80e3f96f8c..f9987c30f0d5 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
+++ b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
@@ -19,6 +19,7 @@ IP Pairing
 Required properties in pwrap device node.
 - compatible:
 	"mediatek,mt2701-pwrap" for MT2701/7623 SoCs
+	"mediatek,mt6797-pwrap" for MT6797 SoCs
 	"mediatek,mt7622-pwrap" for MT7622 SoCs
 	"mediatek,mt8135-pwrap" for MT8135 SoCs
 	"mediatek,mt8173-pwrap" for MT8173 SoCs
-- 
2.12.5

[PATCH v2 2/5] arm64: dts: mt6797: add pwrap support for mt6797

[argus.lin]

[-- Attachment #1.1: Type: text/html, Size: 2265 bytes --]

[-- Attachment #1.2: Type: text/plain, Size: 1225 bytes --]

From: Argus Lin <argus.lin@mediatek.com>

mt6797 is a highly integrated SoCs, and it uses
mt6351 as Power Management IC.
We need to add pwrap device to communicate with
mt6351 by SPI.
The base address of pwrap is 0x1000d000, and IRQ
number is 178. It also using fixed 26Mhz clock
as SPI CLK.

Signed-off-by: Argus Lin <argus.lin@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt6797.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt6797.dtsi b/arch/arm64/boot/dts/mediatek/mt6797.dtsi
index 4beaa71107d7..485546efc9bf 100644
--- a/arch/arm64/boot/dts/mediatek/mt6797.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6797.dtsi
@@ -161,6 +161,20 @@
 		      <0 0x10220690 0 0x10>;
 	};
 
+	pwrap: pwrap@1000d000 {
+		compatible = "mediatek,mt6797-pwrap";
+		reg = <0 0x1000d000 0 0x1000>;
+		reg-names = "pwrap";
+		interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk26m>, <&clk26m>;
+		clock-names = "spi", "wrap";
+
+		pmic: mt6351 {
+			compatible = "mediatek,mt6351";
+			interrupt-controller;
+		};
+	};
+
 	uart0: serial@11002000 {
 		compatible = "mediatek,mt6797-uart",
 			     "mediatek,mt6577-uart";
-- 
2.12.5

Re: [PATCH v2 2/5] arm64: dts: mt6797: add pwrap support for mt6797

[Matthias Brugger]

On 01/29/2018 10:09 AM, argus.lin@mediatek.com wrote:
> From: Argus Lin <argus.lin@mediatek.com>
> 
> mt6797 is a highly integrated SoCs, and it uses
> mt6351 as Power Management IC.
> We need to add pwrap device to communicate with
> mt6351 by SPI.
> The base address of pwrap is 0x1000d000, and IRQ
> number is 178. It also using fixed 26Mhz clock
> as SPI CLK.
> 
> Signed-off-by: Argus Lin <argus.lin@mediatek.com>
> ---

For the next round, can you put the dts patch at the end of the series. Binding
description should be the first patch, but actual dts(i) inclusion should be the
last one. It's bike shedding I know, but as you need a new series anyway.

Thanks.

>  arch/arm64/boot/dts/mediatek/mt6797.dtsi | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt6797.dtsi b/arch/arm64/boot/dts/mediatek/mt6797.dtsi
> index 4beaa71107d7..485546efc9bf 100644
> --- a/arch/arm64/boot/dts/mediatek/mt6797.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt6797.dtsi
> @@ -161,6 +161,20 @@
>  		      <0 0x10220690 0 0x10>;
>  	};
>  
> +	pwrap: pwrap@1000d000 {
> +		compatible = "mediatek,mt6797-pwrap";
> +		reg = <0 0x1000d000 0 0x1000>;
> +		reg-names = "pwrap";
> +		interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&clk26m>, <&clk26m>;
> +		clock-names = "spi", "wrap";
> +
> +		pmic: mt6351 {
> +			compatible = "mediatek,mt6351";
> +			interrupt-controller;
> +		};
> +	};
> +
>  	uart0: serial@11002000 {
>  		compatible = "mediatek,mt6797-uart",
>  			     "mediatek,mt6577-uart";
> -- 
> 2.12.5
> 
> ************* Email Confidentiality Notice
>  ********************
> The information contained in this e-mail message (including any 
> attachments) may be confidential, proprietary, privileged, or otherwise
> exempt from disclosure under applicable laws. It is intended to be 
> conveyed only to the designated recipient(s). Any use, dissemination, 
> distribution, printing, retaining or copying of this e-mail (including its 
> attachments) by unintended recipient(s) is strictly prohibited and may 
> be unlawful. If you are not an intended recipient of this e-mail, or believe
>  
> that you have received this e-mail in error, please notify the sender 
> immediately (by replying to this e-mail), delete any and all copies of 
> this e-mail (including any attachments) from your system, and do not
> disclose the content of this e-mail to any other person. Thank
>  you!
> 

Re: [PATCH v2 2/5] arm64: dts: mt6797: add pwrap support for mt6797

[Argus Lin]

[-- Attachment #1.1: Type: text/html, Size: 5867 bytes --]

[-- Attachment #1.2: Type: text/plain, Size: 2782 bytes --]

On Tue, 2018-01-30 at 13:57 +0100, Matthias Brugger wrote:
> 
> On 01/29/2018 10:09 AM, argus.lin@mediatek.com wrote:
> > From: Argus Lin <argus.lin@mediatek.com>
> > 
> > mt6797 is a highly integrated SoCs, and it uses
> > mt6351 as Power Management IC.
> > We need to add pwrap device to communicate with
> > mt6351 by SPI.
> > The base address of pwrap is 0x1000d000, and IRQ
> > number is 178. It also using fixed 26Mhz clock
> > as SPI CLK.
> > 
> > Signed-off-by: Argus Lin <argus.lin@mediatek.com>
> > ---
> 
> For the next round, can you put the dts patch at the end of the series. Binding
> description should be the first patch, but actual dts(i) inclusion should be the
> last one. It's bike shedding I know, but as you need a new series anyway.
> 
> Thanks.

Dear Matthias:
Sure, I will arrange in the next order.
> 
> >  arch/arm64/boot/dts/mediatek/mt6797.dtsi | 14 ++++++++++++++
> >  1 file changed, 14 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt6797.dtsi b/arch/arm64/boot/dts/mediatek/mt6797.dtsi
> > index 4beaa71107d7..485546efc9bf 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt6797.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt6797.dtsi
> > @@ -161,6 +161,20 @@
> >  		      <0 0x10220690 0 0x10>;
> >  	};
> >  
> > +	pwrap: pwrap@1000d000 {
> > +		compatible = "mediatek,mt6797-pwrap";
> > +		reg = <0 0x1000d000 0 0x1000>;
> > +		reg-names = "pwrap";
> > +		interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
> > +		clocks = <&clk26m>, <&clk26m>;
> > +		clock-names = "spi", "wrap";
> > +
> > +		pmic: mt6351 {
> > +			compatible = "mediatek,mt6351";
> > +			interrupt-controller;
> > +		};
> > +	};
> > +
> >  	uart0: serial@11002000 {
> >  		compatible = "mediatek,mt6797-uart",
> >  			     "mediatek,mt6577-uart";
> > -- 
> > 2.12.5
> > 
> > ************* Email Confidentiality Notice
> >  ********************
> > The information contained in this e-mail message (including any 
> > attachments) may be confidential, proprietary, privileged, or otherwise
> > exempt from disclosure under applicable laws. It is intended to be 
> > conveyed only to the designated recipient(s). Any use, dissemination, 
> > distribution, printing, retaining or copying of this e-mail (including its 
> > attachments) by unintended recipient(s) is strictly prohibited and may 
> > be unlawful. If you are not an intended recipient of this e-mail, or believe
> >  
> > that you have received this e-mail in error, please notify the sender 
> > immediately (by replying to this e-mail), delete any and all copies of 
> > this e-mail (including any attachments) from your system, and do not
> > disclose the content of this e-mail to any other person. Thank
> >  you!
> > 
> 

[PATCH v2 3/5] soc: mediatek: pwrap: add int1_en_all and capability flag

[argus.lin]

[-- Attachment #1.1: Type: text/html, Size: 2436 bytes --]

[-- Attachment #1.2: Type: text/plain, Size: 1500 bytes --]

From: Argus Lin <argus.lin@mediatek.com>

New pwrap support int1_en flag for starvation and channel
request exception. We need to register it for interrupt
handler.
We also add pwrap capability flag used to declare if we
support BRIDGE, RESET, DCM, PRIORITY_SEL and INT1_EN
or not.

Signed-off-by: Argus Lin <argus.lin@mediatek.com>
---
 drivers/soc/mediatek/mtk-pmic-wrap.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
index e9e054a15b7d..9f924d3f8645 100644
--- a/drivers/soc/mediatek/mtk-pmic-wrap.c
+++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
@@ -76,6 +76,13 @@
 #define PWRAP_SLV_CAP_SECURITY	BIT(2)
 #define HAS_CAP(_c, _x)	(((_c) & (_x)) == (_x))
 
+/* Group of bits used for shown pwrap capability */
+#define PWRAP_CAP_BRIDGE	BIT(0)
+#define PWRAP_CAP_RESET		BIT(1)
+#define PWRAP_CAP_DCM		BIT(2)
+#define PWRAP_CAP_PRIORITY_SEL	BIT(3)
+#define PWRAP_CAP_INT1_EN	BIT(4)
+
 /* defines for slave device wrapper registers */
 enum dew_regs {
 	PWRAP_DEW_BASE,
@@ -681,9 +688,11 @@ struct pmic_wrapper_type {
 	enum pwrap_type type;
 	u32 arb_en_all;
 	u32 int_en_all;
+	u32 int1_en_all;
 	u32 spi_w;
 	u32 wdt_src;
-	unsigned int has_bridge:1;
+	/* Flags indicating the capability for the target pwrap */
+	u32 caps;
 	int (*init_reg_clock)(struct pmic_wrapper *wrp);
 	int (*init_soc_specific)(struct pmic_wrapper *wrp);
 };
-- 
2.12.5

Re: [PATCH v2 3/5] soc: mediatek: pwrap: add int1_en_all and capability flag

[Matthias Brugger]

On 01/29/2018 10:09 AM, argus.lin@mediatek.com wrote:
> From: Argus Lin <argus.lin@mediatek.com>
> 
> New pwrap support int1_en flag for starvation and channel
> request exception. We need to register it for interrupt
> handler.
> We also add pwrap capability flag used to declare if we

"We also" wording is nearly always a hint, that this should be done
in two independent patches.

> support BRIDGE, RESET, DCM, PRIORITY_SEL and INT1_EN
> or not.
> 
> Signed-off-by: Argus Lin <argus.lin@mediatek.com>
> ---
>  drivers/soc/mediatek/mtk-pmic-wrap.c | 11 ++++++++++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
> index e9e054a15b7d..9f924d3f8645 100644
> --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
> +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
> @@ -76,6 +76,13 @@
>  #define PWRAP_SLV_CAP_SECURITY	BIT(2)
>  #define HAS_CAP(_c, _x)	(((_c) & (_x)) == (_x))
>  
> +/* Group of bits used for shown pwrap capability */
> +#define PWRAP_CAP_BRIDGE	BIT(0)
> +#define PWRAP_CAP_RESET		BIT(1)
> +#define PWRAP_CAP_DCM		BIT(2)

As you told me the driver will be upstreamed in April, please add this flag when
you upstream the driver, as this will be in a different kernel version.

> +#define PWRAP_CAP_PRIORITY_SEL	BIT(3)
> +#define PWRAP_CAP_INT1_EN	BIT(4)
> +

Add each flag when you add the user of the flag.

>  /* defines for slave device wrapper registers */
>  enum dew_regs {
>  	PWRAP_DEW_BASE,
> @@ -681,9 +688,11 @@ struct pmic_wrapper_type {
>  	enum pwrap_type type;
>  	u32 arb_en_all;
>  	u32 int_en_all;
> +	u32 int1_en_all;
>  	u32 spi_w;
>  	u32 wdt_src;
> -	unsigned int has_bridge:1;
> +	/* Flags indicating the capability for the target pwrap */
> +	u32 caps;

NAK, this will not compile. Please make sure that every patch on it's own does
not break compilation.

Regards,
Matthias

>  	int (*init_reg_clock)(struct pmic_wrapper *wrp);
>  	int (*init_soc_specific)(struct pmic_wrapper *wrp);
>  };
> -- 
> 2.12.5
> 
> ************* Email Confidentiality Notice
>  ********************
> The information contained in this e-mail message (including any 
> attachments) may be confidential, proprietary, privileged, or otherwise
> exempt from disclosure under applicable laws. It is intended to be 
> conveyed only to the designated recipient(s). Any use, dissemination, 
> distribution, printing, retaining or copying of this e-mail (including its 
> attachments) by unintended recipient(s) is strictly prohibited and may 
> be unlawful. If you are not an intended recipient of this e-mail, or believe
>  
> that you have received this e-mail in error, please notify the sender 
> immediately (by replying to this e-mail), delete any and all copies of 
> this e-mail (including any attachments) from your system, and do not
> disclose the content of this e-mail to any other person. Thank
>  you!
> 

Re: [PATCH v2 3/5] soc: mediatek: pwrap: add int1_en_all and capability flag

[Argus Lin]

[-- Attachment #1.1: Type: text/html, Size: 7804 bytes --]

[-- Attachment #1.2: Type: text/plain, Size: 4120 bytes --]

On Tue, 2018-01-30 at 13:55 +0100, Matthias Brugger wrote:
> 
> On 01/29/2018 10:09 AM, argus.lin@mediatek.com wrote:
> > From: Argus Lin <argus.lin@mediatek.com>
> > 
> > New pwrap support int1_en flag for starvation and channel
> > request exception. We need to register it for interrupt
> > handler.
> > We also add pwrap capability flag used to declare if we
> 
> "We also" wording is nearly always a hint, that this should be done
> in two independent patches.
> 
hmm, I see and will modify it.
> > support BRIDGE, RESET, DCM, PRIORITY_SEL and INT1_EN
> > or not.
> > 
> > Signed-off-by: Argus Lin <argus.lin@mediatek.com>
> > ---
> >  drivers/soc/mediatek/mtk-pmic-wrap.c | 11 ++++++++++-
> >  1 file changed, 10 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
> > index e9e054a15b7d..9f924d3f8645 100644
> > --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
> > +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
> > @@ -76,6 +76,13 @@
> >  #define PWRAP_SLV_CAP_SECURITY	BIT(2)
> >  #define HAS_CAP(_c, _x)	(((_c) & (_x)) == (_x))
> >  
> > +/* Group of bits used for shown pwrap capability */
> > +#define PWRAP_CAP_BRIDGE	BIT(0)
> > +#define PWRAP_CAP_RESET		BIT(1)
> > +#define PWRAP_CAP_DCM		BIT(2)
> 
> As you told me the driver will be upstreamed in April, please add this flag when
> you upstream the driver, as this will be in a different kernel version.
> 
Dear Matthias:
I add those flags for different wrap HW IP version.
To be forward compatible, I also modify MT2701/MT7622/MT8135/MT8173's
capability.
You can see [PATCH v2 4/5] soc: mediatek: pwrap: add pwrap for mt6797
SoCs for capability definition.
> > +#define PWRAP_CAP_PRIORITY_SEL	BIT(3)
> > +#define PWRAP_CAP_INT1_EN	BIT(4)
> > +
> 
> Add each flag when you add the user of the flag.

I had added new struct for mt6797, caps was included in it.
It was declared at [PATCH v2 4/5] soc: mediatek: pwrap: add pwrap for
mt6797 SoCs.

+static const struct pmic_wrapper_type pwrap_mt6797 = {
+	.regs = mt6797_regs,
+	.type = PWRAP_MT6797,
+	.arb_en_all = 0x01fff,
+	.int_en_all = 0xfffffffd,
+	.int1_en_all = 0x0001ffff,
+	.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
+	.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
+	.caps = PWRAP_CAP_DCM | PWRAP_CAP_PRIORITY_SEL | PWRAP_CAP_INT1_EN,
+	.init_reg_clock = pwrap_common_init_reg_clock,
+	.init_soc_specific = NULL,
+};
+

> 
> >  /* defines for slave device wrapper registers */
> >  enum dew_regs {
> >  	PWRAP_DEW_BASE,
> > @@ -681,9 +688,11 @@ struct pmic_wrapper_type {
> >  	enum pwrap_type type;
> >  	u32 arb_en_all;
> >  	u32 int_en_all;
> > +	u32 int1_en_all;
> >  	u32 spi_w;
> >  	u32 wdt_src;
> > -	unsigned int has_bridge:1;
> > +	/* Flags indicating the capability for the target pwrap */
> > +	u32 caps;
> 
> NAK, this will not compile. Please make sure that every patch on it's own does
> not break compilation.
> 
OK, I will check it.
> Regards,
> Matthias
> 
> >  	int (*init_reg_clock)(struct pmic_wrapper *wrp);
> >  	int (*init_soc_specific)(struct pmic_wrapper *wrp);
> >  };
> > -- 
> > 2.12.5
> > 
> > ************* Email Confidentiality Notice
> >  ********************
> > The information contained in this e-mail message (including any 
> > attachments) may be confidential, proprietary, privileged, or otherwise
> > exempt from disclosure under applicable laws. It is intended to be 
> > conveyed only to the designated recipient(s). Any use, dissemination, 
> > distribution, printing, retaining or copying of this e-mail (including its 
> > attachments) by unintended recipient(s) is strictly prohibited and may 
> > be unlawful. If you are not an intended recipient of this e-mail, or believe
> >  
> > that you have received this e-mail in error, please notify the sender 
> > immediately (by replying to this e-mail), delete any and all copies of 
> > this e-mail (including any attachments) from your system, and do not
> > disclose the content of this e-mail to any other person. Thank
> >  you!
> > 
> 

[PATCH v2 4/5] soc: mediatek: pwrap: add pwrap for mt6797 SoCs

[argus.lin]

[-- Attachment #1.1: Type: text/html, Size: 10825 bytes --]

[-- Attachment #1.2: Type: text/plain, Size: 9645 bytes --]

From: Argus Lin <argus.lin@mediatek.com>

mt6797 is a highly integrated SoCs, it uses mt6351 for power
management. We need to add pwrap support to access mt6351.
Pwrap of mt6797 also add new feature include starvation and
request exception interrupt, dynamic starvation priority
adjustment mechanism. Pwrap of mt6797 support capability
like dcm, priority selection and INT1 interrupt.

Signed-off-by: Argus Lin <argus.lin@mediatek.com>
---
 drivers/soc/mediatek/mtk-pmic-wrap.c | 137 +++++++++++++++++++++++++++++++----
 1 file changed, 123 insertions(+), 14 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
index 9f924d3f8645..690d2f545b1a 100644
--- a/drivers/soc/mediatek/mtk-pmic-wrap.c
+++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
@@ -285,6 +285,30 @@ enum pwrap_regs {
 	PWRAP_DVFS_WDATA7,
 	PWRAP_SPMINF_STA,
 	PWRAP_CIPHER_EN,
+
+	/* MT6797 series regs */
+	PWRAP_INT1_EN,
+	PWRAP_INT1_FLG_RAW,
+	PWRAP_INT1_FLG,
+	PWRAP_INT1_CLR,
+	PWRAP_PRIORITY_USER_SEL_0,
+	PWRAP_PRIORITY_USER_SEL_1,
+	PWRAP_ARBITER_OUT_SEL_0,
+	PWRAP_ARBITER_OUT_SEL_1,
+	PWRAP_STARV_COUNTER_0,
+	PWRAP_STARV_COUNTER_1,
+	PWRAP_STARV_COUNTER_2,
+	PWRAP_STARV_COUNTER_3,
+	PWRAP_STARV_COUNTER_4,
+	PWRAP_STARV_COUNTER_5,
+	PWRAP_STARV_COUNTER_6,
+	PWRAP_STARV_COUNTER_7,
+	PWRAP_STARV_COUNTER_8,
+	PWRAP_STARV_COUNTER_9,
+	PWRAP_STARV_COUNTER_10,
+	PWRAP_STARV_COUNTER_11,
+	PWRAP_STARV_COUNTER_12,
+	PWRAP_STARV_COUNTER_13,
 };
 
 static int mt2701_regs[] = {
@@ -651,6 +675,7 @@ enum pwrap_type {
 	PWRAP_MT7622,
 	PWRAP_MT8135,
 	PWRAP_MT8173,
+	PWRAP_MT6797,
 };
 
 struct pmic_wrapper;
@@ -1007,6 +1032,12 @@ static void pwrap_init_chip_select_ext(struct pmic_wrapper *wrp, u8 hext_write,
 static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp)
 {
 	switch (wrp->master->type) {
+	case PWRAP_MT6797:
+		pwrap_writel(wrp, 0x8, PWRAP_RDDMY);
+		pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO],
+			    0x8);
+		pwrap_init_chip_select_ext(wrp, 0x88, 0x55, 3, 0);
+		break;
 	case PWRAP_MT8173:
 		pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2);
 		break;
@@ -1077,11 +1108,14 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
 		break;
 	case PWRAP_MT2701:
 	case PWRAP_MT8173:
+	case PWRAP_MT6797:
 		pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
 		break;
 	case PWRAP_MT7622:
 		pwrap_writel(wrp, 0, PWRAP_CIPHER_EN);
 		break;
+	default:
+		break;
 	}
 
 	/* Config cipher mode @PMIC */
@@ -1235,6 +1269,27 @@ static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp)
 	return 0;
 }
 
+static int pwrap_set_starvation(struct pmic_wrapper *wrp)
+{
+	pwrap_writel(wrp, 0x0007, PWRAP_HARB_HPRIO);
+	pwrap_writel(wrp, 0x0402, PWRAP_STARV_COUNTER_0);
+	pwrap_writel(wrp, 0x0402, PWRAP_STARV_COUNTER_1);
+	pwrap_writel(wrp, 0x0403, PWRAP_STARV_COUNTER_2);
+	pwrap_writel(wrp, 0x0414, PWRAP_STARV_COUNTER_3);
+	pwrap_writel(wrp, 0x0420, PWRAP_STARV_COUNTER_4);
+	pwrap_writel(wrp, 0x0420, PWRAP_STARV_COUNTER_5);
+	pwrap_writel(wrp, 0x0420, PWRAP_STARV_COUNTER_6);
+	pwrap_writel(wrp, 0x0428, PWRAP_STARV_COUNTER_7);
+	pwrap_writel(wrp, 0x0428, PWRAP_STARV_COUNTER_8);
+	pwrap_writel(wrp, 0x0417, PWRAP_STARV_COUNTER_9);
+	pwrap_writel(wrp, 0x0563, PWRAP_STARV_COUNTER_10);
+	pwrap_writel(wrp, 0x047c, PWRAP_STARV_COUNTER_11);
+	pwrap_writel(wrp, 0x0740, PWRAP_STARV_COUNTER_12);
+	pwrap_writel(wrp, 0x0740, PWRAP_STARV_COUNTER_13);
+
+	return 0;
+}
+
 static int pwrap_init(struct pmic_wrapper *wrp)
 {
 	int ret;
@@ -1307,7 +1362,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
 	pwrap_writel(wrp, 1, PWRAP_INIT_DONE0);
 	pwrap_writel(wrp, 1, PWRAP_INIT_DONE1);
 
-	if (wrp->master->has_bridge) {
+	if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) {
 		writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3);
 		writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4);
 	}
@@ -1326,6 +1381,15 @@ static irqreturn_t pwrap_interrupt(int irqno, void *dev_id)
 
 	pwrap_writel(wrp, 0xffffffff, PWRAP_INT_CLR);
 
+	/* If we support INT1 interrupt, we also need to clear it */
+	if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN)) {
+		rdata = pwrap_readl(wrp, PWRAP_INT1_FLG);
+
+		dev_err(wrp->dev, "unexpected interrupt int1=0x%x\n", rdata);
+
+		pwrap_writel(wrp, rdata, PWRAP_INT1_CLR);
+	}
+
 	return IRQ_HANDLED;
 }
 
@@ -1400,9 +1464,10 @@ static const struct pmic_wrapper_type pwrap_mt2701 = {
 	.type = PWRAP_MT2701,
 	.arb_en_all = 0x3f,
 	.int_en_all = ~(u32)(BIT(31) | BIT(2)),
+	.int1_en_all = 0,
 	.spi_w = PWRAP_MAN_CMD_SPI_WRITE_NEW,
 	.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
-	.has_bridge = 0,
+	.caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
 	.init_reg_clock = pwrap_mt2701_init_reg_clock,
 	.init_soc_specific = pwrap_mt2701_init_soc_specific,
 };
@@ -1412,9 +1477,10 @@ static const struct pmic_wrapper_type pwrap_mt7622 = {
 	.type = PWRAP_MT7622,
 	.arb_en_all = 0xff,
 	.int_en_all = ~(u32)BIT(31),
+	.int1_en_all = 0,
 	.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
 	.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
-	.has_bridge = 0,
+	.caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
 	.init_reg_clock = pwrap_common_init_reg_clock,
 	.init_soc_specific = pwrap_mt7622_init_soc_specific,
 };
@@ -1424,9 +1490,10 @@ static const struct pmic_wrapper_type pwrap_mt8135 = {
 	.type = PWRAP_MT8135,
 	.arb_en_all = 0x1ff,
 	.int_en_all = ~(u32)(BIT(31) | BIT(1)),
+	.int1_en_all = 0,
 	.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
 	.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
-	.has_bridge = 1,
+	.caps = PWRAP_CAP_BRIDGE | PWRAP_CAP_RESET | PWRAP_CAP_DCM,
 	.init_reg_clock = pwrap_common_init_reg_clock,
 	.init_soc_specific = pwrap_mt8135_init_soc_specific,
 };
@@ -1436,13 +1503,27 @@ static const struct pmic_wrapper_type pwrap_mt8173 = {
 	.type = PWRAP_MT8173,
 	.arb_en_all = 0x3f,
 	.int_en_all = ~(u32)(BIT(31) | BIT(1)),
+	.int1_en_all = 0,
 	.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
 	.wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD,
-	.has_bridge = 0,
+	.caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
 	.init_reg_clock = pwrap_common_init_reg_clock,
 	.init_soc_specific = pwrap_mt8173_init_soc_specific,
 };
 
+static const struct pmic_wrapper_type pwrap_mt6797 = {
+	.regs = mt6797_regs,
+	.type = PWRAP_MT6797,
+	.arb_en_all = 0x01fff,
+	.int_en_all = 0xfffffffd,
+	.int1_en_all = 0x0001ffff,
+	.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
+	.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
+	.caps = PWRAP_CAP_DCM | PWRAP_CAP_PRIORITY_SEL | PWRAP_CAP_INT1_EN,
+	.init_reg_clock = pwrap_common_init_reg_clock,
+	.init_soc_specific = NULL,
+};
+
 static const struct of_device_id of_pwrap_match_tbl[] = {
 	{
 		.compatible = "mediatek,mt2701-pwrap",
@@ -1457,6 +1538,9 @@ static const struct of_device_id of_pwrap_match_tbl[] = {
 		.compatible = "mediatek,mt8173-pwrap",
 		.data = &pwrap_mt8173,
 	}, {
+		.compatible = "mediatek,mt6797-pwrap",
+		.data = &pwrap_mt6797,
+	}, {
 		/* sentinel */
 	}
 };
@@ -1500,14 +1584,16 @@ static int pwrap_probe(struct platform_device *pdev)
 	if (IS_ERR(wrp->base))
 		return PTR_ERR(wrp->base);
 
-	wrp->rstc = devm_reset_control_get(wrp->dev, "pwrap");
-	if (IS_ERR(wrp->rstc)) {
-		ret = PTR_ERR(wrp->rstc);
-		dev_dbg(wrp->dev, "cannot get pwrap reset: %d\n", ret);
-		return ret;
+	if (HAS_CAP(wrp->master->caps, PWRAP_CAP_RESET)) {
+		wrp->rstc = devm_reset_control_get(wrp->dev, "pwrap");
+		if (IS_ERR(wrp->rstc)) {
+			ret = PTR_ERR(wrp->rstc);
+			dev_dbg(wrp->dev, "cannot get pwrap reset: %d\n", ret);
+			return ret;
+		}
 	}
 
-	if (wrp->master->has_bridge) {
+	if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) {
 		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 				"pwrap-bridge");
 		wrp->bridge_base = devm_ioremap_resource(wrp->dev, res);
@@ -1538,6 +1624,16 @@ static int pwrap_probe(struct platform_device *pdev)
 		return PTR_ERR(wrp->clk_wrap);
 	}
 
+	/* Add priority adjust setting, it used to avoid starvation */
+	if (HAS_CAP(wrp->master->caps, PWRAP_CAP_PRIORITY_SEL)) {
+		pwrap_writel(wrp, 0x6543C210, PWRAP_PRIORITY_USER_SEL_0);
+		pwrap_writel(wrp, 0xFEDBA987, PWRAP_PRIORITY_USER_SEL_1);
+		pwrap_writel(wrp, 0x87654210, PWRAP_ARBITER_OUT_SEL_0);
+		pwrap_writel(wrp, 0xFED3CBA9, PWRAP_ARBITER_OUT_SEL_1);
+
+		pwrap_set_starvation(wrp);
+	}
+
 	ret = clk_prepare_enable(wrp->clk_spi);
 	if (ret)
 		return ret;
@@ -1546,9 +1642,16 @@ static int pwrap_probe(struct platform_device *pdev)
 	if (ret)
 		goto err_out1;
 
-	/* Enable internal dynamic clock */
-	pwrap_writel(wrp, 1, PWRAP_DCM_EN);
-	pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
+	/*
+	 * add dcm capability check
+	 */
+	if (HAS_CAP(wrp->master->caps, PWRAP_CAP_DCM)) {
+		if (wrp->master->type == PWRAP_MT6797)
+			pwrap_writel(wrp, 3, PWRAP_DCM_EN);
+		else
+			pwrap_writel(wrp, 1, PWRAP_DCM_EN);
+		pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
+	}
 
 	/*
 	 * The PMIC could already be initialized by the bootloader.
@@ -1577,6 +1680,12 @@ static int pwrap_probe(struct platform_device *pdev)
 	pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN);
 	pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
 	pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN);
+	/*
+	 * We add INT1 interrupt to handle starvation and request exception
+	 * If we support it, we should enable them here.
+	 */
+	if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN))
+		pwrap_writel(wrp, wrp->master->int1_en_all, PWRAP_INT1_EN);
 
 	irq = platform_get_irq(pdev, 0);
 	ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt,
-- 
2.12.5

[PATCH v2 5/5] soc: mediatek: pwrap: add mt6351 for mt6797 SoCs

[argus.lin]

[-- Attachment #1.1: Type: text/html, Size: 5640 bytes --]

[-- Attachment #1.2: Type: text/plain, Size: 4624 bytes --]

From: Argus Lin <argus.lin@mediatek.com>

mt6351 is a new power management IC and it is
used for mt6797 SoCs. We need to add mt6351_regs for
pmic register mapping and pmic_mt6351 for
register accessing by regmap.

Signed-off-by: Argus Lin <argus.lin@mediatek.com>
---
 drivers/soc/mediatek/mtk-pmic-wrap.c | 85 +++++++++++++++++++++++++++++++++++-
 1 file changed, 83 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
index 690d2f545b1a..a333ad6e400a 100644
--- a/drivers/soc/mediatek/mtk-pmic-wrap.c
+++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
@@ -153,6 +153,21 @@ static const u32 mt6397_regs[] = {
 	[PWRAP_DEW_CIPHER_SWRST] =	0xbc24,
 };
 
+static const u32 mt6351_regs[] = {
+	[PWRAP_DEW_DIO_EN] =		0x02F2,
+	[PWRAP_DEW_READ_TEST] =		0x02F4,
+	[PWRAP_DEW_WRITE_TEST] =	0x02F6,
+	[PWRAP_DEW_CRC_EN] =		0x02FA,
+	[PWRAP_DEW_CRC_VAL] =		0x02FC,
+	[PWRAP_DEW_CIPHER_KEY_SEL] =	0x0300,
+	[PWRAP_DEW_CIPHER_IV_SEL] =	0x0302,
+	[PWRAP_DEW_CIPHER_EN] =		0x0304,
+	[PWRAP_DEW_CIPHER_RDY] =	0x0306,
+	[PWRAP_DEW_CIPHER_MODE] =	0x0308,
+	[PWRAP_DEW_CIPHER_SWRST] =	0x030A,
+	[PWRAP_DEW_RDDMY_NO] =		0x030C,
+};
+
 enum pwrap_regs {
 	PWRAP_MUX_SEL,
 	PWRAP_WRAP_EN,
@@ -664,10 +679,65 @@ static int mt8135_regs[] = {
 	[PWRAP_DCM_DBC_PRD] =		0x160,
 };
 
+static int mt6797_regs[] = {
+	[PWRAP_MUX_SEL] =		0x0,
+	[PWRAP_WRAP_EN] =		0x4,
+	[PWRAP_DIO_EN] =		0x8,
+	[PWRAP_SIDLY] =			0xC,
+	[PWRAP_RDDMY] =			0x10,
+	[PWRAP_CSHEXT_WRITE] =		0x18,
+	[PWRAP_CSHEXT_READ] =		0x1C,
+	[PWRAP_CSLEXT_START] =		0x20,
+	[PWRAP_CSLEXT_END] =		0x24,
+	[PWRAP_STAUPD_PRD] =		0x28,
+	[PWRAP_HARB_HPRIO] =		0x50,
+	[PWRAP_HIPRIO_ARB_EN] =		0x54,
+	[PWRAP_MAN_EN] =		0x60,
+	[PWRAP_MAN_CMD] =		0x64,
+	[PWRAP_WACS0_EN] =		0x70,
+	[PWRAP_WACS1_EN] =		0x84,
+	[PWRAP_WACS2_EN] =		0x98,
+	[PWRAP_INIT_DONE2] =		0x9C,
+	[PWRAP_WACS2_CMD] =		0xA0,
+	[PWRAP_WACS2_RDATA] =		0xA4,
+	[PWRAP_WACS2_VLDCLR] =		0xA8,
+	[PWRAP_INT_EN] =		0xC0,
+	[PWRAP_INT_FLG_RAW] =		0xC4,
+	[PWRAP_INT_FLG] =		0xC8,
+	[PWRAP_INT_CLR] =		0xCC,
+	[PWRAP_INT1_EN] =		0xD0,
+	[PWRAP_INT1_FLG_RAW] =		0xD4,
+	[PWRAP_INT1_FLG] =		0xD8,
+	[PWRAP_INT1_CLR] =		0xDC,
+	[PWRAP_TIMER_EN] =		0xF4,
+	[PWRAP_WDT_UNIT] =		0xFC,
+	[PWRAP_WDT_SRC_EN] =		0x100,
+	[PWRAP_DCM_EN] =		0x1CC,
+	[PWRAP_DCM_DBC_PRD] =		0x1D4,
+	[PWRAP_PRIORITY_USER_SEL_0] =	0x288,
+	[PWRAP_PRIORITY_USER_SEL_1] =	0x28C,
+	[PWRAP_ARBITER_OUT_SEL_0] =	0x290,
+	[PWRAP_ARBITER_OUT_SEL_1] =	0x294,
+	[PWRAP_STARV_COUNTER_0] =	0x298,
+	[PWRAP_STARV_COUNTER_1] =	0x29C,
+	[PWRAP_STARV_COUNTER_2] =	0x2A0,
+	[PWRAP_STARV_COUNTER_3] =	0x2A4,
+	[PWRAP_STARV_COUNTER_4] =	0x2A8,
+	[PWRAP_STARV_COUNTER_5] =	0x2AC,
+	[PWRAP_STARV_COUNTER_6] =	0x2B0,
+	[PWRAP_STARV_COUNTER_7] =	0x2B4,
+	[PWRAP_STARV_COUNTER_8] =	0x2B8,
+	[PWRAP_STARV_COUNTER_9] =	0x2BC,
+	[PWRAP_STARV_COUNTER_10] =	0x2C0,
+	[PWRAP_STARV_COUNTER_11] =	0x2C4,
+	[PWRAP_STARV_COUNTER_12] =	0x2C8,
+	[PWRAP_STARV_COUNTER_13] =	0x2CC,
+};
 enum pmic_type {
 	PMIC_MT6323,
 	PMIC_MT6380,
 	PMIC_MT6397,
+	PMIC_MT6351,
 };
 
 enum pwrap_type {
@@ -1123,8 +1193,6 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
 	pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0);
 	pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1);
 	pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2);
-	pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD], 0x1);
-	pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_START], 0x1);
 
 	switch (wrp->slave->type) {
 	case PMIC_MT6397:
@@ -1134,6 +1202,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
 			    0x1);
 		break;
 	case PMIC_MT6323:
+	case PMIC_MT6351:
 		pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_EN],
 			    0x1);
 		break;
@@ -1440,6 +1509,15 @@ static const struct pwrap_slv_type pmic_mt6397 = {
 	.pwrap_write = pwrap_write16,
 };
 
+static const struct pwrap_slv_type pmic_mt6351 = {
+	.dew_regs = mt6351_regs,
+	.type = PMIC_MT6351,
+	.regmap = &pwrap_regmap_config16,
+	.caps = 0,
+	.pwrap_read = pwrap_read16,
+	.pwrap_write = pwrap_write16,
+};
+
 static const struct of_device_id of_slave_match_tbl[] = {
 	{
 		.compatible = "mediatek,mt6323",
@@ -1454,6 +1532,9 @@ static const struct of_device_id of_slave_match_tbl[] = {
 		.compatible = "mediatek,mt6397",
 		.data = &pmic_mt6397,
 	}, {
+		.compatible = "mediatek,mt6351",
+		.data = &pmic_mt6351,
+	}, {
 		/* sentinel */
 	}
 };
-- 
2.12.5

Re: [PATCH v2 1/5] dt-bindings: pwrap: mediatek: add pwrap support for MT6797

[Matthias Brugger]

On 01/29/2018 10:09 AM, argus.lin@mediatek.com wrote:
> From: Argus Lin <argus.lin@mediatek.com>
> 
> We add pwrap support for MT6797 SoCs.
> 
> Signed-off-by: Argus Lin <argus.lin@mediatek.com>
> ---
>  Documentation/devicetree/bindings/soc/mediatek/pwrap.txt | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
> index bf80e3f96f8c..f9987c30f0d5 100644
> --- a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
> +++ b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
> @@ -19,6 +19,7 @@ IP Pairing
>  Required properties in pwrap device node.
>  - compatible:
>  	"mediatek,mt2701-pwrap" for MT2701/7623 SoCs
> +	"mediatek,mt6797-pwrap" for MT6797 SoCs

Looks good to me. When you send the new series, would you mind to add a cover
letter in which you describe which changes you made in every version of the
patch series? That makes the reviewing for me much easier :)

Thanks!

>  	"mediatek,mt7622-pwrap" for MT7622 SoCs
>  	"mediatek,mt8135-pwrap" for MT8135 SoCs
>  	"mediatek,mt8173-pwrap" for MT8173 SoCs
> -- 
> 2.12.5
> 
> ************* Email Confidentiality Notice
>  ********************
> The information contained in this e-mail message (including any 
> attachments) may be confidential, proprietary, privileged, or otherwise
> exempt from disclosure under applicable laws. It is intended to be 
> conveyed only to the designated recipient(s). Any use, dissemination, 
> distribution, printing, retaining or copying of this e-mail (including its 
> attachments) by unintended recipient(s) is strictly prohibited and may 
> be unlawful. If you are not an intended recipient of this e-mail, or believe
>  
> that you have received this e-mail in error, please notify the sender 
> immediately (by replying to this e-mail), delete any and all copies of 
> this e-mail (including any attachments) from your system, and do not
> disclose the content of this e-mail to any other person. Thank
>  you!
> 

RE: [PATCH v2 1/5] dt-bindings: pwrap: mediatek: add pwrap support for MT6797

[Argus Lin (林書慶)]

[-- Attachment #1.1: Type: text/html, Size: 5760 bytes --]

[-- Attachment #1.2: Type: text/plain, Size: 3108 bytes --]



-----Original Message-----
From: Matthias Brugger [mailto:matthias.bgg@gmail.com] 
Sent: Tuesday, January 30, 2018 8:58 PM
To: Argus Lin (林書慶) <argus.lin@mediatek.com>; Rob Herring <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>; Catalin Marinas <catalin.marinas@arm.com>; Will Deacon <will.deacon@arm.com>
Cc: Chenglin Xu (徐成林) <Chenglin.Xu@mediatek.com>; Sean Wang (王志亘) <sean.wang@mediatek.com>; wsd_upstream <wsd_upstream@mediatek.com>; HenryC Chen (陳建豪) <HenryC.Chen@mediatek.com>; Flora Fu (傅君茹) <Flora.Fu@mediatek.com>; Chen Zhong (钟辰) <Chen.Zhong@mediatek.com>; Christophe Jaillet <christophe.jaillet@wanadoo.fr>; shailendra . v <shailendra.v@samsung.com>; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-mediatek@lists.infradead.org
Subject: Re: [PATCH v2 1/5] dt-bindings: pwrap: mediatek: add pwrap support for MT6797



On 01/29/2018 10:09 AM, argus.lin@mediatek.com wrote:
> From: Argus Lin <argus.lin@mediatek.com>
> 
> We add pwrap support for MT6797 SoCs.
> 
> Signed-off-by: Argus Lin <argus.lin@mediatek.com>
> ---
>  Documentation/devicetree/bindings/soc/mediatek/pwrap.txt | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt 
> b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
> index bf80e3f96f8c..f9987c30f0d5 100644
> --- a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
> +++ b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
> @@ -19,6 +19,7 @@ IP Pairing
>  Required properties in pwrap device node.
>  - compatible:
>  	"mediatek,mt2701-pwrap" for MT2701/7623 SoCs
> +	"mediatek,mt6797-pwrap" for MT6797 SoCs

Looks good to me. When you send the new series, would you mind to add a cover letter in which you describe which changes you made in every version of the patch series? That makes the reviewing for me much easier :)

Thanks!

Dear Matthias:
Sure, I will add cover letter next time.
>  	"mediatek,mt7622-pwrap" for MT7622 SoCs
>  	"mediatek,mt8135-pwrap" for MT8135 SoCs
>  	"mediatek,mt8173-pwrap" for MT8173 SoCs
> --
> 2.12.5
> 
> ************* Email Confidentiality Notice
>  ********************
> The information contained in this e-mail message (including any
> attachments) may be confidential, proprietary, privileged, or 
> otherwise exempt from disclosure under applicable laws. It is intended 
> to be conveyed only to the designated recipient(s). Any use, 
> dissemination, distribution, printing, retaining or copying of this 
> e-mail (including its
> attachments) by unintended recipient(s) is strictly prohibited and may 
> be unlawful. If you are not an intended recipient of this e-mail, or 
> believe
>  
> that you have received this e-mail in error, please notify the sender 
> immediately (by replying to this e-mail), delete any and all copies of 
> this e-mail (including any attachments) from your system, and do not 
> disclose the content of this e-mail to any other person. Thank  you!
>