[PATCH v3 0/7] Fix AST2600 quad mode SPI pinmux settings

[PATCH v3 0/7] Fix AST2600 quad mode SPI pinmux settings

[Jae Hyun Yoo]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="UTF-8", Size: 1610 bytes --]

I’m sending this patch series to fix current issues in AST2600 pinmux
settings while enabling quad mode SPI support.

FWSPI18 pins are basically 1.8v logic pins that are different from the
dedicated FWSPI pins that provide 3.3v logic level, so FWSPI18 pins can’t
be grouped with FWSPIDQ2 and FWSPIDQ3, so this series fix the issue.

Also, fixes QSPI1 and QSPI2 function settings in AST2600 pinctrl dtsi to
make it able to enable quad mode on SPI1 and SPI2 interfaces.

With this series, quad mode pinmux can be set like below.

FW SPI:
&fmc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fwqspi_default>;
}

SPI1:
&spi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_qspi1_default>;
}

SPI2:
&spi2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_qspi2_default>;
}

Please review.

Thanks,
Jae

Changes in v3:
 * Added bindings patches. (Andrew)

Changes in v2:
 * Rebased it on the latest.

Jae Hyun Yoo (5):
  ARM: dts: aspeed-g6: remove FWQSPID group in pinctrl dtsi
  pinctrl: pinctrl-aspeed-g6: remove FWQSPID group in pinctrl
  dt-bindings: pinctrl: aspeed-g6: remove FWQSPID group
  dt-bindings: pinctrl: aspeed-g6: add FWQSPI function/group
  ARM: dts: aspeed-g6: fix SPI1/SPI2 quad pin group

Johnny Huang (2):
  pinctrl: pinctrl-aspeed-g6: add FWQSPI function-group
  ARM: dts: aspeed-g6: add FWQSPI group in pinctrl dtsi

 .../pinctrl/aspeed,ast2600-pinctrl.yaml         |  4 ++--
 arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi        | 10 +++++-----
 drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c      | 17 ++++++++---------
 3 files changed, 15 insertions(+), 16 deletions(-)

-- 
2.25.1

[PATCH v3 1/7] ARM: dts: aspeed-g6: remove FWQSPID group in pinctrl dtsi

[Jae Hyun Yoo]

FWSPIDQ2 and FWSPIDQ3 are not part of FWSPI18 interface so remove
FWQSPID group in pinctrl dtsi. These pins must be used with the
FWSPI pins that are dedicated for boot SPI interface which provides
same 3.3v logic level.

Fixes: 2f6edb6bcb2f ("ARM: dts: aspeed: Fix AST2600 quad spi group")
Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
---
Changes in v3:
 * None.

Changes in v2:
 * Rebased it on the latest.
 * Updated 'Fixes' while rebasing it on the latest.

Note:
 * Removing 'pinctrl_fwqspid_default' doesn't break any existing DT since
   it has not been used in any DTs.

 arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi
index e4775bbceecc..06d60a8540e9 100644
--- a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi
@@ -117,11 +117,6 @@ pinctrl_fwspid_default: fwspid_default {
 		groups = "FWSPID";
 	};
 
-	pinctrl_fwqspid_default: fwqspid_default {
-		function = "FWSPID";
-		groups = "FWQSPID";
-	};
-
 	pinctrl_fwspiwp_default: fwspiwp_default {
 		function = "FWSPIWP";
 		groups = "FWSPIWP";
-- 
2.25.1

[PATCH v3 2/7] pinctrl: pinctrl-aspeed-g6: remove FWQSPID group in pinctrl

[Jae Hyun Yoo]

FWSPIDQ2 and FWSPIDQ3 are not part of FWSPI18 interface so remove
FWQSPID group in pinctrl. These pins must be used with the FWSPI
pins that are dedicated for boot SPI interface which provides
same 3.3v logic level.

Fixes: 2eda1cdec49f ("pinctrl: aspeed: Add AST2600 pinmux support")
Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
---
Changes in v3:
 * None.

Changes in v2:
 * None.

 drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 14 +++-----------
 1 file changed, 3 insertions(+), 11 deletions(-)

diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
index a3fa03bcd9a3..54064714d73f 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
@@ -1236,18 +1236,12 @@ FUNC_GROUP_DECL(SALT8, AA12);
 FUNC_GROUP_DECL(WDTRST4, AA12);
 
 #define AE12 196
-SIG_EXPR_LIST_DECL_SEMG(AE12, FWSPIDQ2, FWQSPID, FWSPID,
-			SIG_DESC_SET(SCU438, 4));
 SIG_EXPR_LIST_DECL_SESG(AE12, GPIOY4, GPIOY4);
-PIN_DECL_(AE12, SIG_EXPR_LIST_PTR(AE12, FWSPIDQ2),
-	  SIG_EXPR_LIST_PTR(AE12, GPIOY4));
+PIN_DECL_(AE12, SIG_EXPR_LIST_PTR(AE12, GPIOY4));
 
 #define AF12 197
-SIG_EXPR_LIST_DECL_SEMG(AF12, FWSPIDQ3, FWQSPID, FWSPID,
-			SIG_DESC_SET(SCU438, 5));
 SIG_EXPR_LIST_DECL_SESG(AF12, GPIOY5, GPIOY5);
-PIN_DECL_(AF12, SIG_EXPR_LIST_PTR(AF12, FWSPIDQ3),
-	  SIG_EXPR_LIST_PTR(AF12, GPIOY5));
+PIN_DECL_(AF12, SIG_EXPR_LIST_PTR(AF12, GPIOY5));
 
 #define AC12 198
 SSSF_PIN_DECL(AC12, GPIOY6, FWSPIABR, SIG_DESC_SET(SCU438, 6));
@@ -1520,9 +1514,8 @@ SIG_EXPR_LIST_DECL_SEMG(Y4, EMMCDAT7, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 3));
 PIN_DECL_3(Y4, GPIO18E3, FWSPIDMISO, VBMISO, EMMCDAT7);
 
 GROUP_DECL(FWSPID, Y1, Y2, Y3, Y4);
-GROUP_DECL(FWQSPID, Y1, Y2, Y3, Y4, AE12, AF12);
 GROUP_DECL(EMMCG8, AB4, AA4, AC4, AA5, Y5, AB5, AB6, AC5, Y1, Y2, Y3, Y4);
-FUNC_DECL_2(FWSPID, FWSPID, FWQSPID);
+FUNC_DECL_1(FWSPID, FWSPID);
 FUNC_GROUP_DECL(VB, Y1, Y2, Y3, Y4);
 FUNC_DECL_3(EMMC, EMMCG1, EMMCG4, EMMCG8);
 /*
@@ -1918,7 +1911,6 @@ static const struct aspeed_pin_group aspeed_g6_groups[] = {
 	ASPEED_PINCTRL_GROUP(FSI2),
 	ASPEED_PINCTRL_GROUP(FWSPIABR),
 	ASPEED_PINCTRL_GROUP(FWSPID),
-	ASPEED_PINCTRL_GROUP(FWQSPID),
 	ASPEED_PINCTRL_GROUP(FWSPIWP),
 	ASPEED_PINCTRL_GROUP(GPIT0),
 	ASPEED_PINCTRL_GROUP(GPIT1),
-- 
2.25.1

[PATCH v3 3/7] dt-bindings: pinctrl: aspeed-g6: remove FWQSPID group

[Jae Hyun Yoo]

FWQSPID is not a group of FWSPID so remove it.

Fixes: 7488838f2315 ("dt-bindings: pinctrl: aspeed: Document AST2600 pinmux")
Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
---
Changes in v3:
 * Newly added in v3. (Andrew)

 .../devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml     | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml
index 57b68d6c7c70..eb6e2f2dc9eb 100644
--- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml
@@ -58,7 +58,7 @@ patternProperties:
           $ref: "/schemas/types.yaml#/definitions/string"
           enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, ADC2,
                   ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMCG1, EMMCG4,
-                  EMMCG8, ESPI, ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID, FWQSPID, FWSPIWP,
+                  EMMCG8, ESPI, ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID, FWSPIWP,
                   GPIT0, GPIT1, GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1,
                   GPIU2, GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, HVI3C3, HVI3C4, I2C1, I2C10,
                   I2C11, I2C12, I2C13, I2C14, I2C15, I2C16, I2C2, I2C3, I2C4, I2C5,
-- 
2.25.1

[PATCH v3 4/7] pinctrl: pinctrl-aspeed-g6: add FWQSPI function-group

[Jae Hyun Yoo]

From: Johnny Huang <johnny_huang@aspeedtech.com>

Add FWSPIDQ2 (AE12) and FWSPIDQ3 (AF12) function-group to support
AST2600 FW SPI quad mode. These pins can be used with dedicated FW
SPI pins - FWSPICS0# (AB14), FWSPICK (AF13), FWSPIMOSI (AC14)
and FWSPIMISO (AB13).

Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com>
Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
---
Changes in v3:
 * None.

Changes in v2:
 * None.

 drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
index 54064714d73f..80838dc54b3a 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
@@ -1236,12 +1236,17 @@ FUNC_GROUP_DECL(SALT8, AA12);
 FUNC_GROUP_DECL(WDTRST4, AA12);
 
 #define AE12 196
+SIG_EXPR_LIST_DECL_SESG(AE12, FWSPIQ2, FWQSPI, SIG_DESC_SET(SCU438, 4));
 SIG_EXPR_LIST_DECL_SESG(AE12, GPIOY4, GPIOY4);
-PIN_DECL_(AE12, SIG_EXPR_LIST_PTR(AE12, GPIOY4));
+PIN_DECL_(AE12, SIG_EXPR_LIST_PTR(AE12, FWSPIQ2),
+	  SIG_EXPR_LIST_PTR(AE12, GPIOY4));
 
 #define AF12 197
+SIG_EXPR_LIST_DECL_SESG(AF12, FWSPIQ3, FWQSPI, SIG_DESC_SET(SCU438, 5));
 SIG_EXPR_LIST_DECL_SESG(AF12, GPIOY5, GPIOY5);
-PIN_DECL_(AF12, SIG_EXPR_LIST_PTR(AF12, GPIOY5));
+PIN_DECL_(AF12, SIG_EXPR_LIST_PTR(AF12, FWSPIQ3),
+	  SIG_EXPR_LIST_PTR(AF12, GPIOY5));
+FUNC_GROUP_DECL(FWQSPI, AE12, AF12);
 
 #define AC12 198
 SSSF_PIN_DECL(AC12, GPIOY6, FWSPIABR, SIG_DESC_SET(SCU438, 6));
@@ -1911,6 +1916,7 @@ static const struct aspeed_pin_group aspeed_g6_groups[] = {
 	ASPEED_PINCTRL_GROUP(FSI2),
 	ASPEED_PINCTRL_GROUP(FWSPIABR),
 	ASPEED_PINCTRL_GROUP(FWSPID),
+	ASPEED_PINCTRL_GROUP(FWQSPI),
 	ASPEED_PINCTRL_GROUP(FWSPIWP),
 	ASPEED_PINCTRL_GROUP(GPIT0),
 	ASPEED_PINCTRL_GROUP(GPIT1),
@@ -2152,6 +2158,7 @@ static const struct aspeed_pin_function aspeed_g6_functions[] = {
 	ASPEED_PINCTRL_FUNC(FSI2),
 	ASPEED_PINCTRL_FUNC(FWSPIABR),
 	ASPEED_PINCTRL_FUNC(FWSPID),
+	ASPEED_PINCTRL_FUNC(FWQSPI),
 	ASPEED_PINCTRL_FUNC(FWSPIWP),
 	ASPEED_PINCTRL_FUNC(GPIT0),
 	ASPEED_PINCTRL_FUNC(GPIT1),
-- 
2.25.1

[PATCH v3 5/7] dt-bindings: pinctrl: aspeed-g6: add FWQSPI function/group

[Jae Hyun Yoo]

Add FWQSPI function/group to support QSPI mode on the dedicated
FWSPI interface.

Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
---
Changes in v3:
 * Newly added in v3. (Andrew)

 .../devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml   | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml
index eb6e2f2dc9eb..3666ac5b6518 100644
--- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml
@@ -33,7 +33,7 @@ patternProperties:
           $ref: "/schemas/types.yaml#/definitions/string"
           enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, ADC2,
                   ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMC, ESPI, ESPIALT,
-                  FSI1, FSI2, FWSPIABR, FWSPID, FWSPIWP, GPIT0, GPIT1, GPIT2, GPIT3,
+                  FSI1, FSI2, FWQSPI, FWSPIABR, FWSPID, FWSPIWP, GPIT0, GPIT1, GPIT2, GPIT3,
                   GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1, GPIU2, GPIU3, GPIU4, GPIU5,
                   GPIU6, GPIU7, I2C1, I2C10, I2C11, I2C12, I2C13, I2C14, I2C15, I2C16,
                   I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5,
@@ -58,7 +58,7 @@ patternProperties:
           $ref: "/schemas/types.yaml#/definitions/string"
           enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, ADC2,
                   ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMCG1, EMMCG4,
-                  EMMCG8, ESPI, ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID, FWSPIWP,
+                  EMMCG8, ESPI, ESPIALT, FSI1, FSI2, FWQSPI, FWSPIABR, FWSPID, FWSPIWP,
                   GPIT0, GPIT1, GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1,
                   GPIU2, GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, HVI3C3, HVI3C4, I2C1, I2C10,
                   I2C11, I2C12, I2C13, I2C14, I2C15, I2C16, I2C2, I2C3, I2C4, I2C5,
-- 
2.25.1

[PATCH v3 6/7] ARM: dts: aspeed-g6: add FWQSPI group in pinctrl dtsi

[Jae Hyun Yoo]

From: Johnny Huang <johnny_huang@aspeedtech.com>

Add FWSPIDQ2 and FWSPIDQ3 group to support AST2600 FW SPI quad mode.
These pins can be used with dedicated FW SPI pins - FWSPICS0#,
FWSPICK, FWSPIMOSI and FWSPIMISO.

Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com>
Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
---
Changes in v3:
 * None.

Changes in v2:
 * None.

 arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi
index 06d60a8540e9..47c3fb137cbc 100644
--- a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi
@@ -117,6 +117,11 @@ pinctrl_fwspid_default: fwspid_default {
 		groups = "FWSPID";
 	};
 
+	pinctrl_fwqspi_default: fwqspi_default {
+		function = "FWQSPI";
+		groups = "FWQSPI";
+	};
+
 	pinctrl_fwspiwp_default: fwspiwp_default {
 		function = "FWSPIWP";
 		groups = "FWSPIWP";
-- 
2.25.1

[PATCH v3 7/7] ARM: dts: aspeed-g6: fix SPI1/SPI2 quad pin group

[Jae Hyun Yoo]

Fix incorrect function mappings in pinctrl_qspi1_default and
pinctrl_qspi2_default since their function should be SPI1 and
SPI2 respectively.

Fixes: f510f04c8c83 ("ARM: dts: aspeed: Add AST2600 pinmux nodes")
Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
---
Changes in v3:
 * None.

Changes in v2:
 * None.

 arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi
index 47c3fb137cbc..7cd4f075e325 100644
--- a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi
@@ -653,12 +653,12 @@ pinctrl_pwm9g1_default: pwm9g1_default {
 	};
 
 	pinctrl_qspi1_default: qspi1_default {
-		function = "QSPI1";
+		function = "SPI1";
 		groups = "QSPI1";
 	};
 
 	pinctrl_qspi2_default: qspi2_default {
-		function = "QSPI2";
+		function = "SPI2";
 		groups = "QSPI2";
 	};
 
-- 
2.25.1

Re: [PATCH v3 3/7] dt-bindings: pinctrl: aspeed-g6: remove FWQSPID group

[Rob Herring]

On Tue, 29 Mar 2022 10:39:28 -0700, Jae Hyun Yoo wrote:
> FWQSPID is not a group of FWSPID so remove it.
> 
> Fixes: 7488838f2315 ("dt-bindings: pinctrl: aspeed: Document AST2600 pinmux")
> Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
> ---
> Changes in v3:
>  * Newly added in v3. (Andrew)
> 
>  .../devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml     | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v3 5/7] dt-bindings: pinctrl: aspeed-g6: add FWQSPI function/group

[Rob Herring]

On Tue, 29 Mar 2022 10:39:30 -0700, Jae Hyun Yoo wrote:
> Add FWQSPI function/group to support QSPI mode on the dedicated
> FWSPI interface.
> 
> Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
> ---
> Changes in v3:
>  * Newly added in v3. (Andrew)
> 
>  .../devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml   | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v3 2/7] pinctrl: pinctrl-aspeed-g6: remove FWQSPID group in pinctrl

[Andrew Jeffery]

On Wed, 30 Mar 2022, at 04:09, Jae Hyun Yoo wrote:
> FWSPIDQ2 and FWSPIDQ3 are not part of FWSPI18 interface so remove
> FWQSPID group in pinctrl. These pins must be used with the FWSPI
> pins that are dedicated for boot SPI interface which provides
> same 3.3v logic level.
>
> Fixes: 2eda1cdec49f ("pinctrl: aspeed: Add AST2600 pinmux support")
> Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>

Reviewed-by: Andrew Jeffery <andrew@aj.id.au>

Re: [PATCH v3 3/7] dt-bindings: pinctrl: aspeed-g6: remove FWQSPID group

[Andrew Jeffery]

On Wed, 30 Mar 2022, at 04:09, Jae Hyun Yoo wrote:
> FWQSPID is not a group of FWSPID so remove it.
>
> Fixes: 7488838f2315 ("dt-bindings: pinctrl: aspeed: Document AST2600 pinmux")
> Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>

Reviewed-by: Andrew Jeffery <andrew@aj.id.au>

Re: [PATCH v3 4/7] pinctrl: pinctrl-aspeed-g6: add FWQSPI function-group

[Andrew Jeffery]

On Wed, 30 Mar 2022, at 04:09, Jae Hyun Yoo wrote:
> From: Johnny Huang <johnny_huang@aspeedtech.com>
>
> Add FWSPIDQ2 (AE12) and FWSPIDQ3 (AF12) function-group to support
> AST2600 FW SPI quad mode. These pins can be used with dedicated FW
> SPI pins - FWSPICS0# (AB14), FWSPICK (AF13), FWSPIMOSI (AC14)
> and FWSPIMISO (AB13).
>
> Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com>
> Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>

Reviewed-by: Andrew Jeffery <andrew@aj.id.au>

Re: [PATCH v3 5/7] dt-bindings: pinctrl: aspeed-g6: add FWQSPI function/group

[Andrew Jeffery]

On Wed, 30 Mar 2022, at 04:09, Jae Hyun Yoo wrote:
> Add FWQSPI function/group to support QSPI mode on the dedicated
> FWSPI interface.
>
> Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>

Reviewed-by: Andrew Jeffery <andrew@aj.id.au>

Re: [PATCH v3 6/7] ARM: dts: aspeed-g6: add FWQSPI group in pinctrl dtsi

[Andrew Jeffery]

On Wed, 30 Mar 2022, at 04:09, Jae Hyun Yoo wrote:
> From: Johnny Huang <johnny_huang@aspeedtech.com>
>
> Add FWSPIDQ2 and FWSPIDQ3 group to support AST2600 FW SPI quad mode.
> These pins can be used with dedicated FW SPI pins - FWSPICS0#,
> FWSPICK, FWSPIMOSI and FWSPIMISO.
>
> Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com>
> Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>

Reviewed-by: Andrew Jeffery <andrew@aj.id.au>

Re: [PATCH v3 0/7] Fix AST2600 quad mode SPI pinmux settings

[Joel Stanley]

On Tue, 29 Mar 2022 at 17:40, Jae Hyun Yoo <quic_jaehyoo@quicinc.com> wrote:
>
> I’m sending this patch series to fix current issues in AST2600 pinmux
> settings while enabling quad mode SPI support.
>
> FWSPI18 pins are basically 1.8v logic pins that are different from the
> dedicated FWSPI pins that provide 3.3v logic level, so FWSPI18 pins can’t
> be grouped with FWSPIDQ2 and FWSPIDQ3, so this series fix the issue.
>
> Also, fixes QSPI1 and QSPI2 function settings in AST2600 pinctrl dtsi to
> make it able to enable quad mode on SPI1 and SPI2 interfaces.
>
> With this series, quad mode pinmux can be set like below.
>
> FW SPI:
> &fmc {
>         pinctrl-names = "default";
>         pinctrl-0 = <&pinctrl_fwqspi_default>;
> }
>
> SPI1:
> &spi1 {
>         pinctrl-names = "default";
>         pinctrl-0 = <&pinctrl_qspi1_default>;
> }
>
> SPI2:
> &spi2 {
>         pinctrl-names = "default";
>         pinctrl-0 = <&pinctrl_qspi2_default>;
> }

Thanks. I hope to see a board from you that uses this soon :)

I'll send the patches as fixes once -rc1 is out.

>
> Please review.
>
> Thanks,
> Jae
>
> Changes in v3:
>  * Added bindings patches. (Andrew)
>
> Changes in v2:
>  * Rebased it on the latest.
>
> Jae Hyun Yoo (5):
>   ARM: dts: aspeed-g6: remove FWQSPID group in pinctrl dtsi
>   pinctrl: pinctrl-aspeed-g6: remove FWQSPID group in pinctrl
>   dt-bindings: pinctrl: aspeed-g6: remove FWQSPID group
>   dt-bindings: pinctrl: aspeed-g6: add FWQSPI function/group
>   ARM: dts: aspeed-g6: fix SPI1/SPI2 quad pin group
>
> Johnny Huang (2):
>   pinctrl: pinctrl-aspeed-g6: add FWQSPI function-group
>   ARM: dts: aspeed-g6: add FWQSPI group in pinctrl dtsi
>
>  .../pinctrl/aspeed,ast2600-pinctrl.yaml         |  4 ++--
>  arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi        | 10 +++++-----
>  drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c      | 17 ++++++++---------
>  3 files changed, 15 insertions(+), 16 deletions(-)
>
> --
> 2.25.1
>

Re: [PATCH v3 0/7] Fix AST2600 quad mode SPI pinmux settings

[Jae Hyun Yoo]

On 3/30/2022 10:50 PM, Joel Stanley wrote:
> On Tue, 29 Mar 2022 at 17:40, Jae Hyun Yoo <quic_jaehyoo@quicinc.com> wrote:
>>
>> I’m sending this patch series to fix current issues in AST2600 pinmux
>> settings while enabling quad mode SPI support.
>>
>> FWSPI18 pins are basically 1.8v logic pins that are different from the
>> dedicated FWSPI pins that provide 3.3v logic level, so FWSPI18 pins can’t
>> be grouped with FWSPIDQ2 and FWSPIDQ3, so this series fix the issue.
>>
>> Also, fixes QSPI1 and QSPI2 function settings in AST2600 pinctrl dtsi to
>> make it able to enable quad mode on SPI1 and SPI2 interfaces.
>>
>> With this series, quad mode pinmux can be set like below.
>>
>> FW SPI:
>> &fmc {
>>          pinctrl-names = "default";
>>          pinctrl-0 = <&pinctrl_fwqspi_default>;
>> }
>>
>> SPI1:
>> &spi1 {
>>          pinctrl-names = "default";
>>          pinctrl-0 = <&pinctrl_qspi1_default>;
>> }
>>
>> SPI2:
>> &spi2 {
>>          pinctrl-names = "default";
>>          pinctrl-0 = <&pinctrl_qspi2_default>;
>> }
> 
> Thanks. I hope to see a board from you that uses this soon :)
> 
> I'll send the patches as fixes once -rc1 is out.

Thanks Joel!

Yes, I would be able to send my BMC board dts soon.
Thanks in advance for your review on that too.

Best,
Jae

>>
>> Please review.
>>
>> Thanks,
>> Jae
>>
>> Changes in v3:
>>   * Added bindings patches. (Andrew)
>>
>> Changes in v2:
>>   * Rebased it on the latest.
>>
>> Jae Hyun Yoo (5):
>>    ARM: dts: aspeed-g6: remove FWQSPID group in pinctrl dtsi
>>    pinctrl: pinctrl-aspeed-g6: remove FWQSPID group in pinctrl
>>    dt-bindings: pinctrl: aspeed-g6: remove FWQSPID group
>>    dt-bindings: pinctrl: aspeed-g6: add FWQSPI function/group
>>    ARM: dts: aspeed-g6: fix SPI1/SPI2 quad pin group
>>
>> Johnny Huang (2):
>>    pinctrl: pinctrl-aspeed-g6: add FWQSPI function-group
>>    ARM: dts: aspeed-g6: add FWQSPI group in pinctrl dtsi
>>
>>   .../pinctrl/aspeed,ast2600-pinctrl.yaml         |  4 ++--
>>   arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi        | 10 +++++-----
>>   drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c      | 17 ++++++++---------
>>   3 files changed, 15 insertions(+), 16 deletions(-)
>>
>> --
>> 2.25.1
>>

Re: [PATCH v3 0/7] Fix AST2600 quad mode SPI pinmux settings

[Cédric Le Goater]

Hello Jae,

On 3/31/22 17:44, Jae Hyun Yoo wrote:
> On 3/30/2022 10:50 PM, Joel Stanley wrote:
>> On Tue, 29 Mar 2022 at 17:40, Jae Hyun Yoo <quic_jaehyoo@quicinc.com> wrote:
>>>
>>> I’m sending this patch series to fix current issues in AST2600 pinmux
>>> settings while enabling quad mode SPI support.
>>>
>>> FWSPI18 pins are basically 1.8v logic pins that are different from the
>>> dedicated FWSPI pins that provide 3.3v logic level, so FWSPI18 pins can’t
>>> be grouped with FWSPIDQ2 and FWSPIDQ3, so this series fix the issue.
>>>
>>> Also, fixes QSPI1 and QSPI2 function settings in AST2600 pinctrl dtsi to
>>> make it able to enable quad mode on SPI1 and SPI2 interfaces.
>>>
>>> With this series, quad mode pinmux can be set like below.
>>>
>>> FW SPI:
>>> &fmc {
>>>          pinctrl-names = "default";
>>>          pinctrl-0 = <&pinctrl_fwqspi_default>;
>>> }
>>>
>>> SPI1:
>>> &spi1 {
>>>          pinctrl-names = "default";
>>>          pinctrl-0 = <&pinctrl_qspi1_default>;
>>> }
>>>
>>> SPI2:
>>> &spi2 {
>>>          pinctrl-names = "default";
>>>          pinctrl-0 = <&pinctrl_qspi2_default>;
>>> }
>>
>> Thanks. I hope to see a board from you that uses this soon :)
>>
>> I'll send the patches as fixes once -rc1 is out.
> 
> Thanks Joel!
> 
> Yes, I would be able to send my BMC board dts soon.
> Thanks in advance for your review on that too.

Out of curiosity, which driver are you using ? the one from SDK ?

I proposed a new one for upstream supporting all AST2400, AST2500, AST2600
controllers. I would be glad to have some feedback if you have time.

Thanks,

C.

Re: [PATCH v3 0/7] Fix AST2600 quad mode SPI pinmux settings

[Jae Hyun Yoo]

Hello Cédric,

On 3/31/2022 8:56 AM, Cédric Le Goater wrote:
> Hello Jae,
> 
> On 3/31/22 17:44, Jae Hyun Yoo wrote:
>> On 3/30/2022 10:50 PM, Joel Stanley wrote:
>>> On Tue, 29 Mar 2022 at 17:40, Jae Hyun Yoo <quic_jaehyoo@quicinc.com> 
>>> wrote:
>>>>
>>>> I’m sending this patch series to fix current issues in AST2600 pinmux
>>>> settings while enabling quad mode SPI support.
>>>>
>>>> FWSPI18 pins are basically 1.8v logic pins that are different from the
>>>> dedicated FWSPI pins that provide 3.3v logic level, so FWSPI18 pins 
>>>> can’t
>>>> be grouped with FWSPIDQ2 and FWSPIDQ3, so this series fix the issue.
>>>>
>>>> Also, fixes QSPI1 and QSPI2 function settings in AST2600 pinctrl 
>>>> dtsi to
>>>> make it able to enable quad mode on SPI1 and SPI2 interfaces.
>>>>
>>>> With this series, quad mode pinmux can be set like below.
>>>>
>>>> FW SPI:
>>>> &fmc {
>>>>          pinctrl-names = "default";
>>>>          pinctrl-0 = <&pinctrl_fwqspi_default>;
>>>> }
>>>>
>>>> SPI1:
>>>> &spi1 {
>>>>          pinctrl-names = "default";
>>>>          pinctrl-0 = <&pinctrl_qspi1_default>;
>>>> }
>>>>
>>>> SPI2:
>>>> &spi2 {
>>>>          pinctrl-names = "default";
>>>>          pinctrl-0 = <&pinctrl_qspi2_default>;
>>>> }
>>>
>>> Thanks. I hope to see a board from you that uses this soon :)
>>>
>>> I'll send the patches as fixes once -rc1 is out.
>>
>> Thanks Joel!
>>
>> Yes, I would be able to send my BMC board dts soon.
>> Thanks in advance for your review on that too.
> 
> Out of curiosity, which driver are you using ? the one from SDK ?
> 
> I proposed a new one for upstream supporting all AST2400, AST2500, AST2600
> controllers. I would be glad to have some feedback if you have time.

Yes, I saw your patch set of the new driver.

I'm currently using this fix with legacy aspeed-smc driver after
adding some fixes. I'll give it a try with your new driver as well and
will give you some feedback if I find any.

Thanks,
Jae

> Thanks,
> 
> C.

Re: [PATCH v3 0/7] Fix AST2600 quad mode SPI pinmux settings

[Jae Hyun Yoo]

Hi Cédric,

On 3/31/2022 9:06 AM, Jae Hyun Yoo wrote:
> Hello Cédric,
> 
> On 3/31/2022 8:56 AM, Cédric Le Goater wrote:
>> Hello Jae,
>>
>> On 3/31/22 17:44, Jae Hyun Yoo wrote:
>>> On 3/30/2022 10:50 PM, Joel Stanley wrote:
>>>> On Tue, 29 Mar 2022 at 17:40, Jae Hyun Yoo 
>>>> <quic_jaehyoo@quicinc.com> wrote:
>>>>>
>>>>> I’m sending this patch series to fix current issues in AST2600 pinmux
>>>>> settings while enabling quad mode SPI support.
>>>>>
>>>>> FWSPI18 pins are basically 1.8v logic pins that are different from the
>>>>> dedicated FWSPI pins that provide 3.3v logic level, so FWSPI18 pins 
>>>>> can’t
>>>>> be grouped with FWSPIDQ2 and FWSPIDQ3, so this series fix the issue.
>>>>>
>>>>> Also, fixes QSPI1 and QSPI2 function settings in AST2600 pinctrl 
>>>>> dtsi to
>>>>> make it able to enable quad mode on SPI1 and SPI2 interfaces.
>>>>>
>>>>> With this series, quad mode pinmux can be set like below.
>>>>>
>>>>> FW SPI:
>>>>> &fmc {
>>>>>          pinctrl-names = "default";
>>>>>          pinctrl-0 = <&pinctrl_fwqspi_default>;
>>>>> }
>>>>>
>>>>> SPI1:
>>>>> &spi1 {
>>>>>          pinctrl-names = "default";
>>>>>          pinctrl-0 = <&pinctrl_qspi1_default>;
>>>>> }
>>>>>
>>>>> SPI2:
>>>>> &spi2 {
>>>>>          pinctrl-names = "default";
>>>>>          pinctrl-0 = <&pinctrl_qspi2_default>;
>>>>> }
>>>>
>>>> Thanks. I hope to see a board from you that uses this soon :)
>>>>
>>>> I'll send the patches as fixes once -rc1 is out.
>>>
>>> Thanks Joel!
>>>
>>> Yes, I would be able to send my BMC board dts soon.
>>> Thanks in advance for your review on that too.
>>
>> Out of curiosity, which driver are you using ? the one from SDK ?
>>
>> I proposed a new one for upstream supporting all AST2400, AST2500, 
>> AST2600
>> controllers. I would be glad to have some feedback if you have time.
> 
> Yes, I saw your patch set of the new driver.
> 
> I'm currently using this fix with legacy aspeed-smc driver after
> adding some fixes. I'll give it a try with your new driver as well and
> will give you some feedback if I find any.

I tested this patch series using the new spi-aspeed-smc driver you
proposed.

https://lore.kernel.org/linux-arm-kernel/20220325100849.2019209-1-clg@kaod.org/

I modified my BMC's device tree like below to enable quad mode.

	&fmc {
		status = "okay";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_fwqspi_default>;

		flash@0 {
			status = "okay";
			m25p,fast-read;
			label = "bmc";
			spi-rx-bus-width = <4>;
			spi-max-frequency = <133000000>;
	#include "openbmc-flash-layout-64.dtsi"
		};

		flash@1 {
			status = "okay";
			m25p,fast-read;
			label = "alt-bmc";
			spi-rx-bus-width = <4>;
			spi-max-frequency = <133000000>;
	#include "openbmc-flash-layout-64-alt.dtsi"
		};
	};

And I got these kernel boot logs.

[    0.720745] spi-nor spi0.0: w25q512nwfm (65536 Kbytes)
[    0.837368] spi-aspeed-smc 1e620000.spi: CE0 read buswidth:4 [0x406c0741]
[    0.846352] 5 fixed-partitions partitions found on MTD device bmc
[    0.853220] Creating 5 MTD partitions on "bmc":
[    0.858295] 0x000000000000-0x0000000e0000 : "u-boot"
[    0.865014] 0x0000000e0000-0x000000100000 : "u-boot-env"
[    0.872229] 0x000000100000-0x000000a00000 : "kernel"
[    0.878963] 0x000000a00000-0x000002a00000 : "rofs"
[    0.885406] 0x000002a00000-0x000004000000 : "rwfs"
[    0.892880] spi-nor spi0.1: w25q512nwfm (65536 Kbytes)
[    1.009460] spi-aspeed-smc 1e620000.spi: CE1 read buswidth:4 [0x406c0741]
[    1.018334] 5 fixed-partitions partitions found on MTD device alt-bmc
[    1.025537] Creating 5 MTD partitions on "alt-bmc":
[    1.031027] 0x000000000000-0x0000000e0000 : "u-boot-alt"
[    1.038165] 0x0000000e0000-0x000000100000 : "u-boot-env-alt"
[    1.045623] 0x000000100000-0x000000a00000 : "kernel-alt"
[    1.052807] 0x000000a00000-0x000002a00000 : "rofs-alt"
[    1.059800] 0x000002a00000-0x000004000000 : "rwfs-alt"

As you can see in the log, FMC10[31:28] and FMC14[31:28] are properly
set to 0100b which means 'quad bit read/write, data cycle only'.
I verified that your new driver supports quad mode properly and it has
worked well so far without making any issue.

Thanks for your making the new driver.
I left my comment in your patch proposal thread.

Cheers,

Jae

Re: [PATCH v3 0/7] Fix AST2600 quad mode SPI pinmux settings

[Cédric Le Goater]

Hello Jae,

On 4/1/22 16:10, Jae Hyun Yoo wrote:
> Hi Cédric,
> 
> On 3/31/2022 9:06 AM, Jae Hyun Yoo wrote:
>> Hello Cédric,
>>
>> On 3/31/2022 8:56 AM, Cédric Le Goater wrote:
>>> Hello Jae,
>>>
>>> On 3/31/22 17:44, Jae Hyun Yoo wrote:
>>>> On 3/30/2022 10:50 PM, Joel Stanley wrote:
>>>>> On Tue, 29 Mar 2022 at 17:40, Jae Hyun Yoo <quic_jaehyoo@quicinc.com> wrote:
>>>>>>
>>>>>> I’m sending this patch series to fix current issues in AST2600 pinmux
>>>>>> settings while enabling quad mode SPI support.
>>>>>>
>>>>>> FWSPI18 pins are basically 1.8v logic pins that are different from the
>>>>>> dedicated FWSPI pins that provide 3.3v logic level, so FWSPI18 pins can’t
>>>>>> be grouped with FWSPIDQ2 and FWSPIDQ3, so this series fix the issue.
>>>>>>
>>>>>> Also, fixes QSPI1 and QSPI2 function settings in AST2600 pinctrl dtsi to
>>>>>> make it able to enable quad mode on SPI1 and SPI2 interfaces.
>>>>>>
>>>>>> With this series, quad mode pinmux can be set like below.
>>>>>>
>>>>>> FW SPI:
>>>>>> &fmc {
>>>>>>          pinctrl-names = "default";
>>>>>>          pinctrl-0 = <&pinctrl_fwqspi_default>;
>>>>>> }
>>>>>>
>>>>>> SPI1:
>>>>>> &spi1 {
>>>>>>          pinctrl-names = "default";
>>>>>>          pinctrl-0 = <&pinctrl_qspi1_default>;
>>>>>> }
>>>>>>
>>>>>> SPI2:
>>>>>> &spi2 {
>>>>>>          pinctrl-names = "default";
>>>>>>          pinctrl-0 = <&pinctrl_qspi2_default>;
>>>>>> }
>>>>>
>>>>> Thanks. I hope to see a board from you that uses this soon :)
>>>>>
>>>>> I'll send the patches as fixes once -rc1 is out.
>>>>
>>>> Thanks Joel!
>>>>
>>>> Yes, I would be able to send my BMC board dts soon.
>>>> Thanks in advance for your review on that too.
>>>
>>> Out of curiosity, which driver are you using ? the one from SDK ?
>>>
>>> I proposed a new one for upstream supporting all AST2400, AST2500, AST2600
>>> controllers. I would be glad to have some feedback if you have time.
>>
>> Yes, I saw your patch set of the new driver.
>>
>> I'm currently using this fix with legacy aspeed-smc driver after
>> adding some fixes. I'll give it a try with your new driver as well and
>> will give you some feedback if I find any.
> 
> I tested this patch series using the new spi-aspeed-smc driver you
> proposed.
> 
> https://lore.kernel.org/linux-arm-kernel/20220325100849.2019209-1-clg@kaod.org/
> 
> I modified my BMC's device tree like below to enable quad mode.
> 
>      &fmc {
>          status = "okay";
>          pinctrl-names = "default";
>          pinctrl-0 = <&pinctrl_fwqspi_default>;
> 
>          flash@0 {
>              status = "okay";
>              m25p,fast-read;
>              label = "bmc";
>              spi-rx-bus-width = <4>;
>              spi-max-frequency = <133000000>;
>      #include "openbmc-flash-layout-64.dtsi"
>          };
> 
>          flash@1 {
>              status = "okay";
>              m25p,fast-read;
>              label = "alt-bmc";
>              spi-rx-bus-width = <4>;
>              spi-max-frequency = <133000000>;
>      #include "openbmc-flash-layout-64-alt.dtsi"
>          };
>      };

Ah ! I have an AST2600 A0 EVB without FWQSPI wires and I could not test.
I am glad you did. Thanks.

I did test the SPI1/SPI2 controllers with Quad SPI activated and results
were OK. I think we could include your changes above in my patchset
since A0 boards are pretty rare these days and unsupported.

> And I got these kernel boot logs.
> 
> [    0.720745] spi-nor spi0.0: w25q512nwfm (65536 Kbytes)
> [    0.837368] spi-aspeed-smc 1e620000.spi: CE0 read buswidth:4 [0x406c0741]
> [    0.846352] 5 fixed-partitions partitions found on MTD device bmc
> [    0.853220] Creating 5 MTD partitions on "bmc":
> [    0.858295] 0x000000000000-0x0000000e0000 : "u-boot"
> [    0.865014] 0x0000000e0000-0x000000100000 : "u-boot-env"
> [    0.872229] 0x000000100000-0x000000a00000 : "kernel"
> [    0.878963] 0x000000a00000-0x000002a00000 : "rofs"
> [    0.885406] 0x000002a00000-0x000004000000 : "rwfs"
> [    0.892880] spi-nor spi0.1: w25q512nwfm (65536 Kbytes)
> [    1.009460] spi-aspeed-smc 1e620000.spi: CE1 read buswidth:4 [0x406c0741]
> [    1.018334] 5 fixed-partitions partitions found on MTD device alt-bmc
> [    1.025537] Creating 5 MTD partitions on "alt-bmc":
> [    1.031027] 0x000000000000-0x0000000e0000 : "u-boot-alt"
> [    1.038165] 0x0000000e0000-0x000000100000 : "u-boot-env-alt"
> [    1.045623] 0x000000100000-0x000000a00000 : "kernel-alt"
> [    1.052807] 0x000000a00000-0x000002a00000 : "rofs-alt"
> [    1.059800] 0x000002a00000-0x000004000000 : "rwfs-alt"
> 
> As you can see in the log, FMC10[31:28] and FMC14[31:28] are properly
> set to 0100b which means 'quad bit read/write, data cycle only'.

yes and Quad Output SPI opcode (0x6c)

> I verified that your new driver supports quad mode properly and it has
> worked well so far without making any issue.
> 
> Thanks for your making the new driver.
> I left my comment in your patch proposal thread.

I will include your 'Tested' tag in v5. I hope to address Pratyush comments
next week. Thanks a lot for the support.

Cheers,

C.

Re: [PATCH v3 0/7] Fix AST2600 quad mode SPI pinmux settings

[Jae Hyun Yoo]

Hello Cédric,

On 4/1/2022 3:07 PM, Cédric Le Goater wrote:
> Hello Jae,
> 
> On 4/1/22 16:10, Jae Hyun Yoo wrote:
>> Hi Cédric,
>>
>> On 3/31/2022 9:06 AM, Jae Hyun Yoo wrote:
>>> Hello Cédric,
>>>
>>> On 3/31/2022 8:56 AM, Cédric Le Goater wrote:
>>>> Hello Jae,
>>>>
>>>> On 3/31/22 17:44, Jae Hyun Yoo wrote:
>>>>> On 3/30/2022 10:50 PM, Joel Stanley wrote:
>>>>>> On Tue, 29 Mar 2022 at 17:40, Jae Hyun Yoo 
>>>>>> <quic_jaehyoo@quicinc.com> wrote:
>>>>>>>
>>>>>>> I’m sending this patch series to fix current issues in AST2600 
>>>>>>> pinmux
>>>>>>> settings while enabling quad mode SPI support.
>>>>>>>
>>>>>>> FWSPI18 pins are basically 1.8v logic pins that are different 
>>>>>>> from the
>>>>>>> dedicated FWSPI pins that provide 3.3v logic level, so FWSPI18 
>>>>>>> pins can’t
>>>>>>> be grouped with FWSPIDQ2 and FWSPIDQ3, so this series fix the issue.
>>>>>>>
>>>>>>> Also, fixes QSPI1 and QSPI2 function settings in AST2600 pinctrl 
>>>>>>> dtsi to
>>>>>>> make it able to enable quad mode on SPI1 and SPI2 interfaces.
>>>>>>>
>>>>>>> With this series, quad mode pinmux can be set like below.
>>>>>>>
>>>>>>> FW SPI:
>>>>>>> &fmc {
>>>>>>>          pinctrl-names = "default";
>>>>>>>          pinctrl-0 = <&pinctrl_fwqspi_default>;
>>>>>>> }
>>>>>>>
>>>>>>> SPI1:
>>>>>>> &spi1 {
>>>>>>>          pinctrl-names = "default";
>>>>>>>          pinctrl-0 = <&pinctrl_qspi1_default>;
>>>>>>> }
>>>>>>>
>>>>>>> SPI2:
>>>>>>> &spi2 {
>>>>>>>          pinctrl-names = "default";
>>>>>>>          pinctrl-0 = <&pinctrl_qspi2_default>;
>>>>>>> }
>>>>>>
>>>>>> Thanks. I hope to see a board from you that uses this soon :)
>>>>>>
>>>>>> I'll send the patches as fixes once -rc1 is out.
>>>>>
>>>>> Thanks Joel!
>>>>>
>>>>> Yes, I would be able to send my BMC board dts soon.
>>>>> Thanks in advance for your review on that too.
>>>>
>>>> Out of curiosity, which driver are you using ? the one from SDK ?
>>>>
>>>> I proposed a new one for upstream supporting all AST2400, AST2500, 
>>>> AST2600
>>>> controllers. I would be glad to have some feedback if you have time.
>>>
>>> Yes, I saw your patch set of the new driver.
>>>
>>> I'm currently using this fix with legacy aspeed-smc driver after
>>> adding some fixes. I'll give it a try with your new driver as well and
>>> will give you some feedback if I find any.
>>
>> I tested this patch series using the new spi-aspeed-smc driver you
>> proposed.
>>
>> https://lore.kernel.org/linux-arm-kernel/20220325100849.2019209-1-clg@kaod.org/ 
>>
>>
>> I modified my BMC's device tree like below to enable quad mode.
>>
>>      &fmc {
>>          status = "okay";
>>          pinctrl-names = "default";
>>          pinctrl-0 = <&pinctrl_fwqspi_default>;
>>
>>          flash@0 {
>>              status = "okay";
>>              m25p,fast-read;
>>              label = "bmc";
>>              spi-rx-bus-width = <4>;
>>              spi-max-frequency = <133000000>;
>>      #include "openbmc-flash-layout-64.dtsi"
>>          };
>>
>>          flash@1 {
>>              status = "okay";
>>              m25p,fast-read;
>>              label = "alt-bmc";
>>              spi-rx-bus-width = <4>;
>>              spi-max-frequency = <133000000>;
>>      #include "openbmc-flash-layout-64-alt.dtsi"
>>          };
>>      };
> 
> Ah ! I have an AST2600 A0 EVB without FWQSPI wires and I could not test.
> I am glad you did. Thanks.
> 
> I did test the SPI1/SPI2 controllers with Quad SPI activated and results
> were OK. I think we could include your changes above in my patchset
> since A0 boards are pretty rare these days and unsupported.

Yes, you could include above device tree changes in your patch set for
AST2600 EVB but please test qemu ast2600-evb model first. It would crash
while booting if we enable quad mode because the machine's fmc spi is
set to w25q256 which doesn't emulate quad mode properly, so you may need
to apply below fix on top of the latest qemu tree.

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index a17b75f4940a..f7eea27f7656 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -753,7 +753,7 @@ static void 
aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
      mc->desc       = "Aspeed AST2500 EVB (ARM1176)";
      amc->soc_name  = "ast2500-a1";
      amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
-    amc->fmc_model = "w25q256";
+    amc->fmc_model = "mx25l25635e";
      amc->spi_model = "mx25l25635e";
      amc->num_cs    = 1;
      amc->i2c_init  = ast2500_evb_i2c_init;

>> And I got these kernel boot logs.
>>
>> [    0.720745] spi-nor spi0.0: w25q512nwfm (65536 Kbytes)
>> [    0.837368] spi-aspeed-smc 1e620000.spi: CE0 read buswidth:4 
>> [0x406c0741]
>> [    0.846352] 5 fixed-partitions partitions found on MTD device bmc
>> [    0.853220] Creating 5 MTD partitions on "bmc":
>> [    0.858295] 0x000000000000-0x0000000e0000 : "u-boot"
>> [    0.865014] 0x0000000e0000-0x000000100000 : "u-boot-env"
>> [    0.872229] 0x000000100000-0x000000a00000 : "kernel"
>> [    0.878963] 0x000000a00000-0x000002a00000 : "rofs"
>> [    0.885406] 0x000002a00000-0x000004000000 : "rwfs"
>> [    0.892880] spi-nor spi0.1: w25q512nwfm (65536 Kbytes)
>> [    1.009460] spi-aspeed-smc 1e620000.spi: CE1 read buswidth:4 
>> [0x406c0741]
>> [    1.018334] 5 fixed-partitions partitions found on MTD device alt-bmc
>> [    1.025537] Creating 5 MTD partitions on "alt-bmc":
>> [    1.031027] 0x000000000000-0x0000000e0000 : "u-boot-alt"
>> [    1.038165] 0x0000000e0000-0x000000100000 : "u-boot-env-alt"
>> [    1.045623] 0x000000100000-0x000000a00000 : "kernel-alt"
>> [    1.052807] 0x000000a00000-0x000002a00000 : "rofs-alt"
>> [    1.059800] 0x000002a00000-0x000004000000 : "rwfs-alt"
>>
>> As you can see in the log, FMC10[31:28] and FMC14[31:28] are properly
>> set to 0100b which means 'quad bit read/write, data cycle only'.
> 
> yes and Quad Output SPI opcode (0x6c)

Indeed.

>> I verified that your new driver supports quad mode properly and it has
>> worked well so far without making any issue.
>>
>> Thanks for your making the new driver.
>> I left my comment in your patch proposal thread.
> 
> I will include your 'Tested' tag in v5. I hope to address Pratyush comments
> next week. Thanks a lot for the support.

Sure. Thanks again for the new driver! :)

-Jae

Re: [PATCH v3 0/7] Fix AST2600 quad mode SPI pinmux settings

[Linus Walleij]

Hi Jae,

On Tue, Mar 29, 2022 at 7:40 PM Jae Hyun Yoo <quic_jaehyoo@quicinc.com> wrote:

> Jae Hyun Yoo (5):
>   pinctrl: pinctrl-aspeed-g6: remove FWQSPID group in pinctrl
>   dt-bindings: pinctrl: aspeed-g6: remove FWQSPID group
>   dt-bindings: pinctrl: aspeed-g6: add FWQSPI function/group
>   pinctrl: pinctrl-aspeed-g6: add FWQSPI function-group

These four patches applied to the pinctrl tree.

Please funnel patches 1, 6, 7 through the SoC tree.

Yours,
Linus Walleij

Re: [PATCH v3 0/7] Fix AST2600 quad mode SPI pinmux settings

[Jae Hyun Yoo]

Hi Linus,

On 4/17/2022 4:28 PM, Linus Walleij wrote:
> Hi Jae,
> 
> On Tue, Mar 29, 2022 at 7:40 PM Jae Hyun Yoo <quic_jaehyoo@quicinc.com> wrote:
> 
>> Jae Hyun Yoo (5):
>>    pinctrl: pinctrl-aspeed-g6: remove FWQSPID group in pinctrl
>>    dt-bindings: pinctrl: aspeed-g6: remove FWQSPID group
>>    dt-bindings: pinctrl: aspeed-g6: add FWQSPI function/group
>>    pinctrl: pinctrl-aspeed-g6: add FWQSPI function-group
> 
> These four patches applied to the pinctrl tree.
> 
> Please funnel patches 1, 6, 7 through the SoC tree.

Thanks a lot!

Hi Joel,
Can you please include 1, 6 and 7 in the next pull request of Aspeed
SoC tree?

Thanks,
Jae