[PATCH v3 0/7] Add SM8150 and SM8250 interconnect drivers

[PATCH v3 0/7] Add SM8150 and SM8250 interconnect drivers

[Jonathan Marek]

Most of this is generated from downstream dts using a script.

v2: single yaml file for RPMh interconnect bindings, drop display RSC
v3:
 - removed the sc7180 example from the combined yaml file, two
   examples with conflicting includes doesn't seem possible
 - Removed MASTER_ALC and bcm_alc (sm8150 and sm8250)
 - Set keep alive for SH0, MC0, MM0, SN0 and CN0 (both)
 - Used Sibi Sankar's suggestions for reg base/size in dts

Jonathan Marek (7):
  dt-bindings: interconnect: single yaml file for RPMh interconnect
    drivers
  dt-bindings: interconnect: Add Qualcomm SM8150 DT bindings
  dt-bindings: interconnect: Add Qualcomm SM8250 DT bindings
  interconnect: qcom: Add SM8150 interconnect provider driver
  interconnect: qcom: Add SM8250 interconnect provider driver
  arm64: dts: qcom: sm8150: add interconnect nodes
  arm64: dts: qcom: sm8250: add interconnect nodes

 .../{qcom,sdm845.yaml => qcom,rpmh.yaml}      |  42 +-
 .../bindings/interconnect/qcom,sc7180.yaml    |  85 ---
 arch/arm64/boot/dts/qcom/sm8150.dtsi          |  82 +++
 arch/arm64/boot/dts/qcom/sm8250.dtsi          |  82 +++
 drivers/interconnect/qcom/Kconfig             |  20 +
 drivers/interconnect/qcom/Makefile            |   4 +
 drivers/interconnect/qcom/sm8150.c            | 635 +++++++++++++++++
 drivers/interconnect/qcom/sm8150.h            | 152 ++++
 drivers/interconnect/qcom/sm8250.c            | 651 ++++++++++++++++++
 drivers/interconnect/qcom/sm8250.h            | 162 +++++
 .../dt-bindings/interconnect/qcom,sm8150.h    | 162 +++++
 .../dt-bindings/interconnect/qcom,sm8250.h    | 172 +++++
 12 files changed, 2161 insertions(+), 88 deletions(-)
 rename Documentation/devicetree/bindings/interconnect/{qcom,sdm845.yaml => qcom,rpmh.yaml} (60%)
 delete mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sc7180.yaml
 create mode 100644 drivers/interconnect/qcom/sm8150.c
 create mode 100644 drivers/interconnect/qcom/sm8150.h
 create mode 100644 drivers/interconnect/qcom/sm8250.c
 create mode 100644 drivers/interconnect/qcom/sm8250.h
 create mode 100644 include/dt-bindings/interconnect/qcom,sm8150.h
 create mode 100644 include/dt-bindings/interconnect/qcom,sm8250.h

-- 
2.26.1

[PATCH v3 1/7] dt-bindings: interconnect: single yaml file for RPMh interconnect drivers

[Jonathan Marek]

These two bindings are almost identical, so combine them into one. This
will make it easier to add the sm8150 and sm8250 interconnect bindings.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
 .../{qcom,sdm845.yaml => qcom,rpmh.yaml}      | 20 ++++-
 .../bindings/interconnect/qcom,sc7180.yaml    | 85 -------------------
 2 files changed, 17 insertions(+), 88 deletions(-)
 rename Documentation/devicetree/bindings/interconnect/{qcom,sdm845.yaml => qcom,rpmh.yaml} (76%)
 delete mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sc7180.yaml

diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sdm845.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
similarity index 76%
rename from Documentation/devicetree/bindings/interconnect/qcom,sdm845.yaml
rename to Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
index 74536747b51d..6a457f914bb5 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,sdm845.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
@@ -1,16 +1,17 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: http://devicetree.org/schemas/interconnect/qcom,sdm845.yaml#
+$id: http://devicetree.org/schemas/interconnect/qcom,rpmh.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title:  Qualcomm SDM845 Network-On-Chip Interconnect
+title:  Qualcomm RPMh Network-On-Chip Interconnect
 
 maintainers:
   - Georgi Djakov <georgi.djakov@linaro.org>
+  - Odelu Kukatla <okukatla@codeaurora.org>
 
 description: |
-   SDM845 interconnect providers support system bandwidth requirements through
+   RPMh interconnect providers support system bandwidth requirements through
    RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
    able to communicate with the BCM through the Resource State Coordinator (RSC)
    associated with each execution environment. Provider nodes must point to at
@@ -23,6 +24,19 @@ properties:
 
   compatible:
     enum:
+      - qcom,sc7180-aggre1-noc
+      - qcom,sc7180-aggre2-noc
+      - qcom,sc7180-camnoc-virt
+      - qcom,sc7180-compute-noc
+      - qcom,sc7180-config-noc
+      - qcom,sc7180-dc-noc
+      - qcom,sc7180-gem-noc
+      - qcom,sc7180-ipa-virt
+      - qcom,sc7180-mc-virt
+      - qcom,sc7180-mmss-noc
+      - qcom,sc7180-npu-noc
+      - qcom,sc7180-qup-virt
+      - qcom,sc7180-system-noc
       - qcom,sdm845-aggre1-noc
       - qcom,sdm845-aggre2-noc
       - qcom,sdm845-config-noc
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sc7180.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sc7180.yaml
deleted file mode 100644
index d01bac80d416..000000000000
--- a/Documentation/devicetree/bindings/interconnect/qcom,sc7180.yaml
+++ /dev/null
@@ -1,85 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/interconnect/qcom,sc7180.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title:  Qualcomm SC7180 Network-On-Chip Interconnect
-
-maintainers:
-  - Odelu Kukatla <okukatla@codeaurora.org>
-
-description: |
-   SC7180 interconnect providers support system bandwidth requirements through
-   RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
-   able to communicate with the BCM through the Resource State Coordinator (RSC)
-   associated with each execution environment. Provider nodes must point to at
-   least one RPMh device child node pertaining to their RSC and each provider
-   can map to multiple RPMh resources.
-
-properties:
-  reg:
-    maxItems: 1
-
-  compatible:
-    enum:
-      - qcom,sc7180-aggre1-noc
-      - qcom,sc7180-aggre2-noc
-      - qcom,sc7180-camnoc-virt
-      - qcom,sc7180-compute-noc
-      - qcom,sc7180-config-noc
-      - qcom,sc7180-dc-noc
-      - qcom,sc7180-gem-noc
-      - qcom,sc7180-ipa-virt
-      - qcom,sc7180-mc-virt
-      - qcom,sc7180-mmss-noc
-      - qcom,sc7180-npu-noc
-      - qcom,sc7180-qup-virt
-      - qcom,sc7180-system-noc
-
-  '#interconnect-cells':
-    const: 1
-
-  qcom,bcm-voters:
-    $ref: /schemas/types.yaml#/definitions/phandle-array
-    description: |
-      List of phandles to qcom,bcm-voter nodes that are required by
-      this interconnect to send RPMh commands.
-
-  qcom,bcm-voter-names:
-    $ref: /schemas/types.yaml#/definitions/string-array
-    description: |
-      Names for each of the qcom,bcm-voters specified.
-
-required:
-  - compatible
-  - reg
-  - '#interconnect-cells'
-  - qcom,bcm-voters
-
-additionalProperties: false
-
-examples:
-  - |
-      #include <dt-bindings/interconnect/qcom,sc7180.h>
-
-      config_noc: interconnect@1500000 {
-            compatible = "qcom,sc7180-config-noc";
-            reg = <0x01500000 0x28000>;
-            #interconnect-cells = <1>;
-            qcom,bcm-voters = <&apps_bcm_voter>;
-      };
-
-      system_noc: interconnect@1620000 {
-            compatible = "qcom,sc7180-system-noc";
-            reg = <0x01620000 0x17080>;
-            #interconnect-cells = <1>;
-            qcom,bcm-voters = <&apps_bcm_voter>;
-      };
-
-      mmss_noc: interconnect@1740000 {
-            compatible = "qcom,sc7180-mmss-noc";
-            reg = <0x01740000 0x1c100>;
-            #interconnect-cells = <1>;
-            qcom,bcm-voters = <&apps_bcm_voter>;
-      };
-- 
2.26.1

[PATCH v3 2/7] dt-bindings: interconnect: Add Qualcomm SM8150 DT bindings

[Jonathan Marek]

The Qualcomm SM8150 platform has several bus fabrics that could be
controlled and tuned dynamically according to the bandwidth demand.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../bindings/interconnect/qcom,rpmh.yaml      |  11 ++
 .../dt-bindings/interconnect/qcom,sm8150.h    | 162 ++++++++++++++++++
 2 files changed, 173 insertions(+)
 create mode 100644 include/dt-bindings/interconnect/qcom,sm8150.h

diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
index 6a457f914bb5..e95ccd7b4b5a 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
@@ -45,6 +45,17 @@ properties:
       - qcom,sdm845-mem-noc
       - qcom,sdm845-mmss-noc
       - qcom,sdm845-system-noc
+      - qcom,sm8150-aggre1-noc
+      - qcom,sm8150-aggre2-noc
+      - qcom,sm8150-camnoc-noc
+      - qcom,sm8150-compute-noc
+      - qcom,sm8150-config-noc
+      - qcom,sm8150-dc-noc
+      - qcom,sm8150-gem-noc
+      - qcom,sm8150-ipa-virt
+      - qcom,sm8150-mc-virt
+      - qcom,sm8150-mmss-noc
+      - qcom,sm8150-system-noc
 
   '#interconnect-cells':
     const: 1
diff --git a/include/dt-bindings/interconnect/qcom,sm8150.h b/include/dt-bindings/interconnect/qcom,sm8150.h
new file mode 100644
index 000000000000..a25684680c42
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,sm8150.h
@@ -0,0 +1,162 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Qualcomm SM8150 interconnect IDs
+ *
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8150_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_SM8150_H
+
+#define MASTER_A1NOC_CFG		0
+#define MASTER_QUP_0			1
+#define MASTER_EMAC			2
+#define MASTER_UFS_MEM			3
+#define MASTER_USB3			4
+#define MASTER_USB3_1			5
+#define A1NOC_SNOC_SLV			6
+#define SLAVE_SERVICE_A1NOC		7
+
+#define MASTER_A2NOC_CFG		0
+#define MASTER_QDSS_BAM			1
+#define MASTER_QSPI			2
+#define MASTER_QUP_1			3
+#define MASTER_QUP_2			4
+#define MASTER_SENSORS_AHB		5
+#define MASTER_TSIF			6
+#define MASTER_CNOC_A2NOC		7
+#define MASTER_CRYPTO_CORE_0		8
+#define MASTER_IPA			9
+#define MASTER_PCIE			10
+#define MASTER_PCIE_1			11
+#define MASTER_QDSS_ETR			12
+#define MASTER_SDCC_2			13
+#define MASTER_SDCC_4			14
+#define A2NOC_SNOC_SLV			15
+#define SLAVE_ANOC_PCIE_GEM_NOC		16
+#define SLAVE_SERVICE_A2NOC		17
+
+#define MASTER_CAMNOC_HF0_UNCOMP	0
+#define MASTER_CAMNOC_HF1_UNCOMP	1
+#define MASTER_CAMNOC_SF_UNCOMP		2
+#define SLAVE_CAMNOC_UNCOMP		3
+
+#define MASTER_NPU			0
+#define SLAVE_CDSP_MEM_NOC		1
+
+#define MASTER_SPDM			0
+#define SNOC_CNOC_MAS			1
+#define MASTER_QDSS_DAP			2
+#define SLAVE_A1NOC_CFG			3
+#define SLAVE_A2NOC_CFG			4
+#define SLAVE_AHB2PHY_SOUTH		5
+#define SLAVE_AOP			6
+#define SLAVE_AOSS			7
+#define SLAVE_CAMERA_CFG		8
+#define SLAVE_CLK_CTL			9
+#define SLAVE_CDSP_CFG			10
+#define SLAVE_RBCPR_CX_CFG		11
+#define SLAVE_RBCPR_MMCX_CFG		12
+#define SLAVE_RBCPR_MX_CFG		13
+#define SLAVE_CRYPTO_0_CFG		14
+#define SLAVE_CNOC_DDRSS		15
+#define SLAVE_DISPLAY_CFG		16
+#define SLAVE_EMAC_CFG			17
+#define SLAVE_GLM			18
+#define SLAVE_GRAPHICS_3D_CFG		19
+#define SLAVE_IMEM_CFG			20
+#define SLAVE_IPA_CFG			21
+#define SLAVE_CNOC_MNOC_CFG		22
+#define SLAVE_NPU_CFG			23
+#define SLAVE_PCIE_0_CFG		24
+#define SLAVE_PCIE_1_CFG		25
+#define SLAVE_NORTH_PHY_CFG		26
+#define SLAVE_PIMEM_CFG			27
+#define SLAVE_PRNG			28
+#define SLAVE_QDSS_CFG			29
+#define SLAVE_QSPI			30
+#define SLAVE_QUP_2			31
+#define SLAVE_QUP_1			32
+#define SLAVE_QUP_0			33
+#define SLAVE_SDCC_2			34
+#define SLAVE_SDCC_4			35
+#define SLAVE_SNOC_CFG			36
+#define SLAVE_SPDM_WRAPPER		37
+#define SLAVE_SPSS_CFG			38
+#define SLAVE_SSC_CFG			39
+#define SLAVE_TCSR			40
+#define SLAVE_TLMM_EAST			41
+#define SLAVE_TLMM_NORTH		42
+#define SLAVE_TLMM_SOUTH		43
+#define SLAVE_TLMM_WEST			44
+#define SLAVE_TSIF			45
+#define SLAVE_UFS_CARD_CFG		46
+#define SLAVE_UFS_MEM_CFG		47
+#define SLAVE_USB3			48
+#define SLAVE_USB3_1			49
+#define SLAVE_VENUS_CFG			50
+#define SLAVE_VSENSE_CTRL_CFG		51
+#define SLAVE_CNOC_A2NOC		52
+#define SLAVE_SERVICE_CNOC		53
+
+#define MASTER_CNOC_DC_NOC		0
+#define SLAVE_LLCC_CFG			1
+#define SLAVE_GEM_NOC_CFG		2
+
+#define MASTER_AMPSS_M0			0
+#define MASTER_GPU_TCU			1
+#define MASTER_SYS_TCU			2
+#define MASTER_GEM_NOC_CFG		3
+#define MASTER_COMPUTE_NOC		4
+#define MASTER_GRAPHICS_3D		5
+#define MASTER_MNOC_HF_MEM_NOC		6
+#define MASTER_MNOC_SF_MEM_NOC		7
+#define MASTER_GEM_NOC_PCIE_SNOC	8
+#define MASTER_SNOC_GC_MEM_NOC		9
+#define MASTER_SNOC_SF_MEM_NOC		10
+#define MASTER_ECC			11
+#define SLAVE_MSS_PROC_MS_MPU_CFG	12
+#define SLAVE_ECC			13
+#define SLAVE_GEM_NOC_SNOC		14
+#define SLAVE_LLCC			15
+#define SLAVE_SERVICE_GEM_NOC		16
+
+#define MASTER_IPA_CORE			0
+#define SLAVE_IPA_CORE			1
+
+#define MASTER_LLCC			0
+#define SLAVE_EBI_CH0			1
+
+#define MASTER_CNOC_MNOC_CFG		0
+#define MASTER_CAMNOC_HF0		1
+#define MASTER_CAMNOC_HF1		2
+#define MASTER_CAMNOC_SF		3
+#define MASTER_MDP_PORT0		4
+#define MASTER_MDP_PORT1		5
+#define MASTER_ROTATOR			6
+#define MASTER_VIDEO_P0			7
+#define MASTER_VIDEO_P1			8
+#define MASTER_VIDEO_PROC		9
+#define SLAVE_MNOC_SF_MEM_NOC		10
+#define SLAVE_MNOC_HF_MEM_NOC		11
+#define SLAVE_SERVICE_MNOC		12
+
+#define MASTER_SNOC_CFG			0
+#define A1NOC_SNOC_MAS			1
+#define A2NOC_SNOC_MAS			2
+#define MASTER_GEM_NOC_SNOC		3
+#define MASTER_PIMEM			4
+#define MASTER_GIC			5
+#define SLAVE_APPSS			6
+#define SNOC_CNOC_SLV			7
+#define SLAVE_SNOC_GEM_NOC_GC		8
+#define SLAVE_SNOC_GEM_NOC_SF		9
+#define SLAVE_OCIMEM			10
+#define SLAVE_PIMEM			11
+#define SLAVE_SERVICE_SNOC		12
+#define SLAVE_PCIE_0			13
+#define SLAVE_PCIE_1			14
+#define SLAVE_QDSS_STM			15
+#define SLAVE_TCU			16
+
+#endif
-- 
2.26.1

[PATCH v3 3/7] dt-bindings: interconnect: Add Qualcomm SM8250 DT bindings

[Jonathan Marek]

The Qualcomm SM8250 platform has several bus fabrics that could be
controlled and tuned dynamically according to the bandwidth demand.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../bindings/interconnect/qcom,rpmh.yaml      |  11 ++
 .../dt-bindings/interconnect/qcom,sm8250.h    | 172 ++++++++++++++++++
 2 files changed, 183 insertions(+)
 create mode 100644 include/dt-bindings/interconnect/qcom,sm8250.h

diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
index e95ccd7b4b5a..18c48a2ce191 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
@@ -56,6 +56,17 @@ properties:
       - qcom,sm8150-mc-virt
       - qcom,sm8150-mmss-noc
       - qcom,sm8150-system-noc
+      - qcom,sm8250-aggre1-noc
+      - qcom,sm8250-aggre2-noc
+      - qcom,sm8250-compute-noc
+      - qcom,sm8250-config-noc
+      - qcom,sm8250-dc-noc
+      - qcom,sm8250-gem-noc
+      - qcom,sm8250-ipa-virt
+      - qcom,sm8250-mc-virt
+      - qcom,sm8250-mmss-noc
+      - qcom,sm8250-npu-noc
+      - qcom,sm8250-system-noc
 
   '#interconnect-cells':
     const: 1
diff --git a/include/dt-bindings/interconnect/qcom,sm8250.h b/include/dt-bindings/interconnect/qcom,sm8250.h
new file mode 100644
index 000000000000..1b4d9fbe888d
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,sm8250.h
@@ -0,0 +1,172 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Qualcomm SM8250 interconnect IDs
+ *
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8250_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_SM8250_H
+
+#define MASTER_A1NOC_CFG		0
+#define MASTER_QSPI_0			1
+#define MASTER_QUP_1			2
+#define MASTER_QUP_2			3
+#define MASTER_TSIF			4
+#define MASTER_PCIE_2			5
+#define MASTER_SDCC_4			6
+#define MASTER_UFS_MEM			7
+#define MASTER_USB3			8
+#define MASTER_USB3_1			9
+#define A1NOC_SNOC_SLV			10
+#define SLAVE_ANOC_PCIE_GEM_NOC_1	11
+#define SLAVE_SERVICE_A1NOC		12
+
+#define MASTER_A2NOC_CFG		0
+#define MASTER_QDSS_BAM			1
+#define MASTER_QUP_0			2
+#define MASTER_CNOC_A2NOC		3
+#define MASTER_CRYPTO_CORE_0		4
+#define MASTER_IPA			5
+#define MASTER_PCIE			6
+#define MASTER_PCIE_1			7
+#define MASTER_QDSS_ETR			8
+#define MASTER_SDCC_2			9
+#define MASTER_UFS_CARD			10
+#define A2NOC_SNOC_SLV			11
+#define SLAVE_ANOC_PCIE_GEM_NOC		12
+#define SLAVE_SERVICE_A2NOC		13
+
+#define MASTER_NPU			0
+#define SLAVE_CDSP_MEM_NOC		1
+
+#define SNOC_CNOC_MAS			0
+#define MASTER_QDSS_DAP			1
+#define SLAVE_A1NOC_CFG			2
+#define SLAVE_A2NOC_CFG			3
+#define SLAVE_AHB2PHY_SOUTH		4
+#define SLAVE_AHB2PHY_NORTH		5
+#define SLAVE_AOSS			6
+#define SLAVE_CAMERA_CFG		7
+#define SLAVE_CLK_CTL			8
+#define SLAVE_CDSP_CFG			9
+#define SLAVE_RBCPR_CX_CFG		10
+#define SLAVE_RBCPR_MMCX_CFG		11
+#define SLAVE_RBCPR_MX_CFG		12
+#define SLAVE_CRYPTO_0_CFG		13
+#define SLAVE_CX_RDPM			14
+#define SLAVE_DCC_CFG			15
+#define SLAVE_CNOC_DDRSS		16
+#define SLAVE_DISPLAY_CFG		17
+#define SLAVE_GRAPHICS_3D_CFG		18
+#define SLAVE_IMEM_CFG			19
+#define SLAVE_IPA_CFG			20
+#define SLAVE_IPC_ROUTER_CFG		21
+#define SLAVE_LPASS			22
+#define SLAVE_CNOC_MNOC_CFG		23
+#define SLAVE_NPU_CFG			24
+#define SLAVE_PCIE_0_CFG		25
+#define SLAVE_PCIE_1_CFG		26
+#define SLAVE_PCIE_2_CFG		27
+#define SLAVE_PDM			28
+#define SLAVE_PIMEM_CFG			29
+#define SLAVE_PRNG			30
+#define SLAVE_QDSS_CFG			31
+#define SLAVE_QSPI_0			32
+#define SLAVE_QUP_0			33
+#define SLAVE_QUP_1			34
+#define SLAVE_QUP_2			35
+#define SLAVE_SDCC_2			36
+#define SLAVE_SDCC_4			37
+#define SLAVE_SNOC_CFG			38
+#define SLAVE_TCSR			39
+#define SLAVE_TLMM_NORTH		40
+#define SLAVE_TLMM_SOUTH		41
+#define SLAVE_TLMM_WEST			42
+#define SLAVE_TSIF			43
+#define SLAVE_UFS_CARD_CFG		44
+#define SLAVE_UFS_MEM_CFG		45
+#define SLAVE_USB3			46
+#define SLAVE_USB3_1			47
+#define SLAVE_VENUS_CFG			48
+#define SLAVE_VSENSE_CTRL_CFG		49
+#define SLAVE_CNOC_A2NOC		50
+#define SLAVE_SERVICE_CNOC		51
+
+#define MASTER_CNOC_DC_NOC		0
+#define SLAVE_LLCC_CFG			1
+#define SLAVE_GEM_NOC_CFG		2
+
+#define MASTER_GPU_TCU			0
+#define MASTER_SYS_TCU			1
+#define MASTER_AMPSS_M0			2
+#define MASTER_GEM_NOC_CFG		3
+#define MASTER_COMPUTE_NOC		4
+#define MASTER_GRAPHICS_3D		5
+#define MASTER_MNOC_HF_MEM_NOC		6
+#define MASTER_MNOC_SF_MEM_NOC		7
+#define MASTER_ANOC_PCIE_GEM_NOC	8
+#define MASTER_SNOC_GC_MEM_NOC		9
+#define MASTER_SNOC_SF_MEM_NOC		10
+#define SLAVE_GEM_NOC_SNOC		11
+#define SLAVE_LLCC			12
+#define SLAVE_MEM_NOC_PCIE_SNOC		13
+#define SLAVE_SERVICE_GEM_NOC_1		14
+#define SLAVE_SERVICE_GEM_NOC_2		15
+#define SLAVE_SERVICE_GEM_NOC		16
+
+#define MASTER_IPA_CORE			0
+#define SLAVE_IPA_CORE			1
+
+#define MASTER_LLCC			0
+#define SLAVE_EBI_CH0			1
+
+#define MASTER_CNOC_MNOC_CFG		0
+#define MASTER_CAMNOC_HF		1
+#define MASTER_CAMNOC_ICP		2
+#define MASTER_CAMNOC_SF		3
+#define MASTER_VIDEO_P0			4
+#define MASTER_VIDEO_P1			5
+#define MASTER_VIDEO_PROC		6
+#define MASTER_MDP_PORT0		7
+#define MASTER_MDP_PORT1		8
+#define MASTER_ROTATOR			9
+#define SLAVE_MNOC_HF_MEM_NOC		10
+#define SLAVE_MNOC_SF_MEM_NOC		11
+#define SLAVE_SERVICE_MNOC		12
+
+#define MASTER_NPU_SYS			0
+#define MASTER_NPU_CDP			1
+#define MASTER_NPU_NOC_CFG		2
+#define SLAVE_NPU_CAL_DP0		3
+#define SLAVE_NPU_CAL_DP1		4
+#define SLAVE_NPU_CP			5
+#define SLAVE_NPU_INT_DMA_BWMON_CFG	6
+#define SLAVE_NPU_DPM			7
+#define SLAVE_ISENSE_CFG		8
+#define SLAVE_NPU_LLM_CFG		9
+#define SLAVE_NPU_TCM			10
+#define SLAVE_NPU_COMPUTE_NOC		11
+#define SLAVE_SERVICE_NPU_NOC		12
+
+#define MASTER_SNOC_CFG			0
+#define A1NOC_SNOC_MAS			1
+#define A2NOC_SNOC_MAS			2
+#define MASTER_GEM_NOC_SNOC		3
+#define MASTER_GEM_NOC_PCIE_SNOC	4
+#define MASTER_PIMEM			5
+#define MASTER_GIC			6
+#define SLAVE_APPSS			7
+#define SNOC_CNOC_SLV			8
+#define SLAVE_SNOC_GEM_NOC_GC		9
+#define SLAVE_SNOC_GEM_NOC_SF		10
+#define SLAVE_OCIMEM			11
+#define SLAVE_PIMEM			12
+#define SLAVE_SERVICE_SNOC		13
+#define SLAVE_PCIE_0			14
+#define SLAVE_PCIE_1			15
+#define SLAVE_PCIE_2			16
+#define SLAVE_QDSS_STM			17
+#define SLAVE_TCU			18
+
+#endif
-- 
2.26.1

[PATCH v3 6/7] arm64: dts: qcom: sm8150: add interconnect nodes

[Jonathan Marek]

Add the interconnect dts nodes for sm8150.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
 arch/arm64/boot/dts/qcom/sm8150.dtsi | 82 ++++++++++++++++++++++++++++
 1 file changed, 82 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 33ff99132f4f..e4689c27224b 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -11,6 +11,7 @@
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
+#include <dt-bindings/interconnect/qcom,sm8150.h>
 #include <dt-bindings/thermal/thermal.h>
 
 / {
@@ -440,6 +441,55 @@ uart2: serial@a90000 {
 			};
 		};
 
+		config_noc: interconnect@1500000 {
+			compatible = "qcom,sm8150-config-noc";
+			reg = <0 0x01500000 0 0x7400>;
+			#interconnect-cells = <1>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		system_noc: interconnect@1620000 {
+			compatible = "qcom,sm8150-system-noc";
+			reg = <0 0x01620000 0 0x19400>;
+			#interconnect-cells = <1>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		mc_virt: interconnect@163a000 {
+			compatible = "qcom,sm8150-mc-virt";
+			reg = <0 0x0163a000 0 0x1000>;
+			#interconnect-cells = <1>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		aggre1_noc: interconnect@16e0000 {
+			compatible = "qcom,sm8150-aggre1-noc";
+			reg = <0 0x016e0000 0 0xd080>;
+			#interconnect-cells = <1>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		aggre2_noc: interconnect@1700000 {
+			compatible = "qcom,sm8150-aggre2-noc";
+			reg = <0 0x01700000 0 0x20000>;
+			#interconnect-cells = <1>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		compute_noc: interconnect@1720000 {
+			compatible = "qcom,sm8150-compute-noc";
+			reg = <0 0x01720000 0 0x7000>;
+			#interconnect-cells = <1>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		mmss_noc: interconnect@1740000 {
+			compatible = "qcom,sm8150-mmss-noc";
+			reg = <0 0x01740000 0 0x1c100>;
+			#interconnect-cells = <1>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
 		ufs_mem_hc: ufshc@1d84000 {
 			compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
 				     "jedec,ufs-2.0";
@@ -510,6 +560,13 @@ ufs_mem_phy_lanes: lanes@1d87400 {
 			};
 		};
 
+		ipa_virt: interconnect@1e00000 {
+			compatible = "qcom,sm8150-ipa-virt";
+			reg = <0 0x01e00000 0 0x1000>;
+			#interconnect-cells = <1>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
 		tcsr_mutex_regs: syscon@1f40000 {
 			compatible = "syscon";
 			reg = <0x0 0x01f40000 0x0 0x40000>;
@@ -860,6 +917,20 @@ usb_2_ssphy: lane@88eb200 {
 			};
 		};
 
+		dc_noc: interconnect@9160000 {
+			compatible = "qcom,sm8150-dc-noc";
+			reg = <0 0x09160000 0 0x3200>;
+			#interconnect-cells = <1>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		gem_noc: interconnect@9680000 {
+			compatible = "qcom,sm8150-gem-noc";
+			reg = <0 0x09680000 0 0x3e200>;
+			#interconnect-cells = <1>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
 		usb_1: usb@a6f8800 {
 			compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
 			reg = <0 0x0a6f8800 0 0x400>;
@@ -950,6 +1021,13 @@ usb_2_dwc3: dwc3@a800000 {
 			};
 		};
 
+		camnoc_virt: interconnect@ac00000 {
+			compatible = "qcom,sm8150-camnoc-virt";
+			reg = <0 0x0ac00000 0 0x1000>;
+			#interconnect-cells = <1>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
 		aoss_qmp: power-controller@c300000 {
 			compatible = "qcom,sm8150-aoss-qmp";
 			reg = <0x0 0x0c300000 0x0 0x100000>;
@@ -1280,6 +1358,10 @@ rpmhpd_opp_turbo_l1: opp11 {
 					};
 				};
 			};
+
+			apps_bcm_voter: bcm_voter {
+				compatible = "qcom,bcm-voter";
+			};
 		};
 
 		cpufreq_hw: cpufreq@18323000 {
-- 
2.26.1

[PATCH v3 7/7] arm64: dts: qcom: sm8250: add interconnect nodes

[Jonathan Marek]

Add the interconnect dts nodes for sm8250.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
 arch/arm64/boot/dts/qcom/sm8250.dtsi | 82 ++++++++++++++++++++++++++++
 1 file changed, 82 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 636e2196138c..945bd4a9d640 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -7,6 +7,7 @@
 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interconnect/qcom,sm8250.h>
 #include <dt-bindings/mailbox/qcom-ipcc.h>
 #include <dt-bindings/power/qcom-aoss-qmp.h>
 #include <dt-bindings/power/qcom-rpmpd.h>
@@ -978,6 +979,55 @@ spi13: spi@a94000 {
 			};
 		};
 
+		config_noc: interconnect@1500000 {
+			compatible = "qcom,sm8250-config-noc";
+			reg = <0 0x01500000 0 0xa580>;
+			#interconnect-cells = <1>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		system_noc: interconnect@1620000 {
+			compatible = "qcom,sm8250-system-noc";
+			reg = <0 0x01620000 0 0x1c200>;
+			#interconnect-cells = <1>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		mc_virt: interconnect@163d000 {
+			compatible = "qcom,sm8250-mc-virt";
+			reg = <0 0x0163d000 0 0x1000>;
+			#interconnect-cells = <1>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		aggre1_noc: interconnect@16e0000 {
+			compatible = "qcom,sm8250-aggre1-noc";
+			reg = <0 0x016e0000 0 0x1f180>;
+			#interconnect-cells = <1>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		aggre2_noc: interconnect@1700000 {
+			compatible = "qcom,sm8250-aggre2-noc";
+			reg = <0 0x01700000 0 0x33000>;
+			#interconnect-cells = <1>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		compute_noc: interconnect@1733000 {
+			compatible = "qcom,sm8250-compute-noc";
+			reg = <0 0x01733000 0 0xa180>;
+			#interconnect-cells = <1>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		mmss_noc: interconnect@1740000 {
+			compatible = "qcom,sm8250-mmss-noc";
+			reg = <0 0x01740000 0 0x1f080>;
+			#interconnect-cells = <1>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
 		ufs_mem_hc: ufshc@1d84000 {
 			compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
 				     "jedec,ufs-2.0";
@@ -1050,6 +1100,13 @@ ufs_mem_phy_lanes: lanes@1d87400 {
 			};
 		};
 
+		ipa_virt: interconnect@1e00000 {
+			compatible = "qcom,sm8250-ipa-virt";
+			reg = <0 0x01e00000 0 0x1000>;
+			#interconnect-cells = <1>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
 		tcsr_mutex_regs: syscon@1f40000 {
 			compatible = "syscon";
 			reg = <0x0 0x01f40000 0x0 0x40000>;
@@ -1364,6 +1421,27 @@ usb_2_ssphy: lane@88eb200 {
 			};
 		};
 
+		dc_noc: interconnect@90c0000 {
+			compatible = "qcom,sm8250-dc-noc";
+			reg = <0 0x090c0000 0 0x4200>;
+			#interconnect-cells = <1>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		gem_noc: interconnect@9100000 {
+			compatible = "qcom,sm8250-gem-noc";
+			reg = <0 0x09100000 0 0xb4000>;
+			#interconnect-cells = <1>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		npu_noc: interconnect@9990000 {
+			compatible = "qcom,sm8250-npu-noc";
+			reg = <0 0x09990000 0 0x1600>;
+			#interconnect-cells = <1>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
 		usb_1: usb@a6f8800 {
 			compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
 			reg = <0 0x0a6f8800 0 0x400>;
@@ -2359,6 +2437,10 @@ rpmhpd_opp_turbo_l1: opp10 {
 					};
 				};
 			};
+
+			apps_bcm_voter: bcm_voter {
+				compatible = "qcom,bcm-voter";
+			};
 		};
 	};
 
-- 
2.26.1

Re: [PATCH v3 1/7] dt-bindings: interconnect: single yaml file for RPMh interconnect drivers

[Sibi Sankar]

On 2020-07-28 08:08, Jonathan Marek wrote:
> These two bindings are almost identical, so combine them into one. This
> will make it easier to add the sm8150 and sm8250 interconnect bindings.
> 
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>

Reviewed-by: Sibi Sankar <sibis@codeaurora.org>

> ---
>  .../{qcom,sdm845.yaml => qcom,rpmh.yaml}      | 20 ++++-
>  .../bindings/interconnect/qcom,sc7180.yaml    | 85 -------------------
>  2 files changed, 17 insertions(+), 88 deletions(-)
>  rename
> Documentation/devicetree/bindings/interconnect/{qcom,sdm845.yaml =>
> qcom,rpmh.yaml} (76%)
>  delete mode 100644
> Documentation/devicetree/bindings/interconnect/qcom,sc7180.yaml
> 
> diff --git
> a/Documentation/devicetree/bindings/interconnect/qcom,sdm845.yaml
> b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
> similarity index 76%
> rename from 
> Documentation/devicetree/bindings/interconnect/qcom,sdm845.yaml
> rename to Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
> index 74536747b51d..6a457f914bb5 100644
> --- a/Documentation/devicetree/bindings/interconnect/qcom,sdm845.yaml
> +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
> @@ -1,16 +1,17 @@
>  # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>  %YAML 1.2
>  ---
> -$id: http://devicetree.org/schemas/interconnect/qcom,sdm845.yaml#
> +$id: http://devicetree.org/schemas/interconnect/qcom,rpmh.yaml#
>  $schema: http://devicetree.org/meta-schemas/core.yaml#
> 
> -title:  Qualcomm SDM845 Network-On-Chip Interconnect
> +title:  Qualcomm RPMh Network-On-Chip Interconnect
> 
>  maintainers:
>    - Georgi Djakov <georgi.djakov@linaro.org>
> +  - Odelu Kukatla <okukatla@codeaurora.org>
> 
>  description: |
> -   SDM845 interconnect providers support system bandwidth requirements 
> through
> +   RPMh interconnect providers support system bandwidth requirements 
> through
>     RPMh hardware accelerators known as Bus Clock Manager (BCM). The 
> provider is
>     able to communicate with the BCM through the Resource State
> Coordinator (RSC)
>     associated with each execution environment. Provider nodes must 
> point to at
> @@ -23,6 +24,19 @@ properties:
> 
>    compatible:
>      enum:
> +      - qcom,sc7180-aggre1-noc
> +      - qcom,sc7180-aggre2-noc
> +      - qcom,sc7180-camnoc-virt
> +      - qcom,sc7180-compute-noc
> +      - qcom,sc7180-config-noc
> +      - qcom,sc7180-dc-noc
> +      - qcom,sc7180-gem-noc
> +      - qcom,sc7180-ipa-virt
> +      - qcom,sc7180-mc-virt
> +      - qcom,sc7180-mmss-noc
> +      - qcom,sc7180-npu-noc
> +      - qcom,sc7180-qup-virt
> +      - qcom,sc7180-system-noc
>        - qcom,sdm845-aggre1-noc
>        - qcom,sdm845-aggre2-noc
>        - qcom,sdm845-config-noc
> diff --git
> a/Documentation/devicetree/bindings/interconnect/qcom,sc7180.yaml
> b/Documentation/devicetree/bindings/interconnect/qcom,sc7180.yaml
> deleted file mode 100644
> index d01bac80d416..000000000000
> --- a/Documentation/devicetree/bindings/interconnect/qcom,sc7180.yaml
> +++ /dev/null
> @@ -1,85 +0,0 @@
> -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> -%YAML 1.2
> ----
> -$id: http://devicetree.org/schemas/interconnect/qcom,sc7180.yaml#
> -$schema: http://devicetree.org/meta-schemas/core.yaml#
> -
> -title:  Qualcomm SC7180 Network-On-Chip Interconnect
> -
> -maintainers:
> -  - Odelu Kukatla <okukatla@codeaurora.org>
> -
> -description: |
> -   SC7180 interconnect providers support system bandwidth requirements 
> through
> -   RPMh hardware accelerators known as Bus Clock Manager (BCM). The 
> provider is
> -   able to communicate with the BCM through the Resource State
> Coordinator (RSC)
> -   associated with each execution environment. Provider nodes must 
> point to at
> -   least one RPMh device child node pertaining to their RSC and each 
> provider
> -   can map to multiple RPMh resources.
> -
> -properties:
> -  reg:
> -    maxItems: 1
> -
> -  compatible:
> -    enum:
> -      - qcom,sc7180-aggre1-noc
> -      - qcom,sc7180-aggre2-noc
> -      - qcom,sc7180-camnoc-virt
> -      - qcom,sc7180-compute-noc
> -      - qcom,sc7180-config-noc
> -      - qcom,sc7180-dc-noc
> -      - qcom,sc7180-gem-noc
> -      - qcom,sc7180-ipa-virt
> -      - qcom,sc7180-mc-virt
> -      - qcom,sc7180-mmss-noc
> -      - qcom,sc7180-npu-noc
> -      - qcom,sc7180-qup-virt
> -      - qcom,sc7180-system-noc
> -
> -  '#interconnect-cells':
> -    const: 1
> -
> -  qcom,bcm-voters:
> -    $ref: /schemas/types.yaml#/definitions/phandle-array
> -    description: |
> -      List of phandles to qcom,bcm-voter nodes that are required by
> -      this interconnect to send RPMh commands.
> -
> -  qcom,bcm-voter-names:
> -    $ref: /schemas/types.yaml#/definitions/string-array
> -    description: |
> -      Names for each of the qcom,bcm-voters specified.
> -
> -required:
> -  - compatible
> -  - reg
> -  - '#interconnect-cells'
> -  - qcom,bcm-voters
> -
> -additionalProperties: false
> -
> -examples:
> -  - |
> -      #include <dt-bindings/interconnect/qcom,sc7180.h>
> -
> -      config_noc: interconnect@1500000 {
> -            compatible = "qcom,sc7180-config-noc";
> -            reg = <0x01500000 0x28000>;
> -            #interconnect-cells = <1>;
> -            qcom,bcm-voters = <&apps_bcm_voter>;
> -      };
> -
> -      system_noc: interconnect@1620000 {
> -            compatible = "qcom,sc7180-system-noc";
> -            reg = <0x01620000 0x17080>;
> -            #interconnect-cells = <1>;
> -            qcom,bcm-voters = <&apps_bcm_voter>;
> -      };
> -
> -      mmss_noc: interconnect@1740000 {
> -            compatible = "qcom,sc7180-mmss-noc";
> -            reg = <0x01740000 0x1c100>;
> -            #interconnect-cells = <1>;
> -            qcom,bcm-voters = <&apps_bcm_voter>;
> -      };

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.

Re: [PATCH v3 2/7] dt-bindings: interconnect: Add Qualcomm SM8150 DT bindings

[Sibi Sankar]

On 2020-07-28 08:08, Jonathan Marek wrote:
> The Qualcomm SM8150 platform has several bus fabrics that could be
> controlled and tuned dynamically according to the bandwidth demand.
> 
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> Reviewed-by: Rob Herring <robh@kernel.org>

Reviewed-by: Sibi Sankar <sibis@codeaurora.org>

> ---
>  .../bindings/interconnect/qcom,rpmh.yaml      |  11 ++
>  .../dt-bindings/interconnect/qcom,sm8150.h    | 162 ++++++++++++++++++
>  2 files changed, 173 insertions(+)
>  create mode 100644 include/dt-bindings/interconnect/qcom,sm8150.h
> 
> diff --git
> a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
> b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
> index 6a457f914bb5..e95ccd7b4b5a 100644
> --- a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
> +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
> @@ -45,6 +45,17 @@ properties:
>        - qcom,sdm845-mem-noc
>        - qcom,sdm845-mmss-noc
>        - qcom,sdm845-system-noc
> +      - qcom,sm8150-aggre1-noc
> +      - qcom,sm8150-aggre2-noc
> +      - qcom,sm8150-camnoc-noc
> +      - qcom,sm8150-compute-noc
> +      - qcom,sm8150-config-noc
> +      - qcom,sm8150-dc-noc
> +      - qcom,sm8150-gem-noc
> +      - qcom,sm8150-ipa-virt
> +      - qcom,sm8150-mc-virt
> +      - qcom,sm8150-mmss-noc
> +      - qcom,sm8150-system-noc
> 
>    '#interconnect-cells':
>      const: 1
> diff --git a/include/dt-bindings/interconnect/qcom,sm8150.h
> b/include/dt-bindings/interconnect/qcom,sm8150.h
> new file mode 100644
> index 000000000000..a25684680c42
> --- /dev/null
> +++ b/include/dt-bindings/interconnect/qcom,sm8150.h
> @@ -0,0 +1,162 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Qualcomm SM8150 interconnect IDs
> + *
> + * Copyright (c) 2020, The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8150_H
> +#define __DT_BINDINGS_INTERCONNECT_QCOM_SM8150_H
> +
> +#define MASTER_A1NOC_CFG		0
> +#define MASTER_QUP_0			1
> +#define MASTER_EMAC			2
> +#define MASTER_UFS_MEM			3
> +#define MASTER_USB3			4
> +#define MASTER_USB3_1			5
> +#define A1NOC_SNOC_SLV			6
> +#define SLAVE_SERVICE_A1NOC		7
> +
> +#define MASTER_A2NOC_CFG		0
> +#define MASTER_QDSS_BAM			1
> +#define MASTER_QSPI			2
> +#define MASTER_QUP_1			3
> +#define MASTER_QUP_2			4
> +#define MASTER_SENSORS_AHB		5
> +#define MASTER_TSIF			6
> +#define MASTER_CNOC_A2NOC		7
> +#define MASTER_CRYPTO_CORE_0		8
> +#define MASTER_IPA			9
> +#define MASTER_PCIE			10
> +#define MASTER_PCIE_1			11
> +#define MASTER_QDSS_ETR			12
> +#define MASTER_SDCC_2			13
> +#define MASTER_SDCC_4			14
> +#define A2NOC_SNOC_SLV			15
> +#define SLAVE_ANOC_PCIE_GEM_NOC		16
> +#define SLAVE_SERVICE_A2NOC		17
> +
> +#define MASTER_CAMNOC_HF0_UNCOMP	0
> +#define MASTER_CAMNOC_HF1_UNCOMP	1
> +#define MASTER_CAMNOC_SF_UNCOMP		2
> +#define SLAVE_CAMNOC_UNCOMP		3
> +
> +#define MASTER_NPU			0
> +#define SLAVE_CDSP_MEM_NOC		1
> +
> +#define MASTER_SPDM			0
> +#define SNOC_CNOC_MAS			1
> +#define MASTER_QDSS_DAP			2
> +#define SLAVE_A1NOC_CFG			3
> +#define SLAVE_A2NOC_CFG			4
> +#define SLAVE_AHB2PHY_SOUTH		5
> +#define SLAVE_AOP			6
> +#define SLAVE_AOSS			7
> +#define SLAVE_CAMERA_CFG		8
> +#define SLAVE_CLK_CTL			9
> +#define SLAVE_CDSP_CFG			10
> +#define SLAVE_RBCPR_CX_CFG		11
> +#define SLAVE_RBCPR_MMCX_CFG		12
> +#define SLAVE_RBCPR_MX_CFG		13
> +#define SLAVE_CRYPTO_0_CFG		14
> +#define SLAVE_CNOC_DDRSS		15
> +#define SLAVE_DISPLAY_CFG		16
> +#define SLAVE_EMAC_CFG			17
> +#define SLAVE_GLM			18
> +#define SLAVE_GRAPHICS_3D_CFG		19
> +#define SLAVE_IMEM_CFG			20
> +#define SLAVE_IPA_CFG			21
> +#define SLAVE_CNOC_MNOC_CFG		22
> +#define SLAVE_NPU_CFG			23
> +#define SLAVE_PCIE_0_CFG		24
> +#define SLAVE_PCIE_1_CFG		25
> +#define SLAVE_NORTH_PHY_CFG		26
> +#define SLAVE_PIMEM_CFG			27
> +#define SLAVE_PRNG			28
> +#define SLAVE_QDSS_CFG			29
> +#define SLAVE_QSPI			30
> +#define SLAVE_QUP_2			31
> +#define SLAVE_QUP_1			32
> +#define SLAVE_QUP_0			33
> +#define SLAVE_SDCC_2			34
> +#define SLAVE_SDCC_4			35
> +#define SLAVE_SNOC_CFG			36
> +#define SLAVE_SPDM_WRAPPER		37
> +#define SLAVE_SPSS_CFG			38
> +#define SLAVE_SSC_CFG			39
> +#define SLAVE_TCSR			40
> +#define SLAVE_TLMM_EAST			41
> +#define SLAVE_TLMM_NORTH		42
> +#define SLAVE_TLMM_SOUTH		43
> +#define SLAVE_TLMM_WEST			44
> +#define SLAVE_TSIF			45
> +#define SLAVE_UFS_CARD_CFG		46
> +#define SLAVE_UFS_MEM_CFG		47
> +#define SLAVE_USB3			48
> +#define SLAVE_USB3_1			49
> +#define SLAVE_VENUS_CFG			50
> +#define SLAVE_VSENSE_CTRL_CFG		51
> +#define SLAVE_CNOC_A2NOC		52
> +#define SLAVE_SERVICE_CNOC		53
> +
> +#define MASTER_CNOC_DC_NOC		0
> +#define SLAVE_LLCC_CFG			1
> +#define SLAVE_GEM_NOC_CFG		2
> +
> +#define MASTER_AMPSS_M0			0
> +#define MASTER_GPU_TCU			1
> +#define MASTER_SYS_TCU			2
> +#define MASTER_GEM_NOC_CFG		3
> +#define MASTER_COMPUTE_NOC		4
> +#define MASTER_GRAPHICS_3D		5
> +#define MASTER_MNOC_HF_MEM_NOC		6
> +#define MASTER_MNOC_SF_MEM_NOC		7
> +#define MASTER_GEM_NOC_PCIE_SNOC	8
> +#define MASTER_SNOC_GC_MEM_NOC		9
> +#define MASTER_SNOC_SF_MEM_NOC		10
> +#define MASTER_ECC			11
> +#define SLAVE_MSS_PROC_MS_MPU_CFG	12
> +#define SLAVE_ECC			13
> +#define SLAVE_GEM_NOC_SNOC		14
> +#define SLAVE_LLCC			15
> +#define SLAVE_SERVICE_GEM_NOC		16
> +
> +#define MASTER_IPA_CORE			0
> +#define SLAVE_IPA_CORE			1
> +
> +#define MASTER_LLCC			0
> +#define SLAVE_EBI_CH0			1
> +
> +#define MASTER_CNOC_MNOC_CFG		0
> +#define MASTER_CAMNOC_HF0		1
> +#define MASTER_CAMNOC_HF1		2
> +#define MASTER_CAMNOC_SF		3
> +#define MASTER_MDP_PORT0		4
> +#define MASTER_MDP_PORT1		5
> +#define MASTER_ROTATOR			6
> +#define MASTER_VIDEO_P0			7
> +#define MASTER_VIDEO_P1			8
> +#define MASTER_VIDEO_PROC		9
> +#define SLAVE_MNOC_SF_MEM_NOC		10
> +#define SLAVE_MNOC_HF_MEM_NOC		11
> +#define SLAVE_SERVICE_MNOC		12
> +
> +#define MASTER_SNOC_CFG			0
> +#define A1NOC_SNOC_MAS			1
> +#define A2NOC_SNOC_MAS			2
> +#define MASTER_GEM_NOC_SNOC		3
> +#define MASTER_PIMEM			4
> +#define MASTER_GIC			5
> +#define SLAVE_APPSS			6
> +#define SNOC_CNOC_SLV			7
> +#define SLAVE_SNOC_GEM_NOC_GC		8
> +#define SLAVE_SNOC_GEM_NOC_SF		9
> +#define SLAVE_OCIMEM			10
> +#define SLAVE_PIMEM			11
> +#define SLAVE_SERVICE_SNOC		12
> +#define SLAVE_PCIE_0			13
> +#define SLAVE_PCIE_1			14
> +#define SLAVE_QDSS_STM			15
> +#define SLAVE_TCU			16
> +
> +#endif

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.

Re: [PATCH v3 3/7] dt-bindings: interconnect: Add Qualcomm SM8250 DT bindings

[Sibi Sankar]

On 2020-07-28 08:08, Jonathan Marek wrote:
> The Qualcomm SM8250 platform has several bus fabrics that could be
> controlled and tuned dynamically according to the bandwidth demand.
> 
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> Reviewed-by: Rob Herring <robh@kernel.org>

Reviewed-by: Sibi Sankar <sibis@codeaurora.org>

> ---
>  .../bindings/interconnect/qcom,rpmh.yaml      |  11 ++
>  .../dt-bindings/interconnect/qcom,sm8250.h    | 172 ++++++++++++++++++
>  2 files changed, 183 insertions(+)
>  create mode 100644 include/dt-bindings/interconnect/qcom,sm8250.h
> 
> diff --git
> a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
> b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
> index e95ccd7b4b5a..18c48a2ce191 100644
> --- a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
> +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
> @@ -56,6 +56,17 @@ properties:
>        - qcom,sm8150-mc-virt
>        - qcom,sm8150-mmss-noc
>        - qcom,sm8150-system-noc
> +      - qcom,sm8250-aggre1-noc
> +      - qcom,sm8250-aggre2-noc
> +      - qcom,sm8250-compute-noc
> +      - qcom,sm8250-config-noc
> +      - qcom,sm8250-dc-noc
> +      - qcom,sm8250-gem-noc
> +      - qcom,sm8250-ipa-virt
> +      - qcom,sm8250-mc-virt
> +      - qcom,sm8250-mmss-noc
> +      - qcom,sm8250-npu-noc
> +      - qcom,sm8250-system-noc
> 
>    '#interconnect-cells':
>      const: 1
> diff --git a/include/dt-bindings/interconnect/qcom,sm8250.h
> b/include/dt-bindings/interconnect/qcom,sm8250.h
> new file mode 100644
> index 000000000000..1b4d9fbe888d
> --- /dev/null
> +++ b/include/dt-bindings/interconnect/qcom,sm8250.h
> @@ -0,0 +1,172 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Qualcomm SM8250 interconnect IDs
> + *
> + * Copyright (c) 2020, The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8250_H
> +#define __DT_BINDINGS_INTERCONNECT_QCOM_SM8250_H
> +
> +#define MASTER_A1NOC_CFG		0
> +#define MASTER_QSPI_0			1
> +#define MASTER_QUP_1			2
> +#define MASTER_QUP_2			3
> +#define MASTER_TSIF			4
> +#define MASTER_PCIE_2			5
> +#define MASTER_SDCC_4			6
> +#define MASTER_UFS_MEM			7
> +#define MASTER_USB3			8
> +#define MASTER_USB3_1			9
> +#define A1NOC_SNOC_SLV			10
> +#define SLAVE_ANOC_PCIE_GEM_NOC_1	11
> +#define SLAVE_SERVICE_A1NOC		12
> +
> +#define MASTER_A2NOC_CFG		0
> +#define MASTER_QDSS_BAM			1
> +#define MASTER_QUP_0			2
> +#define MASTER_CNOC_A2NOC		3
> +#define MASTER_CRYPTO_CORE_0		4
> +#define MASTER_IPA			5
> +#define MASTER_PCIE			6
> +#define MASTER_PCIE_1			7
> +#define MASTER_QDSS_ETR			8
> +#define MASTER_SDCC_2			9
> +#define MASTER_UFS_CARD			10
> +#define A2NOC_SNOC_SLV			11
> +#define SLAVE_ANOC_PCIE_GEM_NOC		12
> +#define SLAVE_SERVICE_A2NOC		13
> +
> +#define MASTER_NPU			0
> +#define SLAVE_CDSP_MEM_NOC		1
> +
> +#define SNOC_CNOC_MAS			0
> +#define MASTER_QDSS_DAP			1
> +#define SLAVE_A1NOC_CFG			2
> +#define SLAVE_A2NOC_CFG			3
> +#define SLAVE_AHB2PHY_SOUTH		4
> +#define SLAVE_AHB2PHY_NORTH		5
> +#define SLAVE_AOSS			6
> +#define SLAVE_CAMERA_CFG		7
> +#define SLAVE_CLK_CTL			8
> +#define SLAVE_CDSP_CFG			9
> +#define SLAVE_RBCPR_CX_CFG		10
> +#define SLAVE_RBCPR_MMCX_CFG		11
> +#define SLAVE_RBCPR_MX_CFG		12
> +#define SLAVE_CRYPTO_0_CFG		13
> +#define SLAVE_CX_RDPM			14
> +#define SLAVE_DCC_CFG			15
> +#define SLAVE_CNOC_DDRSS		16
> +#define SLAVE_DISPLAY_CFG		17
> +#define SLAVE_GRAPHICS_3D_CFG		18
> +#define SLAVE_IMEM_CFG			19
> +#define SLAVE_IPA_CFG			20
> +#define SLAVE_IPC_ROUTER_CFG		21
> +#define SLAVE_LPASS			22
> +#define SLAVE_CNOC_MNOC_CFG		23
> +#define SLAVE_NPU_CFG			24
> +#define SLAVE_PCIE_0_CFG		25
> +#define SLAVE_PCIE_1_CFG		26
> +#define SLAVE_PCIE_2_CFG		27
> +#define SLAVE_PDM			28
> +#define SLAVE_PIMEM_CFG			29
> +#define SLAVE_PRNG			30
> +#define SLAVE_QDSS_CFG			31
> +#define SLAVE_QSPI_0			32
> +#define SLAVE_QUP_0			33
> +#define SLAVE_QUP_1			34
> +#define SLAVE_QUP_2			35
> +#define SLAVE_SDCC_2			36
> +#define SLAVE_SDCC_4			37
> +#define SLAVE_SNOC_CFG			38
> +#define SLAVE_TCSR			39
> +#define SLAVE_TLMM_NORTH		40
> +#define SLAVE_TLMM_SOUTH		41
> +#define SLAVE_TLMM_WEST			42
> +#define SLAVE_TSIF			43
> +#define SLAVE_UFS_CARD_CFG		44
> +#define SLAVE_UFS_MEM_CFG		45
> +#define SLAVE_USB3			46
> +#define SLAVE_USB3_1			47
> +#define SLAVE_VENUS_CFG			48
> +#define SLAVE_VSENSE_CTRL_CFG		49
> +#define SLAVE_CNOC_A2NOC		50
> +#define SLAVE_SERVICE_CNOC		51
> +
> +#define MASTER_CNOC_DC_NOC		0
> +#define SLAVE_LLCC_CFG			1
> +#define SLAVE_GEM_NOC_CFG		2
> +
> +#define MASTER_GPU_TCU			0
> +#define MASTER_SYS_TCU			1
> +#define MASTER_AMPSS_M0			2
> +#define MASTER_GEM_NOC_CFG		3
> +#define MASTER_COMPUTE_NOC		4
> +#define MASTER_GRAPHICS_3D		5
> +#define MASTER_MNOC_HF_MEM_NOC		6
> +#define MASTER_MNOC_SF_MEM_NOC		7
> +#define MASTER_ANOC_PCIE_GEM_NOC	8
> +#define MASTER_SNOC_GC_MEM_NOC		9
> +#define MASTER_SNOC_SF_MEM_NOC		10
> +#define SLAVE_GEM_NOC_SNOC		11
> +#define SLAVE_LLCC			12
> +#define SLAVE_MEM_NOC_PCIE_SNOC		13
> +#define SLAVE_SERVICE_GEM_NOC_1		14
> +#define SLAVE_SERVICE_GEM_NOC_2		15
> +#define SLAVE_SERVICE_GEM_NOC		16
> +
> +#define MASTER_IPA_CORE			0
> +#define SLAVE_IPA_CORE			1
> +
> +#define MASTER_LLCC			0
> +#define SLAVE_EBI_CH0			1
> +
> +#define MASTER_CNOC_MNOC_CFG		0
> +#define MASTER_CAMNOC_HF		1
> +#define MASTER_CAMNOC_ICP		2
> +#define MASTER_CAMNOC_SF		3
> +#define MASTER_VIDEO_P0			4
> +#define MASTER_VIDEO_P1			5
> +#define MASTER_VIDEO_PROC		6
> +#define MASTER_MDP_PORT0		7
> +#define MASTER_MDP_PORT1		8
> +#define MASTER_ROTATOR			9
> +#define SLAVE_MNOC_HF_MEM_NOC		10
> +#define SLAVE_MNOC_SF_MEM_NOC		11
> +#define SLAVE_SERVICE_MNOC		12
> +
> +#define MASTER_NPU_SYS			0
> +#define MASTER_NPU_CDP			1
> +#define MASTER_NPU_NOC_CFG		2
> +#define SLAVE_NPU_CAL_DP0		3
> +#define SLAVE_NPU_CAL_DP1		4
> +#define SLAVE_NPU_CP			5
> +#define SLAVE_NPU_INT_DMA_BWMON_CFG	6
> +#define SLAVE_NPU_DPM			7
> +#define SLAVE_ISENSE_CFG		8
> +#define SLAVE_NPU_LLM_CFG		9
> +#define SLAVE_NPU_TCM			10
> +#define SLAVE_NPU_COMPUTE_NOC		11
> +#define SLAVE_SERVICE_NPU_NOC		12
> +
> +#define MASTER_SNOC_CFG			0
> +#define A1NOC_SNOC_MAS			1
> +#define A2NOC_SNOC_MAS			2
> +#define MASTER_GEM_NOC_SNOC		3
> +#define MASTER_GEM_NOC_PCIE_SNOC	4
> +#define MASTER_PIMEM			5
> +#define MASTER_GIC			6
> +#define SLAVE_APPSS			7
> +#define SNOC_CNOC_SLV			8
> +#define SLAVE_SNOC_GEM_NOC_GC		9
> +#define SLAVE_SNOC_GEM_NOC_SF		10
> +#define SLAVE_OCIMEM			11
> +#define SLAVE_PIMEM			12
> +#define SLAVE_SERVICE_SNOC		13
> +#define SLAVE_PCIE_0			14
> +#define SLAVE_PCIE_1			15
> +#define SLAVE_PCIE_2			16
> +#define SLAVE_QDSS_STM			17
> +#define SLAVE_TCU			18
> +
> +#endif

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.

Re: [PATCH v3 6/7] arm64: dts: qcom: sm8150: add interconnect nodes

[Sibi Sankar]

On 2020-07-28 08:08, Jonathan Marek wrote:
> Add the interconnect dts nodes for sm8150.
> 
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
>  arch/arm64/boot/dts/qcom/sm8150.dtsi | 82 ++++++++++++++++++++++++++++
>  1 file changed, 82 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> index 33ff99132f4f..e4689c27224b 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> @@ -11,6 +11,7 @@
>  #include <dt-bindings/clock/qcom,rpmh.h>
>  #include <dt-bindings/clock/qcom,gcc-sm8150.h>
>  #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
> +#include <dt-bindings/interconnect/qcom,sm8150.h>
>  #include <dt-bindings/thermal/thermal.h>
> 
>  / {
> @@ -440,6 +441,55 @@ uart2: serial@a90000 {
>  			};
>  		};
> 
> +		config_noc: interconnect@1500000 {
> +			compatible = "qcom,sm8150-config-noc";
> +			reg = <0 0x01500000 0 0x7400>;
> +			#interconnect-cells = <1>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		system_noc: interconnect@1620000 {
> +			compatible = "qcom,sm8150-system-noc";
> +			reg = <0 0x01620000 0 0x19400>;
> +			#interconnect-cells = <1>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		mc_virt: interconnect@163a000 {
> +			compatible = "qcom,sm8150-mc-virt";
> +			reg = <0 0x0163a000 0 0x1000>;
> +			#interconnect-cells = <1>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		aggre1_noc: interconnect@16e0000 {
> +			compatible = "qcom,sm8150-aggre1-noc";
> +			reg = <0 0x016e0000 0 0xd080>;
> +			#interconnect-cells = <1>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		aggre2_noc: interconnect@1700000 {
> +			compatible = "qcom,sm8150-aggre2-noc";
> +			reg = <0 0x01700000 0 0x20000>;

Though aggre2_noc might need a
larger space in the future lets
lands ^^ for now.

Reviewed-by: Sibi Sankar <sibis@codeaurora.org>

> +			#interconnect-cells = <1>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		compute_noc: interconnect@1720000 {
> +			compatible = "qcom,sm8150-compute-noc";
> +			reg = <0 0x01720000 0 0x7000>;
> +			#interconnect-cells = <1>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		mmss_noc: interconnect@1740000 {
> +			compatible = "qcom,sm8150-mmss-noc";
> +			reg = <0 0x01740000 0 0x1c100>;
> +			#interconnect-cells = <1>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
>  		ufs_mem_hc: ufshc@1d84000 {
>  			compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
>  				     "jedec,ufs-2.0";
> @@ -510,6 +560,13 @@ ufs_mem_phy_lanes: lanes@1d87400 {
>  			};
>  		};
> 
> +		ipa_virt: interconnect@1e00000 {
> +			compatible = "qcom,sm8150-ipa-virt";
> +			reg = <0 0x01e00000 0 0x1000>;
> +			#interconnect-cells = <1>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
>  		tcsr_mutex_regs: syscon@1f40000 {
>  			compatible = "syscon";
>  			reg = <0x0 0x01f40000 0x0 0x40000>;
> @@ -860,6 +917,20 @@ usb_2_ssphy: lane@88eb200 {
>  			};
>  		};
> 
> +		dc_noc: interconnect@9160000 {
> +			compatible = "qcom,sm8150-dc-noc";
> +			reg = <0 0x09160000 0 0x3200>;
> +			#interconnect-cells = <1>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		gem_noc: interconnect@9680000 {
> +			compatible = "qcom,sm8150-gem-noc";
> +			reg = <0 0x09680000 0 0x3e200>;
> +			#interconnect-cells = <1>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
>  		usb_1: usb@a6f8800 {
>  			compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
>  			reg = <0 0x0a6f8800 0 0x400>;
> @@ -950,6 +1021,13 @@ usb_2_dwc3: dwc3@a800000 {
>  			};
>  		};
> 
> +		camnoc_virt: interconnect@ac00000 {
> +			compatible = "qcom,sm8150-camnoc-virt";
> +			reg = <0 0x0ac00000 0 0x1000>;
> +			#interconnect-cells = <1>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
>  		aoss_qmp: power-controller@c300000 {
>  			compatible = "qcom,sm8150-aoss-qmp";
>  			reg = <0x0 0x0c300000 0x0 0x100000>;
> @@ -1280,6 +1358,10 @@ rpmhpd_opp_turbo_l1: opp11 {
>  					};
>  				};
>  			};
> +
> +			apps_bcm_voter: bcm_voter {
> +				compatible = "qcom,bcm-voter";
> +			};
>  		};
> 
>  		cpufreq_hw: cpufreq@18323000 {

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.

Re: [PATCH v3 7/7] arm64: dts: qcom: sm8250: add interconnect nodes

[Sibi Sankar]

On 2020-07-28 08:08, Jonathan Marek wrote:
> Add the interconnect dts nodes for sm8250.
> 
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>

Reviewed-by: Sibi Sankar <sibis@codeaurora.org>

> ---
>  arch/arm64/boot/dts/qcom/sm8250.dtsi | 82 ++++++++++++++++++++++++++++
>  1 file changed, 82 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> index 636e2196138c..945bd4a9d640 100644
> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> @@ -7,6 +7,7 @@
>  #include <dt-bindings/clock/qcom,gcc-sm8250.h>
>  #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
>  #include <dt-bindings/clock/qcom,rpmh.h>
> +#include <dt-bindings/interconnect/qcom,sm8250.h>
>  #include <dt-bindings/mailbox/qcom-ipcc.h>
>  #include <dt-bindings/power/qcom-aoss-qmp.h>
>  #include <dt-bindings/power/qcom-rpmpd.h>
> @@ -978,6 +979,55 @@ spi13: spi@a94000 {
>  			};
>  		};
> 
> +		config_noc: interconnect@1500000 {
> +			compatible = "qcom,sm8250-config-noc";
> +			reg = <0 0x01500000 0 0xa580>;
> +			#interconnect-cells = <1>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		system_noc: interconnect@1620000 {
> +			compatible = "qcom,sm8250-system-noc";
> +			reg = <0 0x01620000 0 0x1c200>;
> +			#interconnect-cells = <1>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		mc_virt: interconnect@163d000 {
> +			compatible = "qcom,sm8250-mc-virt";
> +			reg = <0 0x0163d000 0 0x1000>;
> +			#interconnect-cells = <1>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		aggre1_noc: interconnect@16e0000 {
> +			compatible = "qcom,sm8250-aggre1-noc";
> +			reg = <0 0x016e0000 0 0x1f180>;
> +			#interconnect-cells = <1>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		aggre2_noc: interconnect@1700000 {
> +			compatible = "qcom,sm8250-aggre2-noc";
> +			reg = <0 0x01700000 0 0x33000>;
> +			#interconnect-cells = <1>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		compute_noc: interconnect@1733000 {
> +			compatible = "qcom,sm8250-compute-noc";
> +			reg = <0 0x01733000 0 0xa180>;
> +			#interconnect-cells = <1>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		mmss_noc: interconnect@1740000 {
> +			compatible = "qcom,sm8250-mmss-noc";
> +			reg = <0 0x01740000 0 0x1f080>;
> +			#interconnect-cells = <1>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
>  		ufs_mem_hc: ufshc@1d84000 {
>  			compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
>  				     "jedec,ufs-2.0";
> @@ -1050,6 +1100,13 @@ ufs_mem_phy_lanes: lanes@1d87400 {
>  			};
>  		};
> 
> +		ipa_virt: interconnect@1e00000 {
> +			compatible = "qcom,sm8250-ipa-virt";
> +			reg = <0 0x01e00000 0 0x1000>;
> +			#interconnect-cells = <1>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
>  		tcsr_mutex_regs: syscon@1f40000 {
>  			compatible = "syscon";
>  			reg = <0x0 0x01f40000 0x0 0x40000>;
> @@ -1364,6 +1421,27 @@ usb_2_ssphy: lane@88eb200 {
>  			};
>  		};
> 
> +		dc_noc: interconnect@90c0000 {
> +			compatible = "qcom,sm8250-dc-noc";
> +			reg = <0 0x090c0000 0 0x4200>;
> +			#interconnect-cells = <1>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		gem_noc: interconnect@9100000 {
> +			compatible = "qcom,sm8250-gem-noc";
> +			reg = <0 0x09100000 0 0xb4000>;
> +			#interconnect-cells = <1>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
> +		npu_noc: interconnect@9990000 {
> +			compatible = "qcom,sm8250-npu-noc";
> +			reg = <0 0x09990000 0 0x1600>;
> +			#interconnect-cells = <1>;
> +			qcom,bcm-voters = <&apps_bcm_voter>;
> +		};
> +
>  		usb_1: usb@a6f8800 {
>  			compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
>  			reg = <0 0x0a6f8800 0 0x400>;
> @@ -2359,6 +2437,10 @@ rpmhpd_opp_turbo_l1: opp10 {
>  					};
>  				};
>  			};
> +
> +			apps_bcm_voter: bcm_voter {
> +				compatible = "qcom,bcm-voter";
> +			};
>  		};
>  	};

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.

Re: [PATCH v3 1/7] dt-bindings: interconnect: single yaml file for RPMh interconnect drivers

[Rob Herring]

On Mon, 27 Jul 2020 22:38:00 -0400, Jonathan Marek wrote:
> These two bindings are almost identical, so combine them into one. This
> will make it easier to add the sm8150 and sm8250 interconnect bindings.
> 
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
>  .../{qcom,sdm845.yaml => qcom,rpmh.yaml}      | 20 ++++-
>  .../bindings/interconnect/qcom,sc7180.yaml    | 85 -------------------
>  2 files changed, 17 insertions(+), 88 deletions(-)
>  rename Documentation/devicetree/bindings/interconnect/{qcom,sdm845.yaml => qcom,rpmh.yaml} (76%)
>  delete mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sc7180.yaml
> 

Reviewed-by: Rob Herring <robh@kernel.org>