* [PATCH v3 1/8] dt-bindings: PCI: pci-rcar-gen2: Convert bindings to json-schema
2022-04-22 12:08 [PATCH v3 0/8] RZN1 USB Host support Herve Codina
@ 2022-04-22 12:08 ` Herve Codina
2022-04-26 0:45 ` Rob Herring
2022-04-27 15:05 ` Geert Uytterhoeven
2022-04-22 12:08 ` [PATCH v3 2/8] dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support for r9a06g032 Herve Codina
` (6 subsequent siblings)
7 siblings, 2 replies; 32+ messages in thread
From: Herve Codina @ 2022-04-22 12:08 UTC (permalink / raw)
To: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
Lorenzo Pieralisi, Krzysztof Wilczyński
Cc: Rob Herring, linux-pci, linux-renesas-soc, devicetree,
linux-kernel, Sergey Shtylyov, Thomas Petazzoni, Clement Leger,
Miquel Raynal, Herve Codina
Convert Renesas PCI bridge bindings documentation to json-schema.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
---
.../devicetree/bindings/pci/pci-rcar-gen2.txt | 84 ----------
.../bindings/pci/renesas,pci-rcar-gen2.yaml | 156 ++++++++++++++++++
2 files changed, 156 insertions(+), 84 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
create mode 100644 Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
diff --git a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt b/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
deleted file mode 100644
index aeba38f0a387..000000000000
--- a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
+++ /dev/null
@@ -1,84 +0,0 @@
-Renesas AHB to PCI bridge
--------------------------
-
-This is the bridge used internally to connect the USB controllers to the
-AHB. There is one bridge instance per USB port connected to the internal
-OHCI and EHCI controllers.
-
-Required properties:
-- compatible: "renesas,pci-r8a7742" for the R8A7742 SoC;
- "renesas,pci-r8a7743" for the R8A7743 SoC;
- "renesas,pci-r8a7744" for the R8A7744 SoC;
- "renesas,pci-r8a7745" for the R8A7745 SoC;
- "renesas,pci-r8a7790" for the R8A7790 SoC;
- "renesas,pci-r8a7791" for the R8A7791 SoC;
- "renesas,pci-r8a7793" for the R8A7793 SoC;
- "renesas,pci-r8a7794" for the R8A7794 SoC;
- "renesas,pci-rcar-gen2" for a generic R-Car Gen2 or
- RZ/G1 compatible device.
-
-
- When compatible with the generic version, nodes must list the
- SoC-specific version corresponding to the platform first
- followed by the generic version.
-
-- reg: A list of physical regions to access the device: the first is
- the operational registers for the OHCI/EHCI controllers and the
- second is for the bridge configuration and control registers.
-- interrupts: interrupt for the device.
-- clocks: The reference to the device clock.
-- bus-range: The PCI bus number range; as this is a single bus, the range
- should be specified as the same value twice.
-- #address-cells: must be 3.
-- #size-cells: must be 2.
-- #interrupt-cells: must be 1.
-- interrupt-map: standard property used to define the mapping of the PCI
- interrupts to the GIC interrupts.
-- interrupt-map-mask: standard property that helps to define the interrupt
- mapping.
-
-Optional properties:
-- dma-ranges: a single range for the inbound memory region. If not supplied,
- defaults to 1GiB at 0x40000000. Note there are hardware restrictions on the
- allowed combinations of address and size.
-
-Example SoC configuration:
-
- pci0: pci@ee090000 {
- compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
- clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
- reg = <0x0 0xee090000 0x0 0xc00>,
- <0x0 0xee080000 0x0 0x1100>;
- interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
-
- bus-range = <0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
-
- usb@1,0 {
- reg = <0x800 0 0 0 0>;
- phys = <&usb0 0>;
- phy-names = "usb";
- };
-
- usb@2,0 {
- reg = <0x1000 0 0 0 0>;
- phys = <&usb0 0>;
- phy-names = "usb";
- };
- };
-
-Example board setup:
-
-&pci0 {
- status = "okay";
- pinctrl-0 = <&usb0_pins>;
- pinctrl-names = "default";
-};
diff --git a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
new file mode 100644
index 000000000000..494eb975c146
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
@@ -0,0 +1,156 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/renesas,pci-rcar-gen2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas AHB to PCI bridge
+
+maintainers:
+ - Marek Vasut <marek.vasut+renesas@gmail.com>
+ - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+
+description: |
+ This is the bridge used internally to connect the USB controllers to the
+ AHB. There is one bridge instance per USB port connected to the internal
+ OHCI and EHCI controllers.
+
+allOf:
+ - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - renesas,pci-r8a7742 # RZ/G1H
+ - renesas,pci-r8a7743 # RZ/G1M
+ - renesas,pci-r8a7744 # RZ/G1N
+ - renesas,pci-r8a7745 # RZ/G1E
+ - renesas,pci-r8a7790 # R-Car H2
+ - renesas,pci-r8a7791 # R-Car M2-W
+ - renesas,pci-r8a7793 # R-Car M2-N
+ - renesas,pci-r8a7794 # R-Car E2
+ - const: renesas,pci-rcar-gen2 # R-Car Gen2 and RZ/G1
+
+ reg:
+ items:
+ - description: Operational registers for the OHCI/EHCI controllers.
+ - description: Bridge configuration and control registers.
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Device clock
+
+ clock-names:
+ items:
+ - const: pclk
+
+ resets:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ bus-range:
+ description: |
+ The PCI bus number range; as this is a single bus, the range
+ should be specified as the same value twice.
+
+ dma-ranges:
+ description: |
+ A single range for the inbound memory region. If not supplied,
+ defaults to 1GiB at 0x40000000. Note there are hardware restrictions on
+ the allowed combinations of address and size.
+ maxItems: 1
+
+patternProperties:
+ 'usb@[0-1],0':
+ type: object
+
+ description:
+ This a USB controller PCI device
+
+ properties:
+ reg:
+ description:
+ Identify the correct bus, device and function number in the
+ form <bdf 0 0 0 0>.
+
+ items:
+ minItems: 5
+ maxItems: 5
+
+ phys:
+ description:
+ Reference to the USB phy
+ maxItems: 1
+
+ phy-names:
+ maxItems: 1
+
+ required:
+ - reg
+ - phys
+ - phy-names
+
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-map
+ - interrupt-map-mask
+ - clocks
+ - resets
+ - power-domains
+ - bus-range
+ - "#address-cells"
+ - "#size-cells"
+ - "#interrupt-cells"
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
+ #include <dt-bindings/power/r8a7790-sysc.h>
+
+ pci@ee090000 {
+ compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
+ device_type = "pci";
+ reg = <0xee090000 0xc00>,
+ <0xee080000 0x1100>;
+ clocks = <&cpg CPG_MOD 703>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+
+ bus-range = <0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x02000000 0 0xee080000 0xee080000 0 0x00010000>;
+ dma-ranges = <0x42000000 0 0x40000000 0x40000000 0 0x40000000>;
+ interrupt-map-mask = <0xf800 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+
+ usb@1,0 {
+ reg = <0x800 0 0 0 0>;
+ phys = <&usb0 0>;
+ phy-names = "usb";
+ };
+
+ usb@2,0 {
+ reg = <0x1000 0 0 0 0>;
+ phys = <&usb0 0>;
+ phy-names = "usb";
+ };
+ };
--
2.35.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH v3 1/8] dt-bindings: PCI: pci-rcar-gen2: Convert bindings to json-schema
2022-04-22 12:08 ` [PATCH v3 1/8] dt-bindings: PCI: pci-rcar-gen2: Convert bindings to json-schema Herve Codina
@ 2022-04-26 0:45 ` Rob Herring
2022-04-26 0:47 ` Rob Herring
2022-04-27 15:05 ` Geert Uytterhoeven
1 sibling, 1 reply; 32+ messages in thread
From: Rob Herring @ 2022-04-26 0:45 UTC (permalink / raw)
To: Herve Codina
Cc: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas,
Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
Lorenzo Pieralisi, Krzysztof Wilczyński, linux-pci,
linux-renesas-soc, devicetree, linux-kernel, Sergey Shtylyov,
Thomas Petazzoni, Clement Leger, Miquel Raynal
On Fri, Apr 22, 2022 at 02:08:43PM +0200, Herve Codina wrote:
> Convert Renesas PCI bridge bindings documentation to json-schema.
>
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> ---
> .../devicetree/bindings/pci/pci-rcar-gen2.txt | 84 ----------
> .../bindings/pci/renesas,pci-rcar-gen2.yaml | 156 ++++++++++++++++++
> 2 files changed, 156 insertions(+), 84 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
> create mode 100644 Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
> diff --git a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
> new file mode 100644
> index 000000000000..494eb975c146
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
> @@ -0,0 +1,156 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/renesas,pci-rcar-gen2.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas AHB to PCI bridge
> +
> +maintainers:
> + - Marek Vasut <marek.vasut+renesas@gmail.com>
> + - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> +
> +description: |
> + This is the bridge used internally to connect the USB controllers to the
> + AHB. There is one bridge instance per USB port connected to the internal
> + OHCI and EHCI controllers.
> +
> +allOf:
> + - $ref: /schemas/pci/pci-bus.yaml#
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
Don't need oneOf with only 1 entry. Otherwise,
Reviewed-by: Rob Herring <robh@kernel.org>
> + - enum:
> + - renesas,pci-r8a7742 # RZ/G1H
> + - renesas,pci-r8a7743 # RZ/G1M
> + - renesas,pci-r8a7744 # RZ/G1N
> + - renesas,pci-r8a7745 # RZ/G1E
> + - renesas,pci-r8a7790 # R-Car H2
> + - renesas,pci-r8a7791 # R-Car M2-W
> + - renesas,pci-r8a7793 # R-Car M2-N
> + - renesas,pci-r8a7794 # R-Car E2
> + - const: renesas,pci-rcar-gen2 # R-Car Gen2 and RZ/G1
> +
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 1/8] dt-bindings: PCI: pci-rcar-gen2: Convert bindings to json-schema
2022-04-26 0:45 ` Rob Herring
@ 2022-04-26 0:47 ` Rob Herring
0 siblings, 0 replies; 32+ messages in thread
From: Rob Herring @ 2022-04-26 0:47 UTC (permalink / raw)
To: Herve Codina
Cc: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas,
Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
Lorenzo Pieralisi, Krzysztof Wilczyński, PCI,
open list:MEDIA DRIVERS FOR RENESAS - FCP, devicetree,
linux-kernel, Sergey Shtylyov, Thomas Petazzoni, Clement Leger,
Miquel Raynal
On Mon, Apr 25, 2022 at 7:45 PM Rob Herring <robh@kernel.org> wrote:
>
> On Fri, Apr 22, 2022 at 02:08:43PM +0200, Herve Codina wrote:
> > Convert Renesas PCI bridge bindings documentation to json-schema.
> >
> > Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> > ---
> > .../devicetree/bindings/pci/pci-rcar-gen2.txt | 84 ----------
> > .../bindings/pci/renesas,pci-rcar-gen2.yaml | 156 ++++++++++++++++++
> > 2 files changed, 156 insertions(+), 84 deletions(-)
> > delete mode 100644 Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
> > create mode 100644 Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
>
> > diff --git a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
> > new file mode 100644
> > index 000000000000..494eb975c146
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
> > @@ -0,0 +1,156 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pci/renesas,pci-rcar-gen2.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Renesas AHB to PCI bridge
> > +
> > +maintainers:
> > + - Marek Vasut <marek.vasut+renesas@gmail.com>
> > + - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > +
> > +description: |
> > + This is the bridge used internally to connect the USB controllers to the
> > + AHB. There is one bridge instance per USB port connected to the internal
> > + OHCI and EHCI controllers.
> > +
> > +allOf:
> > + - $ref: /schemas/pci/pci-bus.yaml#
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - items:
>
> Don't need oneOf with only 1 entry. Otherwise,
Nevermind, I see you need it in the next patch.
>
> Reviewed-by: Rob Herring <robh@kernel.org>
>
> > + - enum:
> > + - renesas,pci-r8a7742 # RZ/G1H
> > + - renesas,pci-r8a7743 # RZ/G1M
> > + - renesas,pci-r8a7744 # RZ/G1N
> > + - renesas,pci-r8a7745 # RZ/G1E
> > + - renesas,pci-r8a7790 # R-Car H2
> > + - renesas,pci-r8a7791 # R-Car M2-W
> > + - renesas,pci-r8a7793 # R-Car M2-N
> > + - renesas,pci-r8a7794 # R-Car E2
> > + - const: renesas,pci-rcar-gen2 # R-Car Gen2 and RZ/G1
> > +
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 1/8] dt-bindings: PCI: pci-rcar-gen2: Convert bindings to json-schema
2022-04-22 12:08 ` [PATCH v3 1/8] dt-bindings: PCI: pci-rcar-gen2: Convert bindings to json-schema Herve Codina
2022-04-26 0:45 ` Rob Herring
@ 2022-04-27 15:05 ` Geert Uytterhoeven
1 sibling, 0 replies; 32+ messages in thread
From: Geert Uytterhoeven @ 2022-04-27 15:05 UTC (permalink / raw)
To: Herve Codina
Cc: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
Krzysztof Kozlowski, Magnus Damm, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, linux-pci, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Sergey Shtylyov, Thomas Petazzoni,
Clement Leger, Miquel Raynal
On Fri, Apr 22, 2022 at 2:09 PM Herve Codina <herve.codina@bootlin.com> wrote:
> Convert Renesas PCI bridge bindings documentation to json-schema.
>
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 2/8] dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support for r9a06g032
2022-04-22 12:08 [PATCH v3 0/8] RZN1 USB Host support Herve Codina
2022-04-22 12:08 ` [PATCH v3 1/8] dt-bindings: PCI: pci-rcar-gen2: Convert bindings to json-schema Herve Codina
@ 2022-04-22 12:08 ` Herve Codina
2022-04-26 0:46 ` Rob Herring
2022-04-27 15:15 ` Geert Uytterhoeven
2022-04-22 12:08 ` [PATCH v3 3/8] PCI: rcar-gen2: Add RZ/N1 SOCs support Herve Codina
` (5 subsequent siblings)
7 siblings, 2 replies; 32+ messages in thread
From: Herve Codina @ 2022-04-22 12:08 UTC (permalink / raw)
To: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
Lorenzo Pieralisi, Krzysztof Wilczyński
Cc: Rob Herring, linux-pci, linux-renesas-soc, devicetree,
linux-kernel, Sergey Shtylyov, Thomas Petazzoni, Clement Leger,
Miquel Raynal, Herve Codina
Add internal PCI bridge support for the r9a06g032 SOC. The Renesas
RZ/N1D (R9A06G032) internal PCI bridge is compatible with the one
present in the R-Car Gen2 family.
Compared to the R-Car Gen2 family, it needs three clocks instead of
one.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
---
.../bindings/pci/renesas,pci-rcar-gen2.yaml | 43 ++++++++++++++++---
1 file changed, 37 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
index 494eb975c146..c29c46533e1b 100644
--- a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
+++ b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
@@ -32,6 +32,10 @@ properties:
- renesas,pci-r8a7793 # R-Car M2-N
- renesas,pci-r8a7794 # R-Car E2
- const: renesas,pci-rcar-gen2 # R-Car Gen2 and RZ/G1
+ - items:
+ - enum:
+ - renesas,pci-r9a06g032 # RZ/N1D
+ - const: renesas,pci-rzn1 # RZ/N1
reg:
items:
@@ -41,13 +45,9 @@ properties:
interrupts:
maxItems: 1
- clocks:
- items:
- - description: Device clock
+ clocks: true
- clock-names:
- items:
- - const: pclk
+ clock-names: true
resets:
maxItems: 1
@@ -113,6 +113,37 @@ required:
- "#size-cells"
- "#interrupt-cells"
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,pci-rzn1
+
+then:
+ properties:
+ clocks:
+ items:
+ - description: Internal bus clock (AHB) for HOST
+ - description: Internal bus clock (AHB) Power Management
+ - description: PCI clock for USB subsystem
+ clock-names:
+ items:
+ - const: hclk_usbh
+ - const: hclk_usbpm
+ - const: clk_pci_usb
+ required:
+ - clock-names
+
+else:
+ properties:
+ clocks:
+ items:
+ - description: Device clock
+ clock-names:
+ items:
+ - const: pclk
+
unevaluatedProperties: false
examples:
--
2.35.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH v3 2/8] dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support for r9a06g032
2022-04-22 12:08 ` [PATCH v3 2/8] dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support for r9a06g032 Herve Codina
@ 2022-04-26 0:46 ` Rob Herring
2022-04-27 15:15 ` Geert Uytterhoeven
1 sibling, 0 replies; 32+ messages in thread
From: Rob Herring @ 2022-04-26 0:46 UTC (permalink / raw)
To: Herve Codina
Cc: Rob Herring, Magnus Damm, Yoshihiro Shimoda, Lorenzo Pieralisi,
Krzysztof Wilczyński, linux-renesas-soc, Thomas Petazzoni,
Krzysztof Kozlowski, Sergey Shtylyov, Bjorn Helgaas, devicetree,
linux-kernel, Miquel Raynal, Clement Leger, Marek Vasut,
Geert Uytterhoeven, linux-pci
On Fri, 22 Apr 2022 14:08:44 +0200, Herve Codina wrote:
> Add internal PCI bridge support for the r9a06g032 SOC. The Renesas
> RZ/N1D (R9A06G032) internal PCI bridge is compatible with the one
> present in the R-Car Gen2 family.
> Compared to the R-Car Gen2 family, it needs three clocks instead of
> one.
>
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> ---
> .../bindings/pci/renesas,pci-rcar-gen2.yaml | 43 ++++++++++++++++---
> 1 file changed, 37 insertions(+), 6 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 2/8] dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support for r9a06g032
2022-04-22 12:08 ` [PATCH v3 2/8] dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support for r9a06g032 Herve Codina
2022-04-26 0:46 ` Rob Herring
@ 2022-04-27 15:15 ` Geert Uytterhoeven
2022-04-28 9:08 ` Herve Codina
1 sibling, 1 reply; 32+ messages in thread
From: Geert Uytterhoeven @ 2022-04-27 15:15 UTC (permalink / raw)
To: Herve Codina
Cc: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
Krzysztof Kozlowski, Magnus Damm, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, linux-pci, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Sergey Shtylyov, Thomas Petazzoni,
Clement Leger, Miquel Raynal
Hi Hervé,
On Fri, Apr 22, 2022 at 2:09 PM Herve Codina <herve.codina@bootlin.com> wrote:
> Add internal PCI bridge support for the r9a06g032 SOC. The Renesas
> RZ/N1D (R9A06G032) internal PCI bridge is compatible with the one
> present in the R-Car Gen2 family.
> Compared to the R-Car Gen2 family, it needs three clocks instead of
> one.
>
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Thanks for your patch!
> --- a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
> +++ b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
> @@ -113,6 +113,37 @@ required:
> - "#size-cells"
> - "#interrupt-cells"
>
> +if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - renesas,pci-rzn1
> +
> +then:
> + properties:
> + clocks:
> + items:
> + - description: Internal bus clock (AHB) for HOST
> + - description: Internal bus clock (AHB) Power Management
> + - description: PCI clock for USB subsystem
> + clock-names:
> + items:
> + - const: hclk_usbh
> + - const: hclk_usbpm
> + - const: clk_pci_usb
These are the provider names.
I think they should use the consumer names: usb_hclkh, usb_hclkpm,
and usb_pciclk.
The rest looks good to me.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 2/8] dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support for r9a06g032
2022-04-27 15:15 ` Geert Uytterhoeven
@ 2022-04-28 9:08 ` Herve Codina
0 siblings, 0 replies; 32+ messages in thread
From: Herve Codina @ 2022-04-28 9:08 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
Krzysztof Kozlowski, Magnus Damm, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, linux-pci, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Sergey Shtylyov, Thomas Petazzoni,
Clement Leger, Miquel Raynal
Hi Geert,
On Wed, 27 Apr 2022 17:15:15 +0200
Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> Hi Hervé,
>
> On Fri, Apr 22, 2022 at 2:09 PM Herve Codina <herve.codina@bootlin.com> wrote:
> > Add internal PCI bridge support for the r9a06g032 SOC. The Renesas
> > RZ/N1D (R9A06G032) internal PCI bridge is compatible with the one
> > present in the R-Car Gen2 family.
> > Compared to the R-Car Gen2 family, it needs three clocks instead of
> > one.
> >
> > Signed-off-by: Herve Codina <herve.codina@bootlin.com>
>
> Thanks for your patch!
>
> > --- a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
> > +++ b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
> > @@ -113,6 +113,37 @@ required:
> > - "#size-cells"
> > - "#interrupt-cells"
> >
> > +if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - renesas,pci-rzn1
> > +
> > +then:
> > + properties:
> > + clocks:
> > + items:
> > + - description: Internal bus clock (AHB) for HOST
> > + - description: Internal bus clock (AHB) Power Management
> > + - description: PCI clock for USB subsystem
> > + clock-names:
> > + items:
> > + - const: hclk_usbh
> > + - const: hclk_usbpm
> > + - const: clk_pci_usb
>
> These are the provider names.
> I think they should use the consumer names: usb_hclkh, usb_hclkpm,
> and usb_pciclk.
Yes, it makes sense.
I will changed in v4.
>
> The rest looks good to me.
Perfect.
Thanks for the review,
Hervé
--
Hervé Codina, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 3/8] PCI: rcar-gen2: Add RZ/N1 SOCs support
2022-04-22 12:08 [PATCH v3 0/8] RZN1 USB Host support Herve Codina
2022-04-22 12:08 ` [PATCH v3 1/8] dt-bindings: PCI: pci-rcar-gen2: Convert bindings to json-schema Herve Codina
2022-04-22 12:08 ` [PATCH v3 2/8] dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support for r9a06g032 Herve Codina
@ 2022-04-22 12:08 ` Herve Codina
2022-04-22 16:47 ` Bjorn Helgaas
2022-04-22 12:08 ` [PATCH v3 4/8] soc: renesas: rzn1: Select PM and PM_GENERIC_DOMAINS configs Herve Codina
` (4 subsequent siblings)
7 siblings, 1 reply; 32+ messages in thread
From: Herve Codina @ 2022-04-22 12:08 UTC (permalink / raw)
To: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
Lorenzo Pieralisi, Krzysztof Wilczyński
Cc: Rob Herring, linux-pci, linux-renesas-soc, devicetree,
linux-kernel, Sergey Shtylyov, Thomas Petazzoni, Clement Leger,
Miquel Raynal, Herve Codina
Add Renesas RZ/N1 SOCs family support to the Renesas R-Car
gen2 PCI bridge driver.
The Renesas RZ/N1 SOCs internal PCI bridge is comptible with
the one available in the R-Car Gen2 family.
Tested with the RZ/N1D (R9A06G032) SOC.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
---
drivers/pci/controller/pci-rcar-gen2.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/controller/pci-rcar-gen2.c b/drivers/pci/controller/pci-rcar-gen2.c
index 35804ea394fd..839695791757 100644
--- a/drivers/pci/controller/pci-rcar-gen2.c
+++ b/drivers/pci/controller/pci-rcar-gen2.c
@@ -328,6 +328,7 @@ static const struct of_device_id rcar_pci_of_match[] = {
{ .compatible = "renesas,pci-r8a7791", },
{ .compatible = "renesas,pci-r8a7794", },
{ .compatible = "renesas,pci-rcar-gen2", },
+ { .compatible = "renesas,pci-rzn1", },
{ },
};
--
2.35.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH v3 3/8] PCI: rcar-gen2: Add RZ/N1 SOCs support
2022-04-22 12:08 ` [PATCH v3 3/8] PCI: rcar-gen2: Add RZ/N1 SOCs support Herve Codina
@ 2022-04-22 16:47 ` Bjorn Helgaas
2022-04-28 9:19 ` Herve Codina
0 siblings, 1 reply; 32+ messages in thread
From: Bjorn Helgaas @ 2022-04-22 16:47 UTC (permalink / raw)
To: Herve Codina
Cc: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
linux-pci, linux-renesas-soc, devicetree, linux-kernel,
Sergey Shtylyov, Thomas Petazzoni, Clement Leger, Miquel Raynal
On Fri, Apr 22, 2022 at 02:08:45PM +0200, Herve Codina wrote:
> Add Renesas RZ/N1 SOCs family support to the Renesas R-Car
> gen2 PCI bridge driver.
> The Renesas RZ/N1 SOCs internal PCI bridge is comptible with
> the one available in the R-Car Gen2 family.
> Tested with the RZ/N1D (R9A06G032) SOC.
Nits (only address if you have some other reason to repost this
series):
- Subject claims this adds "support," which suggests that this adds
some piece of new functionality. But it adds no new
functionality, it merely adds a new compatible string. I would
say "Add RZ/N1 SOC compatible string"
- Add blank lines between paragraphs
- Rewrap paragraphs to fill 75 characters
- s/comptible/compatible/
- s/R-Car gen2/R-Car Gen2/ to write this consistently instead of
capitalizing "Gen2" sometimes but not others
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> ---
> drivers/pci/controller/pci-rcar-gen2.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/pci/controller/pci-rcar-gen2.c b/drivers/pci/controller/pci-rcar-gen2.c
> index 35804ea394fd..839695791757 100644
> --- a/drivers/pci/controller/pci-rcar-gen2.c
> +++ b/drivers/pci/controller/pci-rcar-gen2.c
> @@ -328,6 +328,7 @@ static const struct of_device_id rcar_pci_of_match[] = {
> { .compatible = "renesas,pci-r8a7791", },
> { .compatible = "renesas,pci-r8a7794", },
> { .compatible = "renesas,pci-rcar-gen2", },
> + { .compatible = "renesas,pci-rzn1", },
> { },
> };
>
> --
> 2.35.1
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 3/8] PCI: rcar-gen2: Add RZ/N1 SOCs support
2022-04-22 16:47 ` Bjorn Helgaas
@ 2022-04-28 9:19 ` Herve Codina
0 siblings, 0 replies; 32+ messages in thread
From: Herve Codina @ 2022-04-28 9:19 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
linux-pci, linux-renesas-soc, devicetree, linux-kernel,
Sergey Shtylyov, Thomas Petazzoni, Clement Leger, Miquel Raynal
Hi Bjorn,
On Fri, 22 Apr 2022 11:47:44 -0500
Bjorn Helgaas <helgaas@kernel.org> wrote:
> On Fri, Apr 22, 2022 at 02:08:45PM +0200, Herve Codina wrote:
> > Add Renesas RZ/N1 SOCs family support to the Renesas R-Car
> > gen2 PCI bridge driver.
> > The Renesas RZ/N1 SOCs internal PCI bridge is comptible with
> > the one available in the R-Car Gen2 family.
> > Tested with the RZ/N1D (R9A06G032) SOC.
>
> Nits (only address if you have some other reason to repost this
> series):
>
> - Subject claims this adds "support," which suggests that this adds
> some piece of new functionality. But it adds no new
> functionality, it merely adds a new compatible string. I would
> say "Add RZ/N1 SOC compatible string"
>
> - Add blank lines between paragraphs
>
> - Rewrap paragraphs to fill 75 characters
>
> - s/comptible/compatible/
>
> - s/R-Car gen2/R-Car Gen2/ to write this consistently instead of
> capitalizing "Gen2" sometimes but not others
I plan a v4 and so, I will take these points into account.
Thanks for the review.
Regards,
Hervé
--
Hervé Codina, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 4/8] soc: renesas: rzn1: Select PM and PM_GENERIC_DOMAINS configs
2022-04-22 12:08 [PATCH v3 0/8] RZN1 USB Host support Herve Codina
` (2 preceding siblings ...)
2022-04-22 12:08 ` [PATCH v3 3/8] PCI: rcar-gen2: Add RZ/N1 SOCs support Herve Codina
@ 2022-04-22 12:08 ` Herve Codina
2022-04-27 14:58 ` Geert Uytterhoeven
2022-04-22 12:08 ` [PATCH v3 5/8] ARM: dts: r9a06g032: Add missing '#power-domain-cells' Herve Codina
` (3 subsequent siblings)
7 siblings, 1 reply; 32+ messages in thread
From: Herve Codina @ 2022-04-22 12:08 UTC (permalink / raw)
To: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
Lorenzo Pieralisi, Krzysztof Wilczyński
Cc: Rob Herring, linux-pci, linux-renesas-soc, devicetree,
linux-kernel, Sergey Shtylyov, Thomas Petazzoni, Clement Leger,
Miquel Raynal, Herve Codina
PM and PM_GENERIC_DOMAINS configs are required for RZ/N1 SOCs.
Without these configs, the clocks used by the PCI bridge are not
enabled and so accessing the devices leads to a kernel crash:
[ 0.832958] Unhandled fault: external abort on non-linefetch (0x1008) at 0x90b5f848
Select PM and PM_GENERIC_DOMAINS for ARCH_RZN1
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
---
drivers/soc/renesas/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index fdc99a05a7e0..15fff5632167 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -47,6 +47,8 @@ config ARCH_RZG2L
config ARCH_RZN1
bool
+ select PM
+ select PM_GENERIC_DOMAINS
select ARM_AMBA
if ARM && ARCH_RENESAS
--
2.35.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH v3 4/8] soc: renesas: rzn1: Select PM and PM_GENERIC_DOMAINS configs
2022-04-22 12:08 ` [PATCH v3 4/8] soc: renesas: rzn1: Select PM and PM_GENERIC_DOMAINS configs Herve Codina
@ 2022-04-27 14:58 ` Geert Uytterhoeven
2022-04-28 9:15 ` Herve Codina
0 siblings, 1 reply; 32+ messages in thread
From: Geert Uytterhoeven @ 2022-04-27 14:58 UTC (permalink / raw)
To: Herve Codina
Cc: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
linux-pci, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Sergey Shtylyov, Thomas Petazzoni,
Clement Leger, Miquel Raynal
On Fri, Apr 22, 2022 at 2:09 PM Herve Codina <herve.codina@bootlin.com> wrote:
> PM and PM_GENERIC_DOMAINS configs are required for RZ/N1 SOCs.
> Without these configs, the clocks used by the PCI bridge are not
> enabled and so accessing the devices leads to a kernel crash:
> [ 0.832958] Unhandled fault: external abort on non-linefetch (0x1008) at 0x90b5f848
>
> Select PM and PM_GENERIC_DOMAINS for ARCH_RZN1
>
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.19.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 4/8] soc: renesas: rzn1: Select PM and PM_GENERIC_DOMAINS configs
2022-04-27 14:58 ` Geert Uytterhoeven
@ 2022-04-28 9:15 ` Herve Codina
2022-04-28 9:22 ` Geert Uytterhoeven
0 siblings, 1 reply; 32+ messages in thread
From: Herve Codina @ 2022-04-28 9:15 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
linux-pci, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Sergey Shtylyov, Thomas Petazzoni,
Clement Leger, Miquel Raynal
Hi Geert,
On Wed, 27 Apr 2022 16:58:07 +0200
Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Fri, Apr 22, 2022 at 2:09 PM Herve Codina <herve.codina@bootlin.com> wrote:
> > PM and PM_GENERIC_DOMAINS configs are required for RZ/N1 SOCs.
> > Without these configs, the clocks used by the PCI bridge are not
> > enabled and so accessing the devices leads to a kernel crash:
> > [ 0.832958] Unhandled fault: external abort on non-linefetch (0x1008) at 0x90b5f848
> >
> > Select PM and PM_GENERIC_DOMAINS for ARCH_RZN1
> >
> > Signed-off-by: Herve Codina <herve.codina@bootlin.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> i.e. will queue in renesas-devel for v5.19.
>
I plan to send a v4 of this series.
As this patch (4/8) and the following one (5/8) will be
queued for v5.19, I plan to remove them from the v4 version
of the series.
Is that ok for you or do you prefer to still have them
in v4 ?
Regards,
Hervé
--
Hervé Codina, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 4/8] soc: renesas: rzn1: Select PM and PM_GENERIC_DOMAINS configs
2022-04-28 9:15 ` Herve Codina
@ 2022-04-28 9:22 ` Geert Uytterhoeven
2022-04-28 9:25 ` Herve Codina
0 siblings, 1 reply; 32+ messages in thread
From: Geert Uytterhoeven @ 2022-04-28 9:22 UTC (permalink / raw)
To: Herve Codina
Cc: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
linux-pci, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Sergey Shtylyov, Thomas Petazzoni,
Clement Leger, Miquel Raynal
Hi Hervé,
On Thu, Apr 28, 2022 at 11:15 AM Herve Codina <herve.codina@bootlin.com> wrote:
> On Wed, 27 Apr 2022 16:58:07 +0200
> Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Fri, Apr 22, 2022 at 2:09 PM Herve Codina <herve.codina@bootlin.com> wrote:
> > > PM and PM_GENERIC_DOMAINS configs are required for RZ/N1 SOCs.
> > > Without these configs, the clocks used by the PCI bridge are not
> > > enabled and so accessing the devices leads to a kernel crash:
> > > [ 0.832958] Unhandled fault: external abort on non-linefetch (0x1008) at 0x90b5f848
> > >
> > > Select PM and PM_GENERIC_DOMAINS for ARCH_RZN1
> > >
> > > Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> >
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > i.e. will queue in renesas-devel for v5.19.
>
> I plan to send a v4 of this series.
>
> As this patch (4/8) and the following one (5/8) will be
> queued for v5.19, I plan to remove them from the v4 version
> of the series.
>
> Is that ok for you or do you prefer to still have them
> in v4 ?
As these two patches are not strictly related to adding PCI support,
but they are dependencies, I will queue them separately. Hence you
do not need to include them in v5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 4/8] soc: renesas: rzn1: Select PM and PM_GENERIC_DOMAINS configs
2022-04-28 9:22 ` Geert Uytterhoeven
@ 2022-04-28 9:25 ` Herve Codina
0 siblings, 0 replies; 32+ messages in thread
From: Herve Codina @ 2022-04-28 9:25 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
linux-pci, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Sergey Shtylyov, Thomas Petazzoni,
Clement Leger, Miquel Raynal
Hi Geert,
On Thu, 28 Apr 2022 11:22:35 +0200
Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> Hi Hervé,
>
> On Thu, Apr 28, 2022 at 11:15 AM Herve Codina <herve.codina@bootlin.com> wrote:
> > On Wed, 27 Apr 2022 16:58:07 +0200
> > Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > On Fri, Apr 22, 2022 at 2:09 PM Herve Codina <herve.codina@bootlin.com> wrote:
> > > > PM and PM_GENERIC_DOMAINS configs are required for RZ/N1 SOCs.
> > > > Without these configs, the clocks used by the PCI bridge are not
> > > > enabled and so accessing the devices leads to a kernel crash:
> > > > [ 0.832958] Unhandled fault: external abort on non-linefetch (0x1008) at 0x90b5f848
> > > >
> > > > Select PM and PM_GENERIC_DOMAINS for ARCH_RZN1
> > > >
> > > > Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> > >
> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > i.e. will queue in renesas-devel for v5.19.
> >
> > I plan to send a v4 of this series.
> >
> > As this patch (4/8) and the following one (5/8) will be
> > queued for v5.19, I plan to remove them from the v4 version
> > of the series.
> >
> > Is that ok for you or do you prefer to still have them
> > in v4 ?
>
> As these two patches are not strictly related to adding PCI support,
> but they are dependencies, I will queue them separately. Hence you
> do not need to include them in v5.
Perfect.
Thanks,
Hervé
--
Hervé Codina, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 5/8] ARM: dts: r9a06g032: Add missing '#power-domain-cells'
2022-04-22 12:08 [PATCH v3 0/8] RZN1 USB Host support Herve Codina
` (3 preceding siblings ...)
2022-04-22 12:08 ` [PATCH v3 4/8] soc: renesas: rzn1: Select PM and PM_GENERIC_DOMAINS configs Herve Codina
@ 2022-04-22 12:08 ` Herve Codina
2022-04-27 14:59 ` Geert Uytterhoeven
2022-04-22 12:08 ` [PATCH v3 6/8] ARM: dts: r9a06g032: Add internal PCI bridge node Herve Codina
` (2 subsequent siblings)
7 siblings, 1 reply; 32+ messages in thread
From: Herve Codina @ 2022-04-22 12:08 UTC (permalink / raw)
To: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
Lorenzo Pieralisi, Krzysztof Wilczyński
Cc: Rob Herring, linux-pci, linux-renesas-soc, devicetree,
linux-kernel, Sergey Shtylyov, Thomas Petazzoni, Clement Leger,
Miquel Raynal, Herve Codina
Without '#power-domain-cells' property, power-domains cannot
be used. This property is noted required in the device-tree
binding.
Add '#power-domain-cells' as needed.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
---
arch/arm/boot/dts/r9a06g032.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index 636a6ab31c58..20286433d3c6 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -87,6 +87,7 @@ sysctrl: system-controller@4000c000 {
reg = <0x4000c000 0x1000>;
status = "okay";
#clock-cells = <1>;
+ #power-domain-cells = <0>;
clocks = <&ext_mclk>, <&ext_rtc_clk>,
<&ext_jtag_clk>, <&ext_rgmii_ref>;
--
2.35.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH v3 5/8] ARM: dts: r9a06g032: Add missing '#power-domain-cells'
2022-04-22 12:08 ` [PATCH v3 5/8] ARM: dts: r9a06g032: Add missing '#power-domain-cells' Herve Codina
@ 2022-04-27 14:59 ` Geert Uytterhoeven
0 siblings, 0 replies; 32+ messages in thread
From: Geert Uytterhoeven @ 2022-04-27 14:59 UTC (permalink / raw)
To: Herve Codina
Cc: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
Krzysztof Kozlowski, Magnus Damm, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, linux-pci, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Sergey Shtylyov, Thomas Petazzoni,
Clement Leger, Miquel Raynal
On Fri, Apr 22, 2022 at 2:09 PM Herve Codina <herve.codina@bootlin.com> wrote:
> Without '#power-domain-cells' property, power-domains cannot
> be used. This property is noted required in the device-tree
> binding.
>
> Add '#power-domain-cells' as needed.
>
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.19.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 6/8] ARM: dts: r9a06g032: Add internal PCI bridge node
2022-04-22 12:08 [PATCH v3 0/8] RZN1 USB Host support Herve Codina
` (4 preceding siblings ...)
2022-04-22 12:08 ` [PATCH v3 5/8] ARM: dts: r9a06g032: Add missing '#power-domain-cells' Herve Codina
@ 2022-04-22 12:08 ` Herve Codina
2022-04-28 9:49 ` Geert Uytterhoeven
2022-04-22 12:08 ` [PATCH v3 7/8] ARM: dts: r9a06g032: Add USB PHY DT support Herve Codina
2022-04-22 12:08 ` [PATCH v3 8/8] ARM: dts: r9a06g032: Link the PCI USB devices to the USB PHY Herve Codina
7 siblings, 1 reply; 32+ messages in thread
From: Herve Codina @ 2022-04-22 12:08 UTC (permalink / raw)
To: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
Lorenzo Pieralisi, Krzysztof Wilczyński
Cc: Rob Herring, linux-pci, linux-renesas-soc, devicetree,
linux-kernel, Sergey Shtylyov, Thomas Petazzoni, Clement Leger,
Miquel Raynal, Herve Codina
Add the device node for the r9a06g032 internal PCI bridge device.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
---
arch/arm/boot/dts/r9a06g032.dtsi | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index 20286433d3c6..33581f0c55c4 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -212,6 +212,35 @@ gic: interrupt-controller@44101000 {
interrupts =
<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
};
+
+ pci_usb: pci@40030000 {
+ compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1";
+ device_type = "pci";
+ clocks = <&sysctrl R9A06G032_HCLK_USBH>,
+ <&sysctrl R9A06G032_HCLK_USBPM>,
+ <&sysctrl R9A06G032_CLK_PCI_USB>;
+ clock-names = "hclk_usbh", "hclk_usbpm", "clk_pci_usb";
+ power-domains = <&sysctrl>;
+ reg = <0x40030000 0xc00>,
+ <0x40020000 0x1100>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+
+ bus-range = <0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x02000000 0 0x40020000 0x40020000 0 0x00010000>;
+ /* Should map all possible DDR as inbound ranges, but
+ * the IP only supports a 256MB, 512MB, or 1GB window.
+ * flags, PCI addr (64-bit), CPU addr, PCI size (64-bit)
+ */
+ dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>;
+ interrupt-map-mask = <0xf800 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
+ 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
+ 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
timer {
--
2.35.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH v3 6/8] ARM: dts: r9a06g032: Add internal PCI bridge node
2022-04-22 12:08 ` [PATCH v3 6/8] ARM: dts: r9a06g032: Add internal PCI bridge node Herve Codina
@ 2022-04-28 9:49 ` Geert Uytterhoeven
2022-04-28 9:50 ` Geert Uytterhoeven
2022-04-28 10:07 ` Herve Codina
0 siblings, 2 replies; 32+ messages in thread
From: Geert Uytterhoeven @ 2022-04-28 9:49 UTC (permalink / raw)
To: Herve Codina
Cc: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
Krzysztof Kozlowski, Magnus Damm, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, linux-pci, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Sergey Shtylyov, Thomas Petazzoni,
Clement Leger, Miquel Raynal
Hi Hervé
On Fri, Apr 22, 2022 at 2:09 PM Herve Codina <herve.codina@bootlin.com> wrote:
> Add the device node for the r9a06g032 internal PCI bridge device.
>
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Thanks for your patch!
> --- a/arch/arm/boot/dts/r9a06g032.dtsi
> +++ b/arch/arm/boot/dts/r9a06g032.dtsi
> @@ -212,6 +212,35 @@ gic: interrupt-controller@44101000 {
> interrupts =
> <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
> };
> +
> + pci_usb: pci@40030000 {
> + compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1";
> + device_type = "pci";
> + clocks = <&sysctrl R9A06G032_HCLK_USBH>,
> + <&sysctrl R9A06G032_HCLK_USBPM>,
> + <&sysctrl R9A06G032_CLK_PCI_USB>;
> + clock-names = "hclk_usbh", "hclk_usbpm", "clk_pci_usb";
The clock names need an update, cfr. my comment on the bindings.
The rest LGTM, so with the above fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 6/8] ARM: dts: r9a06g032: Add internal PCI bridge node
2022-04-28 9:49 ` Geert Uytterhoeven
@ 2022-04-28 9:50 ` Geert Uytterhoeven
2022-04-28 10:08 ` Herve Codina
2022-04-28 10:07 ` Herve Codina
1 sibling, 1 reply; 32+ messages in thread
From: Geert Uytterhoeven @ 2022-04-28 9:50 UTC (permalink / raw)
To: Herve Codina
Cc: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
Krzysztof Kozlowski, Magnus Damm, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, linux-pci, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Sergey Shtylyov, Thomas Petazzoni,
Clement Leger, Miquel Raynal
Hi Hervé,
On Thu, Apr 28, 2022 at 11:49 AM Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
> > --- a/arch/arm/boot/dts/r9a06g032.dtsi
> > +++ b/arch/arm/boot/dts/r9a06g032.dtsi
> > @@ -212,6 +212,35 @@ gic: interrupt-controller@44101000 {
> > interrupts =
> > <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
> > };
> > +
> > + pci_usb: pci@40030000 {
Please preserve sort order (by unit address).
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 6/8] ARM: dts: r9a06g032: Add internal PCI bridge node
2022-04-28 9:50 ` Geert Uytterhoeven
@ 2022-04-28 10:08 ` Herve Codina
0 siblings, 0 replies; 32+ messages in thread
From: Herve Codina @ 2022-04-28 10:08 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
Krzysztof Kozlowski, Magnus Damm, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, linux-pci, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Sergey Shtylyov, Thomas Petazzoni,
Clement Leger, Miquel Raynal
Hi Geert,
On Thu, 28 Apr 2022 11:50:21 +0200
Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> Hi Hervé,
>
> On Thu, Apr 28, 2022 at 11:49 AM Geert Uytterhoeven
> <geert@linux-m68k.org> wrote:
> > > --- a/arch/arm/boot/dts/r9a06g032.dtsi
> > > +++ b/arch/arm/boot/dts/r9a06g032.dtsi
> > > @@ -212,6 +212,35 @@ gic: interrupt-controller@44101000 {
> > > interrupts =
> > > <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
> > > };
> > > +
> > > + pci_usb: pci@40030000 {
>
> Please preserve sort order (by unit address).
Ok, will be done in v4.
Thanks,
Hervé
--
Hervé Codina, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 6/8] ARM: dts: r9a06g032: Add internal PCI bridge node
2022-04-28 9:49 ` Geert Uytterhoeven
2022-04-28 9:50 ` Geert Uytterhoeven
@ 2022-04-28 10:07 ` Herve Codina
1 sibling, 0 replies; 32+ messages in thread
From: Herve Codina @ 2022-04-28 10:07 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
Krzysztof Kozlowski, Magnus Damm, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, linux-pci, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Sergey Shtylyov, Thomas Petazzoni,
Clement Leger, Miquel Raynal
Hi Geert,
On Thu, 28 Apr 2022 11:49:28 +0200
Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> Hi Hervé
>
> On Fri, Apr 22, 2022 at 2:09 PM Herve Codina <herve.codina@bootlin.com> wrote:
> > Add the device node for the r9a06g032 internal PCI bridge device.
> >
> > Signed-off-by: Herve Codina <herve.codina@bootlin.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm/boot/dts/r9a06g032.dtsi
> > +++ b/arch/arm/boot/dts/r9a06g032.dtsi
> > @@ -212,6 +212,35 @@ gic: interrupt-controller@44101000 {
> > interrupts =
> > <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
> > };
> > +
> > + pci_usb: pci@40030000 {
> > + compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1";
> > + device_type = "pci";
> > + clocks = <&sysctrl R9A06G032_HCLK_USBH>,
> > + <&sysctrl R9A06G032_HCLK_USBPM>,
> > + <&sysctrl R9A06G032_CLK_PCI_USB>;
> > + clock-names = "hclk_usbh", "hclk_usbpm", "clk_pci_usb";
>
> The clock names need an update, cfr. my comment on the bindings.
Sure.
>
> The rest LGTM, so with the above fixed:
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
Thanks for the review.
Regards,
Hervé
--
Hervé Codina, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 7/8] ARM: dts: r9a06g032: Add USB PHY DT support
2022-04-22 12:08 [PATCH v3 0/8] RZN1 USB Host support Herve Codina
` (5 preceding siblings ...)
2022-04-22 12:08 ` [PATCH v3 6/8] ARM: dts: r9a06g032: Add internal PCI bridge node Herve Codina
@ 2022-04-22 12:08 ` Herve Codina
2022-04-23 9:09 ` Sergey Shtylyov
2022-04-28 9:51 ` Geert Uytterhoeven
2022-04-22 12:08 ` [PATCH v3 8/8] ARM: dts: r9a06g032: Link the PCI USB devices to the USB PHY Herve Codina
7 siblings, 2 replies; 32+ messages in thread
From: Herve Codina @ 2022-04-22 12:08 UTC (permalink / raw)
To: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
Lorenzo Pieralisi, Krzysztof Wilczyński
Cc: Rob Herring, linux-pci, linux-renesas-soc, devicetree,
linux-kernel, Sergey Shtylyov, Thomas Petazzoni, Clement Leger,
Miquel Raynal, Herve Codina
Define the r9a06g032 generic part of the USB PHY device node.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
---
arch/arm/boot/dts/r9a06g032.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index 33581f0c55c4..58af07eb75c9 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -59,6 +59,12 @@ ext_rtc_clk: extrtcclk {
clock-frequency = <0>;
};
+ usbphy: usbphy {
+ #phy-cells = <0>;
+ compatible = "usb-nop-xceiv";
+ status = "disabled";
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
--
2.35.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH v3 7/8] ARM: dts: r9a06g032: Add USB PHY DT support
2022-04-22 12:08 ` [PATCH v3 7/8] ARM: dts: r9a06g032: Add USB PHY DT support Herve Codina
@ 2022-04-23 9:09 ` Sergey Shtylyov
2022-04-23 16:41 ` Sergey Shtylyov
2022-04-28 9:51 ` Geert Uytterhoeven
1 sibling, 1 reply; 32+ messages in thread
From: Sergey Shtylyov @ 2022-04-23 9:09 UTC (permalink / raw)
To: Herve Codina, Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas,
Rob Herring, Krzysztof Kozlowski, Geert Uytterhoeven,
Magnus Damm, Lorenzo Pieralisi, Krzysztof Wilczyński
Cc: Rob Herring, linux-pci, linux-renesas-soc, devicetree,
linux-kernel, Sergey Shtylyov, Thomas Petazzoni, Clement Leger,
Miquel Raynal
Hello!
On 4/22/22 3:08 PM, Herve Codina wrote:
> Define the r9a06g032 generic part of the USB PHY device node.
>
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> ---
> arch/arm/boot/dts/r9a06g032.dtsi | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
> index 33581f0c55c4..58af07eb75c9 100644
> --- a/arch/arm/boot/dts/r9a06g032.dtsi
> +++ b/arch/arm/boot/dts/r9a06g032.dtsi
> @@ -59,6 +59,12 @@ ext_rtc_clk: extrtcclk {
> clock-frequency = <0>;
> };
>
> + usbphy: usbphy {
I think the node name should be "usb-phy"...
[...]
MBR, Sergey
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 7/8] ARM: dts: r9a06g032: Add USB PHY DT support
2022-04-23 9:09 ` Sergey Shtylyov
@ 2022-04-23 16:41 ` Sergey Shtylyov
2022-04-28 9:23 ` Herve Codina
0 siblings, 1 reply; 32+ messages in thread
From: Sergey Shtylyov @ 2022-04-23 16:41 UTC (permalink / raw)
To: Herve Codina, Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas,
Rob Herring, Krzysztof Kozlowski, Geert Uytterhoeven,
Magnus Damm, Lorenzo Pieralisi, Krzysztof Wilczyński
Cc: Rob Herring, linux-pci, linux-renesas-soc, devicetree,
linux-kernel, Thomas Petazzoni, Clement Leger, Miquel Raynal
On 4/23/22 12:09 PM, Sergey Shtylyov wrote:
[...]
>> Define the r9a06g032 generic part of the USB PHY device node.
>>
>> Signed-off-by: Herve Codina <herve.codina@bootlin.com>
>> ---
>> arch/arm/boot/dts/r9a06g032.dtsi | 6 ++++++
>> 1 file changed, 6 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
>> index 33581f0c55c4..58af07eb75c9 100644
>> --- a/arch/arm/boot/dts/r9a06g032.dtsi
>> +++ b/arch/arm/boot/dts/r9a06g032.dtsi
>> @@ -59,6 +59,12 @@ ext_rtc_clk: extrtcclk {
>> clock-frequency = <0>;
>> };
>>
>> + usbphy: usbphy {
>
> I think the node name should be "usb-phy"...
It's not my thinking alone, the DT spec documents "usb-phy" in section 2.2.2. :-)
> [...]
MBR, Sergey
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 7/8] ARM: dts: r9a06g032: Add USB PHY DT support
2022-04-23 16:41 ` Sergey Shtylyov
@ 2022-04-28 9:23 ` Herve Codina
0 siblings, 0 replies; 32+ messages in thread
From: Herve Codina @ 2022-04-28 9:23 UTC (permalink / raw)
To: Sergey Shtylyov
Cc: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
linux-pci, linux-renesas-soc, devicetree, linux-kernel,
Thomas Petazzoni, Clement Leger, Miquel Raynal
Hi Sergey,
On Sat, 23 Apr 2022 19:41:09 +0300
Sergey Shtylyov <s.shtylyov@omp.ru> wrote:
> On 4/23/22 12:09 PM, Sergey Shtylyov wrote:
>
> [...]
> >> Define the r9a06g032 generic part of the USB PHY device node.
> >>
> >> Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> >> ---
> >> arch/arm/boot/dts/r9a06g032.dtsi | 6 ++++++
> >> 1 file changed, 6 insertions(+)
> >>
> >> diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
> >> index 33581f0c55c4..58af07eb75c9 100644
> >> --- a/arch/arm/boot/dts/r9a06g032.dtsi
> >> +++ b/arch/arm/boot/dts/r9a06g032.dtsi
> >> @@ -59,6 +59,12 @@ ext_rtc_clk: extrtcclk {
> >> clock-frequency = <0>;
> >> };
> >>
> >> + usbphy: usbphy {
> >
> > I think the node name should be "usb-phy"...
>
> It's not my thinking alone, the DT spec documents "usb-phy" in section 2.2.2. :-)
Will be changed in v4.
Thanks for pointing this.
Regards,
Hervé
--
Hervé Codina, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 7/8] ARM: dts: r9a06g032: Add USB PHY DT support
2022-04-22 12:08 ` [PATCH v3 7/8] ARM: dts: r9a06g032: Add USB PHY DT support Herve Codina
2022-04-23 9:09 ` Sergey Shtylyov
@ 2022-04-28 9:51 ` Geert Uytterhoeven
2022-04-28 10:30 ` Herve Codina
1 sibling, 1 reply; 32+ messages in thread
From: Geert Uytterhoeven @ 2022-04-28 9:51 UTC (permalink / raw)
To: Herve Codina
Cc: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
linux-pci, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Sergey Shtylyov, Thomas Petazzoni,
Clement Leger, Miquel Raynal
Hi Hervé,
On Fri, Apr 22, 2022 at 2:09 PM Herve Codina <herve.codina@bootlin.com> wrote:
> Define the r9a06g032 generic part of the USB PHY device node.
>
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Thanks for your patch!
> --- a/arch/arm/boot/dts/r9a06g032.dtsi
> +++ b/arch/arm/boot/dts/r9a06g032.dtsi
> @@ -59,6 +59,12 @@ ext_rtc_clk: extrtcclk {
> clock-frequency = <0>;
> };
>
> + usbphy: usbphy {
Please preserve sort order (by node name).
> + #phy-cells = <0>;
> + compatible = "usb-nop-xceiv";
> + status = "disabled";
> + };
> +
> soc {
> compatible = "simple-bus";
> #address-cells = <1>;
The rest LGTM, so with the above fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 7/8] ARM: dts: r9a06g032: Add USB PHY DT support
2022-04-28 9:51 ` Geert Uytterhoeven
@ 2022-04-28 10:30 ` Herve Codina
0 siblings, 0 replies; 32+ messages in thread
From: Herve Codina @ 2022-04-28 10:30 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
linux-pci, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Sergey Shtylyov, Thomas Petazzoni,
Clement Leger, Miquel Raynal
Hi Geert,
On Thu, 28 Apr 2022 11:51:44 +0200
Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> Hi Hervé,
>
> On Fri, Apr 22, 2022 at 2:09 PM Herve Codina <herve.codina@bootlin.com> wrote:
> > Define the r9a06g032 generic part of the USB PHY device node.
> >
> > Signed-off-by: Herve Codina <herve.codina@bootlin.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm/boot/dts/r9a06g032.dtsi
> > +++ b/arch/arm/boot/dts/r9a06g032.dtsi
> > @@ -59,6 +59,12 @@ ext_rtc_clk: extrtcclk {
> > clock-frequency = <0>;
> > };
> >
> > + usbphy: usbphy {
>
> Please preserve sort order (by node name).
Ok, will be done.
>
> > + #phy-cells = <0>;
> > + compatible = "usb-nop-xceiv";
> > + status = "disabled";
> > + };
> > +
> > soc {
> > compatible = "simple-bus";
> > #address-cells = <1>;
>
> The rest LGTM, so with the above fixed:
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
Regards,
Hervé
--
Hervé Codina, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 8/8] ARM: dts: r9a06g032: Link the PCI USB devices to the USB PHY
2022-04-22 12:08 [PATCH v3 0/8] RZN1 USB Host support Herve Codina
` (6 preceding siblings ...)
2022-04-22 12:08 ` [PATCH v3 7/8] ARM: dts: r9a06g032: Add USB PHY DT support Herve Codina
@ 2022-04-22 12:08 ` Herve Codina
2022-04-28 9:52 ` Geert Uytterhoeven
7 siblings, 1 reply; 32+ messages in thread
From: Herve Codina @ 2022-04-22 12:08 UTC (permalink / raw)
To: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
Lorenzo Pieralisi, Krzysztof Wilczyński
Cc: Rob Herring, linux-pci, linux-renesas-soc, devicetree,
linux-kernel, Sergey Shtylyov, Thomas Petazzoni, Clement Leger,
Miquel Raynal, Herve Codina
Describe the PCI USB devices that are behind the PCI bridge, adding
necessary links to the USB PHY device.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
---
arch/arm/boot/dts/r9a06g032.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index 58af07eb75c9..8dc50c09ac65 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -246,6 +246,18 @@ pci_usb: pci@40030000 {
interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+
+ usb@1,0 {
+ reg = <0x800 0 0 0 0>;
+ phys = <&usbphy>;
+ phy-names = "usb";
+ };
+
+ usb@2,0 {
+ reg = <0x1000 0 0 0 0>;
+ phys = <&usbphy>;
+ phy-names = "usb";
+ };
};
};
--
2.35.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH v3 8/8] ARM: dts: r9a06g032: Link the PCI USB devices to the USB PHY
2022-04-22 12:08 ` [PATCH v3 8/8] ARM: dts: r9a06g032: Link the PCI USB devices to the USB PHY Herve Codina
@ 2022-04-28 9:52 ` Geert Uytterhoeven
0 siblings, 0 replies; 32+ messages in thread
From: Geert Uytterhoeven @ 2022-04-28 9:52 UTC (permalink / raw)
To: Herve Codina
Cc: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
linux-pci, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Sergey Shtylyov, Thomas Petazzoni,
Clement Leger, Miquel Raynal
On Fri, Apr 22, 2022 at 2:09 PM Herve Codina <herve.codina@bootlin.com> wrote:
> Describe the PCI USB devices that are behind the PCI bridge, adding
> necessary links to the USB PHY device.
>
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>
LGTM, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 32+ messages in thread