From: Catalin Marinas <catalin.marinas@arm.com>
To: Takao Indoh <indou.takao@jp.fujitsu.com>
Cc: Jonathan Corbet <corbet@lwn.net>,
Will Deacon <will.deacon@arm.com>,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
QI Fuli <qi.fuli@fujitsu.com>,
Takao Indoh <indou.takao@fujitsu.com>
Subject: Re: [PATCH 1/2] arm64: mm: Restore mm_cpumask (revert commit 38d96287504a ("arm64: mm: kill mm_cpumask usage"))
Date: Tue, 23 Jul 2019 12:55:16 +0100 [thread overview]
Message-ID: <20190723115516.GA16928@arrakis.emea.arm.com> (raw)
In-Reply-To: <20190617143255.10462-2-indou.takao@jp.fujitsu.com>
Hi,
I know Will is on the case but just expressing some thoughts of my own.
On Mon, Jun 17, 2019 at 11:32:54PM +0900, Takao Indoh wrote:
> From: Takao Indoh <indou.takao@fujitsu.com>
>
> mm_cpumask was deleted by the commit 38d96287504a ("arm64: mm: kill
> mm_cpumask usage") because it was not used at that time. Now this is needed
> to find appropriate CPUs for TLB flush, so this patch reverts this commit.
>
> Signed-off-by: QI Fuli <qi.fuli@fujitsu.com>
> Signed-off-by: Takao Indoh <indou.takao@fujitsu.com>
> ---
> arch/arm64/include/asm/mmu_context.h | 7 ++++++-
> arch/arm64/kernel/smp.c | 6 ++++++
> arch/arm64/mm/context.c | 2 ++
> 3 files changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h
> index 2da3e478fd8f..21ef11590bcb 100644
> --- a/arch/arm64/include/asm/mmu_context.h
> +++ b/arch/arm64/include/asm/mmu_context.h
> @@ -241,8 +241,13 @@ static inline void
> switch_mm(struct mm_struct *prev, struct mm_struct *next,
> struct task_struct *tsk)
> {
> - if (prev != next)
> + unsigned int cpu = smp_processor_id();
> +
> + if (prev != next) {
> __switch_mm(next);
> + cpumask_clear_cpu(cpu, mm_cpumask(prev));
> + local_flush_tlb_mm(prev);
> + }
That's not actually a revert as we've never flushed the TLBs on the
switch_mm() path. Also, this flush is not sufficient on a CnP capable
CPU since another thread of the same CPU could have the prev TTBR0_EL1
value set and loading the TLB back.
--
Catalin
next prev parent reply other threads:[~2019-07-23 11:55 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-17 14:32 [PATCH 0/2] arm64: Introduce boot parameter to disable TLB flush instruction within the same inner shareable domain Takao Indoh
2019-06-17 14:32 ` [PATCH 1/2] arm64: mm: Restore mm_cpumask (revert commit 38d96287504a ("arm64: mm: kill mm_cpumask usage")) Takao Indoh
2019-07-23 11:55 ` Catalin Marinas [this message]
2019-06-17 14:32 ` [PATCH 2/2] arm64: tlb: Add boot parameter to disable TLB flush within the same inner shareable domain Takao Indoh
2019-07-23 12:11 ` Catalin Marinas
2019-06-17 17:03 ` [PATCH 0/2] arm64: Introduce boot parameter to disable TLB flush instruction " Will Deacon
2019-06-24 10:34 ` qi.fuli
2019-06-27 10:27 ` Will Deacon
2019-07-03 2:45 ` qi.fuli
2019-07-09 0:25 ` Jon Masters
2019-07-09 0:29 ` Jon Masters
2019-07-09 8:03 ` Will Deacon
2019-07-09 8:07 ` Will Deacon
2019-11-01 9:56 ` qi.fuli
2019-11-01 17:28 ` Will Deacon
2019-11-26 14:26 ` Matthias Brugger
2019-11-26 14:36 ` Will Deacon
2019-12-01 16:02 ` Jon Masters
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