From: Peter Zijlstra <peterz@infradead.org>
To: Dietmar Eggemann <dietmar.eggemann@arm.com>
Cc: Beata Michalska <beata.michalska@arm.com>,
Valentin Schneider <valentin.schneider@arm.com>,
linux-kernel@vger.kernel.org, mingo@redhat.com,
juri.lelli@redhat.com, vincent.guittot@linaro.org,
corbet@lwn.net, rdunlap@infradead.org, linux-doc@vger.kernel.org
Subject: Re: [PATCH v5 2/3] sched/topology: Rework CPU capacity asymmetry detection
Date: Thu, 27 May 2021 09:03:38 +0200 [thread overview]
Message-ID: <YK9ESqNEo+uacyMD@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <98ad8837-b9b8-ff50-5a91-8d5951ee757c@arm.com>
On Wed, May 26, 2021 at 11:52:25AM +0200, Dietmar Eggemann wrote:
> For me asym_cpu_capacity_classify() is pretty hard to digest ;-) But I
> wasn't able to break it. It also performs correctly on (non-existing SMT)
> layer (with sd span eq. single CPU).
This is the simplest form I could come up with this morning:
static inline int
asym_cpu_capacity_classify(struct sched_domain *sd,
const struct cpumask *cpu_map)
{
struct asym_cap_data *entry;
int i = 0, n = 0;
list_for_each_entry(entry, &asym_cap_list, link) {
if (cpumask_intersects(sched_domain_span(sd), entry->cpu_mask))
i++;
else
n++;
}
if (WARN_ON_ONCE(!i) || i == 1) /* no asymmetry */
return 0;
if (n) /* partial asymmetry */
return SD_ASYM_CPUCAPACITY;
/* full asymmetry */
return SD_ASYM_CPUCAPACITY | SD_ASYM_CPUCAPACITY_FULL;
}
The early termination and everything was cute; but this isn't
performance critical code and clarity is paramount.
next prev parent reply other threads:[~2021-05-27 7:03 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-24 10:16 [PATCH v5 0/3] Rework CPU capacity asymmetry detection Beata Michalska
2021-05-24 10:16 ` [PATCH v5 1/3] sched/core: Introduce SD_ASYM_CPUCAPACITY_FULL sched_domain flag Beata Michalska
2021-05-24 10:16 ` [PATCH v5 2/3] sched/topology: Rework CPU capacity asymmetry detection Beata Michalska
2021-05-24 18:01 ` Valentin Schneider
2021-05-24 22:55 ` Beata Michalska
2021-05-24 23:19 ` Beata Michalska
2021-05-25 9:53 ` Valentin Schneider
2021-05-25 10:29 ` Beata Michalska
2021-05-26 9:52 ` Dietmar Eggemann
2021-05-26 12:15 ` Beata Michalska
2021-05-26 12:51 ` Beata Michalska
2021-05-26 18:17 ` Dietmar Eggemann
2021-05-26 21:40 ` Beata Michalska
2021-05-27 15:08 ` Dietmar Eggemann
2021-05-27 17:07 ` Beata Michalska
2021-06-02 17:17 ` Dietmar Eggemann
2021-06-02 19:48 ` Beata Michalska
2021-06-03 9:09 ` Dietmar Eggemann
2021-06-03 9:24 ` Beata Michalska
2021-05-26 18:17 ` Dietmar Eggemann
2021-05-26 21:43 ` Beata Michalska
2021-05-27 7:03 ` Peter Zijlstra [this message]
2021-05-27 12:22 ` Dietmar Eggemann
2021-05-27 12:32 ` Beata Michalska
2021-05-25 8:25 ` Dietmar Eggemann
2021-05-25 9:30 ` Beata Michalska
2021-05-25 11:59 ` Dietmar Eggemann
2021-05-25 14:04 ` Beata Michalska
2021-05-24 10:16 ` [PATCH v5 3/3] sched/doc: Update the CPU capacity asymmetry bits Beata Michalska
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