* [2/3] EDAC, sb_edac: Early return on ADDRV bit and address type test
@ 2018-09-05 14:01 Borislav Petkov
0 siblings, 0 replies; 3+ messages in thread
From: Borislav Petkov @ 2018-09-05 14:01 UTC (permalink / raw)
To: Qiuxu Zhuo; +Cc: Tony Luck, Mauro Carvalho Chehab, Aristeu Rozanski, linux-edac
On Tue, Sep 04, 2018 at 02:07:58PM -0700, Tony Luck wrote:
> From: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
>
> Current EDAC driver only decodes valid memory physical addresses.
> So move the test for bit 58(ADDRV) into sbridge_mce_check_error(),
> and add a test that the address is the right type (looking as MISC
> bits{8:6}). Get rid of the duplicated test whether it's a memory
> controller error in sbridge_mce_output_error().
So I had to go and look at the code what exactly this patch is fixing.
Above you are explaining *what* this patch changes in the commit message
whereas you should be explaining *why* it is being changed. The *what*
is visible from the diff below.
In general, when writing a commit message, try to structure it somewhat
like this:
Problem is A.
It happens because of B.
Fix it by doing C.
(Potentially do D).
For more detailed info, see
Documentation/process/submitting-patches.rst, Section "2) Describe your
changes".
Thx.
^ permalink raw reply [flat|nested] 3+ messages in thread
* [2/3] EDAC, sb_edac: Early return on ADDRV bit and address type test
@ 2018-09-06 13:18 Qiuxu Zhuo
0 siblings, 0 replies; 3+ messages in thread
From: Qiuxu Zhuo @ 2018-09-06 13:18 UTC (permalink / raw)
To: Borislav Petkov
Cc: Luck, Tony, Mauro Carvalho Chehab, Aristeu Rozanski, linux-edac
> Above you are explaining *what* this patch changes in the commit message
> whereas you should be explaining *why* it is being changed. The *what* is
> visible from the diff below.
>
> In general, when writing a commit message, try to structure it somewhat like
> this:
>
> Problem is A.
>
> It happens because of B.
>
> Fix it by doing C.
>
> (Potentially do D).
>
OK, will update the commit message with above structure in v2.
^ permalink raw reply [flat|nested] 3+ messages in thread
* [2/3] EDAC, sb_edac: Early return on ADDRV bit and address type test
@ 2018-09-04 21:07 Luck, Tony
0 siblings, 0 replies; 3+ messages in thread
From: Luck, Tony @ 2018-09-04 21:07 UTC (permalink / raw)
To: Borislav Petkov
Cc: Qiuxu Zhuo, Tony Luck, Borislav Petkov, Mauro Carvalho Chehab,
Aristeu Rozanski, linux-edac
From: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Current EDAC driver only decodes valid memory physical addresses.
So move the test for bit 58(ADDRV) into sbridge_mce_check_error(),
and add a test that the address is the right type (looking as MISC
bits{8:6}). Get rid of the duplicated test whether it's a memory
controller error in sbridge_mce_output_error().
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
---
drivers/edac/sb_edac.c | 68 ++++++++++++++++++++++--------------------
1 file changed, 35 insertions(+), 33 deletions(-)
diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c
index 07726fb00321..f3678cdada83 100644
--- a/drivers/edac/sb_edac.c
+++ b/drivers/edac/sb_edac.c
@@ -2911,35 +2911,27 @@ static void sbridge_mce_output_error(struct mem_ctl_info *mci,
* cccc = channel
* If the mask doesn't match, report an error to the parsing logic
*/
- if (! ((errcode & 0xef80) == 0x80)) {
- optype = "Can't parse: it is not a mem";
- } else {
- switch (optypenum) {
- case 0:
- optype = "generic undef request error";
- break;
- case 1:
- optype = "memory read error";
- break;
- case 2:
- optype = "memory write error";
- break;
- case 3:
- optype = "addr/cmd error";
- break;
- case 4:
- optype = "memory scrubbing error";
- break;
- default:
- optype = "reserved";
- break;
- }
+ switch (optypenum) {
+ case 0:
+ optype = "generic undef request error";
+ break;
+ case 1:
+ optype = "memory read error";
+ break;
+ case 2:
+ optype = "memory write error";
+ break;
+ case 3:
+ optype = "addr/cmd error";
+ break;
+ case 4:
+ optype = "memory scrubbing error";
+ break;
+ default:
+ optype = "reserved";
+ break;
}
- /* Only decode errors with an valid address (ADDRV) */
- if (!GET_BITFIELD(m->status, 58, 58))
- return;
-
if (pvt->info.type == KNIGHTS_LANDING) {
if (channel == 14) {
edac_dbg(0, "%s%s err_code:%04x:%04x EDRAM bank %d\n",
@@ -3045,17 +3037,11 @@ static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val,
{
struct mce *mce = (struct mce *)data;
struct mem_ctl_info *mci;
- struct sbridge_pvt *pvt;
char *type;
if (edac_get_report_status() == EDAC_REPORTING_DISABLED)
return NOTIFY_DONE;
- mci = get_mci_for_node_id(mce->socketid, IMC0);
- if (!mci)
- return NOTIFY_DONE;
- pvt = mci->pvt_info;
-
/*
* Just let mcelog handle it if the error is
* outside the memory controller. A memory error
@@ -3065,6 +3051,22 @@ static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val,
if ((mce->status & 0xefff) >> 7 != 1)
return NOTIFY_DONE;
+ /* Check ADDRV bit in STATUS */
+ if (!GET_BITFIELD(mce->status, 58, 58))
+ return NOTIFY_DONE;
+
+ /* Check MISCV bit in STATUS */
+ if (!GET_BITFIELD(mce->status, 59, 59))
+ return NOTIFY_DONE;
+
+ /* Check address type in MISC (physical address only) */
+ if (GET_BITFIELD(mce->misc, 6, 8) != 2)
+ return NOTIFY_DONE;
+
+ mci = get_mci_for_node_id(mce->socketid, IMC0);
+ if (!mci)
+ return NOTIFY_DONE;
+
if (mce->mcgstatus & MCG_STATUS_MCIP)
type = "Exception";
else
^ permalink raw reply related [flat|nested] 3+ messages in thread
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