* [V2,2/2] x86/mce: Add macros for corrected error count bit field
@ 2018-09-25 0:03 Luck, Tony
0 siblings, 0 replies; 3+ messages in thread
From: Luck, Tony @ 2018-09-25 0:03 UTC (permalink / raw)
To: Borislav Petkov
Cc: Qiuxu Zhuo, Aristeu Rozanski, Mauro Carvalho Chehab, linux-edac
From: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
The bit field 52:38 of MCi_STATUS is for corrected error count.
Add {*_SHIFT|*_MASK|*_CEC(c)} macros for the bit field.
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
---
V2: Just the CEC change. Vertical alignment of other fields fixed in part 1
arch/x86/include/asm/mce.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 37b29e841757..a81a22e3592c 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -39,6 +39,9 @@
#define MCI_STATUS_PCC BIT_ULL(57) /* processor context corrupt */
#define MCI_STATUS_S BIT_ULL(56) /* Signaled machine check */
#define MCI_STATUS_AR BIT_ULL(55) /* Action required */
+#define MCI_STATUS_CEC_SHIFT 38 /* Corrected Error Count */
+#define MCI_STATUS_CEC_MASK 0x1fffc000000000ULL
+#define MCI_STATUS_CEC(c) (((c) & MCI_STATUS_CEC_MASK) >> MCI_STATUS_CEC_SHIFT)
/* AMD-specific bits */
#define MCI_STATUS_TCC BIT_ULL(55) /* Task context corrupt */
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [V2,2/2] x86/mce: Add macros for corrected error count bit field
@ 2018-09-26 18:25 Luck, Tony
0 siblings, 0 replies; 3+ messages in thread
From: Luck, Tony @ 2018-09-26 18:25 UTC (permalink / raw)
To: Borislav Petkov
Cc: Zhuo, Qiuxu, Aristeu Rozanski, Mauro Carvalho Chehab, linux-edac
>> +#define MCI_STATUS_CEC_MASK 0x1fffc000000000ULL
> GENMASK_ULL(52,38) right?
Yes. Thanks.
-Tony
^ permalink raw reply [flat|nested] 3+ messages in thread
* [V2,2/2] x86/mce: Add macros for corrected error count bit field
@ 2018-09-26 11:05 Borislav Petkov
0 siblings, 0 replies; 3+ messages in thread
From: Borislav Petkov @ 2018-09-26 11:05 UTC (permalink / raw)
To: Luck, Tony
Cc: Qiuxu Zhuo, Aristeu Rozanski, Mauro Carvalho Chehab, linux-edac
On Mon, Sep 24, 2018 at 05:03:43PM -0700, Luck, Tony wrote:
> From: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
>
> The bit field 52:38 of MCi_STATUS is for corrected error count.
> Add {*_SHIFT|*_MASK|*_CEC(c)} macros for the bit field.
>
> Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
> Signed-off-by: Tony Luck <tony.luck@intel.com>
> ---
>
> V2: Just the CEC change. Vertical alignment of other fields fixed in part 1
>
> arch/x86/include/asm/mce.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
> index 37b29e841757..a81a22e3592c 100644
> --- a/arch/x86/include/asm/mce.h
> +++ b/arch/x86/include/asm/mce.h
> @@ -39,6 +39,9 @@
> #define MCI_STATUS_PCC BIT_ULL(57) /* processor context corrupt */
> #define MCI_STATUS_S BIT_ULL(56) /* Signaled machine check */
> #define MCI_STATUS_AR BIT_ULL(55) /* Action required */
> +#define MCI_STATUS_CEC_SHIFT 38 /* Corrected Error Count */
> +#define MCI_STATUS_CEC_MASK 0x1fffc000000000ULL
GENMASK_ULL(52,38) right?
^ permalink raw reply [flat|nested] 3+ messages in thread
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