From: Yazen Ghannam <Yazen.Ghannam@amd.com>
To: linux-edac@vger.kernel.org
Cc: Yazen Ghannam <Yazen.Ghannam@amd.com>,
linux-kernel@vger.kernel.org, tony.luck@intel.com,
x86@kernel.org, Smita.KoralahalliChannabasappa@amd.com
Subject: [PATCH v2 5/8] x86/MCE/AMD: Use macros to get bitfields in translation code
Date: Thu, 3 Sep 2020 20:01:41 +0000 [thread overview]
Message-ID: <20200903200144.310991-6-Yazen.Ghannam@amd.com> (raw)
In-Reply-To: <20200903200144.310991-1-Yazen.Ghannam@amd.com>
From: Yazen Ghannam <yazen.ghannam@amd.com>
Define macros to get individual bits and bitfields. Use these to make
the code more readable.
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
Link:
https://lkml.kernel.org/r/20200814191449.183998-3-Yazen.Ghannam@amd.com
v1 -> v2:
* New patch based on comments for v1 Patch 2.
arch/x86/kernel/cpu/mce/amd.c | 46 +++++++++++++++++------------------
1 file changed, 23 insertions(+), 23 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c
index 1e0510fd5afc..90c3ad61ae19 100644
--- a/arch/x86/kernel/cpu/mce/amd.c
+++ b/arch/x86/kernel/cpu/mce/amd.c
@@ -675,6 +675,9 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
deferred_error_interrupt_enable(c);
}
+#define get_bits(x, msb, lsb) ((x & GENMASK_ULL(msb, lsb)) >> lsb)
+#define get_bit(x, bit) ((x >> bit) & BIT(0))
+
#define DF_F0_FABRICINSTINFO3 0x50
#define DF_F0_MMIOHOLE 0x104
#define DF_F0_DRAMBASEADDR 0x110
@@ -704,7 +707,7 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
/* Remove HiAddrOffset from normalized address, if enabled: */
if (tmp & BIT(0)) {
- u64 hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8;
+ u64 hi_addr_offset = get_bits(tmp, 31, 20) << 28;
/* Check if base 1 is used. */
if (norm_addr >= hi_addr_offset) {
@@ -723,10 +726,10 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
goto out_err;
}
- lgcy_mmio_hole_en = tmp & BIT(1);
- intlv_num_chan = (tmp >> 4) & 0xF;
- intlv_addr_sel = (tmp >> 8) & 0x7;
- dram_base_addr = (tmp & GENMASK_ULL(31, 12)) << 16;
+ lgcy_mmio_hole_en = get_bit(tmp, 1);
+ intlv_num_chan = get_bits(tmp, 7, 4);
+ intlv_addr_sel = get_bits(tmp, 10, 8);
+ dram_base_addr = get_bits(tmp, 31, 12) << 28;
/* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */
if (intlv_addr_sel > 3) {
@@ -738,9 +741,9 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
if (amd_df_indirect_read(nid, 0, DF_F0_DRAMLIMITADDR + (8 * base), umc, &tmp))
goto out_err;
- intlv_num_sockets = (tmp >> 8) & 0x1;
- intlv_num_dies = (tmp >> 10) & 0x3;
- dram_limit_addr = ((tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0);
+ intlv_num_sockets = get_bit(tmp, 8);
+ intlv_num_dies = get_bits(tmp, 11, 10);
+ dram_limit_addr = (get_bits(tmp, 31, 12) << 28) | GENMASK_ULL(27, 0);
intlv_addr_bit = intlv_addr_sel + 8;
@@ -793,7 +796,7 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
if (amd_df_indirect_read(nid, 0, DF_F0_FABRICINSTINFO3, umc, &tmp))
goto out_err;
- cs_fabric_id = (tmp >> 8) & 0xFF;
+ cs_fabric_id = get_bits(tmp, 15, 8);
die_id_bit = 0;
/* If interleaved over more than 1 channel: */
@@ -812,16 +815,16 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
/* If interleaved over more than 1 die. */
if (intlv_num_dies) {
sock_id_bit = die_id_bit + intlv_num_dies;
- die_id_shift = (tmp >> 24) & 0xF;
- die_id_mask = (tmp >> 8) & 0xFF;
+ die_id_shift = get_bits(tmp, 27, 24);
+ die_id_mask = get_bits(tmp, 15, 8);
cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit;
}
/* If interleaved over more than 1 socket. */
if (intlv_num_sockets) {
- socket_id_shift = (tmp >> 28) & 0xF;
- socket_id_mask = (tmp >> 16) & 0xFF;
+ socket_id_shift = get_bits(tmp, 31, 28);
+ socket_id_mask = get_bits(tmp, 23, 16);
cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit;
}
@@ -834,7 +837,7 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
* bits there are. "intlv_addr_bit" tells us how many "Y" bits
* there are (where "I" starts).
*/
- temp_addr_y = ret_addr & GENMASK_ULL(intlv_addr_bit-1, 0);
+ temp_addr_y = get_bits(ret_addr, intlv_addr_bit-1, 0);
temp_addr_i = (cs_id << intlv_addr_bit);
temp_addr_x = (ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits;
ret_addr = temp_addr_x | temp_addr_i | temp_addr_y;
@@ -854,16 +857,13 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
}
if (hash_enabled) {
- /* Save some parentheses and grab ls-bit at the end. */
- hashed_bit = (ret_addr >> 12) ^
- (ret_addr >> 18) ^
- (ret_addr >> 21) ^
- (ret_addr >> 30) ^
- cs_id;
-
- hashed_bit &= BIT(0);
+ hashed_bit = get_bit(ret_addr, 12) ^
+ get_bit(ret_addr, 18) ^
+ get_bit(ret_addr, 21) ^
+ get_bit(ret_addr, 30) ^
+ get_bit(cs_id, 0);
- if (hashed_bit != ((ret_addr >> intlv_addr_bit) & BIT(0)))
+ if (hashed_bit != get_bit(ret_addr, intlv_addr_bit))
ret_addr ^= BIT(intlv_addr_bit);
}
--
2.25.1
next prev parent reply other threads:[~2020-09-03 20:02 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-03 20:01 [PATCH v2 0/8] AMD MCA Address Translation Updates Yazen Ghannam
2020-09-03 20:01 ` [PATCH v2 1/8] x86/CPU/AMD: Save NodeId on AMD-based systems Yazen Ghannam
2020-09-09 18:06 ` Borislav Petkov
2020-09-09 20:17 ` Yazen Ghannam
2020-09-10 10:14 ` Borislav Petkov
2020-09-14 19:20 ` Yazen Ghannam
2020-09-15 8:35 ` Borislav Petkov
2020-09-16 19:51 ` Yazen Ghannam
2020-09-17 10:37 ` Borislav Petkov
2020-09-17 16:20 ` Yazen Ghannam
2020-09-17 16:40 ` Borislav Petkov
2020-09-17 19:44 ` Yazen Ghannam
2020-09-17 20:10 ` Borislav Petkov
2020-09-03 20:01 ` [PATCH v2 2/8] x86/CPU/AMD: Remove amd_get_nb_id() Yazen Ghannam
2020-09-03 20:01 ` [PATCH v2 3/8] EDAC/mce_amd: Use struct cpuinfo_x86.node_id for NodeId Yazen Ghannam
2020-09-03 20:01 ` [PATCH v2 4/8] x86/MCE/AMD: Use defines for register addresses in translation code Yazen Ghannam
2020-09-03 20:01 ` Yazen Ghannam [this message]
2020-09-21 13:58 ` [PATCH v2 5/8] x86/MCE/AMD: Use macros to get bitfields " Borislav Petkov
2020-09-03 20:01 ` [PATCH v2 6/8] x86/MCE/AMD: Drop tmp variable " Yazen Ghannam
2020-09-23 8:05 ` Borislav Petkov
2020-09-23 16:05 ` Yazen Ghannam
2020-09-03 20:01 ` [PATCH v2 7/8] x86/MCE/AMD: Group register reads " Yazen Ghannam
2020-09-03 20:01 ` [PATCH v2 8/8] x86/MCE/AMD Support new memory interleaving modes during address translation Yazen Ghannam
2020-09-23 8:20 ` Borislav Petkov
2020-09-23 16:25 ` Yazen Ghannam
2020-09-25 7:22 ` Borislav Petkov
2020-09-25 19:51 ` Yazen Ghannam
2020-09-28 9:47 ` Borislav Petkov
2020-09-28 15:53 ` Yazen Ghannam
2020-09-28 18:14 ` Borislav Petkov
2020-09-29 13:21 ` Yazen Ghannam
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