From: Yazen Ghannam <yazen.ghannam@amd.com>
To: <bp@alien8.de>, <linux-edac@vger.kernel.org>
Cc: <linux-kernel@vger.kernel.org>, <muralidhara.mk@amd.com>,
<naveenkrishna.chatradhi@amd.com>,
Yazen Ghannam <yazen.ghannam@amd.com>
Subject: [PATCH v2 04/22] EDAC/amd64: Remove PCI Function 0
Date: Fri, 27 Jan 2023 17:04:01 +0000 [thread overview]
Message-ID: <20230127170419.1824692-5-yazen.ghannam@amd.com> (raw)
In-Reply-To: <20230127170419.1824692-1-yazen.ghannam@amd.com>
PCI Function 0 is used on Family 17h and later only to read the "dhar"
value. This value is printed and provided through a module-specific
debug sysfs file. The value is not used for any Family 17h and later
code, and it does not have any apparent debug value on these systems.
Remove "dhar", Function 0 PCI IDs, and all related code.
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
Link:
https://lore.kernel.org/r/20220509145534.44912-5-yazen.ghannam@amd.com
v1->v2:
* Also remove "pvt->F0" pointer.
drivers/edac/amd64_edac.c | 38 +++++---------------------------------
drivers/edac/amd64_edac.h | 12 ++----------
2 files changed, 7 insertions(+), 43 deletions(-)
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index dce2179ad454..352cbcda53f9 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -1428,9 +1428,6 @@ static void __dump_misc_regs_df(struct amd64_pvt *pvt)
debug_display_dimm_sizes_df(pvt, i);
}
-
- edac_dbg(1, "F0x104 (DRAM Hole Address): 0x%08x, base: 0x%08x\n",
- pvt->dhar, dhar_base(pvt));
}
/* Display and decode various NB registers for debug purposes. */
@@ -1465,6 +1462,8 @@ static void __dump_misc_regs(struct amd64_pvt *pvt)
/* Only if NOT ganged does dclr1 have valid info */
if (!dct_ganging_enabled(pvt))
debug_dump_dramcfg_low(pvt, pvt->dclr1, 1);
+
+ edac_dbg(1, " DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");
}
/* Display and decode various NB registers for debug purposes. */
@@ -1475,8 +1474,6 @@ static void dump_misc_regs(struct amd64_pvt *pvt)
else
__dump_misc_regs(pvt);
- edac_dbg(1, " DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");
-
amd64_info("using x%u syndromes.\n", pvt->ecc_sym_sz);
}
@@ -2905,7 +2902,6 @@ static struct amd64_family_type family_types[] = {
},
[F17_CPUS] = {
.ctl_name = "F17h",
- .f0_id = PCI_DEVICE_ID_AMD_17H_DF_F0,
.max_mcs = 2,
.ops = {
.early_channel_count = f17_early_channel_count,
@@ -2914,7 +2910,6 @@ static struct amd64_family_type family_types[] = {
},
[F17_M10H_CPUS] = {
.ctl_name = "F17h_M10h",
- .f0_id = PCI_DEVICE_ID_AMD_17H_M10H_DF_F0,
.max_mcs = 2,
.ops = {
.early_channel_count = f17_early_channel_count,
@@ -2923,7 +2918,6 @@ static struct amd64_family_type family_types[] = {
},
[F17_M30H_CPUS] = {
.ctl_name = "F17h_M30h",
- .f0_id = PCI_DEVICE_ID_AMD_17H_M30H_DF_F0,
.max_mcs = 8,
.ops = {
.early_channel_count = f17_early_channel_count,
@@ -2932,7 +2926,6 @@ static struct amd64_family_type family_types[] = {
},
[F17_M60H_CPUS] = {
.ctl_name = "F17h_M60h",
- .f0_id = PCI_DEVICE_ID_AMD_17H_M60H_DF_F0,
.max_mcs = 2,
.ops = {
.early_channel_count = f17_early_channel_count,
@@ -2941,7 +2934,6 @@ static struct amd64_family_type family_types[] = {
},
[F17_M70H_CPUS] = {
.ctl_name = "F17h_M70h",
- .f0_id = PCI_DEVICE_ID_AMD_17H_M70H_DF_F0,
.max_mcs = 2,
.ops = {
.early_channel_count = f17_early_channel_count,
@@ -2950,7 +2942,6 @@ static struct amd64_family_type family_types[] = {
},
[F19_CPUS] = {
.ctl_name = "F19h",
- .f0_id = PCI_DEVICE_ID_AMD_19H_DF_F0,
.max_mcs = 8,
.ops = {
.early_channel_count = f17_early_channel_count,
@@ -2959,7 +2950,6 @@ static struct amd64_family_type family_types[] = {
},
[F19_M10H_CPUS] = {
.ctl_name = "F19h_M10h",
- .f0_id = PCI_DEVICE_ID_AMD_19H_M10H_DF_F0,
.max_mcs = 12,
.flags.zn_regs_v2 = 1,
.ops = {
@@ -2969,7 +2959,6 @@ static struct amd64_family_type family_types[] = {
},
[F19_M50H_CPUS] = {
.ctl_name = "F19h_M50h",
- .f0_id = PCI_DEVICE_ID_AMD_19H_M50H_DF_F0,
.max_mcs = 2,
.ops = {
.early_channel_count = f17_early_channel_count,
@@ -3282,26 +3271,12 @@ static void decode_umc_error(int node_id, struct mce *m)
/*
* Use pvt->F3 which contains the F3 CPU PCI device to get the related
* F1 (AddrMap) and F2 (Dct) devices. Return negative value on error.
- * Reserve F0 on systems with a UMC.
*/
static int
reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 pci_id1, u16 pci_id2)
{
- if (pvt->umc) {
- pvt->F0 = pci_get_related_function(pvt->F3->vendor, pci_id1, pvt->F3);
- if (!pvt->F0) {
- edac_dbg(1, "F0 not found, device 0x%x\n", pci_id1);
- return -ENODEV;
- }
-
- if (!pci_ctl_dev)
- pci_ctl_dev = &pvt->F0->dev;
-
- edac_dbg(1, "F0: %s\n", pci_name(pvt->F0));
- edac_dbg(1, "F3: %s\n", pci_name(pvt->F3));
-
+ if (pvt->umc)
return 0;
- }
/* Reserve the ADDRESS MAP Device */
pvt->F1 = pci_get_related_function(pvt->F3->vendor, pci_id1, pvt->F3);
@@ -3333,7 +3308,7 @@ reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 pci_id1, u16 pci_id2)
static void free_mc_sibling_devs(struct amd64_pvt *pvt)
{
if (pvt->umc) {
- pci_dev_put(pvt->F0);
+ return;
} else {
pci_dev_put(pvt->F1);
pci_dev_put(pvt->F2);
@@ -3423,7 +3398,6 @@ static void read_mc_regs(struct amd64_pvt *pvt)
if (pvt->umc) {
__read_mc_regs_df(pvt);
- amd64_read_pci_cfg(pvt->F0, DF_DHAR, &pvt->dhar);
goto skip;
}
@@ -4057,8 +4031,6 @@ static int hw_info_get(struct amd64_pvt *pvt)
pvt->umc = kcalloc(fam_type->max_mcs, sizeof(struct amd64_umc), GFP_KERNEL);
if (!pvt->umc)
return -ENOMEM;
-
- pci_id1 = fam_type->f0_id;
} else {
pci_id1 = fam_type->f1_id;
pci_id2 = fam_type->f2_id;
@@ -4075,7 +4047,7 @@ static int hw_info_get(struct amd64_pvt *pvt)
static void hw_info_put(struct amd64_pvt *pvt)
{
- if (pvt->F0 || pvt->F1)
+ if (pvt->F1)
free_mc_sibling_devs(pvt);
kfree(pvt->umc);
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index 2d5ea9ca3868..398fb58dacbf 100644
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -114,14 +114,6 @@
#define PCI_DEVICE_ID_AMD_16H_NB_F2 0x1532
#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581
#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582
-#define PCI_DEVICE_ID_AMD_17H_DF_F0 0x1460
-#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F0 0x15e8
-#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F0 0x1490
-#define PCI_DEVICE_ID_AMD_17H_M60H_DF_F0 0x1448
-#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F0 0x1440
-#define PCI_DEVICE_ID_AMD_19H_DF_F0 0x1650
-#define PCI_DEVICE_ID_AMD_19H_M10H_DF_F0 0x14ad
-#define PCI_DEVICE_ID_AMD_19H_M50H_DF_F0 0x166a
/*
* Function 1 - Address Map
@@ -346,7 +338,7 @@ struct amd64_pvt {
struct low_ops *ops;
/* pci_device handles which we utilize */
- struct pci_dev *F0, *F1, *F2, *F3;
+ struct pci_dev *F1, *F2, *F3;
u16 mc_node_id; /* MC index of this MC node */
u8 fam; /* CPU family */
@@ -493,7 +485,7 @@ struct amd64_family_flags {
struct amd64_family_type {
const char *ctl_name;
- u16 f0_id, f1_id, f2_id;
+ u16 f1_id, f2_id;
/* Maximum number of memory controllers per die/node. */
u8 max_mcs;
struct amd64_family_flags flags;
--
2.25.1
next prev parent reply other threads:[~2023-01-27 17:05 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-27 17:03 [PATCH v2 00/22] AMD64 EDAC Cleanup and Refactor Yazen Ghannam
2023-01-27 17:03 ` [PATCH v2 01/22] EDAC/amd64: Don't set up EDAC PCI control on Family 17h+ Yazen Ghannam
2023-01-27 17:03 ` [PATCH v2 02/22] EDAC/amd64: Remove scrub rate control for Family 17h and later Yazen Ghannam
2023-01-27 17:04 ` [PATCH v2 03/22] EDAC/amd64: Remove PCI Function 6 Yazen Ghannam
2023-01-27 17:04 ` Yazen Ghannam [this message]
2023-01-27 17:04 ` [PATCH v2 05/22] EDAC/amd64: Remove early_channel_count() Yazen Ghannam
2023-02-10 12:16 ` Borislav Petkov
2023-02-13 16:54 ` Yazen Ghannam
2023-01-27 17:04 ` [PATCH v2 06/22] EDAC/amd64: Rename debug_display_dimm_sizes() Yazen Ghannam
2023-02-09 14:25 ` Borislav Petkov
2023-02-13 16:53 ` Yazen Ghannam
2023-01-27 17:04 ` [PATCH v2 07/22] EDAC/amd64: Split get_csrow_nr_pages() into dct/umc functions Yazen Ghannam
2023-01-27 17:04 ` [PATCH v2 08/22] EDAC/amd64: Drop dbam_to_cs() for Family 17h and later Yazen Ghannam
2023-01-27 17:04 ` [PATCH v2 09/22] EDAC/amd64: Don't find ECC symbol size " Yazen Ghannam
2023-01-27 17:04 ` [PATCH v2 10/22] EDAC/amd64: Merge struct amd64_family_type into struct amd64_pvt Yazen Ghannam
2023-03-18 15:39 ` Borislav Petkov
2023-01-27 17:04 ` [PATCH v2 11/22] EDAC/amd64: Rework hw_info_{get,put} Yazen Ghannam
2023-01-27 17:04 ` [PATCH v2 12/22] EDAC/amd64: Split prep_chip_selects() into dct/umc functions Yazen Ghannam
2023-01-27 17:04 ` [PATCH v2 13/22] EDAC/amd64: Split read_base_mask() " Yazen Ghannam
2023-01-27 17:04 ` [PATCH v2 14/22] EDAC/amd64: Split determine_memory_type() " Yazen Ghannam
2023-01-27 17:04 ` [PATCH v2 15/22] EDAC/amd64: Split read_mc_regs() " Yazen Ghannam
2023-01-27 17:04 ` [PATCH v2 16/22] EDAC/amd64: Split ecc_enabled() " Yazen Ghannam
2023-01-27 17:04 ` [PATCH v2 17/22] EDAC/amd64: Split setup_mci_misc_attrs() " Yazen Ghannam
2023-01-27 17:04 ` [PATCH v2 18/22] EDAC/amd64: Rename f17h_determine_edac_ctl_cap() Yazen Ghannam
2023-01-27 17:04 ` [PATCH v2 19/22] EDAC/amd64: Split determine_edac_cap() into dct/umc functions Yazen Ghannam
2023-01-27 17:04 ` [PATCH v2 20/22] EDAC/amd64: Split init_csrows() " Yazen Ghannam
2023-01-27 17:04 ` [PATCH v2 21/22] EDAC/amd64: Split dump_misc_regs() " Yazen Ghannam
2023-01-27 17:04 ` [PATCH v2 22/22] EDAC/amd64: Add get_err_info() to pvt->ops Yazen Ghannam
2023-03-23 11:01 ` [PATCH v2 00/22] AMD64 EDAC Cleanup and Refactor Borislav Petkov
2023-03-23 15:19 ` Yazen Ghannam
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