[v4,4/4] dt-bindings: msm: Update documentation of qcom,llcc

[v4,4/4] dt-bindings: msm: Update documentation of qcom,llcc

[Venkata Narendra Kumar Gutta]

On 2018-09-06 06:16, Sai Prakash Ranjan wrote:
> On 9/5/2018 4:52 AM, Venkata Narendra Kumar Gutta wrote:
>> Add reg-names and interrupts for LLCC documentation and the usage
>> examples. llcc broadcast base is added in addition to llcc base,
>> which is used for llcc broadcast writes.
>> 
>> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
>> Reviewed-by: Rob Herring <robh@kernel.org>
>> ---
>>   .../devicetree/bindings/arm/msm/qcom,llcc.txt         | 19 
>> +++++++++++++++++--
>>   1 file changed, 17 insertions(+), 2 deletions(-)
>> 
>> diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt 
>> b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
>> index 5e85749..2e007dc 100644
>> --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
>> +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
>> @@ -16,11 +16,26 @@ Properties:
>>   - reg:
>>   	Usage: required
>>   	Value Type: <prop-encoded-array>
>> -	Definition: Start address and the the size of the register region.
>> +	Definition: The first element specifies the llcc base start address 
>> and
>> +		    the size of the register region. The second element specifies
>> +		    the llcc broadcast base address and size of the register 
>> region.
>> +
>> +- reg-names:
>> +        Usage: required
>> +        Value Type: <stringlist>
>> +        Definition: Register region names. Must be "llcc_base", 
>> "llcc_bcast_base".
>> +
>> +- interrupts:
>> +	Usage: required
>> +	Definition: The interrupt is associated with the llcc edac device.
>> +			It's used for llcc cache single and double bit error detection
>> +			and reporting.
>>     Example:
>>     	cache-controller@1100000 {
>>   		compatible = "qcom,sdm845-llcc";
>> -		reg = <0x1100000 0x250000>;
>> +		reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
>> +		reg-names = "llcc_base", "llcc_bcast_base";
>> +		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
>>   	};
>> 
> 
> Also, llcc_bcast_base should be llcc_broadcast_base as given in Patch
> 1 or you can change to llcc_bcast_base in Patch 1 of series.

My bad, I'll correct that in the next series.

[v4,4/4] dt-bindings: msm: Update documentation of qcom,llcc

[saiprakash.ranjan]

On 9/5/2018 4:52 AM, Venkata Narendra Kumar Gutta wrote:
> Add reg-names and interrupts for LLCC documentation and the usage
> examples. llcc broadcast base is added in addition to llcc base,
> which is used for llcc broadcast writes.
> 
> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
>   .../devicetree/bindings/arm/msm/qcom,llcc.txt         | 19 +++++++++++++++++--
>   1 file changed, 17 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
> index 5e85749..2e007dc 100644
> --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
> +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
> @@ -16,11 +16,26 @@ Properties:
>   - reg:
>   	Usage: required
>   	Value Type: <prop-encoded-array>
> -	Definition: Start address and the the size of the register region.
> +	Definition: The first element specifies the llcc base start address and
> +		    the size of the register region. The second element specifies
> +		    the llcc broadcast base address and size of the register region.
> +
> +- reg-names:
> +        Usage: required
> +        Value Type: <stringlist>
> +        Definition: Register region names. Must be "llcc_base", "llcc_bcast_base".
> +
> +- interrupts:
> +	Usage: required
> +	Definition: The interrupt is associated with the llcc edac device.
> +			It's used for llcc cache single and double bit error detection
> +			and reporting.
>   
>   Example:
>   
>   	cache-controller@1100000 {
>   		compatible = "qcom,sdm845-llcc";
> -		reg = <0x1100000 0x250000>;
> +		reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
> +		reg-names = "llcc_base", "llcc_bcast_base";
> +		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
>   	};
> 

Also, llcc_bcast_base should be llcc_broadcast_base as given in Patch 1 
or you can change to llcc_bcast_base in Patch 1 of series.

[v4,4/4] dt-bindings: msm: Update documentation of qcom,llcc

[Venkata Narendra Kumar Gutta]

Add reg-names and interrupts for LLCC documentation and the usage
examples. llcc broadcast base is added in addition to llcc base,
which is used for llcc broadcast writes.

Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/arm/msm/qcom,llcc.txt         | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
index 5e85749..2e007dc 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
@@ -16,11 +16,26 @@ Properties:
 - reg:
 	Usage: required
 	Value Type: <prop-encoded-array>
-	Definition: Start address and the the size of the register region.
+	Definition: The first element specifies the llcc base start address and
+		    the size of the register region. The second element specifies
+		    the llcc broadcast base address and size of the register region.
+
+- reg-names:
+        Usage: required
+        Value Type: <stringlist>
+        Definition: Register region names. Must be "llcc_base", "llcc_bcast_base".
+
+- interrupts:
+	Usage: required
+	Definition: The interrupt is associated with the llcc edac device.
+			It's used for llcc cache single and double bit error detection
+			and reporting.
 
 Example:
 
 	cache-controller@1100000 {
 		compatible = "qcom,sdm845-llcc";
-		reg = <0x1100000 0x250000>;
+		reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
+		reg-names = "llcc_base", "llcc_bcast_base";
+		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
 	};