From: Joel Stanley <joel@jms.id.au>
To: Troy Lee <troy_lee@aspeedtech.com>
Cc: Stefan Schaeckeler <sschaeck@cisco.com>,
Rob Herring <robh+dt@kernel.org>,
Andrew Jeffery <andrew@aj.id.au>, Borislav Petkov <bp@alien8.de>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Tony Luck <tony.luck@intel.com>,
James Morse <james.morse@arm.com>,
Robert Richter <rrichter@marvell.com>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
"moderated list:ARM/ASPEED MACHINE SUPPORT"
<linux-arm-kernel@lists.infradead.org>,
"moderated list:ARM/ASPEED MACHINE SUPPORT"
<linux-aspeed@lists.ozlabs.org>,
open list <linux-kernel@vger.kernel.org>,
"open list:EDAC-CORE" <linux-edac@vger.kernel.org>,
leetroy@gmail.com, Ryan Chen <ryan_chen@aspeedtech.com>
Subject: Re: [PATCH v2 1/3] dt-bindings: edac: aspeed-sdram-edac: Add ast2400/ast2600 support
Date: Wed, 2 Dec 2020 06:40:47 +0000 [thread overview]
Message-ID: <CACPK8XfySi5=r4e__djHg-LtFqhV7j+-Pp+t4zevro=KK0eBig@mail.gmail.com> (raw)
In-Reply-To: <20201202063612.21241-1-troy_lee@aspeedtech.com>
On Wed, 2 Dec 2020 at 06:37, Troy Lee <troy_lee@aspeedtech.com> wrote:
>
> Adding Aspeed AST2400 and AST2600 binding for edac driver.
>
> Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Acked-by: Joel Stanley <joel@jms.id.au>
> ---
> .../devicetree/bindings/edac/aspeed-sdram-edac.txt | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
> index 6a0f3d90d682..8ca9e0a049d8 100644
> --- a/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
> +++ b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
> @@ -1,6 +1,6 @@
> -Aspeed AST2500 SoC EDAC node
> +Aspeed BMC SoC EDAC node
>
> -The Aspeed AST2500 SoC supports DDR3 and DDR4 memory with and without ECC (error
> +The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error
> correction check).
>
> The memory controller supports SECDED (single bit error correction, double bit
> @@ -11,7 +11,10 @@ Note, the bootloader must configure ECC mode in the memory controller.
>
>
> Required properties:
> -- compatible: should be "aspeed,ast2500-sdram-edac"
> +- compatible: should be one of
> + - "aspeed,ast2400-sdram-edac"
> + - "aspeed,ast2500-sdram-edac"
> + - "aspeed,ast2600-sdram-edac"
> - reg: sdram controller register set should be <0x1e6e0000 0x174>
> - interrupts: should be AVIC interrupt #0
>
> --
> 2.17.1
>
prev parent reply other threads:[~2020-12-02 6:41 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-02 6:36 [PATCH v2 1/3] dt-bindings: edac: aspeed-sdram-edac: Add ast2400/ast2600 support Troy Lee
2020-12-02 6:36 ` [PATCH v2 2/3] ARM: dts: aspeed: Add AST2600 edac into common devicetree Troy Lee
2020-12-02 7:02 ` Joel Stanley
2020-12-02 6:36 ` [PATCH v2 3/3] edac: Supporting AST2400 and AST2600 edac driver Troy Lee
2020-12-02 7:01 ` Joel Stanley
2020-12-02 8:41 ` Troy Lee
2020-12-02 15:02 ` Andrew Jeffery
2020-12-02 18:23 ` Borislav Petkov
2020-12-03 1:27 ` Troy Lee
2020-12-03 7:20 ` Borislav Petkov
2020-12-02 6:40 ` Joel Stanley [this message]
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