From: mroos@linux.ee
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Borislav Petkov <bp@alien8.de>,
Linux Kernel list <linux-kernel@vger.kernel.org>,
x86@kernel.org, linux-edac@vger.kernel.org,
Tom Lendacky <thomas.lendacky@amd.com>
Subject: 4.15-rc6 PTI regression: L1 TLB mismatch MCE on Athlon64
Date: Wed, 3 Jan 2018 16:01:11 +0200 (EET) [thread overview]
Message-ID: <alpine.LRH.2.21.1801031557370.4107@math.ut.ee> (raw)
> That's the entry area, which is mapped into kernel _AND_ user space. Now
> that's special because we switch CR3 while we are executing there.
>
> And this one is:
>
> 0xffffffff81e00000-0xffffffff82000000 2M ro PSE GLB x pmd
>
> and the one we switch to is:
>
> 0xffffffff81000000-0xffffffff82000000 16M ro PSE x pmd
>
> Meelis, does the patch below fix it for you?
Yes, the MCE-s are gone with this patch on top of 4.15-rc6.
>
> Thanks,
>
> tglx
>
> 8<-------------------
>
> --- a/arch/x86/mm/pti.c
> +++ b/arch/x86/mm/pti.c
> @@ -367,7 +367,8 @@ static void __init pti_setup_espfix64(vo
> static void __init pti_clone_entry_text(void)
> {
> pti_clone_pmds((unsigned long) __entry_text_start,
> - (unsigned long) __irqentry_text_end, _PAGE_RW);
> + (unsigned long) __irqentry_text_end,
> + _PAGE_RW | _PAGE_GLOBAL);
> }
>
> /*
>
next reply other threads:[~2018-01-03 14:01 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-03 14:01 mroos [this message]
-- strict thread matches above, loose matches on Subject: below --
2018-01-03 13:17 4.15-rc6 PTI regression: L1 TLB mismatch MCE on Athlon64 Thomas Gleixner
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