From: "M K, Muralidhara" <muralimk@amd.com>
To: Borislav Petkov <bp@alien8.de>
Cc: linux-edac@vger.kernel.org, x86@kernel.org,
linux-kernel@vger.kernel.org, mingo@redhat.com,
mchehab@kernel.org, nchatrad@amd.com, yazen.ghannam@amd.com,
Muralidhara M K <muralidhara.mk@amd.com>
Subject: Re: [PATCH 2/7] EDAC/mce_amd: Remove SMCA Extended Error code descriptions
Date: Thu, 20 Jul 2023 20:55:01 +0530 [thread overview]
Message-ID: <b70fa364-2f68-1336-8d1c-7687f5c4f1b4@amd.com> (raw)
In-Reply-To: <20230720135950.GHZLk91jGbX7l+7AMz@fat_crate.local>
Hi Boris,
On 7/20/2023 7:29 PM, Borislav Petkov wrote:
> Caution: This message originated from an External Source. Use proper caution when opening attachments, clicking links, or responding.
>
>
> On Thu, Jul 20, 2023 at 12:54:20PM +0000, Muralidhara M K wrote:
>> From: Muralidhara M K <muralidhara.mk@amd.com>
>>
>> On AMD systems with Scalable MCA, each machine check error of a SMCA bank
>> type has an associated bit position in the bank's control (CTL) register.
>>
>> An error's bit position in the CTL register is used during error decoding
>> for offsetting into the corresponding bank's error description structure.
>> As new errors are being added in newer AMD systems for existing SMCA bank
>> types, the underlying SMCA architecture guarantees that the bit positions
>> of existing errors are not altered.
>>
>> However, on some AMD systems some of the existing bit definitions in the
>> CTL register of SMCA bank type are reassigned without defining new HWID
>> and McaType. Consequently, the errors whose bit definitions have been
>> reassigned in the CTL register are being erroneously decoded.
>>
>> Remove SMCA Extended Error Code descriptions. This avoids decoding issues
>> for incorrectly reassigned bits, and avoids the related maintenance burden
>> in the kernel. This decoding can be done in external tools or by referring
>> to AMD documentation. The bank type and Extended Error Code value for an
>> error will continue to be printed as a convenience.
>>
>> Signed-off-by: Muralidhara M K <muralidhara.mk@amd.com>
>> Reviewed-by: Yazen Ghannam <yazen.ghannam@amd.com>
>> ---
>> drivers/edac/mce_amd.c | 480 -----------------------------------------
>> 1 file changed, 480 deletions(-)
>
> This needs to stay until rasdaemon has support for decoding errors - and
> I've told you already.
>
> Lemme tell you again, maybe it'll stick this time.
>
> In any case, NAK.
>
Pull request created in rasdaemon for the same.
https://github.com/mchehab/rasdaemon/pull/106/commits/09026653864305b7a91dcb3604b91a9c0c0d74f3
> --
> Regards/Gruss,
> Boris.
>
> https://people.kernel.org/tglx/notes-about-netiquette
>
next prev parent reply other threads:[~2023-07-20 15:25 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-20 12:54 [PATCH 0/7] AMD Family 19h Models 90h-9fh EDAC Support Muralidhara M K
2023-07-20 12:54 ` [PATCH 1/7] x86/amd_nb: Add AMD Family 19h Models(80h-80fh) and (90h-9fh) PCI IDs Muralidhara M K
2023-07-21 14:44 ` Yazen Ghannam
2023-07-20 12:54 ` [PATCH 2/7] EDAC/mce_amd: Remove SMCA Extended Error code descriptions Muralidhara M K
2023-07-20 13:59 ` Borislav Petkov
2023-07-20 15:25 ` M K, Muralidhara [this message]
2023-07-20 15:55 ` Borislav Petkov
2023-07-21 14:45 ` Yazen Ghannam
2023-10-24 6:18 ` M K, Muralidhara
2023-07-20 12:54 ` [PATCH 3/7] x86/MCE/AMD: Add new MA_LLC, USR_DP, and USR_CP bank types Muralidhara M K
2023-07-22 8:20 ` Borislav Petkov
2023-07-20 12:54 ` [PATCH 4/7] EDAC/mc: Add new HBM3 memory type Muralidhara M K
2023-08-03 10:27 ` Borislav Petkov
2023-07-20 12:54 ` [PATCH 5/7] EDAC/amd64: Add Fam19h Model 90h ~ 9fh enumeration support Muralidhara M K
2023-08-05 10:10 ` Borislav Petkov
2023-07-20 12:54 ` [PATCH 6/7] EDAC/amd64: Add error instance get_err_info() to pvt->ops Muralidhara M K
2023-07-21 14:47 ` Yazen Ghannam
2023-07-20 12:54 ` [PATCH 7/7] EDAC/amd64: Add Error address conversion for UMC Muralidhara M K
2023-07-21 14:49 ` Yazen Ghannam
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