From: Palmer Dabbelt <palmer@dabbelt.com>
To: yash.shah@sifive.com
Cc: robh+dt@kernel.org, Paul Walmsley <paul.walmsley@sifive.com>,
bp@alien8.de, mchehab@kernel.org, tony.luck@intel.com,
aou@eecs.berkeley.edu, james.morse@arm.com, rrichter@marvell.com,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org,
sachin.ghadi@sifive.com, yash.shah@sifive.com
Subject: Re: [PATCH 1/3] dt-bindings: riscv: Add DT documentation for DDR Controller in SiFive SoCs
Date: Tue, 25 Aug 2020 09:02:51 -0700 (PDT) [thread overview]
Message-ID: <mhng-45ab2484-537a-45da-8fb2-b19329728caa@palmerdabbelt-glaptop1> (raw)
In-Reply-To: <1598357182-4226-2-git-send-email-yash.shah@sifive.com>
On Tue, 25 Aug 2020 05:06:20 PDT (-0700), yash.shah@sifive.com wrote:
> Add device tree bindings for SiFive FU540 DDR controller driver
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> ---
> .../devicetree/bindings/riscv/sifive-ddr.yaml | 41 ++++++++++++++++++++++
> 1 file changed, 41 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/riscv/sifive-ddr.yaml
>
> diff --git a/Documentation/devicetree/bindings/riscv/sifive-ddr.yaml b/Documentation/devicetree/bindings/riscv/sifive-ddr.yaml
> new file mode 100644
> index 0000000..0288119
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/riscv/sifive-ddr.yaml
> @@ -0,0 +1,41 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/riscv/sifive-ddr.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: SiFive DDR memory controller binding
> +
> +description: |
> + The Sifive DDR controller driver is used to manage the Cadence DDR
> + controller present in SiFive FU540-C000 SoC. Currently the driver is
> + used to manage EDAC feature of the DDR controller.
> +
> +maintainers:
> + - Yash Shah <yash.shah@sifive.com>
> +
> +properties:
> + compatible:
> + enum:
> + - sifive,fu540-c000-ddr
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + memory-controller@100b0000 {
> + compatible = "sifive,fu540-c000-ddr";
> + reg = <0x100b0000 0x4000>;
> + interrupts = <31>;
> + };
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
next prev parent reply other threads:[~2020-08-25 16:03 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-25 12:06 [PATCH 0/3] SiFive DDR controller and EDAC support Yash Shah
2020-08-25 12:06 ` [PATCH 1/3] dt-bindings: riscv: Add DT documentation for DDR Controller in SiFive SoCs Yash Shah
2020-08-25 16:02 ` Palmer Dabbelt [this message]
2020-08-25 12:06 ` [PATCH 2/3] soc: sifive: Add SiFive specific Cadence DDR controller driver Yash Shah
2020-08-25 16:02 ` Palmer Dabbelt
2020-08-25 12:06 ` [PATCH 3/3] edac: sifive: Add EDAC support for Memory Controller in SiFive SoCs Yash Shah
2020-08-25 16:02 ` Palmer Dabbelt
2020-08-31 8:52 ` Borislav Petkov
2020-09-02 4:36 ` Yash Shah
2020-08-25 16:02 ` [PATCH 0/3] SiFive DDR controller and EDAC support Palmer Dabbelt
2020-08-25 16:19 ` Borislav Petkov
2020-08-25 16:21 ` Palmer Dabbelt
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