From: Ard Biesheuvel <ardb@kernel.org>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-efi@vger.kernel.org, Ard Biesheuvel <ardb@kernel.org>,
Marc Zyngier <maz@kernel.org>, Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Kees Cook <keescook@chromium.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Mark Brown <broonie@kernel.org>
Subject: [PATCH v3 21/30] arm64: head: remap the kernel text/inittext region read-only
Date: Mon, 11 Apr 2022 11:48:15 +0200 [thread overview]
Message-ID: <20220411094824.4176877-22-ardb@kernel.org> (raw)
In-Reply-To: <20220411094824.4176877-1-ardb@kernel.org>
In order to be able to run with WXN from boot (which could potentially
be under a hypervisor regime that mandates this), update the temporary
kernel page tables with read-only attributes for the text regions before
attempting to execute from them.
This is rather straight-forward for 16k and 64k granule configurations,
as the split between executable and writable regions is guaranteed to be
aligned to the granule used for the early kernel page tables. For 4k, it
involves installing a single table entry and populating it accordingly.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
---
arch/arm64/kernel/head.S | 71 +++++++++++++++++++-
arch/arm64/kernel/vmlinux.lds.S | 2 +-
2 files changed, 69 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 87498e414725..54886c4b6347 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -86,7 +86,7 @@
* x20 primary_entry() .. __primary_switch() CPU boot mode
* x21 primary_entry() .. start_kernel() FDT pointer passed at boot in x0
* x23 __primary_switch() .. relocate_kernel() physical misalignment/KASLR offset
- * x28 create_idmap() callee preserved temp register
+ * x28 create_idmap(), remap_kernel_text() callee preserved temp register
*/
SYM_CODE_START(primary_entry)
bl preserve_boot_args
@@ -372,10 +372,62 @@ SYM_FUNC_START_LOCAL(create_kernel_mapping)
mov x7, SWAPPER_RW_MMUFLAGS
map_memory x0, x1, x5, x6, x7, x3, (VA_BITS - PGDIR_SHIFT), x10, x11, x12, x13, x14
-
ret
SYM_FUNC_END(create_kernel_mapping)
+SYM_FUNC_START_LOCAL(remap_kernel_text)
+ mov x28, lr
+
+ ldr x1, =_text
+ mov x2, x1
+ ldr x3, =__initdata_begin - 1
+ adrp x4, _text
+ bic x4, x4, #SWAPPER_BLOCK_SIZE - 1
+ mov x5, SWAPPER_RX_MMUFLAGS
+ mov x6, #SWAPPER_BLOCK_SHIFT
+ bl remap_region
+
+#if SWAPPER_BLOCK_SHIFT > PAGE_SHIFT
+ /*
+ * If the boundary between inittext and initdata happens to be aligned
+ * sufficiently, we are done here. Otherwise, we have to replace its block
+ * entry with a table entry, and populate the lower level table accordingly.
+ */
+ ldr x3, =__initdata_begin
+ tst x3, #SWAPPER_BLOCK_SIZE - 1
+ b.eq 0f
+
+ /* First, create a table mapping to replace the block mapping */
+ ldr x1, =_text
+ bic x2, x3, #SWAPPER_BLOCK_SIZE - 1
+ adrp x4, init_pg_end - PAGE_SIZE
+ mov x5, #PMD_TYPE_TABLE
+ mov x6, #SWAPPER_BLOCK_SHIFT
+ bl remap_region
+
+ /* Apply executable permissions to the first subregion */
+ adrp x0, init_pg_end - PAGE_SIZE
+ ldr x3, =__initdata_begin - 1
+ bic x1, x3, #SWAPPER_BLOCK_SIZE - 1
+ mov x2, x1
+ adrp x4, __initdata_begin
+ bic x4, x4, #SWAPPER_BLOCK_SIZE - 1
+ mov x5, SWAPPER_RX_MMUFLAGS | PTE_TYPE_PAGE
+ mov x6, #PAGE_SHIFT
+ bl remap_region
+
+ /* Apply writable permissions to the second subregion */
+ ldr x2, =__initdata_begin
+ bic x1, x2, #SWAPPER_BLOCK_SIZE - 1
+ orr x3, x1, #SWAPPER_BLOCK_SIZE - 1
+ adrp x4, __initdata_begin
+ mov x5, SWAPPER_RW_MMUFLAGS | PTE_TYPE_PAGE
+ mov x6, #PAGE_SHIFT
+ bl remap_region
+#endif
+0: ret x28
+SYM_FUNC_END(remap_kernel_text)
+
/*
* Initialize CPU registers with task-specific and cpu-specific context.
*
@@ -805,12 +857,25 @@ SYM_FUNC_START_LOCAL(__primary_switch)
#endif
bl clear_page_tables
bl create_kernel_mapping
+#ifdef CONFIG_RELOCATABLE
+ mov x29, x0 // preserve returned page table pointer
adrp x1, init_pg_dir
load_ttbr1 x1, x2
-#ifdef CONFIG_RELOCATABLE
bl __relocate_kernel
+ adrp x1, reserved_pg_dir
+ load_ttbr1 x1, x2
+
+ tlbi vmalle1
+ dsb nsh
+ isb
+
+ mov x0, x29 // pass page table pointer to remap_kernel_text
#endif
+ bl remap_kernel_text
+ adrp x1, init_pg_dir
+ load_ttbr1 x1, x2
+
ldr x8, =__primary_switched
adrp x0, __PHYS_OFFSET
br x8
diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S
index 21ca72e7ad22..cb4821c411f4 100644
--- a/arch/arm64/kernel/vmlinux.lds.S
+++ b/arch/arm64/kernel/vmlinux.lds.S
@@ -298,7 +298,7 @@ SECTIONS
. = ALIGN(PAGE_SIZE);
init_pg_dir = .;
- . += INIT_DIR_SIZE;
+ . += INIT_DIR_SIZE + PAGE_SIZE;
init_pg_end = .;
. = ALIGN(SEGMENT_ALIGN);
--
2.30.2
next prev parent reply other threads:[~2022-04-11 9:51 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-11 9:47 [PATCH v3 00/30] arm64: support WXN and entry with MMU enabled Ard Biesheuvel
2022-04-11 9:47 ` [PATCH v3 01/30] arm64: head: move kimage_vaddr variable into C file Ard Biesheuvel
2022-04-11 9:47 ` [PATCH v3 02/30] arm64: mm: make vabits_actual a build time constant if possible Ard Biesheuvel
2022-04-11 9:47 ` [PATCH v3 03/30] arm64: head: move assignment of idmap_t0sz to C code Ard Biesheuvel
2022-04-11 9:47 ` [PATCH v3 04/30] arm64: head: drop idmap_ptrs_per_pgd Ard Biesheuvel
2022-04-11 9:47 ` [PATCH v3 05/30] arm64: head: simplify page table mapping macros (slightly) Ard Biesheuvel
2022-04-11 9:48 ` [PATCH v3 06/30] arm64: head: switch to map_memory macro for the extended ID map Ard Biesheuvel
2022-04-11 9:48 ` [PATCH v3 07/30] arm64: head: split off idmap creation code Ard Biesheuvel
2022-04-11 9:48 ` [PATCH v3 08/30] arm64: kernel: drop unnecessary PoC cache clean+invalidate Ard Biesheuvel
2022-04-11 9:48 ` [PATCH v3 09/30] arm64: head: pass ID map root table address to __enable_mmu() Ard Biesheuvel
2022-04-11 9:48 ` [PATCH v3 10/30] arm64: mm: provide idmap pointer to cpu_replace_ttbr1() Ard Biesheuvel
2022-04-11 9:48 ` [PATCH v3 11/30] arm64: head: add helper function to remap regions in early page tables Ard Biesheuvel
2022-04-11 9:48 ` [PATCH v3 12/30] arm64: head: cover entire kernel image in initial ID map Ard Biesheuvel
2022-04-11 9:48 ` [PATCH v3 13/30] arm64: head: use relative references to the RELA and RELR tables Ard Biesheuvel
2022-04-11 9:48 ` [PATCH v3 14/30] arm64: head: create a temporary FDT mapping in the initial ID map Ard Biesheuvel
2022-04-11 9:48 ` [PATCH v3 15/30] arm64: idreg-override: use early FDT mapping in " Ard Biesheuvel
2022-04-11 9:48 ` [PATCH v3 16/30] arm64: head: factor out TTBR1 assignment into a macro Ard Biesheuvel
2022-04-11 9:48 ` [PATCH v3 17/30] arm64: head: populate kernel page tables with MMU and caches on Ard Biesheuvel
2022-04-11 9:48 ` [PATCH v3 18/30] arm64: head: record CPU boot mode after enabling the MMU Ard Biesheuvel
2022-04-11 9:48 ` [PATCH v3 19/30] arm64: kaslr: deal with init called with VA randomization enabled Ard Biesheuvel
2022-04-11 9:48 ` [PATCH v3 20/30] arm64: head: relocate kernel only a single time if KASLR is enabled Ard Biesheuvel
2022-04-11 9:48 ` Ard Biesheuvel [this message]
2022-04-11 9:48 ` [PATCH v3 22/30] arm64: setup: drop early FDT pointer helpers Ard Biesheuvel
2022-04-11 9:48 ` [PATCH v3 23/30] arm64: mm: move ro_after_init section into the data segment Ard Biesheuvel
2022-04-11 9:48 ` [PATCH v3 24/30] arm64: mm: add support for WXN memory translation attribute Ard Biesheuvel
2022-04-11 9:48 ` [PATCH v3 25/30] arm64: head: record the MMU state at primary entry Ard Biesheuvel
2022-04-11 9:48 ` [PATCH v3 26/30] arm64: head: avoid cache invalidation when entering with the MMU on Ard Biesheuvel
2022-04-11 9:48 ` [PATCH v3 27/30] arm64: head: clean the ID map page to the PoC Ard Biesheuvel
2022-04-11 9:48 ` [PATCH v3 28/30] efi: libstub: pass image handle to handle_kernel_image() Ard Biesheuvel
2022-04-11 9:48 ` [PATCH v3 29/30] efi/arm64: libstub: run image in place if randomized by the loader Ard Biesheuvel
2022-04-11 9:48 ` [PATCH v3 30/30] arm64: efi/libstub: enter with the MMU on if executing in place Ard Biesheuvel
2022-04-12 16:59 ` [PATCH v3 00/30] arm64: support WXN and entry with MMU enabled Kees Cook
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