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* [PATCH v1 01/10] pinctrl: intel: Disable input and output buffer when switching to GPIO
@ 2020-06-10 18:35 Andy Shevchenko
  2020-06-10 18:35 ` [PATCH v1 02/10] pinctrl: intel: Reduce scope of the lock Andy Shevchenko
                   ` (9 more replies)
  0 siblings, 10 replies; 11+ messages in thread
From: Andy Shevchenko @ 2020-06-10 18:35 UTC (permalink / raw)
  To: Mika Westerberg, linux-gpio, Linus Walleij; +Cc: Andy Shevchenko

It's possible scenario that pin has been in different mode, while
the respective GPIO register has a leftover output buffer enabled.
In such case when we request GPIO it will switch to GPIO mode, and
thus to output with unknown value, followed by switching to input
mode. This can produce a glitch on the pin.

Disable input and output buffer when switching to GPIO to avoid
potential glitches.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/pinctrl/intel/pinctrl-intel.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c
index 6a274e20d926..9df5a0c0d416 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.c
+++ b/drivers/pinctrl/intel/pinctrl-intel.c
@@ -435,11 +435,20 @@ static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
 {
 	u32 value;
 
+	value = readl(padcfg0);
+
 	/* Put the pad into GPIO mode */
-	value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
+	value &= ~PADCFG0_PMODE_MASK;
+	value |= PADCFG0_PMODE_GPIO;
+
+	/* Disable input and output buffers */
+	value &= ~PADCFG0_GPIORXDIS;
+	value &= ~PADCFG0_GPIOTXDIS;
+
 	/* Disable SCI/SMI/NMI generation */
 	value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
 	value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
+
 	writel(value, padcfg0);
 }
 
@@ -1036,6 +1045,9 @@ static int intel_gpio_irq_type(struct irq_data *d, unsigned int type)
 
 	intel_gpio_set_gpio_mode(reg);
 
+	/* Disable TX buffer and enable RX (this will be input) */
+	__intel_gpio_set_direction(reg, true);
+
 	value = readl(reg);
 
 	value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
-- 
2.27.0.rc2


^ permalink raw reply related	[flat|nested] 11+ messages in thread

end of thread, other threads:[~2020-06-12 14:33 UTC | newest]

Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-06-10 18:35 [PATCH v1 01/10] pinctrl: intel: Disable input and output buffer when switching to GPIO Andy Shevchenko
2020-06-10 18:35 ` [PATCH v1 02/10] pinctrl: intel: Reduce scope of the lock Andy Shevchenko
2020-06-10 18:35 ` [PATCH v1 03/10] pinctrl: intel: Make use of IRQ_RETVAL() Andy Shevchenko
2020-06-10 18:35 ` [PATCH v1 04/10] pinctrl: intel: Split intel_config_get() to three functions Andy Shevchenko
2020-06-10 18:35 ` [PATCH v1 05/10] pinctrl: intel: Get rid of redundant 'else' in intel_config_set_debounce() Andy Shevchenko
2020-06-10 18:35 ` [PATCH v1 06/10] pinctrl: intel: Drop the only label in the code for consistency Andy Shevchenko
2020-06-10 18:35 ` [PATCH v1 07/10] pinctrl: intel: Protect IO in few call backs by lock Andy Shevchenko
2020-06-10 18:35 ` [PATCH v1 08/10] pinctrl: intel: Introduce for_each_requested_gpio() macro Andy Shevchenko
2020-06-10 18:35 ` [PATCH v1 09/10] pinctrl: intel: Make use of for_each_requested_gpio() Andy Shevchenko
2020-06-10 18:35 ` [PATCH v1 10/10] pinctrl: lynxpoint: " Andy Shevchenko
2020-06-12 14:33 ` [PATCH v1 01/10] pinctrl: intel: Disable input and output buffer when switching to GPIO Andy Shevchenko

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