linux-gpio.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
* [PATCH -next v1 0/1] gpio-aspeed-sgpio: Fix irq handling issue.
@ 2021-09-07  9:55 Steven Lee
  2021-09-07  9:55 ` [PATCH -next v1 1/1] gpio: gpio-aspeed-sgpio: Fix wrong hwirq in irq handler Steven Lee
  0 siblings, 1 reply; 3+ messages in thread
From: Steven Lee @ 2021-09-07  9:55 UTC (permalink / raw)
  To: Linus Walleij, Bartosz Golaszewski, Joel Stanley, Andrew Jeffery,
	open list:GPIO SUBSYSTEM,
	moderated list:ARM/ASPEED MACHINE SUPPORT,
	moderated list:ARM/ASPEED MACHINE SUPPORT, open list
  Cc: steven_lee, Hongweiz, ryan_chen, billy_tsai

SGPIO input/output pin order was changed, thus hwirq should be calculated
based on the new GPIO pin order.
This patch series contains a patch for fixing wrong hwirq in irq handler.

Please help to review.

Thanks,
Steven

Steven Lee (1):
  gpio: gpio-aspeed-sgpio: Fix wrong hwirq in irq handler.

 drivers/gpio/gpio-aspeed-sgpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--
2.17.1


^ permalink raw reply	[flat|nested] 3+ messages in thread

* [PATCH -next v1 1/1] gpio: gpio-aspeed-sgpio: Fix wrong hwirq in irq handler.
  2021-09-07  9:55 [PATCH -next v1 0/1] gpio-aspeed-sgpio: Fix irq handling issue Steven Lee
@ 2021-09-07  9:55 ` Steven Lee
  2021-09-22  9:24   ` Bartosz Golaszewski
  0 siblings, 1 reply; 3+ messages in thread
From: Steven Lee @ 2021-09-07  9:55 UTC (permalink / raw)
  To: Linus Walleij, Bartosz Golaszewski, Joel Stanley, Andrew Jeffery,
	open list:GPIO SUBSYSTEM,
	moderated list:ARM/ASPEED MACHINE SUPPORT,
	moderated list:ARM/ASPEED MACHINE SUPPORT, open list
  Cc: steven_lee, Hongweiz, ryan_chen, billy_tsai

The current hwirq is calculated based on the old GPIO pin order(input
GPIO range is from 0 to ngpios - 1).
It should be calculated based on the current GPIO input pin order(input
GPIOs are 0, 2, 4, ..., (ngpios - 1) * 2).

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
---
 drivers/gpio/gpio-aspeed-sgpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
index 10f303d15225..3d6ef37a7702 100644
--- a/drivers/gpio/gpio-aspeed-sgpio.c
+++ b/drivers/gpio/gpio-aspeed-sgpio.c
@@ -395,7 +395,7 @@ static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
 		reg = ioread32(bank_reg(data, bank, reg_irq_status));
 
 		for_each_set_bit(p, &reg, 32)
-			generic_handle_domain_irq(gc->irq.domain, i * 32 + p);
+			generic_handle_domain_irq(gc->irq.domain, i * 32 + p * 2);
 	}
 
 	chained_irq_exit(ic, desc);
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 3+ messages in thread

* Re: [PATCH -next v1 1/1] gpio: gpio-aspeed-sgpio: Fix wrong hwirq in irq handler.
  2021-09-07  9:55 ` [PATCH -next v1 1/1] gpio: gpio-aspeed-sgpio: Fix wrong hwirq in irq handler Steven Lee
@ 2021-09-22  9:24   ` Bartosz Golaszewski
  0 siblings, 0 replies; 3+ messages in thread
From: Bartosz Golaszewski @ 2021-09-22  9:24 UTC (permalink / raw)
  To: Steven Lee
  Cc: Linus Walleij, Joel Stanley, Andrew Jeffery,
	open list:GPIO SUBSYSTEM,
	moderated list:ARM/ASPEED MACHINE SUPPORT,
	moderated list:ARM/ASPEED MACHINE SUPPORT, open list,
	Hongwei Zhang, Ryan Chen, Billy Tsai

On Tue, Sep 7, 2021 at 11:55 AM Steven Lee <steven_lee@aspeedtech.com> wrote:
>
> The current hwirq is calculated based on the old GPIO pin order(input
> GPIO range is from 0 to ngpios - 1).
> It should be calculated based on the current GPIO input pin order(input
> GPIOs are 0, 2, 4, ..., (ngpios - 1) * 2).
>
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> ---
>  drivers/gpio/gpio-aspeed-sgpio.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
> index 10f303d15225..3d6ef37a7702 100644
> --- a/drivers/gpio/gpio-aspeed-sgpio.c
> +++ b/drivers/gpio/gpio-aspeed-sgpio.c
> @@ -395,7 +395,7 @@ static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
>                 reg = ioread32(bank_reg(data, bank, reg_irq_status));
>
>                 for_each_set_bit(p, &reg, 32)
> -                       generic_handle_domain_irq(gc->irq.domain, i * 32 + p);
> +                       generic_handle_domain_irq(gc->irq.domain, i * 32 + p * 2);
>         }
>
>         chained_irq_exit(ic, desc);
> --
> 2.17.1
>

Applied for fixes, thanks!

Bart

^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2021-09-22  9:24 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-09-07  9:55 [PATCH -next v1 0/1] gpio-aspeed-sgpio: Fix irq handling issue Steven Lee
2021-09-07  9:55 ` [PATCH -next v1 1/1] gpio: gpio-aspeed-sgpio: Fix wrong hwirq in irq handler Steven Lee
2021-09-22  9:24   ` Bartosz Golaszewski

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).