* [PATCH v4 00/16] Allwinner A100 Initial support
@ 2020-07-14 6:55 Frank Lee
2020-07-14 7:03 ` [PATCH v4 03/16] dt-bindings: pinctrl: sunxi: Get rid of continual nesting Frank Lee
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: Frank Lee @ 2020-07-14 6:55 UTC (permalink / raw)
To: robh+dt, mripard, wens, mturquette, sboyd, gregory.clement, tglx,
jason, maz, srinivas.kandagatla, linus.walleij, anarsoul,
tiny.windzz, rui.zhang, daniel.lezcano, amit.kucheria, lee.jones,
p.zabel, clabbe, icenowy, megous, stefan, bage, devicetree
Cc: linux-arm-kernel, linux-kernel, linux-clk, linux-i2c, linux-gpio,
linux-pm, Yangtao Li
From: Yangtao Li <frank@allwinnertech.com>
This patch set adds initial support for allwinner a100 soc,
which is a 64-bit tablet chip.
v4:
-drop "dt-bindings: pinctrl: sunxi: make gpio banks supplies required"
-fix dcdc1 regulator name
-get rid of underscore in dts node name
-Some trivial things in yaml files
v3:
-Add pmu and nmi support
-Add read data mask for calibration
-Code style
-Some trivial things in yaml files
v2:
-Some naming consistency
-Repair email address
-Fix mmc clock
-Don't export system clock
-Fix checkpatch warning
-Drop unneeded pin function, convert to jtag_gpu and i2s_x
Yangtao Li (16):
dt-bindings: clk: sunxi-ccu: add compatible string for A100 CCU and
R-CCU
clk: sunxi-ng: add support for the Allwinner A100 CCU
dt-bindings: pinctrl: sunxi: Get rid of continual nesting
dt-bindings: pinctrl: sunxi: Add A100 pinctrl bindings
pinctrl: sunxi: add support for the Allwinner A100 pin controller
dt-bindings: nvmem: SID: add binding for A100's SID controller
dt-bindings: thermal: sun8i: Add binding for A100's THS controller
thermal: sun8i: add TEMP_CALIB_MASK for calibration data in
sun50i_h6_ths_calibrate
thermal: sun8i: Add A100's THS controller support
mfd: axp20x: Allow the AXP803 to be probed by I2C
dt-bindings: irq: sun7i-nmi: fix dt-binding for a80 nmi
dt-bindings: irq: sun7i-nmi: Add binding for A100's NMI controller
dt-bindings: i2c: mv64xxx: Add compatible for the A100 i2c node.
arm64: allwinner: A100: add the basical Allwinner A100 DTSI file
dt-bindings: arm: sunxi: Add Allwinner A100 Perf1 Board bindings
arm64: allwinner: A100: add support for Allwinner Perf1 board
.../devicetree/bindings/arm/sunxi.yaml | 5 +
.../clock/allwinner,sun4i-a10-ccu.yaml | 7 +-
.../bindings/i2c/marvell,mv64xxx-i2c.yaml | 3 +
.../allwinner,sun7i-a20-sc-nmi.yaml | 5 +-
.../nvmem/allwinner,sun4i-a10-sid.yaml | 19 +-
.../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 139 +-
.../thermal/allwinner,sun8i-a83t-ths.yaml | 6 +-
arch/arm64/boot/dts/allwinner/Makefile | 1 +
.../allwinner/sun50i-a100-allwinner-perf1.dts | 180 +++
.../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 364 +++++
drivers/clk/sunxi-ng/Kconfig | 10 +
drivers/clk/sunxi-ng/Makefile | 2 +
drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c | 214 +++
drivers/clk/sunxi-ng/ccu-sun50i-a100-r.h | 21 +
drivers/clk/sunxi-ng/ccu-sun50i-a100.c | 1276 +++++++++++++++++
drivers/clk/sunxi-ng/ccu-sun50i-a100.h | 56 +
drivers/mfd/axp20x-i2c.c | 2 +
drivers/pinctrl/sunxi/Kconfig | 10 +
drivers/pinctrl/sunxi/Makefile | 2 +
drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c | 105 ++
drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 708 +++++++++
drivers/thermal/sun8i_thermal.c | 16 +-
include/dt-bindings/clock/sun50i-a100-ccu.h | 116 ++
include/dt-bindings/clock/sun50i-a100-r-ccu.h | 23 +
include/dt-bindings/reset/sun50i-a100-ccu.h | 68 +
include/dt-bindings/reset/sun50i-a100-r-ccu.h | 18 +
26 files changed, 3308 insertions(+), 68 deletions(-)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100-r.h
create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100.h
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
create mode 100644 include/dt-bindings/clock/sun50i-a100-ccu.h
create mode 100644 include/dt-bindings/clock/sun50i-a100-r-ccu.h
create mode 100644 include/dt-bindings/reset/sun50i-a100-ccu.h
create mode 100644 include/dt-bindings/reset/sun50i-a100-r-ccu.h
--
2.24.0
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v4 03/16] dt-bindings: pinctrl: sunxi: Get rid of continual nesting
2020-07-14 6:55 [PATCH v4 00/16] Allwinner A100 Initial support Frank Lee
@ 2020-07-14 7:03 ` Frank Lee
2020-07-14 20:50 ` Rob Herring
2020-07-14 7:06 ` [PATCH v4 04/16] dt-bindings: pinctrl: sunxi: Add A100 pinctrl bindings Frank Lee
` (2 subsequent siblings)
3 siblings, 1 reply; 8+ messages in thread
From: Frank Lee @ 2020-07-14 7:03 UTC (permalink / raw)
To: linus.walleij, robh+dt, mripard, wens, linux-gpio, devicetree,
linux-arm-kernel, linux-kernel
Cc: tiny.windzz, huangshuosheng, liyong, Yangtao Li
From: Yangtao Li <frank@allwinnertech.com>
Rather than a continual nesting of 'else' clauses, just make
each 'if' a new entry under 'allOf' and get rid of the else.
Signed-off-by: Yangtao Li <frank@allwinnertech.com>
---
.../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 124 ++++++++++--------
1 file changed, 68 insertions(+), 56 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
index 7556be6e2754..35a26abb02e7 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
@@ -155,62 +155,74 @@ allOf:
minItems: 5
maxItems: 5
- else:
- if:
- properties:
- compatible:
- enum:
- - allwinner,sun6i-a31-pinctrl
- - allwinner,sun6i-a31s-pinctrl
- - allwinner,sun50i-h6-pinctrl
-
- then:
- properties:
- interrupts:
- minItems: 4
- maxItems: 4
-
- else:
- if:
- properties:
- compatible:
- enum:
- - allwinner,sun8i-a23-pinctrl
- - allwinner,sun8i-a83t-pinctrl
- - allwinner,sun50i-a64-pinctrl
- - allwinner,sun50i-h5-pinctrl
- - allwinner,suniv-f1c100s-pinctrl
-
- then:
- properties:
- interrupts:
- minItems: 3
- maxItems: 3
-
- else:
- if:
- properties:
- compatible:
- enum:
- - allwinner,sun6i-a31-r-pinctrl
- - allwinner,sun8i-a33-pinctrl
- - allwinner,sun8i-h3-pinctrl
- - allwinner,sun8i-v3-pinctrl
- - allwinner,sun8i-v3s-pinctrl
- - allwinner,sun9i-a80-r-pinctrl
- - allwinner,sun50i-h6-r-pinctrl
-
- then:
- properties:
- interrupts:
- minItems: 2
- maxItems: 2
-
- else:
- properties:
- interrupts:
- minItems: 1
- maxItems: 1
+ - if:
+ properties:
+ compatible:
+ enum:
+ - allwinner,sun6i-a31-pinctrl
+ - allwinner,sun6i-a31s-pinctrl
+ - allwinner,sun50i-h6-pinctrl
+
+ then:
+ properties:
+ interrupts:
+ minItems: 4
+ maxItems: 4
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - allwinner,sun8i-a23-pinctrl
+ - allwinner,sun8i-a83t-pinctrl
+ - allwinner,sun50i-a64-pinctrl
+ - allwinner,sun50i-h5-pinctrl
+ - allwinner,suniv-f1c100s-pinctrl
+
+ then:
+ properties:
+ interrupts:
+ minItems: 3
+ maxItems: 3
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - allwinner,sun6i-a31-r-pinctrl
+ - allwinner,sun8i-a33-pinctrl
+ - allwinner,sun8i-h3-pinctrl
+ - allwinner,sun8i-v3-pinctrl
+ - allwinner,sun8i-v3s-pinctrl
+ - allwinner,sun9i-a80-r-pinctrl
+ - allwinner,sun50i-h6-r-pinctrl
+
+ then:
+ properties:
+ interrupts:
+ minItems: 2
+ maxItems: 2
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - allwinner,sun4i-a10-pinctrl
+ - allwinner,sun5i-a10s-pinctrl
+ - allwinner,sun5i-a13-pinctrl
+ - allwinner,sun7i-a20-pinctrl
+ - allwinner,sun8i-a23-r-pinctrl
+ - allwinner,sun8i-a83t-r-pinctrl
+ - allwinner,sun8i-h3-r-pinctrl
+ - allwinner,sun8i-r40-pinctrl
+ - allwinner,sun50i-a64-r-pinctrl
+ - nextthing,gr8-pinctrl
+
+ then:
+ properties:
+ interrupts:
+ minItems: 1
+ maxItems: 1
additionalProperties: false
--
2.24.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v4 04/16] dt-bindings: pinctrl: sunxi: Add A100 pinctrl bindings
2020-07-14 6:55 [PATCH v4 00/16] Allwinner A100 Initial support Frank Lee
2020-07-14 7:03 ` [PATCH v4 03/16] dt-bindings: pinctrl: sunxi: Get rid of continual nesting Frank Lee
@ 2020-07-14 7:06 ` Frank Lee
2020-07-14 20:51 ` Rob Herring
2020-07-14 7:07 ` [PATCH v4 05/16] pinctrl: sunxi: add support for the Allwinner A100 pin controller Frank Lee
2020-07-17 4:28 ` [PATCH v4 00/16] Allwinner A100 Initial support Daniel Lezcano
3 siblings, 1 reply; 8+ messages in thread
From: Frank Lee @ 2020-07-14 7:06 UTC (permalink / raw)
To: linus.walleij, robh+dt, mripard, wens
Cc: linux-gpio, devicetree, linux-arm-kernel, linux-kernel,
tiny.windzz, huangshuosheng, liyong, Yangtao Li
From: Yangtao Li <frank@allwinnertech.com>
Add device tree binding Documentation details for A100 pinctrl driver,
which has a r pin controller and a pin controller with more irq lines.
Signed-off-by: Yangtao Li <frank@allwinnertech.com>
---
.../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
index 35a26abb02e7..34a17d5c6135 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
@@ -48,6 +48,8 @@ properties:
- allwinner,sun9i-a80-r-pinctrl
- allwinner,sun50i-a64-pinctrl
- allwinner,sun50i-a64-r-pinctrl
+ - allwinner,sun50i-a100-pinctrl
+ - allwinner,sun50i-a100-r-pinctrl
- allwinner,sun50i-h5-pinctrl
- allwinner,sun50i-h6-pinctrl
- allwinner,sun50i-h6-r-pinctrl
@@ -143,6 +145,18 @@ allOf:
# boards are defining it at the moment so it would generate a lot of
# warnings.
+ - if:
+ properties:
+ compatible:
+ enum:
+ - allwinner,sun50i-a100-pinctrl
+
+ then:
+ properties:
+ interrupts:
+ minItems: 7
+ maxItems: 7
+
- if:
properties:
compatible:
@@ -216,6 +230,7 @@ allOf:
- allwinner,sun8i-h3-r-pinctrl
- allwinner,sun8i-r40-pinctrl
- allwinner,sun50i-a64-r-pinctrl
+ - allwinner,sun50i-a100-r-pinctrl
- nextthing,gr8-pinctrl
then:
--
2.24.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v4 05/16] pinctrl: sunxi: add support for the Allwinner A100 pin controller
2020-07-14 6:55 [PATCH v4 00/16] Allwinner A100 Initial support Frank Lee
2020-07-14 7:03 ` [PATCH v4 03/16] dt-bindings: pinctrl: sunxi: Get rid of continual nesting Frank Lee
2020-07-14 7:06 ` [PATCH v4 04/16] dt-bindings: pinctrl: sunxi: Add A100 pinctrl bindings Frank Lee
@ 2020-07-14 7:07 ` Frank Lee
2020-07-17 4:28 ` [PATCH v4 00/16] Allwinner A100 Initial support Daniel Lezcano
3 siblings, 0 replies; 8+ messages in thread
From: Frank Lee @ 2020-07-14 7:07 UTC (permalink / raw)
To: linus.walleij, mripard, wens, linux-kernel, linux-gpio, linux-arm-kernel
Cc: tiny.windzz, huangshuosheng, liyong, Yangtao Li
From: Yangtao Li <frank@allwinnertech.com>
This commit introduces support for the pin controller on A100.
Signed-off-by: Yangtao Li <frank@allwinnertech.com>
---
drivers/pinctrl/sunxi/Kconfig | 10 +
drivers/pinctrl/sunxi/Makefile | 2 +
drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c | 105 +++
drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 708 ++++++++++++++++++
4 files changed, 825 insertions(+)
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index f7aae200ee15..593293584ecc 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -94,6 +94,16 @@ config PINCTRL_SUN50I_A64_R
default ARM64 && ARCH_SUNXI
select PINCTRL_SUNXI
+config PINCTRL_SUN50I_A100
+ bool "Support for the Allwinner A100 PIO"
+ default ARM64 && ARCH_SUNXI
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_A100_R
+ bool "Support for the Allwinner A100 R-PIO"
+ default ARM64 && ARCH_SUNXI
+ select PINCTRL_SUNXI
+
config PINCTRL_SUN50I_H5
bool "Support for the Allwinner H5 PIO"
default ARM64 && ARCH_SUNXI
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index fafcdae8134f..8b7ff0dc3bdf 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -13,6 +13,8 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o
obj-$(CONFIG_PINCTRL_SUN8I_A33) += pinctrl-sun8i-a33.o
obj-$(CONFIG_PINCTRL_SUN50I_A64) += pinctrl-sun50i-a64.o
obj-$(CONFIG_PINCTRL_SUN50I_A64_R) += pinctrl-sun50i-a64-r.o
+obj-$(CONFIG_PINCTRL_SUN50I_A100) += pinctrl-sun50i-a100.o
+obj-$(CONFIG_PINCTRL_SUN50I_A100_R) += pinctrl-sun50i-a100-r.o
obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o
obj-$(CONFIG_PINCTRL_SUN8I_A83T_R) += pinctrl-sun8i-a83t-r.o
obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c
new file mode 100644
index 000000000000..21054fcacd34
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
+ *
+ * Based on:
+ * huangshuosheng <huangshuosheng@allwinnertech.com>
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin a100_r_pins[] = {
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_i2c0"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_i2c0"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_uart0"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_uart0"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"), /* MS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"), /* CK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"), /* DO */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"), /* DI */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_i2c1"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_i2c1"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_pwm"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "s_cir"), /* IN */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)),
+};
+
+static const struct sunxi_pinctrl_desc a100_r_pinctrl_data = {
+ .pins = a100_r_pins,
+ .npins = ARRAY_SIZE(a100_r_pins),
+ .pin_base = PL_BASE,
+ .irq_banks = 1,
+};
+
+static int a100_r_pinctrl_probe(struct platform_device *pdev)
+{
+ return sunxi_pinctrl_init(pdev, &a100_r_pinctrl_data);
+}
+
+static const struct of_device_id a100_r_pinctrl_match[] = {
+ { .compatible = "allwinner,sun50i-a100-r-pinctrl", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, a100_r_pinctrl_match);
+
+static struct platform_driver a100_r_pinctrl_driver = {
+ .probe = a100_r_pinctrl_probe,
+ .driver = {
+ .name = "sun50iw10p1-r-pinctrl",
+ .of_match_table = a100_r_pinctrl_match,
+ },
+};
+module_platform_driver(a100_r_pinctrl_driver);
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
new file mode 100644
index 000000000000..19cfd1e76ee2
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
@@ -0,0 +1,708 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
+ *
+ * Based on:
+ * huangshuosheng <huangshuosheng@allwinnertech.com>
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin a100_pins[] = {
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* TX */
+ SUNXI_FUNCTION(0x3, "spi2"), /* CS */
+ SUNXI_FUNCTION(0x4, "jtag"), /* MS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* RX */
+ SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
+ SUNXI_FUNCTION(0x4, "jtag"), /* CK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
+ SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
+ SUNXI_FUNCTION(0x4, "jtag"), /* DO */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
+ SUNXI_FUNCTION(0x3, "spi2"), /* MISO */
+ SUNXI_FUNCTION(0x4, "jtag"), /* DI */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
+ SUNXI_FUNCTION(0x3, "i2s0"), /* MCLK */
+ SUNXI_FUNCTION(0x4, "jtag_gpu"), /* MS_GPU */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */
+ SUNXI_FUNCTION(0x3, "i2s0"), /* BCLK */
+ SUNXI_FUNCTION(0x4, "jtag_gpu"), /* CK_GPU */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "i2s0"), /* LRCK */
+ SUNXI_FUNCTION(0x4, "jtag_gpu"), /* DO_GPU */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spdif"), /* DIN */
+ SUNXI_FUNCTION(0x3, "i2s0_dout0"), /* DOUT0 */
+ SUNXI_FUNCTION(0x4, "i2s0_din1"), /* DIN1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spdif"), /* DOUT */
+ SUNXI_FUNCTION(0x3, "i2s0_din0"), /* DIN0 */
+ SUNXI_FUNCTION(0x4, "i2s0_dout1"), /* DOUT1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart0"), /* TX */
+ SUNXI_FUNCTION(0x3, "i2c0"), /* SCK */
+ SUNXI_FUNCTION(0x4, "jtag_gpu"), /* DI_GPU */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart0"), /* RX */
+ SUNXI_FUNCTION(0x3, "i2c0"), /* SDA */
+ SUNXI_FUNCTION(0x4, "pwm1"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),
+ /* HOLE */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* WE */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* DS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* RST */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
+ SUNXI_FUNCTION(0x4, "spi0"), /* MOSI */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */
+ SUNXI_FUNCTION(0x4, "spi0"), /* CS0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* CE0 */
+ SUNXI_FUNCTION(0x4, "spi0"), /* MISO */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* RE */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */
+ SUNXI_FUNCTION(0x4, "spi0"), /* CS1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D3 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D4 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D5 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
+ SUNXI_FUNCTION(0x4, "spi0"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D6 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 14)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D2 */
+ SUNXI_FUNCTION(0x4, "spi0"), /* WP */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D7 */
+ SUNXI_FUNCTION(0x4, "spi0"), /* HOLD */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 16)),
+ /* HOLE */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* D0P */
+ SUNXI_FUNCTION(0x4, "dsi0"), /* DP0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* D0N */
+ SUNXI_FUNCTION(0x4, "dsi0"), /* DM0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* D1P */
+ SUNXI_FUNCTION(0x4, "dsi0"), /* DP1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* D1N */
+ SUNXI_FUNCTION(0x4, "dsi0"), /* DM1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* D2P */
+ SUNXI_FUNCTION(0x4, "dsi0"), /* CKP */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* D2N */
+ SUNXI_FUNCTION(0x4, "dsi0"), /* CKM */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* CKP */
+ SUNXI_FUNCTION(0x4, "dsi0"), /* DP2 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* CKN */
+ SUNXI_FUNCTION(0x4, "dsi0"), /* DM2 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
+ SUNXI_FUNCTION(0x4, "dsi0"), /* DP3 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
+ SUNXI_FUNCTION(0x4, "dsi0"), /* DM3 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
+ SUNXI_FUNCTION(0x4, "spi1"), /* CS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
+ SUNXI_FUNCTION(0x4, "spi1"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
+ SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
+ SUNXI_FUNCTION(0x4, "spi1"), /* MISO */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
+ SUNXI_FUNCTION(0x4, "uart3"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
+ SUNXI_FUNCTION(0x4, "uart3"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
+ SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
+ SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 17)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
+ SUNXI_FUNCTION(0x4, "uart4"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 18)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
+ SUNXI_FUNCTION(0x4, "uart4"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 19)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
+ SUNXI_FUNCTION(0x3, "pwm2"),
+ SUNXI_FUNCTION(0x4, "uart4"), /* RTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 20)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
+ SUNXI_FUNCTION(0x3, "pwm3"),
+ SUNXI_FUNCTION(0x4, "uart4"), /* CTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 21)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "pwm1"),
+ SUNXI_FUNCTION(0x4, "i2c0"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 22)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "pwm0"),
+ SUNXI_FUNCTION(0x4, "i2c0"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 23)),
+ /* HOLE */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c2"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c2"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
+ SUNXI_FUNCTION(0x3, "pll"), /* LOCK_DBG */
+ SUNXI_FUNCTION(0x4, "i2s2"), /* MCLK */
+ SUNXI_FUNCTION(0x5, "ledc"), /* LEDC */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "bist0"), /* RESULT0 */
+ SUNXI_FUNCTION(0x4, "i2s2"), /* BCLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* SM_VS */
+ SUNXI_FUNCTION(0x3, "bist0"), /* RESULT1 */
+ SUNXI_FUNCTION(0x4, "i2s2"), /* LRCK */
+ SUNXI_FUNCTION(0x5, "tcon0"), /* TRIG */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "bist0"), /* RESULT2 */
+ SUNXI_FUNCTION(0x4, "i2s2"), /* DOUT0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "bist0"), /* RESULT3 */
+ SUNXI_FUNCTION(0x4, "i2s2"), /* DIN0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)),
+ /* HOLE */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
+ SUNXI_FUNCTION(0x3, "jtag"), /* MS1 */
+ SUNXI_FUNCTION(0x4, "jtag_gpu"), /* MS_GPU */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 0)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
+ SUNXI_FUNCTION(0x3, "jtag"), /* DI1 */
+ SUNXI_FUNCTION(0x4, "jtag_gpu"), /* DI_GPU */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 1)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
+ SUNXI_FUNCTION(0x3, "uart0"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 2)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
+ SUNXI_FUNCTION(0x3, "jtag"), /* DO */
+ SUNXI_FUNCTION(0x4, "jtag_gpu"), /* DO_GPU */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 3)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
+ SUNXI_FUNCTION(0x3, "uart0"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
+ SUNXI_FUNCTION(0x3, "jtag"), /* CK */
+ SUNXI_FUNCTION(0x4, "jtag_gpu"), /* CK_GPU */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 5)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 6)),
+ /* HOLE */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 0)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 1)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 2)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 3)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 4)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 5)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart1"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 6)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart1"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 7)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 8)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
+ SUNXI_FUNCTION(0x3, "i2s1"), /* MCLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 9)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "i2s1"), /* BCLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 10)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "i2s1"), /* LRCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 11)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "i2s1_dout0"), /* DOUT0 */
+ SUNXI_FUNCTION(0x4, "i2s1_din1"), /* DIN1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 12)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "i2s1_din0"), /* DIN0 */
+ SUNXI_FUNCTION(0x4, "i2s1_dout1"), /* DOUT1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 13)),
+ /* HOLE */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
+ SUNXI_FUNCTION(0x5, "emac0"), /* RXD1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 0)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
+ SUNXI_FUNCTION(0x5, "emac0"), /* RXD0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 1)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
+ SUNXI_FUNCTION(0x5, "emac0"), /* RXCTL */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 2)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */
+ SUNXI_FUNCTION(0x3, "cir0"), /* OUT */
+ SUNXI_FUNCTION(0x5, "emac0"), /* CLKIN */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 3)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart3"), /* TX */
+ SUNXI_FUNCTION(0x3, "spi1"), /* CS */
+ SUNXI_FUNCTION(0x5, "emac0"), /* TXD1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 4)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart3"), /* RX */
+ SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
+ SUNXI_FUNCTION(0x4, "ledc"),
+ SUNXI_FUNCTION(0x5, "emac0"), /* TXD0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 5)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart3"), /* RTS */
+ SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
+ SUNXI_FUNCTION(0x5, "emac0"), /* TXCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 6)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart3"), /* CTS */
+ SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
+ SUNXI_FUNCTION(0x4, "spdif"), /* OUT */
+ SUNXI_FUNCTION(0x5, "emac0"), /* TXCTL */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 7)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "dmic"), /* CLK */
+ SUNXI_FUNCTION(0x3, "spi2"), /* CS */
+ SUNXI_FUNCTION(0x4, "i2s2"), /* MCLK */
+ SUNXI_FUNCTION(0x5, "i2s2_din2"), /* DIN2 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 8)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "dmic"), /* DATA0 */
+ SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
+ SUNXI_FUNCTION(0x4, "i2s2"), /* BCLK */
+ SUNXI_FUNCTION(0x5, "emac0"), /* MDC */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 9)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "dmic"), /* DATA1 */
+ SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
+ SUNXI_FUNCTION(0x4, "i2s2"), /* LRCK */
+ SUNXI_FUNCTION(0x5, "emac0"), /* MDIO */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 10)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "dmic"), /* DATA2 */
+ SUNXI_FUNCTION(0x3, "spi2"), /* MISO */
+ SUNXI_FUNCTION(0x4, "i2s2_dout0"), /* DOUT0 */
+ SUNXI_FUNCTION(0x5, "i2s2_din1"), /* DIN1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 11)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "dmic"), /* DATA3 */
+ SUNXI_FUNCTION(0x3, "i2c3"), /* SCK */
+ SUNXI_FUNCTION(0x4, "i2s2_din0"), /* DIN0 */
+ SUNXI_FUNCTION(0x5, "i2s2_dout1"), /* DOUT1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 12)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "i2c3"), /* SCK */
+ SUNXI_FUNCTION(0x4, "i2s3"), /* MCLK */
+ SUNXI_FUNCTION(0x5, "emac0"), /* EPHY */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 13)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x4, "i2s3"), /* BCLK */
+ SUNXI_FUNCTION(0x5, "emac0"), /* RXD3 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 14)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x4, "i2s3"), /* LRCK */
+ SUNXI_FUNCTION(0x5, "emac0"), /* RXD2 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 15)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "i2s3_dout0"), /* DOUT0 */
+ SUNXI_FUNCTION(0x4, "i2s3_din1"), /* DIN1 */
+ SUNXI_FUNCTION(0x5, "emac0"), /* RXCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 16)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "i2s3_dout1"), /* DOUT1 */
+ SUNXI_FUNCTION(0x4, "i2s3_din0"), /* DIN0 */
+ SUNXI_FUNCTION(0x5, "emac0"), /* TXD3 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 17)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "cir0"), /* OUT */
+ SUNXI_FUNCTION(0x3, "i2s3_dout2"), /* DOUT2 */
+ SUNXI_FUNCTION(0x4, "i2s3_din2"), /* DIN2 */
+ SUNXI_FUNCTION(0x5, "emac0"), /* TXD2 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 18)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "cir0"), /* IN */
+ SUNXI_FUNCTION(0x3, "i2s3_dout3"), /* DOUT3 */
+ SUNXI_FUNCTION(0x4, "i2s3_din3"), /* DIN3 */
+ SUNXI_FUNCTION(0x5, "ledc"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 19)),
+};
+
+static const unsigned int a100_irq_bank_map[] = { 0, 1, 2, 3, 4, 5, 6};
+
+static const struct sunxi_pinctrl_desc a100_pinctrl_data = {
+ .pins = a100_pins,
+ .npins = ARRAY_SIZE(a100_pins),
+ .irq_banks = 7,
+ .irq_bank_map = a100_irq_bank_map,
+ .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
+};
+
+static int a100_pinctrl_probe(struct platform_device *pdev)
+{
+ return sunxi_pinctrl_init(pdev, &a100_pinctrl_data);
+}
+
+static const struct of_device_id a100_pinctrl_match[] = {
+ { .compatible = "allwinner,sun50i-a100-pinctrl", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, a100_pinctrl_match);
+
+static struct platform_driver a100_pinctrl_driver = {
+ .probe = a100_pinctrl_probe,
+ .driver = {
+ .name = "sun50i-a100-pinctrl",
+ .of_match_table = a100_pinctrl_match,
+ },
+};
+module_platform_driver(a100_pinctrl_driver);
--
2.24.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v4 03/16] dt-bindings: pinctrl: sunxi: Get rid of continual nesting
2020-07-14 7:03 ` [PATCH v4 03/16] dt-bindings: pinctrl: sunxi: Get rid of continual nesting Frank Lee
@ 2020-07-14 20:50 ` Rob Herring
0 siblings, 0 replies; 8+ messages in thread
From: Rob Herring @ 2020-07-14 20:50 UTC (permalink / raw)
To: Frank Lee
Cc: wens, liyong, linux-kernel, robh+dt, devicetree,
linux-arm-kernel, huangshuosheng, mripard, linus.walleij,
tiny.windzz, linux-gpio
On Tue, 14 Jul 2020 15:03:53 +0800, Frank Lee wrote:
> From: Yangtao Li <frank@allwinnertech.com>
>
> Rather than a continual nesting of 'else' clauses, just make
> each 'if' a new entry under 'allOf' and get rid of the else.
>
> Signed-off-by: Yangtao Li <frank@allwinnertech.com>
> ---
> .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 124 ++++++++++--------
> 1 file changed, 68 insertions(+), 56 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v4 04/16] dt-bindings: pinctrl: sunxi: Add A100 pinctrl bindings
2020-07-14 7:06 ` [PATCH v4 04/16] dt-bindings: pinctrl: sunxi: Add A100 pinctrl bindings Frank Lee
@ 2020-07-14 20:51 ` Rob Herring
0 siblings, 0 replies; 8+ messages in thread
From: Rob Herring @ 2020-07-14 20:51 UTC (permalink / raw)
To: Frank Lee
Cc: liyong, linus.walleij, linux-kernel, robh+dt, tiny.windzz,
huangshuosheng, linux-arm-kernel, wens, linux-gpio, mripard,
devicetree
On Tue, 14 Jul 2020 15:06:23 +0800, Frank Lee wrote:
> From: Yangtao Li <frank@allwinnertech.com>
>
> Add device tree binding Documentation details for A100 pinctrl driver,
> which has a r pin controller and a pin controller with more irq lines.
>
> Signed-off-by: Yangtao Li <frank@allwinnertech.com>
> ---
> .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v4 00/16] Allwinner A100 Initial support
2020-07-14 6:55 [PATCH v4 00/16] Allwinner A100 Initial support Frank Lee
` (2 preceding siblings ...)
2020-07-14 7:07 ` [PATCH v4 05/16] pinctrl: sunxi: add support for the Allwinner A100 pin controller Frank Lee
@ 2020-07-17 4:28 ` Daniel Lezcano
2020-07-17 7:38 ` Frank Lee
3 siblings, 1 reply; 8+ messages in thread
From: Daniel Lezcano @ 2020-07-17 4:28 UTC (permalink / raw)
To: Frank Lee, robh+dt, mripard, wens, mturquette, sboyd,
gregory.clement, tglx, jason, maz, srinivas.kandagatla,
linus.walleij, anarsoul, tiny.windzz, rui.zhang, amit.kucheria,
lee.jones, p.zabel, clabbe, icenowy, megous, stefan, bage,
devicetree
Cc: linux-arm-kernel, linux-kernel, linux-clk, linux-i2c, linux-gpio,
linux-pm
On 14/07/2020 08:55, Frank Lee wrote:
> From: Yangtao Li <frank@allwinnertech.com>
Do you expect me to pick patches 7,8,9 or ack them ?
> v4:
> -drop "dt-bindings: pinctrl: sunxi: make gpio banks supplies required"
> -fix dcdc1 regulator name
> -get rid of underscore in dts node name
> -Some trivial things in yaml files
>
> v3:
> -Add pmu and nmi support
> -Add read data mask for calibration
> -Code style
> -Some trivial things in yaml files
>
> v2:
> -Some naming consistency
> -Repair email address
> -Fix mmc clock
> -Don't export system clock
> -Fix checkpatch warning
> -Drop unneeded pin function, convert to jtag_gpu and i2s_x
>
> Yangtao Li (16):
> dt-bindings: clk: sunxi-ccu: add compatible string for A100 CCU and
> R-CCU
> clk: sunxi-ng: add support for the Allwinner A100 CCU
> dt-bindings: pinctrl: sunxi: Get rid of continual nesting
> dt-bindings: pinctrl: sunxi: Add A100 pinctrl bindings
> pinctrl: sunxi: add support for the Allwinner A100 pin controller
> dt-bindings: nvmem: SID: add binding for A100's SID controller
> dt-bindings: thermal: sun8i: Add binding for A100's THS controller
> thermal: sun8i: add TEMP_CALIB_MASK for calibration data in
> sun50i_h6_ths_calibrate
> thermal: sun8i: Add A100's THS controller support
> mfd: axp20x: Allow the AXP803 to be probed by I2C
> dt-bindings: irq: sun7i-nmi: fix dt-binding for a80 nmi
> dt-bindings: irq: sun7i-nmi: Add binding for A100's NMI controller
> dt-bindings: i2c: mv64xxx: Add compatible for the A100 i2c node.
> arm64: allwinner: A100: add the basical Allwinner A100 DTSI file
> dt-bindings: arm: sunxi: Add Allwinner A100 Perf1 Board bindings
> arm64: allwinner: A100: add support for Allwinner Perf1 board
>
> .../devicetree/bindings/arm/sunxi.yaml | 5 +
> .../clock/allwinner,sun4i-a10-ccu.yaml | 7 +-
> .../bindings/i2c/marvell,mv64xxx-i2c.yaml | 3 +
> .../allwinner,sun7i-a20-sc-nmi.yaml | 5 +-
> .../nvmem/allwinner,sun4i-a10-sid.yaml | 19 +-
> .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 139 +-
> .../thermal/allwinner,sun8i-a83t-ths.yaml | 6 +-
> arch/arm64/boot/dts/allwinner/Makefile | 1 +
> .../allwinner/sun50i-a100-allwinner-perf1.dts | 180 +++
> .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 364 +++++
> drivers/clk/sunxi-ng/Kconfig | 10 +
> drivers/clk/sunxi-ng/Makefile | 2 +
> drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c | 214 +++
> drivers/clk/sunxi-ng/ccu-sun50i-a100-r.h | 21 +
> drivers/clk/sunxi-ng/ccu-sun50i-a100.c | 1276 +++++++++++++++++
> drivers/clk/sunxi-ng/ccu-sun50i-a100.h | 56 +
> drivers/mfd/axp20x-i2c.c | 2 +
> drivers/pinctrl/sunxi/Kconfig | 10 +
> drivers/pinctrl/sunxi/Makefile | 2 +
> drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c | 105 ++
> drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 708 +++++++++
> drivers/thermal/sun8i_thermal.c | 16 +-
> include/dt-bindings/clock/sun50i-a100-ccu.h | 116 ++
> include/dt-bindings/clock/sun50i-a100-r-ccu.h | 23 +
> include/dt-bindings/reset/sun50i-a100-ccu.h | 68 +
> include/dt-bindings/reset/sun50i-a100-r-ccu.h | 18 +
> 26 files changed, 3308 insertions(+), 68 deletions(-)
> create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
> create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
> create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100-r.h
> create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100.c
> create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100.h
> create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c
> create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> create mode 100644 include/dt-bindings/clock/sun50i-a100-ccu.h
> create mode 100644 include/dt-bindings/clock/sun50i-a100-r-ccu.h
> create mode 100644 include/dt-bindings/reset/sun50i-a100-ccu.h
> create mode 100644 include/dt-bindings/reset/sun50i-a100-r-ccu.h
>
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v4 00/16] Allwinner A100 Initial support
2020-07-17 4:28 ` [PATCH v4 00/16] Allwinner A100 Initial support Daniel Lezcano
@ 2020-07-17 7:38 ` Frank Lee
0 siblings, 0 replies; 8+ messages in thread
From: Frank Lee @ 2020-07-17 7:38 UTC (permalink / raw)
To: Daniel Lezcano
Cc: Frank Lee, Rob Herring, Maxime Ripard, Chen-Yu Tsai,
Michael Turquette, Stephen Boyd, gregory.clement,
Thomas Gleixner, jason, Marc Zyngier, Srini Kandagatla,
Linus Walleij, Vasily Khoruzhick, Zhang Rui, Amit Kucheria,
Lee Jones, p.zabel, clabbe, Icenowy Zheng, Ondřej Jirman,
stefan, bage, devicetree, Linux ARM, Linux Kernel Mailing List,
linux-clk, linux-i2c, linux-gpio, Linux PM
On Fri, Jul 17, 2020 at 12:28 PM Daniel Lezcano
<daniel.lezcano@linaro.org> wrote:
>
> On 14/07/2020 08:55, Frank Lee wrote:
> > From: Yangtao Li <frank@allwinnertech.com>
>
> Do you expect me to pick patches 7,8,9 or ack them ?
>
Please pick it.
Thx,
Yangtao
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-07-17 7:38 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-07-14 6:55 [PATCH v4 00/16] Allwinner A100 Initial support Frank Lee
2020-07-14 7:03 ` [PATCH v4 03/16] dt-bindings: pinctrl: sunxi: Get rid of continual nesting Frank Lee
2020-07-14 20:50 ` Rob Herring
2020-07-14 7:06 ` [PATCH v4 04/16] dt-bindings: pinctrl: sunxi: Add A100 pinctrl bindings Frank Lee
2020-07-14 20:51 ` Rob Herring
2020-07-14 7:07 ` [PATCH v4 05/16] pinctrl: sunxi: add support for the Allwinner A100 pin controller Frank Lee
2020-07-17 4:28 ` [PATCH v4 00/16] Allwinner A100 Initial support Daniel Lezcano
2020-07-17 7:38 ` Frank Lee
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