* [PATCH v2 00/13] v2: ARM: move lpc32xx to multiplatform
@ 2019-08-09 14:40 Arnd Bergmann
2019-08-09 14:40 ` [PATCH v2 05/13] gpio: lpc32xx: allow building on non-lpc32xx targets Arnd Bergmann
0 siblings, 1 reply; 3+ messages in thread
From: Arnd Bergmann @ 2019-08-09 14:40 UTC (permalink / raw)
To: soc
Cc: Vladimir Zapolskiy, Sylvain Lemieux, linux-arm-kernel,
linux-kernel, Arnd Bergmann, Linus Walleij, David S. Miller,
Greg Kroah-Hartman, Alan Stern, Guenter Roeck, linux-gpio,
netdev, linux-serial, linux-usb, linux-watchdog
Version 2 contains some minor changes based on earlier feedback
and from the 0day build bot testing on other architectures. The
only patch that changed significantly is the one for the gpio driver.
I would suggest we merge this version into the soc tree directly
if there are no further concerns.
Arnd
Arnd Bergmann (12):
usb: ohci-nxp: enable compile-testing
usb: udc: lpc32xx: allow compile-testing
watchdog: pnx4008_wdt: allow compile-testing
serial: lpc32xx_hs: allow compile-testing
gpio: lpc32xx: allow building on non-lpc32xx targets
net: lpc-enet: factor out iram access
net: lpc-enet: move phy setup into platform code
net: lpc-enet: fix printk format strings
net: lpc-enet: allow compile testing
serial: lpc32xx: allow compile testing
ARM: lpc32xx: clean up header files
ARM: lpc32xx: allow multiplatform build
kbuild test robot (1):
net: lpc-enet: fix badzero.cocci warnings
arch/arm/Kconfig | 17 +--
arch/arm/configs/lpc32xx_defconfig | 2 +
arch/arm/mach-lpc32xx/Kconfig | 11 ++
arch/arm/mach-lpc32xx/common.c | 24 +++-
arch/arm/mach-lpc32xx/common.h | 1 -
arch/arm/mach-lpc32xx/include/mach/board.h | 15 ---
.../mach-lpc32xx/include/mach/entry-macro.S | 28 -----
arch/arm/mach-lpc32xx/include/mach/hardware.h | 25 ----
.../mach-lpc32xx/include/mach/uncompress.h | 50 --------
.../{include/mach/platform.h => lpc32xx.h} | 18 ++-
arch/arm/mach-lpc32xx/pm.c | 3 +-
arch/arm/mach-lpc32xx/serial.c | 33 ++++-
arch/arm/mach-lpc32xx/suspend.S | 3 +-
drivers/gpio/Kconfig | 7 ++
drivers/gpio/Makefile | 2 +-
drivers/gpio/gpio-lpc32xx.c | 118 ++++++++++--------
drivers/net/ethernet/nxp/Kconfig | 2 +-
drivers/net/ethernet/nxp/lpc_eth.c | 45 +++----
drivers/tty/serial/Kconfig | 3 +-
drivers/tty/serial/lpc32xx_hs.c | 37 +-----
drivers/usb/gadget/udc/Kconfig | 3 +-
drivers/usb/gadget/udc/lpc32xx_udc.c | 3 +-
drivers/usb/host/Kconfig | 3 +-
drivers/usb/host/ohci-nxp.c | 25 ++--
drivers/watchdog/Kconfig | 2 +-
drivers/watchdog/pnx4008_wdt.c | 1 -
include/linux/soc/nxp/lpc32xx-misc.h | 33 +++++
27 files changed, 242 insertions(+), 272 deletions(-)
create mode 100644 arch/arm/mach-lpc32xx/Kconfig
delete mode 100644 arch/arm/mach-lpc32xx/include/mach/board.h
delete mode 100644 arch/arm/mach-lpc32xx/include/mach/entry-macro.S
delete mode 100644 arch/arm/mach-lpc32xx/include/mach/hardware.h
delete mode 100644 arch/arm/mach-lpc32xx/include/mach/uncompress.h
rename arch/arm/mach-lpc32xx/{include/mach/platform.h => lpc32xx.h} (98%)
create mode 100644 include/linux/soc/nxp/lpc32xx-misc.h
--
2.20.0
Cc: soc@kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Sylvain Lemieux <slemieux.tyco@gmail.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Alan Stern <stern@rowland.harvard.edu>
Cc: Guenter Roeck <linux@roeck-us.net>
Cc: linux-gpio@vger.kernel.org
Cc: netdev@vger.kernel.org
Cc: linux-serial@vger.kernel.org
Cc: linux-usb@vger.kernel.org
Cc: linux-watchdog@vger.kernel.org
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH v2 05/13] gpio: lpc32xx: allow building on non-lpc32xx targets
2019-08-09 14:40 [PATCH v2 00/13] v2: ARM: move lpc32xx to multiplatform Arnd Bergmann
@ 2019-08-09 14:40 ` Arnd Bergmann
2019-08-12 7:09 ` Bartosz Golaszewski
0 siblings, 1 reply; 3+ messages in thread
From: Arnd Bergmann @ 2019-08-09 14:40 UTC (permalink / raw)
To: soc
Cc: Vladimir Zapolskiy, Sylvain Lemieux, linux-arm-kernel,
linux-kernel, Arnd Bergmann, Linus Walleij, Bartosz Golaszewski,
linux-gpio
The driver uses hardwire MMIO addresses instead of the data
that is passed in device tree. Change it over to only
hardcode the register offset values and allow compile-testing.
Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
Tested-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
arch/arm/configs/lpc32xx_defconfig | 1 +
drivers/gpio/Kconfig | 7 ++
drivers/gpio/Makefile | 2 +-
drivers/gpio/gpio-lpc32xx.c | 118 +++++++++++++++++------------
4 files changed, 77 insertions(+), 51 deletions(-)
diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig
index 0cdc6c7974b3..3772d5a8975a 100644
--- a/arch/arm/configs/lpc32xx_defconfig
+++ b/arch/arm/configs/lpc32xx_defconfig
@@ -93,6 +93,7 @@ CONFIG_SERIAL_HS_LPC32XX_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_PNX=y
+CONFIG_GPIO_LPC32XX=y
CONFIG_SPI=y
CONFIG_SPI_PL022=y
CONFIG_GPIO_SYSFS=y
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index bb13c266c329..8b40a578963c 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -311,6 +311,13 @@ config GPIO_LPC18XX
Select this option to enable GPIO driver for
NXP LPC18XX/43XX devices.
+config GPIO_LPC32XX
+ tristate "NXP LPC32XX GPIO support"
+ depends on OF_GPIO && (ARCH_LPC32XX || COMPILE_TEST)
+ help
+ Select this option to enable GPIO driver for
+ NXP LPC32XX devices.
+
config GPIO_LYNXPOINT
tristate "Intel Lynxpoint GPIO support"
depends on ACPI && X86
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index a4e91175c708..87d659ae95eb 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -74,7 +74,7 @@ obj-$(CONFIG_GPIO_LP3943) += gpio-lp3943.o
obj-$(CONFIG_GPIO_LP873X) += gpio-lp873x.o
obj-$(CONFIG_GPIO_LP87565) += gpio-lp87565.o
obj-$(CONFIG_GPIO_LPC18XX) += gpio-lpc18xx.o
-obj-$(CONFIG_ARCH_LPC32XX) += gpio-lpc32xx.o
+obj-$(CONFIG_GPIO_LPC32XX) += gpio-lpc32xx.o
obj-$(CONFIG_GPIO_LYNXPOINT) += gpio-lynxpoint.o
obj-$(CONFIG_GPIO_MADERA) += gpio-madera.o
obj-$(CONFIG_GPIO_MAX3191X) += gpio-max3191x.o
diff --git a/drivers/gpio/gpio-lpc32xx.c b/drivers/gpio/gpio-lpc32xx.c
index 24885b3db3d5..4e626c4235c2 100644
--- a/drivers/gpio/gpio-lpc32xx.c
+++ b/drivers/gpio/gpio-lpc32xx.c
@@ -16,36 +16,33 @@
#include <linux/platform_device.h>
#include <linux/module.h>
-#include <mach/hardware.h>
-#include <mach/platform.h>
-
-#define LPC32XX_GPIO_P3_INP_STATE _GPREG(0x000)
-#define LPC32XX_GPIO_P3_OUTP_SET _GPREG(0x004)
-#define LPC32XX_GPIO_P3_OUTP_CLR _GPREG(0x008)
-#define LPC32XX_GPIO_P3_OUTP_STATE _GPREG(0x00C)
-#define LPC32XX_GPIO_P2_DIR_SET _GPREG(0x010)
-#define LPC32XX_GPIO_P2_DIR_CLR _GPREG(0x014)
-#define LPC32XX_GPIO_P2_DIR_STATE _GPREG(0x018)
-#define LPC32XX_GPIO_P2_INP_STATE _GPREG(0x01C)
-#define LPC32XX_GPIO_P2_OUTP_SET _GPREG(0x020)
-#define LPC32XX_GPIO_P2_OUTP_CLR _GPREG(0x024)
-#define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028)
-#define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C)
-#define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030)
-#define LPC32XX_GPIO_P0_INP_STATE _GPREG(0x040)
-#define LPC32XX_GPIO_P0_OUTP_SET _GPREG(0x044)
-#define LPC32XX_GPIO_P0_OUTP_CLR _GPREG(0x048)
-#define LPC32XX_GPIO_P0_OUTP_STATE _GPREG(0x04C)
-#define LPC32XX_GPIO_P0_DIR_SET _GPREG(0x050)
-#define LPC32XX_GPIO_P0_DIR_CLR _GPREG(0x054)
-#define LPC32XX_GPIO_P0_DIR_STATE _GPREG(0x058)
-#define LPC32XX_GPIO_P1_INP_STATE _GPREG(0x060)
-#define LPC32XX_GPIO_P1_OUTP_SET _GPREG(0x064)
-#define LPC32XX_GPIO_P1_OUTP_CLR _GPREG(0x068)
-#define LPC32XX_GPIO_P1_OUTP_STATE _GPREG(0x06C)
-#define LPC32XX_GPIO_P1_DIR_SET _GPREG(0x070)
-#define LPC32XX_GPIO_P1_DIR_CLR _GPREG(0x074)
-#define LPC32XX_GPIO_P1_DIR_STATE _GPREG(0x078)
+#define LPC32XX_GPIO_P3_INP_STATE (0x000)
+#define LPC32XX_GPIO_P3_OUTP_SET (0x004)
+#define LPC32XX_GPIO_P3_OUTP_CLR (0x008)
+#define LPC32XX_GPIO_P3_OUTP_STATE (0x00C)
+#define LPC32XX_GPIO_P2_DIR_SET (0x010)
+#define LPC32XX_GPIO_P2_DIR_CLR (0x014)
+#define LPC32XX_GPIO_P2_DIR_STATE (0x018)
+#define LPC32XX_GPIO_P2_INP_STATE (0x01C)
+#define LPC32XX_GPIO_P2_OUTP_SET (0x020)
+#define LPC32XX_GPIO_P2_OUTP_CLR (0x024)
+#define LPC32XX_GPIO_P2_MUX_SET (0x028)
+#define LPC32XX_GPIO_P2_MUX_CLR (0x02C)
+#define LPC32XX_GPIO_P2_MUX_STATE (0x030)
+#define LPC32XX_GPIO_P0_INP_STATE (0x040)
+#define LPC32XX_GPIO_P0_OUTP_SET (0x044)
+#define LPC32XX_GPIO_P0_OUTP_CLR (0x048)
+#define LPC32XX_GPIO_P0_OUTP_STATE (0x04C)
+#define LPC32XX_GPIO_P0_DIR_SET (0x050)
+#define LPC32XX_GPIO_P0_DIR_CLR (0x054)
+#define LPC32XX_GPIO_P0_DIR_STATE (0x058)
+#define LPC32XX_GPIO_P1_INP_STATE (0x060)
+#define LPC32XX_GPIO_P1_OUTP_SET (0x064)
+#define LPC32XX_GPIO_P1_OUTP_CLR (0x068)
+#define LPC32XX_GPIO_P1_OUTP_STATE (0x06C)
+#define LPC32XX_GPIO_P1_DIR_SET (0x070)
+#define LPC32XX_GPIO_P1_DIR_CLR (0x074)
+#define LPC32XX_GPIO_P1_DIR_STATE (0x078)
#define GPIO012_PIN_TO_BIT(x) (1 << (x))
#define GPIO3_PIN_TO_BIT(x) (1 << ((x) + 25))
@@ -72,12 +69,12 @@
#define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX)
struct gpio_regs {
- void __iomem *inp_state;
- void __iomem *outp_state;
- void __iomem *outp_set;
- void __iomem *outp_clr;
- void __iomem *dir_set;
- void __iomem *dir_clr;
+ unsigned long inp_state;
+ unsigned long outp_state;
+ unsigned long outp_set;
+ unsigned long outp_clr;
+ unsigned long dir_set;
+ unsigned long dir_clr;
};
/*
@@ -165,16 +162,27 @@ static struct gpio_regs gpio_grp_regs_p3 = {
struct lpc32xx_gpio_chip {
struct gpio_chip chip;
struct gpio_regs *gpio_grp;
+ void __iomem *reg_base;
};
+static inline u32 gpreg_read(struct lpc32xx_gpio_chip *group, unsigned long offset)
+{
+ return __raw_readl(group->reg_base + offset);
+}
+
+static inline void gpreg_write(struct lpc32xx_gpio_chip *group, u32 val, unsigned long offset)
+{
+ __raw_writel(val, group->reg_base + offset);
+}
+
static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group,
unsigned pin, int input)
{
if (input)
- __raw_writel(GPIO012_PIN_TO_BIT(pin),
+ gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
group->gpio_grp->dir_clr);
else
- __raw_writel(GPIO012_PIN_TO_BIT(pin),
+ gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
group->gpio_grp->dir_set);
}
@@ -184,19 +192,19 @@ static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group,
u32 u = GPIO3_PIN_TO_BIT(pin);
if (input)
- __raw_writel(u, group->gpio_grp->dir_clr);
+ gpreg_write(group, u, group->gpio_grp->dir_clr);
else
- __raw_writel(u, group->gpio_grp->dir_set);
+ gpreg_write(group, u, group->gpio_grp->dir_set);
}
static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group,
unsigned pin, int high)
{
if (high)
- __raw_writel(GPIO012_PIN_TO_BIT(pin),
+ gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
group->gpio_grp->outp_set);
else
- __raw_writel(GPIO012_PIN_TO_BIT(pin),
+ gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
group->gpio_grp->outp_clr);
}
@@ -206,31 +214,31 @@ static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group,
u32 u = GPIO3_PIN_TO_BIT(pin);
if (high)
- __raw_writel(u, group->gpio_grp->outp_set);
+ gpreg_write(group, u, group->gpio_grp->outp_set);
else
- __raw_writel(u, group->gpio_grp->outp_clr);
+ gpreg_write(group, u, group->gpio_grp->outp_clr);
}
static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group,
unsigned pin, int high)
{
if (high)
- __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
+ gpreg_write(group, GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
else
- __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
+ gpreg_write(group, GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
}
static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group,
unsigned pin)
{
- return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state),
+ return GPIO012_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->inp_state),
pin);
}
static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
unsigned pin)
{
- int state = __raw_readl(group->gpio_grp->inp_state);
+ int state = gpreg_read(group, group->gpio_grp->inp_state);
/*
* P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped
@@ -242,13 +250,13 @@ static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group,
unsigned pin)
{
- return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin);
+ return GPI3_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->inp_state), pin);
}
static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group,
unsigned pin)
{
- return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin);
+ return GPO3_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->outp_state), pin);
}
/*
@@ -497,12 +505,18 @@ static int lpc32xx_of_xlate(struct gpio_chip *gc,
static int lpc32xx_gpio_probe(struct platform_device *pdev)
{
int i;
+ void __iomem *reg_base;
+
+ reg_base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(reg_base))
+ return PTR_ERR(reg_base);
for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) {
if (pdev->dev.of_node) {
lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate;
lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3;
lpc32xx_gpiochip[i].chip.of_node = pdev->dev.of_node;
+ lpc32xx_gpiochip[i].reg_base = reg_base;
}
devm_gpiochip_add_data(&pdev->dev, &lpc32xx_gpiochip[i].chip,
&lpc32xx_gpiochip[i]);
@@ -527,3 +541,7 @@ static struct platform_driver lpc32xx_gpio_driver = {
};
module_platform_driver(lpc32xx_gpio_driver);
+
+MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("GPIO driver for LPC32xx SoC");
--
2.20.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v2 05/13] gpio: lpc32xx: allow building on non-lpc32xx targets
2019-08-09 14:40 ` [PATCH v2 05/13] gpio: lpc32xx: allow building on non-lpc32xx targets Arnd Bergmann
@ 2019-08-12 7:09 ` Bartosz Golaszewski
0 siblings, 0 replies; 3+ messages in thread
From: Bartosz Golaszewski @ 2019-08-12 7:09 UTC (permalink / raw)
To: Arnd Bergmann
Cc: soc, Vladimir Zapolskiy, Sylvain Lemieux, arm-soc, LKML,
Linus Walleij, linux-gpio
pt., 9 sie 2019 o 16:43 Arnd Bergmann <arnd@arndb.de> napisał(a):
>
> The driver uses hardwire MMIO addresses instead of the data
> that is passed in device tree. Change it over to only
> hardcode the register offset values and allow compile-testing.
>
> Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
> Tested-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
> arch/arm/configs/lpc32xx_defconfig | 1 +
> drivers/gpio/Kconfig | 7 ++
> drivers/gpio/Makefile | 2 +-
> drivers/gpio/gpio-lpc32xx.c | 118 +++++++++++++++++------------
> 4 files changed, 77 insertions(+), 51 deletions(-)
>
> diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig
> index 0cdc6c7974b3..3772d5a8975a 100644
> --- a/arch/arm/configs/lpc32xx_defconfig
> +++ b/arch/arm/configs/lpc32xx_defconfig
> @@ -93,6 +93,7 @@ CONFIG_SERIAL_HS_LPC32XX_CONSOLE=y
> # CONFIG_HW_RANDOM is not set
> CONFIG_I2C_CHARDEV=y
> CONFIG_I2C_PNX=y
> +CONFIG_GPIO_LPC32XX=y
> CONFIG_SPI=y
> CONFIG_SPI_PL022=y
> CONFIG_GPIO_SYSFS=y
> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> index bb13c266c329..8b40a578963c 100644
> --- a/drivers/gpio/Kconfig
> +++ b/drivers/gpio/Kconfig
> @@ -311,6 +311,13 @@ config GPIO_LPC18XX
> Select this option to enable GPIO driver for
> NXP LPC18XX/43XX devices.
>
> +config GPIO_LPC32XX
> + tristate "NXP LPC32XX GPIO support"
> + depends on OF_GPIO && (ARCH_LPC32XX || COMPILE_TEST)
> + help
> + Select this option to enable GPIO driver for
> + NXP LPC32XX devices.
> +
> config GPIO_LYNXPOINT
> tristate "Intel Lynxpoint GPIO support"
> depends on ACPI && X86
> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> index a4e91175c708..87d659ae95eb 100644
> --- a/drivers/gpio/Makefile
> +++ b/drivers/gpio/Makefile
> @@ -74,7 +74,7 @@ obj-$(CONFIG_GPIO_LP3943) += gpio-lp3943.o
> obj-$(CONFIG_GPIO_LP873X) += gpio-lp873x.o
> obj-$(CONFIG_GPIO_LP87565) += gpio-lp87565.o
> obj-$(CONFIG_GPIO_LPC18XX) += gpio-lpc18xx.o
> -obj-$(CONFIG_ARCH_LPC32XX) += gpio-lpc32xx.o
> +obj-$(CONFIG_GPIO_LPC32XX) += gpio-lpc32xx.o
> obj-$(CONFIG_GPIO_LYNXPOINT) += gpio-lynxpoint.o
> obj-$(CONFIG_GPIO_MADERA) += gpio-madera.o
> obj-$(CONFIG_GPIO_MAX3191X) += gpio-max3191x.o
> diff --git a/drivers/gpio/gpio-lpc32xx.c b/drivers/gpio/gpio-lpc32xx.c
> index 24885b3db3d5..4e626c4235c2 100644
> --- a/drivers/gpio/gpio-lpc32xx.c
> +++ b/drivers/gpio/gpio-lpc32xx.c
> @@ -16,36 +16,33 @@
> #include <linux/platform_device.h>
> #include <linux/module.h>
>
> -#include <mach/hardware.h>
> -#include <mach/platform.h>
> -
> -#define LPC32XX_GPIO_P3_INP_STATE _GPREG(0x000)
> -#define LPC32XX_GPIO_P3_OUTP_SET _GPREG(0x004)
> -#define LPC32XX_GPIO_P3_OUTP_CLR _GPREG(0x008)
> -#define LPC32XX_GPIO_P3_OUTP_STATE _GPREG(0x00C)
> -#define LPC32XX_GPIO_P2_DIR_SET _GPREG(0x010)
> -#define LPC32XX_GPIO_P2_DIR_CLR _GPREG(0x014)
> -#define LPC32XX_GPIO_P2_DIR_STATE _GPREG(0x018)
> -#define LPC32XX_GPIO_P2_INP_STATE _GPREG(0x01C)
> -#define LPC32XX_GPIO_P2_OUTP_SET _GPREG(0x020)
> -#define LPC32XX_GPIO_P2_OUTP_CLR _GPREG(0x024)
> -#define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028)
> -#define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C)
> -#define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030)
> -#define LPC32XX_GPIO_P0_INP_STATE _GPREG(0x040)
> -#define LPC32XX_GPIO_P0_OUTP_SET _GPREG(0x044)
> -#define LPC32XX_GPIO_P0_OUTP_CLR _GPREG(0x048)
> -#define LPC32XX_GPIO_P0_OUTP_STATE _GPREG(0x04C)
> -#define LPC32XX_GPIO_P0_DIR_SET _GPREG(0x050)
> -#define LPC32XX_GPIO_P0_DIR_CLR _GPREG(0x054)
> -#define LPC32XX_GPIO_P0_DIR_STATE _GPREG(0x058)
> -#define LPC32XX_GPIO_P1_INP_STATE _GPREG(0x060)
> -#define LPC32XX_GPIO_P1_OUTP_SET _GPREG(0x064)
> -#define LPC32XX_GPIO_P1_OUTP_CLR _GPREG(0x068)
> -#define LPC32XX_GPIO_P1_OUTP_STATE _GPREG(0x06C)
> -#define LPC32XX_GPIO_P1_DIR_SET _GPREG(0x070)
> -#define LPC32XX_GPIO_P1_DIR_CLR _GPREG(0x074)
> -#define LPC32XX_GPIO_P1_DIR_STATE _GPREG(0x078)
> +#define LPC32XX_GPIO_P3_INP_STATE (0x000)
> +#define LPC32XX_GPIO_P3_OUTP_SET (0x004)
> +#define LPC32XX_GPIO_P3_OUTP_CLR (0x008)
> +#define LPC32XX_GPIO_P3_OUTP_STATE (0x00C)
> +#define LPC32XX_GPIO_P2_DIR_SET (0x010)
> +#define LPC32XX_GPIO_P2_DIR_CLR (0x014)
> +#define LPC32XX_GPIO_P2_DIR_STATE (0x018)
> +#define LPC32XX_GPIO_P2_INP_STATE (0x01C)
> +#define LPC32XX_GPIO_P2_OUTP_SET (0x020)
> +#define LPC32XX_GPIO_P2_OUTP_CLR (0x024)
> +#define LPC32XX_GPIO_P2_MUX_SET (0x028)
> +#define LPC32XX_GPIO_P2_MUX_CLR (0x02C)
> +#define LPC32XX_GPIO_P2_MUX_STATE (0x030)
> +#define LPC32XX_GPIO_P0_INP_STATE (0x040)
> +#define LPC32XX_GPIO_P0_OUTP_SET (0x044)
> +#define LPC32XX_GPIO_P0_OUTP_CLR (0x048)
> +#define LPC32XX_GPIO_P0_OUTP_STATE (0x04C)
> +#define LPC32XX_GPIO_P0_DIR_SET (0x050)
> +#define LPC32XX_GPIO_P0_DIR_CLR (0x054)
> +#define LPC32XX_GPIO_P0_DIR_STATE (0x058)
> +#define LPC32XX_GPIO_P1_INP_STATE (0x060)
> +#define LPC32XX_GPIO_P1_OUTP_SET (0x064)
> +#define LPC32XX_GPIO_P1_OUTP_CLR (0x068)
> +#define LPC32XX_GPIO_P1_OUTP_STATE (0x06C)
> +#define LPC32XX_GPIO_P1_DIR_SET (0x070)
> +#define LPC32XX_GPIO_P1_DIR_CLR (0x074)
> +#define LPC32XX_GPIO_P1_DIR_STATE (0x078)
>
> #define GPIO012_PIN_TO_BIT(x) (1 << (x))
> #define GPIO3_PIN_TO_BIT(x) (1 << ((x) + 25))
> @@ -72,12 +69,12 @@
> #define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX)
>
> struct gpio_regs {
> - void __iomem *inp_state;
> - void __iomem *outp_state;
> - void __iomem *outp_set;
> - void __iomem *outp_clr;
> - void __iomem *dir_set;
> - void __iomem *dir_clr;
> + unsigned long inp_state;
> + unsigned long outp_state;
> + unsigned long outp_set;
> + unsigned long outp_clr;
> + unsigned long dir_set;
> + unsigned long dir_clr;
> };
>
> /*
> @@ -165,16 +162,27 @@ static struct gpio_regs gpio_grp_regs_p3 = {
> struct lpc32xx_gpio_chip {
> struct gpio_chip chip;
> struct gpio_regs *gpio_grp;
> + void __iomem *reg_base;
> };
>
> +static inline u32 gpreg_read(struct lpc32xx_gpio_chip *group, unsigned long offset)
> +{
> + return __raw_readl(group->reg_base + offset);
> +}
> +
> +static inline void gpreg_write(struct lpc32xx_gpio_chip *group, u32 val, unsigned long offset)
> +{
> + __raw_writel(val, group->reg_base + offset);
> +}
> +
> static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group,
> unsigned pin, int input)
> {
> if (input)
> - __raw_writel(GPIO012_PIN_TO_BIT(pin),
> + gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
> group->gpio_grp->dir_clr);
> else
> - __raw_writel(GPIO012_PIN_TO_BIT(pin),
> + gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
> group->gpio_grp->dir_set);
> }
>
> @@ -184,19 +192,19 @@ static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group,
> u32 u = GPIO3_PIN_TO_BIT(pin);
>
> if (input)
> - __raw_writel(u, group->gpio_grp->dir_clr);
> + gpreg_write(group, u, group->gpio_grp->dir_clr);
> else
> - __raw_writel(u, group->gpio_grp->dir_set);
> + gpreg_write(group, u, group->gpio_grp->dir_set);
> }
>
> static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group,
> unsigned pin, int high)
> {
> if (high)
> - __raw_writel(GPIO012_PIN_TO_BIT(pin),
> + gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
> group->gpio_grp->outp_set);
> else
> - __raw_writel(GPIO012_PIN_TO_BIT(pin),
> + gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
> group->gpio_grp->outp_clr);
> }
>
> @@ -206,31 +214,31 @@ static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group,
> u32 u = GPIO3_PIN_TO_BIT(pin);
>
> if (high)
> - __raw_writel(u, group->gpio_grp->outp_set);
> + gpreg_write(group, u, group->gpio_grp->outp_set);
> else
> - __raw_writel(u, group->gpio_grp->outp_clr);
> + gpreg_write(group, u, group->gpio_grp->outp_clr);
> }
>
> static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group,
> unsigned pin, int high)
> {
> if (high)
> - __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
> + gpreg_write(group, GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
> else
> - __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
> + gpreg_write(group, GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
> }
>
> static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group,
> unsigned pin)
> {
> - return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state),
> + return GPIO012_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->inp_state),
> pin);
> }
>
> static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
> unsigned pin)
> {
> - int state = __raw_readl(group->gpio_grp->inp_state);
> + int state = gpreg_read(group, group->gpio_grp->inp_state);
>
> /*
> * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped
> @@ -242,13 +250,13 @@ static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
> static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group,
> unsigned pin)
> {
> - return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin);
> + return GPI3_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->inp_state), pin);
> }
>
> static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group,
> unsigned pin)
> {
> - return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin);
> + return GPO3_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->outp_state), pin);
> }
>
> /*
> @@ -497,12 +505,18 @@ static int lpc32xx_of_xlate(struct gpio_chip *gc,
> static int lpc32xx_gpio_probe(struct platform_device *pdev)
> {
> int i;
> + void __iomem *reg_base;
> +
> + reg_base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(reg_base))
> + return PTR_ERR(reg_base);
>
> for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) {
> if (pdev->dev.of_node) {
> lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate;
> lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3;
> lpc32xx_gpiochip[i].chip.of_node = pdev->dev.of_node;
> + lpc32xx_gpiochip[i].reg_base = reg_base;
> }
> devm_gpiochip_add_data(&pdev->dev, &lpc32xx_gpiochip[i].chip,
> &lpc32xx_gpiochip[i]);
> @@ -527,3 +541,7 @@ static struct platform_driver lpc32xx_gpio_driver = {
> };
>
> module_platform_driver(lpc32xx_gpio_driver);
> +
> +MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
> +MODULE_LICENSE("GPL");
> +MODULE_DESCRIPTION("GPIO driver for LPC32xx SoC");
> --
> 2.20.0
>
Applied, thanks!
Bart
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2019-08-12 7:10 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-08-09 14:40 [PATCH v2 00/13] v2: ARM: move lpc32xx to multiplatform Arnd Bergmann
2019-08-09 14:40 ` [PATCH v2 05/13] gpio: lpc32xx: allow building on non-lpc32xx targets Arnd Bergmann
2019-08-12 7:09 ` Bartosz Golaszewski
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