* [PATCH v3 1/3] i2c: i801: Enlarge device name field in i801_ids table
@ 2023-05-12 11:49 Jarkko Nikula
2023-05-12 11:50 ` [PATCH v3 2/3] i2c: i801: Add support for Intel Meteor Lake SoC-S Jarkko Nikula
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Jarkko Nikula @ 2023-05-12 11:49 UTC (permalink / raw)
To: linux-i2c; +Cc: Jean Delvare, Wolfram Sang, Andi Shyti, Jarkko Nikula
Indent data field in the i801_ids table by one tab to make more space for
longer device names.
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
---
drivers/i2c/busses/i2c-i801.c | 122 +++++++++++++++++-----------------
1 file changed, 61 insertions(+), 61 deletions(-)
diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
index ac5326747c51..7431e8411e99 100644
--- a/drivers/i2c/busses/i2c-i801.c
+++ b/drivers/i2c/busses/i2c-i801.c
@@ -977,67 +977,67 @@ static const struct i2c_algorithm smbus_algorithm = {
FEATURE_HOST_NOTIFY)
static const struct pci_device_id i801_ids[] = {
- { PCI_DEVICE_DATA(INTEL, 82801AA_3, 0) },
- { PCI_DEVICE_DATA(INTEL, 82801AB_3, 0) },
- { PCI_DEVICE_DATA(INTEL, 82801BA_2, 0) },
- { PCI_DEVICE_DATA(INTEL, 82801CA_3, FEATURE_HOST_NOTIFY) },
- { PCI_DEVICE_DATA(INTEL, 82801DB_3, FEATURES_ICH4) },
- { PCI_DEVICE_DATA(INTEL, 82801EB_3, FEATURES_ICH5) },
- { PCI_DEVICE_DATA(INTEL, ESB_4, FEATURES_ICH5) },
- { PCI_DEVICE_DATA(INTEL, ICH6_16, FEATURES_ICH5) },
- { PCI_DEVICE_DATA(INTEL, ICH7_17, FEATURES_ICH5) },
- { PCI_DEVICE_DATA(INTEL, ESB2_17, FEATURES_ICH5) },
- { PCI_DEVICE_DATA(INTEL, ICH8_5, FEATURES_ICH5) },
- { PCI_DEVICE_DATA(INTEL, ICH9_6, FEATURES_ICH5) },
- { PCI_DEVICE_DATA(INTEL, EP80579_1, FEATURES_ICH5) },
- { PCI_DEVICE_DATA(INTEL, ICH10_4, FEATURES_ICH5) },
- { PCI_DEVICE_DATA(INTEL, ICH10_5, FEATURES_ICH5) },
- { PCI_DEVICE_DATA(INTEL, 5_3400_SERIES_SMBUS, FEATURES_ICH5) },
- { PCI_DEVICE_DATA(INTEL, COUGARPOINT_SMBUS, FEATURES_ICH5) },
- { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS, FEATURES_ICH5) },
- { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF0, FEATURES_ICH5 | FEATURE_IDF) },
- { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF1, FEATURES_ICH5 | FEATURE_IDF) },
- { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF2, FEATURES_ICH5 | FEATURE_IDF) },
- { PCI_DEVICE_DATA(INTEL, DH89XXCC_SMBUS, FEATURES_ICH5) },
- { PCI_DEVICE_DATA(INTEL, PANTHERPOINT_SMBUS, FEATURES_ICH5) },
- { PCI_DEVICE_DATA(INTEL, LYNXPOINT_SMBUS, FEATURES_ICH5) },
- { PCI_DEVICE_DATA(INTEL, LYNXPOINT_LP_SMBUS, FEATURES_ICH5) },
- { PCI_DEVICE_DATA(INTEL, AVOTON_SMBUS, FEATURES_ICH5) },
- { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS, FEATURES_ICH5) },
- { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS0, FEATURES_ICH5 | FEATURE_IDF) },
- { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS1, FEATURES_ICH5 | FEATURE_IDF) },
- { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS2, FEATURES_ICH5 | FEATURE_IDF) },
- { PCI_DEVICE_DATA(INTEL, COLETOCREEK_SMBUS, FEATURES_ICH5) },
- { PCI_DEVICE_DATA(INTEL, GEMINILAKE_SMBUS, FEATURES_ICH5) },
- { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_SMBUS, FEATURES_ICH5) },
- { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_LP_SMBUS, FEATURES_ICH5) },
- { PCI_DEVICE_DATA(INTEL, BAYTRAIL_SMBUS, FEATURES_ICH5) },
- { PCI_DEVICE_DATA(INTEL, BRASWELL_SMBUS, FEATURES_ICH5) },
- { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
- { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
- { PCI_DEVICE_DATA(INTEL, CDF_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
- { PCI_DEVICE_DATA(INTEL, DNV_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
- { PCI_DEVICE_DATA(INTEL, EBG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
- { PCI_DEVICE_DATA(INTEL, BROXTON_SMBUS, FEATURES_ICH5) },
- { PCI_DEVICE_DATA(INTEL, LEWISBURG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
- { PCI_DEVICE_DATA(INTEL, LEWISBURG_SSKU_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
- { PCI_DEVICE_DATA(INTEL, KABYLAKE_PCH_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
- { PCI_DEVICE_DATA(INTEL, CANNONLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
- { PCI_DEVICE_DATA(INTEL, CANNONLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
- { PCI_DEVICE_DATA(INTEL, ICELAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
- { PCI_DEVICE_DATA(INTEL, ICELAKE_N_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
- { PCI_DEVICE_DATA(INTEL, COMETLAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
- { PCI_DEVICE_DATA(INTEL, COMETLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
- { PCI_DEVICE_DATA(INTEL, COMETLAKE_V_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
- { PCI_DEVICE_DATA(INTEL, ELKHART_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
- { PCI_DEVICE_DATA(INTEL, TIGERLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
- { PCI_DEVICE_DATA(INTEL, TIGERLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
- { PCI_DEVICE_DATA(INTEL, JASPER_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
- { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
- { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
- { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_M_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
- { PCI_DEVICE_DATA(INTEL, RAPTOR_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
- { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
+ { PCI_DEVICE_DATA(INTEL, 82801AA_3, 0) },
+ { PCI_DEVICE_DATA(INTEL, 82801AB_3, 0) },
+ { PCI_DEVICE_DATA(INTEL, 82801BA_2, 0) },
+ { PCI_DEVICE_DATA(INTEL, 82801CA_3, FEATURE_HOST_NOTIFY) },
+ { PCI_DEVICE_DATA(INTEL, 82801DB_3, FEATURES_ICH4) },
+ { PCI_DEVICE_DATA(INTEL, 82801EB_3, FEATURES_ICH5) },
+ { PCI_DEVICE_DATA(INTEL, ESB_4, FEATURES_ICH5) },
+ { PCI_DEVICE_DATA(INTEL, ICH6_16, FEATURES_ICH5) },
+ { PCI_DEVICE_DATA(INTEL, ICH7_17, FEATURES_ICH5) },
+ { PCI_DEVICE_DATA(INTEL, ESB2_17, FEATURES_ICH5) },
+ { PCI_DEVICE_DATA(INTEL, ICH8_5, FEATURES_ICH5) },
+ { PCI_DEVICE_DATA(INTEL, ICH9_6, FEATURES_ICH5) },
+ { PCI_DEVICE_DATA(INTEL, EP80579_1, FEATURES_ICH5) },
+ { PCI_DEVICE_DATA(INTEL, ICH10_4, FEATURES_ICH5) },
+ { PCI_DEVICE_DATA(INTEL, ICH10_5, FEATURES_ICH5) },
+ { PCI_DEVICE_DATA(INTEL, 5_3400_SERIES_SMBUS, FEATURES_ICH5) },
+ { PCI_DEVICE_DATA(INTEL, COUGARPOINT_SMBUS, FEATURES_ICH5) },
+ { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS, FEATURES_ICH5) },
+ { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF0, FEATURES_ICH5 | FEATURE_IDF) },
+ { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF1, FEATURES_ICH5 | FEATURE_IDF) },
+ { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF2, FEATURES_ICH5 | FEATURE_IDF) },
+ { PCI_DEVICE_DATA(INTEL, DH89XXCC_SMBUS, FEATURES_ICH5) },
+ { PCI_DEVICE_DATA(INTEL, PANTHERPOINT_SMBUS, FEATURES_ICH5) },
+ { PCI_DEVICE_DATA(INTEL, LYNXPOINT_SMBUS, FEATURES_ICH5) },
+ { PCI_DEVICE_DATA(INTEL, LYNXPOINT_LP_SMBUS, FEATURES_ICH5) },
+ { PCI_DEVICE_DATA(INTEL, AVOTON_SMBUS, FEATURES_ICH5) },
+ { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS, FEATURES_ICH5) },
+ { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS0, FEATURES_ICH5 | FEATURE_IDF) },
+ { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS1, FEATURES_ICH5 | FEATURE_IDF) },
+ { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS2, FEATURES_ICH5 | FEATURE_IDF) },
+ { PCI_DEVICE_DATA(INTEL, COLETOCREEK_SMBUS, FEATURES_ICH5) },
+ { PCI_DEVICE_DATA(INTEL, GEMINILAKE_SMBUS, FEATURES_ICH5) },
+ { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_SMBUS, FEATURES_ICH5) },
+ { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_LP_SMBUS, FEATURES_ICH5) },
+ { PCI_DEVICE_DATA(INTEL, BAYTRAIL_SMBUS, FEATURES_ICH5) },
+ { PCI_DEVICE_DATA(INTEL, BRASWELL_SMBUS, FEATURES_ICH5) },
+ { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
+ { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
+ { PCI_DEVICE_DATA(INTEL, CDF_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
+ { PCI_DEVICE_DATA(INTEL, DNV_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
+ { PCI_DEVICE_DATA(INTEL, EBG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
+ { PCI_DEVICE_DATA(INTEL, BROXTON_SMBUS, FEATURES_ICH5) },
+ { PCI_DEVICE_DATA(INTEL, LEWISBURG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
+ { PCI_DEVICE_DATA(INTEL, LEWISBURG_SSKU_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
+ { PCI_DEVICE_DATA(INTEL, KABYLAKE_PCH_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
+ { PCI_DEVICE_DATA(INTEL, CANNONLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
+ { PCI_DEVICE_DATA(INTEL, CANNONLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
+ { PCI_DEVICE_DATA(INTEL, ICELAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
+ { PCI_DEVICE_DATA(INTEL, ICELAKE_N_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
+ { PCI_DEVICE_DATA(INTEL, COMETLAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
+ { PCI_DEVICE_DATA(INTEL, COMETLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
+ { PCI_DEVICE_DATA(INTEL, COMETLAKE_V_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
+ { PCI_DEVICE_DATA(INTEL, ELKHART_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
+ { PCI_DEVICE_DATA(INTEL, TIGERLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
+ { PCI_DEVICE_DATA(INTEL, TIGERLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
+ { PCI_DEVICE_DATA(INTEL, JASPER_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
+ { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
+ { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
+ { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_M_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
+ { PCI_DEVICE_DATA(INTEL, RAPTOR_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
+ { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
{ 0, }
};
--
2.39.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v3 2/3] i2c: i801: Add support for Intel Meteor Lake SoC-S
2023-05-12 11:49 [PATCH v3 1/3] i2c: i801: Enlarge device name field in i801_ids table Jarkko Nikula
@ 2023-05-12 11:50 ` Jarkko Nikula
2023-05-19 11:07 ` Andi Shyti
2023-05-23 17:35 ` Jean Delvare
2023-05-12 11:50 ` [PATCH v3 3/3] i2c: i801: Add support for Intel Meteor Lake PCH-S Jarkko Nikula
` (2 subsequent siblings)
3 siblings, 2 replies; 9+ messages in thread
From: Jarkko Nikula @ 2023-05-12 11:50 UTC (permalink / raw)
To: linux-i2c; +Cc: Jean Delvare, Wolfram Sang, Andi Shyti, Jarkko Nikula
Add SMBus PCI ID on Intel Meteor Lake SoC-S South.
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
---
v3: Call this explicitly as Meteor Lake SoC-S SMBus controller for
distinguish from Meteor Lake PCH-S SMBus controller in patch 3/3.
v2: Keep PCI ID define list sorted and define
PCI_DEVICE_ID_INTEL_METEOR_LAKE_S_SMBUS in correct place.
---
drivers/i2c/busses/i2c-i801.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
index 7431e8411e99..bc2576188e0a 100644
--- a/drivers/i2c/busses/i2c-i801.c
+++ b/drivers/i2c/busses/i2c-i801.c
@@ -77,6 +77,7 @@
* Alder Lake-M (PCH) 0x54a3 32 hard yes yes yes
* Raptor Lake-S (PCH) 0x7a23 32 hard yes yes yes
* Meteor Lake-P (SOC) 0x7e22 32 hard yes yes yes
+ * Meteor Lake SoC-S (SOC) 0xae22 32 hard yes yes yes
*
* Features supported by this driver:
* Software PEC no
@@ -250,6 +251,7 @@
#define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3
#define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323
#define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS 0xa3a3
+#define PCI_DEVICE_ID_INTEL_METEOR_LAKE_SOC_S_SMBUS 0xae22
struct i801_mux_config {
char *gpio_chip;
@@ -1038,6 +1040,7 @@ static const struct pci_device_id i801_ids[] = {
{ PCI_DEVICE_DATA(INTEL, ALDER_LAKE_M_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
{ PCI_DEVICE_DATA(INTEL, RAPTOR_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
{ PCI_DEVICE_DATA(INTEL, METEOR_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
+ { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_SOC_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
{ 0, }
};
--
2.39.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v3 3/3] i2c: i801: Add support for Intel Meteor Lake PCH-S
2023-05-12 11:49 [PATCH v3 1/3] i2c: i801: Enlarge device name field in i801_ids table Jarkko Nikula
2023-05-12 11:50 ` [PATCH v3 2/3] i2c: i801: Add support for Intel Meteor Lake SoC-S Jarkko Nikula
@ 2023-05-12 11:50 ` Jarkko Nikula
2023-05-19 11:08 ` Andi Shyti
2023-05-23 17:35 ` Jean Delvare
2023-05-19 11:05 ` [PATCH v3 1/3] i2c: i801: Enlarge device name field in i801_ids table Andi Shyti
2023-05-23 16:42 ` Jean Delvare
3 siblings, 2 replies; 9+ messages in thread
From: Jarkko Nikula @ 2023-05-12 11:50 UTC (permalink / raw)
To: linux-i2c; +Cc: Jean Delvare, Wolfram Sang, Andi Shyti, Jarkko Nikula
Add SMBus PCI ID on Intel Meteor Lake PCH-S.
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
---
v3: Drop the idea to call this as Meteor Point-S in code since it's confusing.
Intel Meteor Lake-S platform can have the SMBus controller both in
SoC die and PCH. I decided earlier to call latter as Meteor Point-S since
it fitted nicely into i801_ids table and I saw it to be used somewhere in
internal documentation. But it's more historical naming convension for
PCHs and to be honest internal documentation uses mostly Meteor Lake PCH-S.
v2: "SOC/PCH" -> "SOC and PCH" in documentation and Kconfig. PCI ID
define according to updated patch 1/2.
---
Documentation/i2c/busses/i2c-i801.rst | 2 +-
drivers/i2c/busses/Kconfig | 2 +-
drivers/i2c/busses/i2c-i801.c | 3 +++
3 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/Documentation/i2c/busses/i2c-i801.rst b/Documentation/i2c/busses/i2c-i801.rst
index ab9e850e8fe0..e76e68ccf718 100644
--- a/Documentation/i2c/busses/i2c-i801.rst
+++ b/Documentation/i2c/busses/i2c-i801.rst
@@ -46,7 +46,7 @@ Supported adapters:
* Intel Emmitsburg (PCH)
* Intel Alder Lake (PCH)
* Intel Raptor Lake (PCH)
- * Intel Meteor Lake (SOC)
+ * Intel Meteor Lake (SOC and PCH)
Datasheets: Publicly available at the Intel website
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 87600b4aacb3..3144ef99f040 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -157,7 +157,7 @@ config I2C_I801
Emmitsburg (PCH)
Alder Lake (PCH)
Raptor Lake (PCH)
- Meteor Lake (SOC)
+ Meteor Lake (SOC and PCH)
This driver can also be built as a module. If so, the module
will be called i2c-i801.
diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
index bc2576188e0a..943b8e6d026d 100644
--- a/drivers/i2c/busses/i2c-i801.c
+++ b/drivers/i2c/busses/i2c-i801.c
@@ -78,6 +78,7 @@
* Raptor Lake-S (PCH) 0x7a23 32 hard yes yes yes
* Meteor Lake-P (SOC) 0x7e22 32 hard yes yes yes
* Meteor Lake SoC-S (SOC) 0xae22 32 hard yes yes yes
+ * Meteor Lake PCH-S (PCH) 0x7f23 32 hard yes yes yes
*
* Features supported by this driver:
* Software PEC no
@@ -234,6 +235,7 @@
#define PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_S_SMBUS 0x7a23
#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS 0x7aa3
#define PCI_DEVICE_ID_INTEL_METEOR_LAKE_P_SMBUS 0x7e22
+#define PCI_DEVICE_ID_INTEL_METEOR_LAKE_PCH_S_SMBUS 0x7f23
#define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2
#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
@@ -1041,6 +1043,7 @@ static const struct pci_device_id i801_ids[] = {
{ PCI_DEVICE_DATA(INTEL, RAPTOR_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
{ PCI_DEVICE_DATA(INTEL, METEOR_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
{ PCI_DEVICE_DATA(INTEL, METEOR_LAKE_SOC_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
+ { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_PCH_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
{ 0, }
};
--
2.39.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v3 1/3] i2c: i801: Enlarge device name field in i801_ids table
2023-05-12 11:49 [PATCH v3 1/3] i2c: i801: Enlarge device name field in i801_ids table Jarkko Nikula
2023-05-12 11:50 ` [PATCH v3 2/3] i2c: i801: Add support for Intel Meteor Lake SoC-S Jarkko Nikula
2023-05-12 11:50 ` [PATCH v3 3/3] i2c: i801: Add support for Intel Meteor Lake PCH-S Jarkko Nikula
@ 2023-05-19 11:05 ` Andi Shyti
2023-05-23 16:42 ` Jean Delvare
3 siblings, 0 replies; 9+ messages in thread
From: Andi Shyti @ 2023-05-19 11:05 UTC (permalink / raw)
To: Jarkko Nikula; +Cc: linux-i2c, Jean Delvare, Wolfram Sang
Hi Jarkko,
On Fri, May 12, 2023 at 02:49:59PM +0300, Jarkko Nikula wrote:
> Indent data field in the i801_ids table by one tab to make more space for
> longer device names.
>
> Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Reviewed-by: Andi Shyti <andi.shyti@kernel.org>
Andi
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 2/3] i2c: i801: Add support for Intel Meteor Lake SoC-S
2023-05-12 11:50 ` [PATCH v3 2/3] i2c: i801: Add support for Intel Meteor Lake SoC-S Jarkko Nikula
@ 2023-05-19 11:07 ` Andi Shyti
2023-05-23 17:35 ` Jean Delvare
1 sibling, 0 replies; 9+ messages in thread
From: Andi Shyti @ 2023-05-19 11:07 UTC (permalink / raw)
To: Jarkko Nikula; +Cc: linux-i2c, Jean Delvare, Wolfram Sang
Hi Jarkko,
On Fri, May 12, 2023 at 02:50:00PM +0300, Jarkko Nikula wrote:
> Add SMBus PCI ID on Intel Meteor Lake SoC-S South.
>
> Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Reviewed-by: Andi Shyti <andi.shyti@kernel.org>
Andi
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 3/3] i2c: i801: Add support for Intel Meteor Lake PCH-S
2023-05-12 11:50 ` [PATCH v3 3/3] i2c: i801: Add support for Intel Meteor Lake PCH-S Jarkko Nikula
@ 2023-05-19 11:08 ` Andi Shyti
2023-05-23 17:35 ` Jean Delvare
1 sibling, 0 replies; 9+ messages in thread
From: Andi Shyti @ 2023-05-19 11:08 UTC (permalink / raw)
To: Jarkko Nikula; +Cc: linux-i2c, Jean Delvare, Wolfram Sang
Hi Jarkko,
On Fri, May 12, 2023 at 02:50:01PM +0300, Jarkko Nikula wrote:
> Add SMBus PCI ID on Intel Meteor Lake PCH-S.
>
> Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Reviewed-by: Andi Shyti <andi.shyti@kernel.org>
Andi
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 1/3] i2c: i801: Enlarge device name field in i801_ids table
2023-05-12 11:49 [PATCH v3 1/3] i2c: i801: Enlarge device name field in i801_ids table Jarkko Nikula
` (2 preceding siblings ...)
2023-05-19 11:05 ` [PATCH v3 1/3] i2c: i801: Enlarge device name field in i801_ids table Andi Shyti
@ 2023-05-23 16:42 ` Jean Delvare
3 siblings, 0 replies; 9+ messages in thread
From: Jean Delvare @ 2023-05-23 16:42 UTC (permalink / raw)
To: Jarkko Nikula; +Cc: linux-i2c, Wolfram Sang, Andi Shyti
On Fri, 12 May 2023 14:49:59 +0300, Jarkko Nikula wrote:
> Indent data field in the i801_ids table by one tab to make more space for
> longer device names.
>
> Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
> ---
> drivers/i2c/busses/i2c-i801.c | 122 +++++++++++++++++-----------------
> 1 file changed, 61 insertions(+), 61 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
> index ac5326747c51..7431e8411e99 100644
> --- a/drivers/i2c/busses/i2c-i801.c
> +++ b/drivers/i2c/busses/i2c-i801.c
> @@ -977,67 +977,67 @@ static const struct i2c_algorithm smbus_algorithm = {
> FEATURE_HOST_NOTIFY)
>
> static const struct pci_device_id i801_ids[] = {
> - { PCI_DEVICE_DATA(INTEL, 82801AA_3, 0) },
> - { PCI_DEVICE_DATA(INTEL, 82801AB_3, 0) },
> - { PCI_DEVICE_DATA(INTEL, 82801BA_2, 0) },
> - { PCI_DEVICE_DATA(INTEL, 82801CA_3, FEATURE_HOST_NOTIFY) },
> - { PCI_DEVICE_DATA(INTEL, 82801DB_3, FEATURES_ICH4) },
> - { PCI_DEVICE_DATA(INTEL, 82801EB_3, FEATURES_ICH5) },
> - { PCI_DEVICE_DATA(INTEL, ESB_4, FEATURES_ICH5) },
> - { PCI_DEVICE_DATA(INTEL, ICH6_16, FEATURES_ICH5) },
> - { PCI_DEVICE_DATA(INTEL, ICH7_17, FEATURES_ICH5) },
> - { PCI_DEVICE_DATA(INTEL, ESB2_17, FEATURES_ICH5) },
> - { PCI_DEVICE_DATA(INTEL, ICH8_5, FEATURES_ICH5) },
> - { PCI_DEVICE_DATA(INTEL, ICH9_6, FEATURES_ICH5) },
> - { PCI_DEVICE_DATA(INTEL, EP80579_1, FEATURES_ICH5) },
> - { PCI_DEVICE_DATA(INTEL, ICH10_4, FEATURES_ICH5) },
> - { PCI_DEVICE_DATA(INTEL, ICH10_5, FEATURES_ICH5) },
> - { PCI_DEVICE_DATA(INTEL, 5_3400_SERIES_SMBUS, FEATURES_ICH5) },
> - { PCI_DEVICE_DATA(INTEL, COUGARPOINT_SMBUS, FEATURES_ICH5) },
> - { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS, FEATURES_ICH5) },
> - { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF0, FEATURES_ICH5 | FEATURE_IDF) },
> - { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF1, FEATURES_ICH5 | FEATURE_IDF) },
> - { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF2, FEATURES_ICH5 | FEATURE_IDF) },
> - { PCI_DEVICE_DATA(INTEL, DH89XXCC_SMBUS, FEATURES_ICH5) },
> - { PCI_DEVICE_DATA(INTEL, PANTHERPOINT_SMBUS, FEATURES_ICH5) },
> - { PCI_DEVICE_DATA(INTEL, LYNXPOINT_SMBUS, FEATURES_ICH5) },
> - { PCI_DEVICE_DATA(INTEL, LYNXPOINT_LP_SMBUS, FEATURES_ICH5) },
> - { PCI_DEVICE_DATA(INTEL, AVOTON_SMBUS, FEATURES_ICH5) },
> - { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS, FEATURES_ICH5) },
> - { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS0, FEATURES_ICH5 | FEATURE_IDF) },
> - { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS1, FEATURES_ICH5 | FEATURE_IDF) },
> - { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS2, FEATURES_ICH5 | FEATURE_IDF) },
> - { PCI_DEVICE_DATA(INTEL, COLETOCREEK_SMBUS, FEATURES_ICH5) },
> - { PCI_DEVICE_DATA(INTEL, GEMINILAKE_SMBUS, FEATURES_ICH5) },
> - { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_SMBUS, FEATURES_ICH5) },
> - { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_LP_SMBUS, FEATURES_ICH5) },
> - { PCI_DEVICE_DATA(INTEL, BAYTRAIL_SMBUS, FEATURES_ICH5) },
> - { PCI_DEVICE_DATA(INTEL, BRASWELL_SMBUS, FEATURES_ICH5) },
> - { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
> - { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
> - { PCI_DEVICE_DATA(INTEL, CDF_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> - { PCI_DEVICE_DATA(INTEL, DNV_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
> - { PCI_DEVICE_DATA(INTEL, EBG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> - { PCI_DEVICE_DATA(INTEL, BROXTON_SMBUS, FEATURES_ICH5) },
> - { PCI_DEVICE_DATA(INTEL, LEWISBURG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
> - { PCI_DEVICE_DATA(INTEL, LEWISBURG_SSKU_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
> - { PCI_DEVICE_DATA(INTEL, KABYLAKE_PCH_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
> - { PCI_DEVICE_DATA(INTEL, CANNONLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> - { PCI_DEVICE_DATA(INTEL, CANNONLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> - { PCI_DEVICE_DATA(INTEL, ICELAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> - { PCI_DEVICE_DATA(INTEL, ICELAKE_N_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> - { PCI_DEVICE_DATA(INTEL, COMETLAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> - { PCI_DEVICE_DATA(INTEL, COMETLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> - { PCI_DEVICE_DATA(INTEL, COMETLAKE_V_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
> - { PCI_DEVICE_DATA(INTEL, ELKHART_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> - { PCI_DEVICE_DATA(INTEL, TIGERLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> - { PCI_DEVICE_DATA(INTEL, TIGERLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> - { PCI_DEVICE_DATA(INTEL, JASPER_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> - { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> - { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> - { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_M_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> - { PCI_DEVICE_DATA(INTEL, RAPTOR_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> - { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> + { PCI_DEVICE_DATA(INTEL, 82801AA_3, 0) },
> + { PCI_DEVICE_DATA(INTEL, 82801AB_3, 0) },
> + { PCI_DEVICE_DATA(INTEL, 82801BA_2, 0) },
> + { PCI_DEVICE_DATA(INTEL, 82801CA_3, FEATURE_HOST_NOTIFY) },
> + { PCI_DEVICE_DATA(INTEL, 82801DB_3, FEATURES_ICH4) },
> + { PCI_DEVICE_DATA(INTEL, 82801EB_3, FEATURES_ICH5) },
> + { PCI_DEVICE_DATA(INTEL, ESB_4, FEATURES_ICH5) },
> + { PCI_DEVICE_DATA(INTEL, ICH6_16, FEATURES_ICH5) },
> + { PCI_DEVICE_DATA(INTEL, ICH7_17, FEATURES_ICH5) },
> + { PCI_DEVICE_DATA(INTEL, ESB2_17, FEATURES_ICH5) },
> + { PCI_DEVICE_DATA(INTEL, ICH8_5, FEATURES_ICH5) },
> + { PCI_DEVICE_DATA(INTEL, ICH9_6, FEATURES_ICH5) },
> + { PCI_DEVICE_DATA(INTEL, EP80579_1, FEATURES_ICH5) },
> + { PCI_DEVICE_DATA(INTEL, ICH10_4, FEATURES_ICH5) },
> + { PCI_DEVICE_DATA(INTEL, ICH10_5, FEATURES_ICH5) },
> + { PCI_DEVICE_DATA(INTEL, 5_3400_SERIES_SMBUS, FEATURES_ICH5) },
> + { PCI_DEVICE_DATA(INTEL, COUGARPOINT_SMBUS, FEATURES_ICH5) },
> + { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS, FEATURES_ICH5) },
> + { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF0, FEATURES_ICH5 | FEATURE_IDF) },
> + { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF1, FEATURES_ICH5 | FEATURE_IDF) },
> + { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF2, FEATURES_ICH5 | FEATURE_IDF) },
> + { PCI_DEVICE_DATA(INTEL, DH89XXCC_SMBUS, FEATURES_ICH5) },
> + { PCI_DEVICE_DATA(INTEL, PANTHERPOINT_SMBUS, FEATURES_ICH5) },
> + { PCI_DEVICE_DATA(INTEL, LYNXPOINT_SMBUS, FEATURES_ICH5) },
> + { PCI_DEVICE_DATA(INTEL, LYNXPOINT_LP_SMBUS, FEATURES_ICH5) },
> + { PCI_DEVICE_DATA(INTEL, AVOTON_SMBUS, FEATURES_ICH5) },
> + { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS, FEATURES_ICH5) },
> + { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS0, FEATURES_ICH5 | FEATURE_IDF) },
> + { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS1, FEATURES_ICH5 | FEATURE_IDF) },
> + { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS2, FEATURES_ICH5 | FEATURE_IDF) },
> + { PCI_DEVICE_DATA(INTEL, COLETOCREEK_SMBUS, FEATURES_ICH5) },
> + { PCI_DEVICE_DATA(INTEL, GEMINILAKE_SMBUS, FEATURES_ICH5) },
> + { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_SMBUS, FEATURES_ICH5) },
> + { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_LP_SMBUS, FEATURES_ICH5) },
> + { PCI_DEVICE_DATA(INTEL, BAYTRAIL_SMBUS, FEATURES_ICH5) },
> + { PCI_DEVICE_DATA(INTEL, BRASWELL_SMBUS, FEATURES_ICH5) },
> + { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
> + { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
> + { PCI_DEVICE_DATA(INTEL, CDF_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> + { PCI_DEVICE_DATA(INTEL, DNV_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
> + { PCI_DEVICE_DATA(INTEL, EBG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> + { PCI_DEVICE_DATA(INTEL, BROXTON_SMBUS, FEATURES_ICH5) },
> + { PCI_DEVICE_DATA(INTEL, LEWISBURG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
> + { PCI_DEVICE_DATA(INTEL, LEWISBURG_SSKU_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
> + { PCI_DEVICE_DATA(INTEL, KABYLAKE_PCH_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
> + { PCI_DEVICE_DATA(INTEL, CANNONLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> + { PCI_DEVICE_DATA(INTEL, CANNONLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> + { PCI_DEVICE_DATA(INTEL, ICELAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> + { PCI_DEVICE_DATA(INTEL, ICELAKE_N_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> + { PCI_DEVICE_DATA(INTEL, COMETLAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> + { PCI_DEVICE_DATA(INTEL, COMETLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> + { PCI_DEVICE_DATA(INTEL, COMETLAKE_V_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
> + { PCI_DEVICE_DATA(INTEL, ELKHART_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> + { PCI_DEVICE_DATA(INTEL, TIGERLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> + { PCI_DEVICE_DATA(INTEL, TIGERLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> + { PCI_DEVICE_DATA(INTEL, JASPER_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> + { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> + { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> + { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_M_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> + { PCI_DEVICE_DATA(INTEL, RAPTOR_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> + { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> { 0, }
> };
>
Reviewed-by: Jean Delvare <jdelvare@suse.de>
--
Jean Delvare
SUSE L3 Support
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 2/3] i2c: i801: Add support for Intel Meteor Lake SoC-S
2023-05-12 11:50 ` [PATCH v3 2/3] i2c: i801: Add support for Intel Meteor Lake SoC-S Jarkko Nikula
2023-05-19 11:07 ` Andi Shyti
@ 2023-05-23 17:35 ` Jean Delvare
1 sibling, 0 replies; 9+ messages in thread
From: Jean Delvare @ 2023-05-23 17:35 UTC (permalink / raw)
To: Jarkko Nikula; +Cc: linux-i2c, Wolfram Sang, Andi Shyti
On Fri, 12 May 2023 14:50:00 +0300, Jarkko Nikula wrote:
> Add SMBus PCI ID on Intel Meteor Lake SoC-S South.
>
> Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
> ---
> v3: Call this explicitly as Meteor Lake SoC-S SMBus controller for
> distinguish from Meteor Lake PCH-S SMBus controller in patch 3/3.
> v2: Keep PCI ID define list sorted and define
> PCI_DEVICE_ID_INTEL_METEOR_LAKE_S_SMBUS in correct place.
> ---
> drivers/i2c/busses/i2c-i801.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
> index 7431e8411e99..bc2576188e0a 100644
> --- a/drivers/i2c/busses/i2c-i801.c
> +++ b/drivers/i2c/busses/i2c-i801.c
> @@ -77,6 +77,7 @@
> * Alder Lake-M (PCH) 0x54a3 32 hard yes yes yes
> * Raptor Lake-S (PCH) 0x7a23 32 hard yes yes yes
> * Meteor Lake-P (SOC) 0x7e22 32 hard yes yes yes
> + * Meteor Lake SoC-S (SOC) 0xae22 32 hard yes yes yes
> *
> * Features supported by this driver:
> * Software PEC no
> @@ -250,6 +251,7 @@
> #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3
> #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323
> #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS 0xa3a3
> +#define PCI_DEVICE_ID_INTEL_METEOR_LAKE_SOC_S_SMBUS 0xae22
>
> struct i801_mux_config {
> char *gpio_chip;
> @@ -1038,6 +1040,7 @@ static const struct pci_device_id i801_ids[] = {
> { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_M_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> { PCI_DEVICE_DATA(INTEL, RAPTOR_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> + { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_SOC_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> { 0, }
> };
>
Reviewed-by: Jean Delvare <jdelvare@suse.de>
--
Jean Delvare
SUSE L3 Support
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 3/3] i2c: i801: Add support for Intel Meteor Lake PCH-S
2023-05-12 11:50 ` [PATCH v3 3/3] i2c: i801: Add support for Intel Meteor Lake PCH-S Jarkko Nikula
2023-05-19 11:08 ` Andi Shyti
@ 2023-05-23 17:35 ` Jean Delvare
1 sibling, 0 replies; 9+ messages in thread
From: Jean Delvare @ 2023-05-23 17:35 UTC (permalink / raw)
To: Jarkko Nikula; +Cc: linux-i2c, Wolfram Sang, Andi Shyti
On Fri, 12 May 2023 14:50:01 +0300, Jarkko Nikula wrote:
> Add SMBus PCI ID on Intel Meteor Lake PCH-S.
>
> Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
> ---
> v3: Drop the idea to call this as Meteor Point-S in code since it's confusing.
> Intel Meteor Lake-S platform can have the SMBus controller both in
> SoC die and PCH. I decided earlier to call latter as Meteor Point-S since
> it fitted nicely into i801_ids table and I saw it to be used somewhere in
> internal documentation. But it's more historical naming convension for
> PCHs and to be honest internal documentation uses mostly Meteor Lake PCH-S.
> v2: "SOC/PCH" -> "SOC and PCH" in documentation and Kconfig. PCI ID
> define according to updated patch 1/2.
> ---
> Documentation/i2c/busses/i2c-i801.rst | 2 +-
> drivers/i2c/busses/Kconfig | 2 +-
> drivers/i2c/busses/i2c-i801.c | 3 +++
> 3 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/i2c/busses/i2c-i801.rst b/Documentation/i2c/busses/i2c-i801.rst
> index ab9e850e8fe0..e76e68ccf718 100644
> --- a/Documentation/i2c/busses/i2c-i801.rst
> +++ b/Documentation/i2c/busses/i2c-i801.rst
> @@ -46,7 +46,7 @@ Supported adapters:
> * Intel Emmitsburg (PCH)
> * Intel Alder Lake (PCH)
> * Intel Raptor Lake (PCH)
> - * Intel Meteor Lake (SOC)
> + * Intel Meteor Lake (SOC and PCH)
>
> Datasheets: Publicly available at the Intel website
>
> diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
> index 87600b4aacb3..3144ef99f040 100644
> --- a/drivers/i2c/busses/Kconfig
> +++ b/drivers/i2c/busses/Kconfig
> @@ -157,7 +157,7 @@ config I2C_I801
> Emmitsburg (PCH)
> Alder Lake (PCH)
> Raptor Lake (PCH)
> - Meteor Lake (SOC)
> + Meteor Lake (SOC and PCH)
>
> This driver can also be built as a module. If so, the module
> will be called i2c-i801.
> diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
> index bc2576188e0a..943b8e6d026d 100644
> --- a/drivers/i2c/busses/i2c-i801.c
> +++ b/drivers/i2c/busses/i2c-i801.c
> @@ -78,6 +78,7 @@
> * Raptor Lake-S (PCH) 0x7a23 32 hard yes yes yes
> * Meteor Lake-P (SOC) 0x7e22 32 hard yes yes yes
> * Meteor Lake SoC-S (SOC) 0xae22 32 hard yes yes yes
> + * Meteor Lake PCH-S (PCH) 0x7f23 32 hard yes yes yes
> *
> * Features supported by this driver:
> * Software PEC no
> @@ -234,6 +235,7 @@
> #define PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_S_SMBUS 0x7a23
> #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS 0x7aa3
> #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_P_SMBUS 0x7e22
> +#define PCI_DEVICE_ID_INTEL_METEOR_LAKE_PCH_S_SMBUS 0x7f23
> #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
> #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2
> #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
> @@ -1041,6 +1043,7 @@ static const struct pci_device_id i801_ids[] = {
> { PCI_DEVICE_DATA(INTEL, RAPTOR_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_SOC_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> + { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_PCH_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
> { 0, }
> };
>
Reviewed-by: Jean Delvare <jdelvare@suse.de>
--
Jean Delvare
SUSE L3 Support
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2023-05-23 17:36 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-05-12 11:49 [PATCH v3 1/3] i2c: i801: Enlarge device name field in i801_ids table Jarkko Nikula
2023-05-12 11:50 ` [PATCH v3 2/3] i2c: i801: Add support for Intel Meteor Lake SoC-S Jarkko Nikula
2023-05-19 11:07 ` Andi Shyti
2023-05-23 17:35 ` Jean Delvare
2023-05-12 11:50 ` [PATCH v3 3/3] i2c: i801: Add support for Intel Meteor Lake PCH-S Jarkko Nikula
2023-05-19 11:08 ` Andi Shyti
2023-05-23 17:35 ` Jean Delvare
2023-05-19 11:05 ` [PATCH v3 1/3] i2c: i801: Enlarge device name field in i801_ids table Andi Shyti
2023-05-23 16:42 ` Jean Delvare
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).