linux-i2c.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
* [PATCH v2] i2c: cadence: Avoid fifo clear after start
@ 2024-05-03  9:42 Sai Pavan Boddu
  2024-05-03 18:46 ` Andi Shyti
  0 siblings, 1 reply; 2+ messages in thread
From: Sai Pavan Boddu @ 2024-05-03  9:42 UTC (permalink / raw)
  To: linux-arm-kernel, linux-i2c, linux-kernel
  Cc: Michal Simek, Andi Shyti, Lars-Peter Clausen, Wolfram Sang

The Driver unintentionally programs ctrl reg to clear the fifo, which
happens after the start of transaction. Previously, this was not an issue
as it involved read-modified-write. However, this issue breaks i2c reads
on QEMU, as i2c-read is executed before guest starts programming control
register.

Fixes: ff0cf7bca630 ("i2c: cadence: Remove unnecessary register reads")
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
Acked-by: Michal Simek <michal.simek@amd.com>
---
Changes for V2:
	Fix commit message.

 drivers/i2c/busses/i2c-cadence.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/i2c/busses/i2c-cadence.c b/drivers/i2c/busses/i2c-cadence.c
index 4bb7d6756947..2fce3e84ba64 100644
--- a/drivers/i2c/busses/i2c-cadence.c
+++ b/drivers/i2c/busses/i2c-cadence.c
@@ -633,6 +633,7 @@ static void cdns_i2c_mrecv(struct cdns_i2c *id)
 
 	if (hold_clear) {
 		ctrl_reg &= ~CDNS_I2C_CR_HOLD;
+		ctrl_reg &= ~CDNS_I2C_CR_CLR_FIFO;
 		/*
 		 * In case of Xilinx Zynq SOC, clear the HOLD bit before transfer size
 		 * register reaches '0'. This is an IP bug which causes transfer size
-- 
2.37.6


^ permalink raw reply related	[flat|nested] 2+ messages in thread

* Re: [PATCH v2] i2c: cadence: Avoid fifo clear after start
  2024-05-03  9:42 [PATCH v2] i2c: cadence: Avoid fifo clear after start Sai Pavan Boddu
@ 2024-05-03 18:46 ` Andi Shyti
  0 siblings, 0 replies; 2+ messages in thread
From: Andi Shyti @ 2024-05-03 18:46 UTC (permalink / raw)
  To: Sai Pavan Boddu
  Cc: linux-arm-kernel, linux-i2c, linux-kernel, Michal Simek,
	Lars-Peter Clausen, Wolfram Sang

Hi Sai Pavan,

On Fri, May 03, 2024 at 03:12:08PM +0530, Sai Pavan Boddu wrote:
> The Driver unintentionally programs ctrl reg to clear the fifo, which
> happens after the start of transaction. Previously, this was not an issue
> as it involved read-modified-write. However, this issue breaks i2c reads
> on QEMU, as i2c-read is executed before guest starts programming control
> register.
> 
> Fixes: ff0cf7bca630 ("i2c: cadence: Remove unnecessary register reads")
> Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
> Acked-by: Michal Simek <michal.simek@amd.com>

pushed to i2c/i2c-host-fixes.

I will send it for pull request next week as this week is already
too late and I want to see a few rounds of tests before asking
Wolfram to take it.

Thanks,
Andi

^ permalink raw reply	[flat|nested] 2+ messages in thread

end of thread, other threads:[~2024-05-03 18:46 UTC | newest]

Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-05-03  9:42 [PATCH v2] i2c: cadence: Avoid fifo clear after start Sai Pavan Boddu
2024-05-03 18:46 ` Andi Shyti

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).