[Patch V8 0/3] Tegra TPM driver with HW flow control

[Patch V8 0/3] Tegra TPM driver with HW flow control

[Krishna Yarlagadda]

TPM devices may insert wait state on last clock cycle of ADDR phase.
For SPI controllers that support full-duplex transfers, this can be
detected using software by reading the MISO line. For SPI controllers
that only support half-duplex transfers, such as the Tegra QSPI, it is
not possible to detect the wait signal from software. The QSPI
controller in Tegra234 and Tegra241 implement hardware detection of the
wait signal which can be enabled in the controller for TPM devices.

Add HW flow control in TIS driver and a flag in SPI data to indicate
wait detection is required in HW. SPI controller driver determines if
this is supported. Add HW detection in Tegra QSPI controller.

Updates in this patch set 
 - Tegra QSPI identifies itself as half duplex.
 - TPM TIS SPI driver skips flow control for half duplex and send
   transfers in single message for controller to handle it.
 - TPM device identifies as TPM device for controller to detect and
   enable HW TPM wait poll feature.

Verified with a TPM device on Tegra241 ref board using TPM2 tools.

V8:
 - fix compile warning.
V7:
 - updated patch description.
 - TPM flag set in probe.
 - minor comments.
V6:
 - Fix typo in chip name Tegra234.
 - Debug logs change skipped to be sent later.
 - Consistent usage of soc flag.
V5:
 - No SPI bus locking.
V4:
 - Split api change to different patch.
 - Describe TPM HW flow control.
V3:
 - Use SPI device mode flag and SPI controller flags.
 - Drop usage of device tree flags.
 - Generic TPM half duplex controller handling.
 - HW & SW flow control for TPM. Drop additional driver.
V2:
 - Fix dt schema errors.

Krishna Yarlagadda (3):
  spi: Add TPM HW flow flag
  tpm_tis-spi: Add hardware wait polling
  spi: tegra210-quad: Enable TPM wait polling

 drivers/char/tpm/tpm_tis_spi_main.c | 95 ++++++++++++++++++++++++++++-
 drivers/spi/spi-tegra210-quad.c     | 14 +++++
 include/linux/spi/spi.h             | 16 ++++-
 3 files changed, 120 insertions(+), 5 deletions(-)

-- 
2.17.1

[Patch V8 1/3] spi: Add TPM HW flow flag

[Krishna Yarlagadda]

TPM specification [1] defines flow control over SPI. Client device can
insert a wait state on MISO when address is transmitted by controller
on MOSI. Detecting the wait state in software is only possible for
full duplex controllers. For controllers that support only half-
duplex, the wait state detection needs to be implemented in hardware.

Add a flag SPI_TPM_HW_FLOW for TPM device to set when software flow
control is not possible and hardware flow control is expected from
SPI controller.

Reference:
[1] https://trustedcomputinggroup.org/resource/pc-client-work-group-
pc-client-specific-tpm-interface-specification-tis/

Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
---
 include/linux/spi/spi.h | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 4fa26b9a3572..b9e49ed42955 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -184,8 +184,18 @@ struct spi_device {
 	u8			chip_select;
 	u8			bits_per_word;
 	bool			rt;
-#define SPI_NO_TX	BIT(31)		/* No transmit wire */
-#define SPI_NO_RX	BIT(30)		/* No receive wire */
+#define SPI_NO_TX		BIT(31)		/* No transmit wire */
+#define SPI_NO_RX		BIT(30)		/* No receive wire */
+	/*
+	 * TPM specification defines flow control over SPI. Client device
+	 * can insert a wait state on MISO when address is transmitted by
+	 * controller on MOSI. Detecting the wait state in software is only
+	 * possible for full duplex controllers. For controllers that support
+	 * only half-duplex, the wait state detection needs to be implemented
+	 * in hardware. TPM devices would set this flag when hardware flow
+	 * control is expected from SPI controller.
+	 */
+#define SPI_TPM_HW_FLOW		BIT(29)		/* TPM HW flow control */
 	/*
 	 * All bits defined above should be covered by SPI_MODE_KERNEL_MASK.
 	 * The SPI_MODE_KERNEL_MASK has the SPI_MODE_USER_MASK counterpart,
@@ -195,7 +205,7 @@ struct spi_device {
 	 * These bits must not overlap. A static assert check should make sure of that.
 	 * If adding extra bits, make sure to decrease the bit index below as well.
 	 */
-#define SPI_MODE_KERNEL_MASK	(~(BIT(30) - 1))
+#define SPI_MODE_KERNEL_MASK	(~(BIT(29) - 1))
 	u32			mode;
 	int			irq;
 	void			*controller_state;
-- 
2.17.1

[Patch V8 2/3] tpm_tis-spi: Add hardware wait polling

[Krishna Yarlagadda]

TPM devices may insert wait state on last clock cycle of ADDR phase.
For SPI controllers that support full-duplex transfers, this can be
detected using software by reading the MISO line. For SPI controllers
that only support half-duplex transfers, such as the Tegra QSPI, it is
not possible to detect the wait signal from software. The QSPI
controller in Tegra234 and Tegra241 implement hardware detection of the
wait signal which can be enabled in the controller for TPM devices.

The current TPM TIS driver only supports software detection of the wait
signal. To support SPI controllers that use hardware to detect the wait
signal, add the function tpm_tis_spi_hw_flow_transfer() and move the
existing code for software based detection into a function called
tpm_tis_spi_sw_flow_transfer(). SPI controllers that only support
half-duplex transfers will always call tpm_tis_spi_hw_flow_transfer()
because they cannot support software based detection. The bit
SPI_TPM_HW_FLOW is set to indicate to the SPI controller that hardware
detection is required and it is the responsibility of the SPI controller
driver to determine if this is supported or not.

For hardware flow control, CMD-ADDR-DATA messages are combined into a
single message where as for software flow control exiting method of
CMD-ADDR in a message and DATA in another is followed.

Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
---
 drivers/char/tpm/tpm_tis_spi_main.c | 95 ++++++++++++++++++++++++++++-
 1 file changed, 93 insertions(+), 2 deletions(-)

diff --git a/drivers/char/tpm/tpm_tis_spi_main.c b/drivers/char/tpm/tpm_tis_spi_main.c
index a0963a3e92bd..d0c1073bfa06 100644
--- a/drivers/char/tpm/tpm_tis_spi_main.c
+++ b/drivers/char/tpm/tpm_tis_spi_main.c
@@ -71,8 +71,76 @@ static int tpm_tis_spi_flow_control(struct tpm_tis_spi_phy *phy,
 	return 0;
 }
 
-int tpm_tis_spi_transfer(struct tpm_tis_data *data, u32 addr, u16 len,
-			 u8 *in, const u8 *out)
+/*
+ * Half duplex controller with support for TPM wait state detection like
+ * Tegra QSPI need CMD, ADDR & DATA sent in single message to manage HW flow
+ * control. Each phase sent in different transfer for controller to idenity
+ * phase.
+ */
+static int tpm_tis_spi_hw_flow_transfer(struct tpm_tis_data *data,
+					u32 addr, u16 len, u8 *in,
+					const u8 *out)
+{
+	struct tpm_tis_spi_phy *phy = to_tpm_tis_spi_phy(data);
+	struct spi_transfer spi_xfer[3];
+	struct spi_message m;
+	u8 transfer_len;
+	int ret;
+
+	while (len) {
+		transfer_len = min_t(u16, len, MAX_SPI_FRAMESIZE);
+
+		spi_message_init(&m);
+		phy->iobuf[0] = (in ? 0x80 : 0) | (transfer_len - 1);
+		phy->iobuf[1] = 0xd4;
+		phy->iobuf[2] = addr >> 8;
+		phy->iobuf[3] = addr;
+
+		memset(&spi_xfer, 0, sizeof(spi_xfer));
+
+		spi_xfer[0].tx_buf = phy->iobuf;
+		spi_xfer[0].len = 1;
+		spi_message_add_tail(&spi_xfer[0], &m);
+
+		spi_xfer[1].tx_buf = phy->iobuf + 1;
+		spi_xfer[1].len = 3;
+		spi_message_add_tail(&spi_xfer[1], &m);
+
+		if (out) {
+			spi_xfer[2].tx_buf = &phy->iobuf[4];
+			spi_xfer[2].rx_buf = NULL;
+			memcpy(&phy->iobuf[4], out, transfer_len);
+			out += transfer_len;
+		}
+
+		if (in) {
+			spi_xfer[2].tx_buf = NULL;
+			spi_xfer[2].rx_buf = &phy->iobuf[4];
+		}
+
+		spi_xfer[2].len = transfer_len;
+		spi_message_add_tail(&spi_xfer[2], &m);
+
+		reinit_completion(&phy->ready);
+
+		ret = spi_sync_locked(phy->spi_device, &m);
+		if (ret < 0)
+			return ret;
+
+		if (in) {
+			memcpy(in, &phy->iobuf[4], transfer_len);
+			in += transfer_len;
+		}
+
+		len -= transfer_len;
+	}
+
+	return ret;
+}
+
+static int tpm_tis_spi_sw_flow_transfer(struct tpm_tis_data *data,
+					u32 addr, u16 len, u8 *in,
+					const u8 *out)
 {
 	struct tpm_tis_spi_phy *phy = to_tpm_tis_spi_phy(data);
 	int ret = 0;
@@ -140,6 +208,26 @@ int tpm_tis_spi_transfer(struct tpm_tis_data *data, u32 addr, u16 len,
 	return ret;
 }
 
+int tpm_tis_spi_transfer(struct tpm_tis_data *data, u32 addr, u16 len,
+			 u8 *in, const u8 *out)
+{
+	struct tpm_tis_spi_phy *phy = to_tpm_tis_spi_phy(data);
+	struct spi_controller *ctlr = phy->spi_device->controller;
+
+	/*
+	 * TPM flow control over SPI requires full duplex support.
+	 * Send entire message to a half duplex controller to handle
+	 * wait polling in controller.
+	 * Set TPM HW flow control flag..
+	 */
+	if (ctlr->flags & SPI_CONTROLLER_HALF_DUPLEX)
+		return tpm_tis_spi_hw_flow_transfer(data, addr, len, in,
+						    out);
+	else
+		return tpm_tis_spi_sw_flow_transfer(data, addr, len, in,
+						    out);
+}
+
 static int tpm_tis_spi_read_bytes(struct tpm_tis_data *data, u32 addr,
 				  u16 len, u8 *result, enum tpm_tis_io_mode io_mode)
 {
@@ -181,6 +269,9 @@ static int tpm_tis_spi_probe(struct spi_device *dev)
 
 	phy->flow_control = tpm_tis_spi_flow_control;
 
+	if (dev->controller->flags & SPI_CONTROLLER_HALF_DUPLEX)
+		dev->mode |= SPI_TPM_HW_FLOW;
+
 	/* If the SPI device has an IRQ then use that */
 	if (dev->irq > 0)
 		irq = dev->irq;
-- 
2.17.1

[Patch V8 3/3] spi: tegra210-quad: Enable TPM wait polling

[Krishna Yarlagadda]

Trusted Platform Module requires flow control. As defined in TPM
interface specification, client would drive MISO line at same cycle as
last address bit on MOSI.
Tegra234 and Tegra241 QSPI controllers have TPM wait state detection
feature which is enabled for TPM client devices reported in SPI device
mode bits.

Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
---
 drivers/spi/spi-tegra210-quad.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c
index 0b9bc3b7f53a..82aec6cb7863 100644
--- a/drivers/spi/spi-tegra210-quad.c
+++ b/drivers/spi/spi-tegra210-quad.c
@@ -142,6 +142,7 @@
 
 #define QSPI_GLOBAL_CONFIG			0X1a4
 #define QSPI_CMB_SEQ_EN				BIT(0)
+#define QSPI_TPM_WAIT_POLL_EN			BIT(1)
 
 #define QSPI_CMB_SEQ_ADDR			0x1a8
 #define QSPI_ADDRESS_VALUE_SET(X)		(((x) & 0xFFFF) << 0)
@@ -164,6 +165,7 @@
 struct tegra_qspi_soc_data {
 	bool has_dma;
 	bool cmb_xfer_capable;
+	bool supports_tpm;
 	unsigned int cs_count;
 };
 
@@ -1065,6 +1067,12 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi,
 
 	/* Enable Combined sequence mode */
 	val = tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG);
+	if (spi->mode & SPI_TPM_HW_FLOW) {
+		if (tqspi->soc_data->supports_tpm)
+			val |= QSPI_TPM_WAIT_POLL_EN;
+		else
+			return -EIO;
+	}
 	val |= QSPI_CMB_SEQ_EN;
 	tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG);
 	/* Process individual transfer list */
@@ -1196,6 +1204,8 @@ static int tegra_qspi_non_combined_seq_xfer(struct tegra_qspi *tqspi,
 	/* Disable Combined sequence mode */
 	val = tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG);
 	val &= ~QSPI_CMB_SEQ_EN;
+	if (tqspi->soc_data->supports_tpm)
+		val &= ~QSPI_TPM_WAIT_POLL_EN;
 	tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG);
 	list_for_each_entry(transfer, &msg->transfers, transfer_list) {
 		struct spi_transfer *xfer = transfer;
@@ -1454,24 +1464,28 @@ static irqreturn_t tegra_qspi_isr_thread(int irq, void *context_data)
 static struct tegra_qspi_soc_data tegra210_qspi_soc_data = {
 	.has_dma = true,
 	.cmb_xfer_capable = false,
+	.supports_tpm = false,
 	.cs_count = 1,
 };
 
 static struct tegra_qspi_soc_data tegra186_qspi_soc_data = {
 	.has_dma = true,
 	.cmb_xfer_capable = true,
+	.supports_tpm = false,
 	.cs_count = 1,
 };
 
 static struct tegra_qspi_soc_data tegra234_qspi_soc_data = {
 	.has_dma = false,
 	.cmb_xfer_capable = true,
+	.supports_tpm = true,
 	.cs_count = 1,
 };
 
 static struct tegra_qspi_soc_data tegra241_qspi_soc_data = {
 	.has_dma = false,
 	.cmb_xfer_capable = true,
+	.supports_tpm = true,
 	.cs_count = 4,
 };
 
-- 
2.17.1

Re: [Patch V8 2/3] tpm_tis-spi: Add hardware wait polling

[Jarkko Sakkinen]

On Thu, 2023-03-02 at 09:48 +0530, Krishna Yarlagadda wrote:
> +int tpm_tis_spi_transfer(struct tpm_tis_data *data, u32 addr, u16
> len,
> +                        u8 *in, const u8 *out)
> +{
> +       struct tpm_tis_spi_phy *phy = to_tpm_tis_spi_phy(data);
> +       struct spi_controller *ctlr = phy->spi_device->controller;
> +
> +       /*
> +        * TPM flow control over SPI requires full duplex support.
> +        * Send entire message to a half duplex controller to handle
> +        * wait polling in controller.
> +        * Set TPM HW flow control flag..
> +        */
> +       if (ctlr->flags & SPI_CONTROLLER_HALF_DUPLEX)
> +               return tpm_tis_spi_hw_flow_transfer(data, addr, len,
> in,
> +                                                   out);
> +       else
> +               return tpm_tis_spi_sw_flow_transfer(data, addr, len,
> in,
> +                                                   out);
> +}
> +

Based on the condition, better names would be

1. tpm_tis_spi_transfer_half()
2. tpm_tis_spi_transfer_full()

BR, Jarkko

RE: [Patch V8 2/3] tpm_tis-spi: Add hardware wait polling

[Krishna Yarlagadda]

> -----Original Message-----
> From: Jarkko Sakkinen <jarkko@kernel.org>
> Sent: 12 March 2023 03:19
> To: Krishna Yarlagadda <kyarlagadda@nvidia.com>; robh+dt@kernel.org;
> broonie@kernel.org; peterhuewe@gmx.de; jgg@ziepe.ca;
> krzysztof.kozlowski+dt@linaro.org; linux-spi@vger.kernel.org; linux-
> tegra@vger.kernel.org; linux-integrity@vger.kernel.org; linux-
> kernel@vger.kernel.org
> Cc: thierry.reding@gmail.com; Jonathan Hunter <jonathanh@nvidia.com>;
> Sowjanya Komatineni <skomatineni@nvidia.com>; Laxman Dewangan
> <ldewangan@nvidia.com>
> Subject: Re: [Patch V8 2/3] tpm_tis-spi: Add hardware wait polling
> 
> External email: Use caution opening links or attachments
> 
> 
> On Thu, 2023-03-02 at 09:48 +0530, Krishna Yarlagadda wrote:
> > +int tpm_tis_spi_transfer(struct tpm_tis_data *data, u32 addr, u16
> > len,
> > +                        u8 *in, const u8 *out)
> > +{
> > +       struct tpm_tis_spi_phy *phy = to_tpm_tis_spi_phy(data);
> > +       struct spi_controller *ctlr = phy->spi_device->controller;
> > +
> > +       /*
> > +        * TPM flow control over SPI requires full duplex support.
> > +        * Send entire message to a half duplex controller to handle
> > +        * wait polling in controller.
> > +        * Set TPM HW flow control flag..
> > +        */
> > +       if (ctlr->flags & SPI_CONTROLLER_HALF_DUPLEX)
> > +               return tpm_tis_spi_hw_flow_transfer(data, addr, len,
> > in,
> > +                                                   out);
> > +       else
> > +               return tpm_tis_spi_sw_flow_transfer(data, addr, len,
> > in,
> > +                                                   out);
> > +}
> > +
> 
> Based on the condition, better names would be
Though condition is based on half duplex, functions are implementing
HW or SW flow of the transfer.
KY
> 
> 1. tpm_tis_spi_transfer_half()
> 2. tpm_tis_spi_transfer_full()
> 
> BR, Jarkko

Re: [Patch V8 2/3] tpm_tis-spi: Add hardware wait polling

[Jarkko Sakkinen]

On Wed, Mar 15, 2023 at 03:47:33PM +0000, Krishna Yarlagadda wrote:
> 
> > -----Original Message-----
> > From: Jarkko Sakkinen <jarkko@kernel.org>
> > Sent: 12 March 2023 03:19
> > To: Krishna Yarlagadda <kyarlagadda@nvidia.com>; robh+dt@kernel.org;
> > broonie@kernel.org; peterhuewe@gmx.de; jgg@ziepe.ca;
> > krzysztof.kozlowski+dt@linaro.org; linux-spi@vger.kernel.org; linux-
> > tegra@vger.kernel.org; linux-integrity@vger.kernel.org; linux-
> > kernel@vger.kernel.org
> > Cc: thierry.reding@gmail.com; Jonathan Hunter <jonathanh@nvidia.com>;
> > Sowjanya Komatineni <skomatineni@nvidia.com>; Laxman Dewangan
> > <ldewangan@nvidia.com>
> > Subject: Re: [Patch V8 2/3] tpm_tis-spi: Add hardware wait polling
> > 
> > External email: Use caution opening links or attachments
> > 
> > 
> > On Thu, 2023-03-02 at 09:48 +0530, Krishna Yarlagadda wrote:
> > > +int tpm_tis_spi_transfer(struct tpm_tis_data *data, u32 addr, u16
> > > len,
> > > +                        u8 *in, const u8 *out)
> > > +{
> > > +       struct tpm_tis_spi_phy *phy = to_tpm_tis_spi_phy(data);
> > > +       struct spi_controller *ctlr = phy->spi_device->controller;
> > > +
> > > +       /*
> > > +        * TPM flow control over SPI requires full duplex support.
> > > +        * Send entire message to a half duplex controller to handle
> > > +        * wait polling in controller.
> > > +        * Set TPM HW flow control flag..
> > > +        */
> > > +       if (ctlr->flags & SPI_CONTROLLER_HALF_DUPLEX)
> > > +               return tpm_tis_spi_hw_flow_transfer(data, addr, len,
> > > in,
> > > +                                                   out);
> > > +       else
> > > +               return tpm_tis_spi_sw_flow_transfer(data, addr, len,
> > > in,
> > > +                                                   out);
> > > +}
> > > +
> > 
> > Based on the condition, better names would be
> Though condition is based on half duplex, functions are implementing
> HW or SW flow of the transfer.

Both are hardwaw flows in the sense that you are controlling a piece of hardware.

BR, Jarkko

RE: [Patch V8 2/3] tpm_tis-spi: Add hardware wait polling

[Krishna Yarlagadda]

> -----Original Message-----
> From: Jarkko Sakkinen <jarkko@kernel.org>
> Sent: 19 March 2023 19:13
> To: Krishna Yarlagadda <kyarlagadda@nvidia.com>
> Cc: robh+dt@kernel.org; broonie@kernel.org; peterhuewe@gmx.de;
> jgg@ziepe.ca; krzysztof.kozlowski+dt@linaro.org; linux-spi@vger.kernel.org;
> linux-tegra@vger.kernel.org; linux-integrity@vger.kernel.org; linux-
> kernel@vger.kernel.org; thierry.reding@gmail.com; Jonathan Hunter
> <jonathanh@nvidia.com>; Sowjanya Komatineni
> <skomatineni@nvidia.com>; Laxman Dewangan <ldewangan@nvidia.com>
> Subject: Re: [Patch V8 2/3] tpm_tis-spi: Add hardware wait polling
> 
> External email: Use caution opening links or attachments
> 
> 
> On Wed, Mar 15, 2023 at 03:47:33PM +0000, Krishna Yarlagadda wrote:
> >
> > > -----Original Message-----
> > > From: Jarkko Sakkinen <jarkko@kernel.org>
> > > Sent: 12 March 2023 03:19
> > > To: Krishna Yarlagadda <kyarlagadda@nvidia.com>; robh+dt@kernel.org;
> > > broonie@kernel.org; peterhuewe@gmx.de; jgg@ziepe.ca;
> > > krzysztof.kozlowski+dt@linaro.org; linux-spi@vger.kernel.org; linux-
> > > tegra@vger.kernel.org; linux-integrity@vger.kernel.org; linux-
> > > kernel@vger.kernel.org
> > > Cc: thierry.reding@gmail.com; Jonathan Hunter
> <jonathanh@nvidia.com>;
> > > Sowjanya Komatineni <skomatineni@nvidia.com>; Laxman Dewangan
> > > <ldewangan@nvidia.com>
> > > Subject: Re: [Patch V8 2/3] tpm_tis-spi: Add hardware wait polling
> > >
> > > External email: Use caution opening links or attachments
> > >
> > >
> > > On Thu, 2023-03-02 at 09:48 +0530, Krishna Yarlagadda wrote:
> > > > +int tpm_tis_spi_transfer(struct tpm_tis_data *data, u32 addr, u16
> > > > len,
> > > > +                        u8 *in, const u8 *out)
> > > > +{
> > > > +       struct tpm_tis_spi_phy *phy = to_tpm_tis_spi_phy(data);
> > > > +       struct spi_controller *ctlr = phy->spi_device->controller;
> > > > +
> > > > +       /*
> > > > +        * TPM flow control over SPI requires full duplex support.
> > > > +        * Send entire message to a half duplex controller to handle
> > > > +        * wait polling in controller.
> > > > +        * Set TPM HW flow control flag..
> > > > +        */
> > > > +       if (ctlr->flags & SPI_CONTROLLER_HALF_DUPLEX)
> > > > +               return tpm_tis_spi_hw_flow_transfer(data, addr, len,
> > > > in,
> > > > +                                                   out);
> > > > +       else
> > > > +               return tpm_tis_spi_sw_flow_transfer(data, addr, len,
> > > > in,
> > > > +                                                   out);
> > > > +}
> > > > +
> > >
> > > Based on the condition, better names would be
> > Though condition is based on half duplex, functions are implementing
> > HW or SW flow of the transfer.
> 
> Both are hardwaw flows in the sense that you are controlling a piece of
> hardware.
> 
> BR, Jarkko
Yes. I will push new version with naming suggested.
KY

Re: [Patch V8 1/3] spi: Add TPM HW flow flag

[Jerry Snitselaar]

On Thu, Mar 02, 2023 at 09:48:02AM +0530, Krishna Yarlagadda wrote:
> TPM specification [1] defines flow control over SPI. Client device can
> insert a wait state on MISO when address is transmitted by controller
> on MOSI. Detecting the wait state in software is only possible for
> full duplex controllers. For controllers that support only half-
> duplex, the wait state detection needs to be implemented in hardware.
> 
> Add a flag SPI_TPM_HW_FLOW for TPM device to set when software flow
> control is not possible and hardware flow control is expected from
> SPI controller.
> 
> Reference:
> [1] https://trustedcomputinggroup.org/resource/pc-client-work-group-
> pc-client-specific-tpm-interface-specification-tis/
> 

Minor thing, but should this reference the newer specification [1]?

[1] https://trustedcomputinggroup.org/resource/pc-client-platform-tpm-profile-ptp-specification/


Regards,
Jerry

> Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
> ---
>  include/linux/spi/spi.h | 16 +++++++++++++---
>  1 file changed, 13 insertions(+), 3 deletions(-)
> 
> diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
> index 4fa26b9a3572..b9e49ed42955 100644
> --- a/include/linux/spi/spi.h
> +++ b/include/linux/spi/spi.h
> @@ -184,8 +184,18 @@ struct spi_device {
>  	u8			chip_select;
>  	u8			bits_per_word;
>  	bool			rt;
> -#define SPI_NO_TX	BIT(31)		/* No transmit wire */
> -#define SPI_NO_RX	BIT(30)		/* No receive wire */
> +#define SPI_NO_TX		BIT(31)		/* No transmit wire */
> +#define SPI_NO_RX		BIT(30)		/* No receive wire */
> +	/*
> +	 * TPM specification defines flow control over SPI. Client device
> +	 * can insert a wait state on MISO when address is transmitted by
> +	 * controller on MOSI. Detecting the wait state in software is only
> +	 * possible for full duplex controllers. For controllers that support
> +	 * only half-duplex, the wait state detection needs to be implemented
> +	 * in hardware. TPM devices would set this flag when hardware flow
> +	 * control is expected from SPI controller.
> +	 */
> +#define SPI_TPM_HW_FLOW		BIT(29)		/* TPM HW flow control */
>  	/*
>  	 * All bits defined above should be covered by SPI_MODE_KERNEL_MASK.
>  	 * The SPI_MODE_KERNEL_MASK has the SPI_MODE_USER_MASK counterpart,
> @@ -195,7 +205,7 @@ struct spi_device {
>  	 * These bits must not overlap. A static assert check should make sure of that.
>  	 * If adding extra bits, make sure to decrease the bit index below as well.
>  	 */
> -#define SPI_MODE_KERNEL_MASK	(~(BIT(30) - 1))
> +#define SPI_MODE_KERNEL_MASK	(~(BIT(29) - 1))
>  	u32			mode;
>  	int			irq;
>  	void			*controller_state;
> -- 
> 2.17.1
>