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* [PATCH 1/2] iommu/vt-d: Check capability before disabling protected memory
@ 2019-03-20  1:58 Lu Baolu
  2019-03-20  1:58 ` [PATCH 2/2] iommu/vt-d: Save the right domain ID used by hardware Lu Baolu
  2019-03-22  9:38 ` [PATCH 1/2] iommu/vt-d: Check capability before disabling protected memory Joerg Roedel
  0 siblings, 2 replies; 3+ messages in thread
From: Lu Baolu @ 2019-03-20  1:58 UTC (permalink / raw)
  To: Joerg Roedel, David Woodhouse
  Cc: ashok.raj, jacob.jun.pan, kevin.tian, yi.l.liu, iommu,
	linux-kernel, Lu Baolu, Jacob Pan, mark gross

The spec states in 10.4.16 that the Protected Memory Enable
Register should be treated as read-only for implementations
not supporting protected memory regions (PLMR and PHMR fields
reported as Clear in the Capability register).

Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
Cc: mark gross <mgross@intel.com>
Suggested-by: Ashok Raj <ashok.raj@intel.com>
Fixes: f8bab73515ca5 ("intel-iommu: PMEN support")
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
---
 drivers/iommu/intel-iommu.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index 87274b54febd..f002d47d2f27 100644
--- a/drivers/iommu/intel-iommu.c
+++ b/drivers/iommu/intel-iommu.c
@@ -1538,6 +1538,9 @@ static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
 	u32 pmen;
 	unsigned long flags;
 
+	if (!cap_plmr(iommu->cap) && !cap_phmr(iommu->cap))
+		return;
+
 	raw_spin_lock_irqsave(&iommu->register_lock, flags);
 	pmen = readl(iommu->reg + DMAR_PMEN_REG);
 	pmen &= ~DMA_PMEN_EPM;
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 3+ messages in thread

* [PATCH 2/2] iommu/vt-d: Save the right domain ID used by hardware
  2019-03-20  1:58 [PATCH 1/2] iommu/vt-d: Check capability before disabling protected memory Lu Baolu
@ 2019-03-20  1:58 ` Lu Baolu
  2019-03-22  9:38 ` [PATCH 1/2] iommu/vt-d: Check capability before disabling protected memory Joerg Roedel
  1 sibling, 0 replies; 3+ messages in thread
From: Lu Baolu @ 2019-03-20  1:58 UTC (permalink / raw)
  To: Joerg Roedel, David Woodhouse
  Cc: ashok.raj, jacob.jun.pan, kevin.tian, yi.l.liu, iommu,
	linux-kernel, Lu Baolu, Jacob Pan

The driver sets a default domain id (FLPT_DEFAULT_DID) in the
first level only pasid entry, but saves a different domain id
in @sdev->did. The value saved in @sdev->did will be used to
invalidate the translation caches. Hence, the driver might
result in invalidating the caches with a wrong domain id.

Cc: Ashok Raj <ashok.raj@intel.com>
Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
Fixes: 1c4f88b7f1f92 ("iommu/vt-d: Shared virtual address in scalable mode")
Signed-off-by: Liu Yi L <yi.l.liu@intel.com>
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
---
 drivers/iommu/intel-iommu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index f002d47d2f27..28cb713d728c 100644
--- a/drivers/iommu/intel-iommu.c
+++ b/drivers/iommu/intel-iommu.c
@@ -5335,7 +5335,7 @@ int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct intel_svm_dev *sd
 
 	ctx_lo = context[0].lo;
 
-	sdev->did = domain->iommu_did[iommu->seq_id];
+	sdev->did = FLPT_DEFAULT_DID;
 	sdev->sid = PCI_DEVID(info->bus, info->devfn);
 
 	if (!(ctx_lo & CONTEXT_PASIDE)) {
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 3+ messages in thread

* Re: [PATCH 1/2] iommu/vt-d: Check capability before disabling protected memory
  2019-03-20  1:58 [PATCH 1/2] iommu/vt-d: Check capability before disabling protected memory Lu Baolu
  2019-03-20  1:58 ` [PATCH 2/2] iommu/vt-d: Save the right domain ID used by hardware Lu Baolu
@ 2019-03-22  9:38 ` Joerg Roedel
  1 sibling, 0 replies; 3+ messages in thread
From: Joerg Roedel @ 2019-03-22  9:38 UTC (permalink / raw)
  To: Lu Baolu
  Cc: David Woodhouse, ashok.raj, jacob.jun.pan, kevin.tian, yi.l.liu,
	iommu, linux-kernel, Jacob Pan, mark gross

On Wed, Mar 20, 2019 at 09:58:33AM +0800, Lu Baolu wrote:
> The spec states in 10.4.16 that the Protected Memory Enable
> Register should be treated as read-only for implementations
> not supporting protected memory regions (PLMR and PHMR fields
> reported as Clear in the Capability register).
> 
> Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
> Cc: mark gross <mgross@intel.com>
> Suggested-by: Ashok Raj <ashok.raj@intel.com>
> Fixes: f8bab73515ca5 ("intel-iommu: PMEN support")
> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
> ---
>  drivers/iommu/intel-iommu.c | 3 +++
>  1 file changed, 3 insertions(+)

Applied both, thanks.

^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2019-03-22  9:38 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2019-03-20  1:58 [PATCH 1/2] iommu/vt-d: Check capability before disabling protected memory Lu Baolu
2019-03-20  1:58 ` [PATCH 2/2] iommu/vt-d: Save the right domain ID used by hardware Lu Baolu
2019-03-22  9:38 ` [PATCH 1/2] iommu/vt-d: Check capability before disabling protected memory Joerg Roedel

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