* [PATCH 1/2] dt-bindings: iommu: Convert Arm SMMU to DT schema
@ 2019-09-20 13:48 Rob Herring
2019-09-20 13:48 ` [PATCH 2/2] dt-bindings: iommu: Convert Arm SMMUv3 " Rob Herring
0 siblings, 1 reply; 4+ messages in thread
From: Rob Herring @ 2019-09-20 13:48 UTC (permalink / raw)
To: devicetree; +Cc: Mark Rutland, Will Deacon, linux-kernel, iommu, Robin Murphy
Convert the Arm SMMU binding to DT schema.
The existing binding doc doesn't cover the number of variations of
compatible properties found in .dts files. "qcom,msm8998-smmu-v2" was
also missing, so add it.
SoCFPGA Stratix10 has a single clock defined which doesn't match the
binding. This issue remains.
Cc: Joerg Roedel <joro@8bytes.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Robin Murphy <Robin.Murphy@arm.com>
Cc: iommu@lists.linux-foundation.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/iommu/arm,smmu.txt | 182 --------------
.../devicetree/bindings/iommu/arm,smmu.yaml | 229 ++++++++++++++++++
2 files changed, 229 insertions(+), 182 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/iommu/arm,smmu.txt
create mode 100644 Documentation/devicetree/bindings/iommu/arm,smmu.yaml
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
deleted file mode 100644
index 3133f3ba7567..000000000000
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
+++ /dev/null
@@ -1,182 +0,0 @@
-* ARM System MMU Architecture Implementation
-
-ARM SoCs may contain an implementation of the ARM System Memory
-Management Unit Architecture, which can be used to provide 1 or 2 stages
-of address translation to bus masters external to the CPU.
-
-The SMMU may also raise interrupts in response to various fault
-conditions.
-
-** System MMU required properties:
-
-- compatible : Should be one of:
-
- "arm,smmu-v1"
- "arm,smmu-v2"
- "arm,mmu-400"
- "arm,mmu-401"
- "arm,mmu-500"
- "cavium,smmu-v2"
- "qcom,smmu-v2"
-
- depending on the particular implementation and/or the
- version of the architecture implemented.
-
- Qcom SoCs must contain, as below, SoC-specific compatibles
- along with "qcom,smmu-v2":
- "qcom,msm8996-smmu-v2", "qcom,smmu-v2",
- "qcom,sdm845-smmu-v2", "qcom,smmu-v2".
-
- Qcom SoCs implementing "arm,mmu-500" must also include,
- as below, SoC-specific compatibles:
- "qcom,sdm845-smmu-500", "arm,mmu-500"
-
-- reg : Base address and size of the SMMU.
-
-- #global-interrupts : The number of global interrupts exposed by the
- device.
-
-- interrupts : Interrupt list, with the first #global-irqs entries
- corresponding to the global interrupts and any
- following entries corresponding to context interrupts,
- specified in order of their indexing by the SMMU.
-
- For SMMUv2 implementations, there must be exactly one
- interrupt per context bank. In the case of a single,
- combined interrupt, it must be listed multiple times.
-
-- #iommu-cells : See Documentation/devicetree/bindings/iommu/iommu.txt
- for details. With a value of 1, each IOMMU specifier
- represents a distinct stream ID emitted by that device
- into the relevant SMMU.
-
- SMMUs with stream matching support and complex masters
- may use a value of 2, where the second cell of the
- IOMMU specifier represents an SMR mask to combine with
- the ID in the first cell. Care must be taken to ensure
- the set of matched IDs does not result in conflicts.
-
-** System MMU optional properties:
-
-- dma-coherent : Present if page table walks made by the SMMU are
- cache coherent with the CPU.
-
- NOTE: this only applies to the SMMU itself, not
- masters connected upstream of the SMMU.
-
-- calxeda,smmu-secure-config-access : Enable proper handling of buggy
- implementations that always use secure access to
- SMMU configuration registers. In this case non-secure
- aliases of secure registers have to be used during
- SMMU configuration.
-
-- stream-match-mask : For SMMUs supporting stream matching and using
- #iommu-cells = <1>, specifies a mask of bits to ignore
- when matching stream IDs (e.g. this may be programmed
- into the SMRn.MASK field of every stream match register
- used). For cases where it is desirable to ignore some
- portion of every Stream ID (e.g. for certain MMU-500
- configurations given globally unique input IDs). This
- property is not valid for SMMUs using stream indexing,
- or using stream matching with #iommu-cells = <2>, and
- may be ignored if present in such cases.
-
-- clock-names: List of the names of clocks input to the device. The
- required list depends on particular implementation and
- is as follows:
- - for "qcom,smmu-v2":
- - "bus": clock required for downstream bus access and
- for the smmu ptw,
- - "iface": clock required to access smmu's registers
- through the TCU's programming interface.
- - unspecified for other implementations.
-
-- clocks: Specifiers for all clocks listed in the clock-names property,
- as per generic clock bindings.
-
-- power-domains: Specifiers for power domains required to be powered on for
- the SMMU to operate, as per generic power domain bindings.
-
-** Deprecated properties:
-
-- mmu-masters (deprecated in favour of the generic "iommus" binding) :
- A list of phandles to device nodes representing bus
- masters for which the SMMU can provide a translation
- and their corresponding Stream IDs. Each device node
- linked from this list must have a "#stream-id-cells"
- property, indicating the number of Stream ID
- arguments associated with its phandle.
-
-** Examples:
-
- /* SMMU with stream matching or stream indexing */
- smmu1: iommu {
- compatible = "arm,smmu-v1";
- reg = <0xba5e0000 0x10000>;
- #global-interrupts = <2>;
- interrupts = <0 32 4>,
- <0 33 4>,
- <0 34 4>, /* This is the first context interrupt */
- <0 35 4>,
- <0 36 4>,
- <0 37 4>;
- #iommu-cells = <1>;
- };
-
- /* device with two stream IDs, 0 and 7 */
- master1 {
- iommus = <&smmu1 0>,
- <&smmu1 7>;
- };
-
-
- /* SMMU with stream matching */
- smmu2: iommu {
- ...
- #iommu-cells = <2>;
- };
-
- /* device with stream IDs 0 and 7 */
- master2 {
- iommus = <&smmu2 0 0>,
- <&smmu2 7 0>;
- };
-
- /* device with stream IDs 1, 17, 33 and 49 */
- master3 {
- iommus = <&smmu2 1 0x30>;
- };
-
-
- /* ARM MMU-500 with 10-bit stream ID input configuration */
- smmu3: iommu {
- compatible = "arm,mmu-500", "arm,smmu-v2";
- ...
- #iommu-cells = <1>;
- /* always ignore appended 5-bit TBU number */
- stream-match-mask = 0x7c00;
- };
-
- bus {
- /* bus whose child devices emit one unique 10-bit stream
- ID each, but may master through multiple SMMU TBUs */
- iommu-map = <0 &smmu3 0 0x400>;
- ...
- };
-
- /* Qcom's arm,smmu-v2 implementation */
- smmu4: iommu@d00000 {
- compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
- reg = <0xd00000 0x10000>;
-
- #global-interrupts = <1>;
- interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- power-domains = <&mmcc MDSS_GDSC>;
-
- clocks = <&mmcc SMMU_MDP_AXI_CLK>,
- <&mmcc SMMU_MDP_AHB_CLK>;
- clock-names = "bus", "iface";
- };
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
new file mode 100644
index 000000000000..3b31b4802a54
--- /dev/null
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
@@ -0,0 +1,229 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM System MMU Architecture Implementation
+
+maintainers:
+ - Will Deacon <will@kernel.org>
+ - Robin Murphy <Robin.Murphy@arm.com>
+
+description: |+
+ ARM SoCs may contain an implementation of the ARM System Memory
+ Management Unit Architecture, which can be used to provide 1 or 2 stages
+ of address translation to bus masters external to the CPU.
+
+ The SMMU may also raise interrupts in response to various fault
+ conditions.
+
+properties:
+ $nodename:
+ pattern: "^iommu@[0-9a-f]*"
+ compatible:
+ oneOf:
+ - description: Qcom SoCs implementing "arm,smmu-v2"
+ items:
+ - enum:
+ - qcom,msm8996-smmu-v2
+ - qcom,msm8998-smmu-v2
+ - qcom,sdm845-smmu-v2
+ - const: qcom,smmu-v2
+
+ - description: Qcom SoCs implementing "arm,mmu-500"
+ items:
+ - enum:
+ - qcom,sdm845-smmu-500
+ - const: arm,mmu-500
+ - items:
+ - const: arm,mmu-500
+ - const: arm,smmu-v2
+ - items:
+ - const: arm,mmu-401
+ - const: arm,smmu-v1
+ - enum:
+ - arm,smmu-v1
+ - arm,smmu-v2
+ - arm,mmu-400
+ - arm,mmu-401
+ - arm,mmu-500
+ - cavium,smmu-v2
+
+ reg:
+ maxItems: 1
+
+ '#global-interrupts':
+ description: The number of global interrupts exposed by the device.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters
+
+ '#iommu-cells':
+ enum: [ 1, 2 ]
+ description: |
+ See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a
+ value of 1, each IOMMU specifier represents a distinct stream ID emitted
+ by that device into the relevant SMMU.
+
+ SMMUs with stream matching support and complex masters may use a value of
+ 2, where the second cell of the IOMMU specifier represents an SMR mask to
+ combine with the ID in the first cell. Care must be taken to ensure the
+ set of matched IDs does not result in conflicts.
+
+ interrupts:
+ minItems: 1
+ maxItems: 388 # 260 plus 128 contexts
+ description: |
+ Interrupt list, with the first #global-interrupts entries corresponding to
+ the global interrupts and any following entries corresponding to context
+ interrupts, specified in order of their indexing by the SMMU.
+
+ For SMMUv2 implementations, there must be exactly one interrupt per
+ context bank. In the case of a single, combined interrupt, it must be
+ listed multiple times.
+
+ dma-coherent:
+ description: |
+ Present if page table walks made by the SMMU are cache coherent with the
+ CPU.
+
+ NOTE: this only applies to the SMMU itself, not masters connected
+ upstream of the SMMU.
+
+ calxeda,smmu-secure-config-access:
+ type: boolean
+ description:
+ Enable proper handling of buggy implementations that always use secure
+ access to SMMU configuration registers. In this case non-secure aliases of
+ secure registers have to be used during SMMU configuration.
+
+ stream-match-mask:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ For SMMUs supporting stream matching and using #iommu-cells = <1>,
+ specifies a mask of bits to ignore when matching stream IDs (e.g. this may
+ be programmed into the SMRn.MASK field of every stream match register
+ used). For cases where it is desirable to ignore some portion of every
+ Stream ID (e.g. for certain MMU-500 configurations given globally unique
+ input IDs). This property is not valid for SMMUs using stream indexing, or
+ using stream matching with #iommu-cells = <2>, and may be ignored if
+ present in such cases.
+
+ clock-names:
+ items:
+ - const: bus
+ - const: iface
+
+ clocks:
+ items:
+ - description: bus clock required for downstream bus access and for the
+ smmu ptw
+ - description: interface clock required to access smmu's registers
+ through the TCU's programming interface.
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - '#global-interrupts'
+ - '#iommu-cells'
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |+
+ /* SMMU with stream matching or stream indexing */
+ smmu1: iommu@ba5e0000 {
+ compatible = "arm,smmu-v1";
+ reg = <0xba5e0000 0x10000>;
+ #global-interrupts = <2>;
+ interrupts = <0 32 4>,
+ <0 33 4>,
+ <0 34 4>, /* This is the first context interrupt */
+ <0 35 4>,
+ <0 36 4>,
+ <0 37 4>;
+ #iommu-cells = <1>;
+ };
+
+ /* device with two stream IDs, 0 and 7 */
+ master1 {
+ iommus = <&smmu1 0>,
+ <&smmu1 7>;
+ };
+
+
+ /* SMMU with stream matching */
+ smmu2: iommu@ba5f0000 {
+ compatible = "arm,smmu-v1";
+ reg = <0xba5f0000 0x10000>;
+ #global-interrupts = <2>;
+ interrupts = <0 38 4>,
+ <0 39 4>,
+ <0 40 4>, /* This is the first context interrupt */
+ <0 41 4>,
+ <0 42 4>,
+ <0 43 4>;
+ #iommu-cells = <2>;
+ };
+
+ /* device with stream IDs 0 and 7 */
+ master2 {
+ iommus = <&smmu2 0 0>,
+ <&smmu2 7 0>;
+ };
+
+ /* device with stream IDs 1, 17, 33 and 49 */
+ master3 {
+ iommus = <&smmu2 1 0x30>;
+ };
+
+
+ /* ARM MMU-500 with 10-bit stream ID input configuration */
+ smmu3: iommu@ba600000 {
+ compatible = "arm,mmu-500", "arm,smmu-v2";
+ reg = <0xba600000 0x10000>;
+ #global-interrupts = <2>;
+ interrupts = <0 44 4>,
+ <0 45 4>,
+ <0 46 4>, /* This is the first context interrupt */
+ <0 47 4>,
+ <0 48 4>,
+ <0 49 4>;
+ #iommu-cells = <1>;
+ /* always ignore appended 5-bit TBU number */
+ stream-match-mask = <0x7c00>;
+ };
+
+ bus {
+ /* bus whose child devices emit one unique 10-bit stream
+ ID each, but may master through multiple SMMU TBUs */
+ iommu-map = <0 &smmu3 0 0x400>;
+
+
+ };
+
+ - |+
+ /* Qcom's arm,smmu-v2 implementation */
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ smmu4: iommu@d00000 {
+ compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
+ reg = <0xd00000 0x10000>;
+
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ power-domains = <&mmcc 0>;
+
+ clocks = <&mmcc 123>,
+ <&mmcc 124>;
+ clock-names = "bus", "iface";
+ };
--
2.20.1
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] dt-bindings: iommu: Convert Arm SMMUv3 to DT schema
2019-09-20 13:48 [PATCH 1/2] dt-bindings: iommu: Convert Arm SMMU to DT schema Rob Herring
@ 2019-09-20 13:48 ` Rob Herring
2019-09-20 14:17 ` Robin Murphy
0 siblings, 1 reply; 4+ messages in thread
From: Rob Herring @ 2019-09-20 13:48 UTC (permalink / raw)
To: devicetree; +Cc: Mark Rutland, Will Deacon, linux-kernel, iommu, Robin Murphy
Convert the Arm SMMv3 binding to the DT schema format.
Cc: Joerg Roedel <joro@8bytes.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Robin Murphy <Robin.Murphy@arm.com>
Cc: iommu@lists.linux-foundation.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/iommu/arm,smmu-v3.txt | 77 -------------
.../bindings/iommu/arm,smmu-v3.yaml | 103 ++++++++++++++++++
2 files changed, 103 insertions(+), 77 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt
create mode 100644 Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt
deleted file mode 100644
index c9abbf3e4f68..000000000000
--- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt
+++ /dev/null
@@ -1,77 +0,0 @@
-* ARM SMMUv3 Architecture Implementation
-
-The SMMUv3 architecture is a significant departure from previous
-revisions, replacing the MMIO register interface with in-memory command
-and event queues and adding support for the ATS and PRI components of
-the PCIe specification.
-
-** SMMUv3 required properties:
-
-- compatible : Should include:
-
- * "arm,smmu-v3" for any SMMUv3 compliant
- implementation. This entry should be last in the
- compatible list.
-
-- reg : Base address and size of the SMMU.
-
-- interrupts : Non-secure interrupt list describing the wired
- interrupt sources corresponding to entries in
- interrupt-names. If no wired interrupts are
- present then this property may be omitted.
-
-- interrupt-names : When the interrupts property is present, should
- include the following:
- * "eventq" - Event Queue not empty
- * "priq" - PRI Queue not empty
- * "cmdq-sync" - CMD_SYNC complete
- * "gerror" - Global Error activated
- * "combined" - The combined interrupt is optional,
- and should only be provided if the
- hardware supports just a single,
- combined interrupt line.
- If provided, then the combined interrupt
- will be used in preference to any others.
-
-- #iommu-cells : See the generic IOMMU binding described in
- devicetree/bindings/pci/pci-iommu.txt
- for details. For SMMUv3, must be 1, with each cell
- describing a single stream ID. All possible stream
- IDs which a device may emit must be described.
-
-** SMMUv3 optional properties:
-
-- dma-coherent : Present if DMA operations made by the SMMU (page
- table walks, stream table accesses etc) are cache
- coherent with the CPU.
-
- NOTE: this only applies to the SMMU itself, not
- masters connected upstream of the SMMU.
-
-- msi-parent : See the generic MSI binding described in
- devicetree/bindings/interrupt-controller/msi.txt
- for a description of the msi-parent property.
-
-- hisilicon,broken-prefetch-cmd
- : Avoid sending CMD_PREFETCH_* commands to the SMMU.
-
-- cavium,cn9900-broken-page1-regspace
- : Replaces all page 1 offsets used for EVTQ_PROD/CONS,
- PRIQ_PROD/CONS register access with page 0 offsets.
- Set for Cavium ThunderX2 silicon that doesn't support
- SMMU page1 register space.
-
-** Example
-
- smmu@2b400000 {
- compatible = "arm,smmu-v3";
- reg = <0x0 0x2b400000 0x0 0x20000>;
- interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
- dma-coherent;
- #iommu-cells = <1>;
- msi-parent = <&its 0xff0000>;
- };
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
new file mode 100644
index 000000000000..1c97bcfbf82b
--- /dev/null
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
@@ -0,0 +1,103 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM SMMUv3 Architecture Implementation
+
+maintainers:
+ - Will Deacon <will@kernel.org>
+ - Robin Murphy <Robin.Murphy@arm.com>
+
+description: |+
+ The SMMUv3 architecture is a significant departure from previous
+ revisions, replacing the MMIO register interface with in-memory command
+ and event queues and adding support for the ATS and PRI components of
+ the PCIe specification.
+
+properties:
+ $nodename:
+ pattern: "^iommu@[0-9a-f]*"
+ compatible:
+ const: arm,smmu-v3
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 1
+ maxItems: 4
+
+ interrupt-names:
+ oneOf:
+ - const: combined
+ description:
+ The combined interrupt is optional, and should only be provided if the
+ hardware supports just a single, combined interrupt line.
+ If provided, then the combined interrupt will be used in preference to
+ any others.
+ - items:
+ - const: eventq # Event Queue not empty
+ - const: priq # PRI Queue not empty
+ - const: cmdq-sync # CMD_SYNC complete
+ - const: gerror # Global Error activated
+ - items:
+ - const: eventq
+ - const: gerror
+ - const: priq
+ - items:
+ - const: eventq
+ - const: gerror
+ - items:
+ - const: eventq
+ - const: priq
+
+ '#iommu-cells':
+ const: 1
+
+ dma-coherent:
+ description: |
+ Present if page table walks made by the SMMU are cache coherent with the
+ CPU.
+
+ NOTE: this only applies to the SMMU itself, not masters connected
+ upstream of the SMMU.
+
+ msi-parent: true
+
+ hisilicon,broken-prefetch-cmd:
+ type: boolean
+ description: Avoid sending CMD_PREFETCH_* commands to the SMMU.
+
+ cavium,cn9900-broken-page1-regspace:
+ type: boolean
+ description:
+ Replaces all page 1 offsets used for EVTQ_PROD/CONS, PRIQ_PROD/CONS
+ register access with page 0 offsets. Set for Cavium ThunderX2 silicon that
+ doesn't support SMMU page1 register space.
+
+required:
+ - compatible
+ - reg
+ - '#iommu-cells'
+
+additionalProperties: false
+
+examples:
+ - |+
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ iommu@2b400000 {
+ compatible = "arm,smmu-v3";
+ reg = <0x2b400000 0x20000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
+ dma-coherent;
+ #iommu-cells = <1>;
+ msi-parent = <&its 0xff0000>;
+ };
--
2.20.1
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 2/2] dt-bindings: iommu: Convert Arm SMMUv3 to DT schema
2019-09-20 13:48 ` [PATCH 2/2] dt-bindings: iommu: Convert Arm SMMUv3 " Rob Herring
@ 2019-09-20 14:17 ` Robin Murphy
2019-09-20 14:40 ` Rob Herring
0 siblings, 1 reply; 4+ messages in thread
From: Robin Murphy @ 2019-09-20 14:17 UTC (permalink / raw)
To: Rob Herring, devicetree; +Cc: Mark Rutland, Will Deacon, linux-kernel, iommu
On 20/09/2019 14:48, Rob Herring wrote:
> Convert the Arm SMMv3 binding to the DT schema format.
>
> Cc: Joerg Roedel <joro@8bytes.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Robin Murphy <Robin.Murphy@arm.com>
> Cc: iommu@lists.linux-foundation.org
> Signed-off-by: Rob Herring <robh@kernel.org>
> ---
> .../devicetree/bindings/iommu/arm,smmu-v3.txt | 77 -------------
> .../bindings/iommu/arm,smmu-v3.yaml | 103 ++++++++++++++++++
> 2 files changed, 103 insertions(+), 77 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt
> create mode 100644 Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
>
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt
> deleted file mode 100644
> index c9abbf3e4f68..000000000000
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt
> +++ /dev/null
> @@ -1,77 +0,0 @@
> -* ARM SMMUv3 Architecture Implementation
> -
> -The SMMUv3 architecture is a significant departure from previous
> -revisions, replacing the MMIO register interface with in-memory command
> -and event queues and adding support for the ATS and PRI components of
> -the PCIe specification.
> -
> -** SMMUv3 required properties:
> -
> -- compatible : Should include:
> -
> - * "arm,smmu-v3" for any SMMUv3 compliant
> - implementation. This entry should be last in the
> - compatible list.
> -
> -- reg : Base address and size of the SMMU.
> -
> -- interrupts : Non-secure interrupt list describing the wired
> - interrupt sources corresponding to entries in
> - interrupt-names. If no wired interrupts are
> - present then this property may be omitted.
> -
> -- interrupt-names : When the interrupts property is present, should
> - include the following:
> - * "eventq" - Event Queue not empty
> - * "priq" - PRI Queue not empty
> - * "cmdq-sync" - CMD_SYNC complete
> - * "gerror" - Global Error activated
> - * "combined" - The combined interrupt is optional,
> - and should only be provided if the
> - hardware supports just a single,
> - combined interrupt line.
> - If provided, then the combined interrupt
> - will be used in preference to any others.
> -
> -- #iommu-cells : See the generic IOMMU binding described in
> - devicetree/bindings/pci/pci-iommu.txt
> - for details. For SMMUv3, must be 1, with each cell
> - describing a single stream ID. All possible stream
> - IDs which a device may emit must be described.
> -
> -** SMMUv3 optional properties:
> -
> -- dma-coherent : Present if DMA operations made by the SMMU (page
> - table walks, stream table accesses etc) are cache
> - coherent with the CPU.
> -
> - NOTE: this only applies to the SMMU itself, not
> - masters connected upstream of the SMMU.
> -
> -- msi-parent : See the generic MSI binding described in
> - devicetree/bindings/interrupt-controller/msi.txt
> - for a description of the msi-parent property.
> -
> -- hisilicon,broken-prefetch-cmd
> - : Avoid sending CMD_PREFETCH_* commands to the SMMU.
> -
> -- cavium,cn9900-broken-page1-regspace
> - : Replaces all page 1 offsets used for EVTQ_PROD/CONS,
> - PRIQ_PROD/CONS register access with page 0 offsets.
> - Set for Cavium ThunderX2 silicon that doesn't support
> - SMMU page1 register space.
> -
> -** Example
> -
> - smmu@2b400000 {
> - compatible = "arm,smmu-v3";
> - reg = <0x0 0x2b400000 0x0 0x20000>;
> - interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
> - <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
> - <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
> - <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;
> - interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
> - dma-coherent;
> - #iommu-cells = <1>;
> - msi-parent = <&its 0xff0000>;
> - };
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> new file mode 100644
> index 000000000000..1c97bcfbf82b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> @@ -0,0 +1,103 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ARM SMMUv3 Architecture Implementation
> +
> +maintainers:
> + - Will Deacon <will@kernel.org>
> + - Robin Murphy <Robin.Murphy@arm.com>
> +
> +description: |+
> + The SMMUv3 architecture is a significant departure from previous
> + revisions, replacing the MMIO register interface with in-memory command
> + and event queues and adding support for the ATS and PRI components of
> + the PCIe specification.
> +
> +properties:
> + $nodename:
> + pattern: "^iommu@[0-9a-f]*"
> + compatible:
> + const: arm,smmu-v3
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + minItems: 1
> + maxItems: 4
> +
> + interrupt-names:
> + oneOf:
> + - const: combined
> + description:
> + The combined interrupt is optional, and should only be provided if the
> + hardware supports just a single, combined interrupt line.
> + If provided, then the combined interrupt will be used in preference to
> + any others.
> + - items:
> + - const: eventq # Event Queue not empty
> + - const: priq # PRI Queue not empty
> + - const: cmdq-sync # CMD_SYNC complete
> + - const: gerror # Global Error activated
> + - items:
> + - const: eventq
> + - const: gerror
> + - const: priq
> + - items:
> + - const: eventq
> + - const: gerror
> + - items:
> + - const: eventq
> + - const: priq
This looks a bit off - in the absence of MSIs, at least "gerror" and
"eventq" should be mandatory; "cmdq-sync" should probably also be from a
binding perspective, but Linux doesn't care about it. PRI is an optional
feature of the architecture, so that IRQ should always be optional. If
we do have MSIs, then technically the implementation is allowed to not
support wired IRQs at all, although in practice is likely to have at
least "gerror" to signal the double-fault condition of a GERROR MSI
write aborting.
Robin.
> +
> + '#iommu-cells':
> + const: 1
> +
> + dma-coherent:
> + description: |
> + Present if page table walks made by the SMMU are cache coherent with the
> + CPU.
> +
> + NOTE: this only applies to the SMMU itself, not masters connected
> + upstream of the SMMU.
> +
> + msi-parent: true
> +
> + hisilicon,broken-prefetch-cmd:
> + type: boolean
> + description: Avoid sending CMD_PREFETCH_* commands to the SMMU.
> +
> + cavium,cn9900-broken-page1-regspace:
> + type: boolean
> + description:
> + Replaces all page 1 offsets used for EVTQ_PROD/CONS, PRIQ_PROD/CONS
> + register access with page 0 offsets. Set for Cavium ThunderX2 silicon that
> + doesn't support SMMU page1 register space.
> +
> +required:
> + - compatible
> + - reg
> + - '#iommu-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |+
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> +
> + iommu@2b400000 {
> + compatible = "arm,smmu-v3";
> + reg = <0x2b400000 0x20000>;
> + interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
> + dma-coherent;
> + #iommu-cells = <1>;
> + msi-parent = <&its 0xff0000>;
> + };
>
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 2/2] dt-bindings: iommu: Convert Arm SMMUv3 to DT schema
2019-09-20 14:17 ` Robin Murphy
@ 2019-09-20 14:40 ` Rob Herring
0 siblings, 0 replies; 4+ messages in thread
From: Rob Herring @ 2019-09-20 14:40 UTC (permalink / raw)
To: Robin Murphy
Cc: Mark Rutland, devicetree, linux-kernel, Linux IOMMU, Will Deacon
On Fri, Sep 20, 2019 at 9:17 AM Robin Murphy <robin.murphy@arm.com> wrote:
>
> On 20/09/2019 14:48, Rob Herring wrote:
> > Convert the Arm SMMv3 binding to the DT schema format.
> >
> > Cc: Joerg Roedel <joro@8bytes.org>
> > Cc: Mark Rutland <mark.rutland@arm.com>
> > Cc: Will Deacon <will@kernel.org>
> > Cc: Robin Murphy <Robin.Murphy@arm.com>
> > Cc: iommu@lists.linux-foundation.org
> > Signed-off-by: Rob Herring <robh@kernel.org>
> > ---
> > .../devicetree/bindings/iommu/arm,smmu-v3.txt | 77 -------------
> > .../bindings/iommu/arm,smmu-v3.yaml | 103 ++++++++++++++++++
> > 2 files changed, 103 insertions(+), 77 deletions(-)
> > delete mode 100644 Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt
> > create mode 100644 Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> > new file mode 100644
> > index 000000000000..1c97bcfbf82b
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> > @@ -0,0 +1,103 @@
> > +# SPDX-License-Identifier: GPL-2.0-only
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: ARM SMMUv3 Architecture Implementation
> > +
> > +maintainers:
> > + - Will Deacon <will@kernel.org>
> > + - Robin Murphy <Robin.Murphy@arm.com>
> > +
> > +description: |+
> > + The SMMUv3 architecture is a significant departure from previous
> > + revisions, replacing the MMIO register interface with in-memory command
> > + and event queues and adding support for the ATS and PRI components of
> > + the PCIe specification.
> > +
> > +properties:
> > + $nodename:
> > + pattern: "^iommu@[0-9a-f]*"
> > + compatible:
> > + const: arm,smmu-v3
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + minItems: 1
> > + maxItems: 4
> > +
> > + interrupt-names:
> > + oneOf:
> > + - const: combined
> > + description:
> > + The combined interrupt is optional, and should only be provided if the
> > + hardware supports just a single, combined interrupt line.
> > + If provided, then the combined interrupt will be used in preference to
> > + any others.
> > + - items:
> > + - const: eventq # Event Queue not empty
> > + - const: priq # PRI Queue not empty
> > + - const: cmdq-sync # CMD_SYNC complete
> > + - const: gerror # Global Error activated
> > + - items:
> > + - const: eventq
> > + - const: gerror
> > + - const: priq
> > + - items:
> > + - const: eventq
> > + - const: gerror
> > + - items:
> > + - const: eventq
> > + - const: priq
>
> This looks a bit off - in the absence of MSIs, at least "gerror" and
> "eventq" should be mandatory; "cmdq-sync" should probably also be from a
> binding perspective, but Linux doesn't care about it. PRI is an optional
> feature of the architecture, so that IRQ should always be optional. If
> we do have MSIs, then technically the implementation is allowed to not
> support wired IRQs at all, although in practice is likely to have at
> least "gerror" to signal the double-fault condition of a GERROR MSI
> write aborting.
Well, now I'm not sure where I came up with the last case, it can be
dropped. These are the cases we have:
arch/arm64/boot/dts/arm/fvp-base-revc.dts:
interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
arch/arm64/boot/dts/hisilicon/hip07.dtsi:
interrupt-names = "eventq", "gerror", "priq";
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi:
interrupt-names = "eventq", "gerror";
I'm fine if we leave warnings and expect dts files to be fixed.
In an ideal world we'd have this with optional irq on the end:
- minItems: 3
maxItems: 4
items:
- const: eventq # Event Queue not empty
- const: cmdq-sync # CMD_SYNC complete
- const: gerror # Global Error activated
- const: priq # PRI Queue not empty
A less invasive approach would be:
- items:
- const: eventq # Event Queue not empty
- const: priq # PRI Queue not empty
- const: cmdq-sync # CMD_SYNC complete
- const: gerror # Global Error activated
- minItems: 2
maxItems: 4
items:
- const: eventq
- const: gerror
- const: priq
- const: cmdq-sync
Rob
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2019-09-20 14:40 UTC | newest]
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2019-09-20 13:48 [PATCH 1/2] dt-bindings: iommu: Convert Arm SMMU to DT schema Rob Herring
2019-09-20 13:48 ` [PATCH 2/2] dt-bindings: iommu: Convert Arm SMMUv3 " Rob Herring
2019-09-20 14:17 ` Robin Murphy
2019-09-20 14:40 ` Rob Herring
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