From: Joerg Roedel <joro@8bytes.org>
To: Lu Baolu <baolu.lu@linux.intel.com>
Cc: kevin.tian@intel.com, ashok.raj@intel.com,
linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org,
jacob.jun.pan@intel.com, David Woodhouse <dwmw2@infradead.org>
Subject: Re: [PATCH 1/1] iommu/vt-d: Remove incorrect PSI capability check
Date: Wed, 18 Dec 2019 16:18:57 +0100 [thread overview]
Message-ID: <20191218151856.GA2995@8bytes.org> (raw)
In-Reply-To: <20191120061016.31386-1-baolu.lu@linux.intel.com>
On Wed, Nov 20, 2019 at 02:10:16PM +0800, Lu Baolu wrote:
> The PSI (Page Selective Invalidation) bit in the capability register
> is only valid for second-level translation. Intel IOMMU supporting
> scalable mode must support page/address selective IOTLB invalidation
> for first-level translation. Remove the PSI capability check in SVA
> cache invalidation code.
>
> Fixes: 8744daf4b0699 ("iommu/vt-d: Remove global page flush support")
> Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
> ---
> drivers/iommu/intel-svm.c | 6 +-----
> 1 file changed, 1 insertion(+), 5 deletions(-)
Applied for v5.5, thanks.
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parent reply other threads:[~2019-12-18 15:19 UTC|newest]
Thread overview: expand[flat|nested] mbox.gz Atom feed
[parent not found: <20191120061016.31386-1-baolu.lu@linux.intel.com>]
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