* Re: [PATCH 1/1] iommu/vt-d: Remove incorrect PSI capability check
[not found] <20191120061016.31386-1-baolu.lu@linux.intel.com>
@ 2019-12-18 15:18 ` Joerg Roedel
0 siblings, 0 replies; only message in thread
From: Joerg Roedel @ 2019-12-18 15:18 UTC (permalink / raw)
To: Lu Baolu
Cc: kevin.tian, ashok.raj, linux-kernel, iommu, jacob.jun.pan,
David Woodhouse
On Wed, Nov 20, 2019 at 02:10:16PM +0800, Lu Baolu wrote:
> The PSI (Page Selective Invalidation) bit in the capability register
> is only valid for second-level translation. Intel IOMMU supporting
> scalable mode must support page/address selective IOTLB invalidation
> for first-level translation. Remove the PSI capability check in SVA
> cache invalidation code.
>
> Fixes: 8744daf4b0699 ("iommu/vt-d: Remove global page flush support")
> Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
> ---
> drivers/iommu/intel-svm.c | 6 +-----
> 1 file changed, 1 insertion(+), 5 deletions(-)
Applied for v5.5, thanks.
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] only message in thread
only message in thread, other threads:[~2019-12-18 15:19 UTC | newest]
Thread overview: (only message) (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
[not found] <20191120061016.31386-1-baolu.lu@linux.intel.com>
2019-12-18 15:18 ` [PATCH 1/1] iommu/vt-d: Remove incorrect PSI capability check Joerg Roedel
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).