* [PATCH v2 01/19] dt-bindings: mediatek: Add bindings for MT6779
2020-01-05 10:45 [PATCH v2 00/19] MT6779 IOMMU SUPPORT Chao Hao
@ 2020-01-05 10:45 ` Chao Hao
2020-01-06 21:57 ` Rob Herring
2020-01-05 10:45 ` [PATCH v2 02/19] iommu/mediatek: Add m4u1_mask to distinguish m4u_id Chao Hao
` (17 subsequent siblings)
18 siblings, 1 reply; 22+ messages in thread
From: Chao Hao @ 2020-01-05 10:45 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger
Cc: Anan Sun, devicetree, Jun Yan, wsd_upstream, linux-kernel,
Chao Hao, iommu, linux-mediatek, Cui Zhang, linux-arm-kernel
This patch adds description for MT6779 IOMMU.
MT6779 has two iommus, they are MM_IOMMU and APU_IOMMU which
use ARM Short-Descriptor translation format.
The MT6779 IOMMU hardware diagram is as below, it is only a brief
diagram about iommu, it don't focus on the part of smi_larb, so
I don't describe the smi_larb detailedly.
EMI
|
--------------------------------------
| |
MM_IOMMU APU_IOMMU
| |
SMI_COMMOM----------- APU_BUS
| | |
SMI_LARB(0~11) SMI_LARB12(FAKE) SMI_LARB13(FAKE)
| | |
| | --------------
| | | | |
Multimedia engine CCU VPU MDLA EMDA
All the connections are hardware fixed, software can not adjust it.
From the diagram above, MM_IOMMU provides mapping for multimedia engine,
but CCU is connected with smi_common directly, we can take them as larb12.
APU_IOMMU provides mapping for APU engine, we can take them larb13.
Larb12 and Larb13 are fake larbs.
Signed-off-by: Chao Hao <chao.hao@mediatek.com>
---
.../bindings/iommu/mediatek,iommu.txt | 2 +
include/dt-bindings/memory/mt6779-larb-port.h | 215 ++++++++++++++++++
2 files changed, 217 insertions(+)
create mode 100644 include/dt-bindings/memory/mt6779-larb-port.h
diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
index ce59a505f5a4..c1ccd8582eb2 100644
--- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
+++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
@@ -58,6 +58,7 @@ Required properties:
- compatible : must be one of the following string:
"mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW.
"mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW.
+ "mediatek,mt6779-m4u" for mt6779 which uses generation two m4u HW.
"mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses
generation one m4u HW.
"mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW.
@@ -78,6 +79,7 @@ Required properties:
Specifies the mtk_m4u_id as defined in
dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623
dt-binding/memory/mt2712-larb-port.h for mt2712,
+ dt-binding/memory/mt6779-larb-port.h for mt6779,
dt-binding/memory/mt8173-larb-port.h for mt8173, and
dt-binding/memory/mt8183-larb-port.h for mt8183.
diff --git a/include/dt-bindings/memory/mt6779-larb-port.h b/include/dt-bindings/memory/mt6779-larb-port.h
new file mode 100644
index 000000000000..4fd162062373
--- /dev/null
+++ b/include/dt-bindings/memory/mt6779-larb-port.h
@@ -0,0 +1,215 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Chao Hao <chao.hao@mediatek.com>
+ */
+
+#ifndef _DTS_IOMMU_PORT_MT6779_H_
+#define _DTS_IOMMU_PORT_MT6779_H_
+
+#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port))
+
+#define M4U_LARB0_ID 0
+#define M4U_LARB1_ID 1
+#define M4U_LARB2_ID 2
+#define M4U_LARB3_ID 3
+#define M4U_LARB4_ID 4
+#define M4U_LARB5_ID 5
+#define M4U_LARB6_ID 6
+#define M4U_LARB7_ID 7
+#define M4U_LARB8_ID 8
+#define M4U_LARB9_ID 9
+#define M4U_LARB10_ID 10
+#define M4U_LARB11_ID 11
+#define M4U_LARB12_ID 12
+#define M4U_LARB13_ID 13
+
+/* larb0 */
+#define M4U_PORT_DISP_POSTMASK0 MTK_M4U_ID(M4U_LARB0_ID, 0)
+#define M4U_PORT_DISP_OVL0_HDR MTK_M4U_ID(M4U_LARB0_ID, 1)
+#define M4U_PORT_DISP_OVL1_HDR MTK_M4U_ID(M4U_LARB0_ID, 2)
+#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 3)
+#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB0_ID, 4)
+#define M4U_PORT_DISP_PVRIC0 MTK_M4U_ID(M4U_LARB0_ID, 5)
+#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 6)
+#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 7)
+#define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 8)
+
+/* larb1 */
+#define M4U_PORT_DISP_OVL0_2L_HDR MTK_M4U_ID(M4U_LARB1_ID, 0)
+#define M4U_PORT_DISP_OVL1_2L_HDR MTK_M4U_ID(M4U_LARB1_ID, 1)
+#define M4U_PORT_DISP_OVL0_2L MTK_M4U_ID(M4U_LARB1_ID, 2)
+#define M4U_PORT_DISP_OVL1_2L MTK_M4U_ID(M4U_LARB1_ID, 3)
+#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB1_ID, 4)
+#define M4U_PORT_MDP_PVRIC0 MTK_M4U_ID(M4U_LARB1_ID, 5)
+#define M4U_PORT_MDP_PVRIC1 MTK_M4U_ID(M4U_LARB1_ID, 6)
+#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB1_ID, 7)
+#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB1_ID, 8)
+#define M4U_PORT_MDP_WROT0_R MTK_M4U_ID(M4U_LARB1_ID, 9)
+#define M4U_PORT_MDP_WROT0_W MTK_M4U_ID(M4U_LARB1_ID, 10)
+#define M4U_PORT_MDP_WROT1_R MTK_M4U_ID(M4U_LARB1_ID, 11)
+#define M4U_PORT_MDP_WROT1_W MTK_M4U_ID(M4U_LARB1_ID, 12)
+#define M4U_PORT_DISP_FAKE1 MTK_M4U_ID(M4U_LARB1_ID, 13)
+
+/* larb2-VDEC */
+#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB2_ID, 0)
+#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB2_ID, 1)
+#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB2_ID, 2)
+#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB2_ID, 3)
+#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB2_ID, 4)
+#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB2_ID, 5)
+#define M4U_PORT_HW_VDEC_TILE_EXT MTK_M4U_ID(M4U_LARB2_ID, 6)
+#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB2_ID, 7)
+#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB2_ID, 8)
+#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB2_ID, 9)
+#define M4U_PORT_HW_VDEC_UFO_ENC_EXT MTK_M4U_ID(M4U_LARB2_ID, 10)
+#define M4U_PORT_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(M4U_LARB2_ID, 11)
+
+/* larb3-VENC */
+#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0)
+#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1)
+#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2)
+#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3)
+#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4)
+#define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB3_ID, 5)
+#define M4U_PORT_VENC_NBM_RDMA_LITE MTK_M4U_ID(M4U_LARB3_ID, 6)
+#define M4U_PORT_JPGENC_Y_RDMA MTK_M4U_ID(M4U_LARB3_ID, 7)
+#define M4U_PORT_JPGENC_C_RDMA MTK_M4U_ID(M4U_LARB3_ID, 8)
+#define M4U_PORT_JPGENC_Q_TABLE MTK_M4U_ID(M4U_LARB3_ID, 9)
+#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 10)
+#define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 11)
+#define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 12)
+#define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB3_ID, 13)
+#define M4U_PORT_VENC_NBM_WDMA_LITE MTK_M4U_ID(M4U_LARB3_ID, 14)
+#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 15)
+#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 16)
+#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 17)
+#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 18)
+
+/* larb4-dummy */
+
+/* larb5-IMG */
+#define M4U_PORT_IMGI_D1 MTK_M4U_ID(M4U_LARB5_ID, 0)
+#define M4U_PORT_IMGBI_D1 MTK_M4U_ID(M4U_LARB5_ID, 1)
+#define M4U_PORT_DMGI_D1 MTK_M4U_ID(M4U_LARB5_ID, 2)
+#define M4U_PORT_DEPI_D1 MTK_M4U_ID(M4U_LARB5_ID, 3)
+#define M4U_PORT_LCEI_D1 MTK_M4U_ID(M4U_LARB5_ID, 4)
+#define M4U_PORT_SMTI_D1 MTK_M4U_ID(M4U_LARB5_ID, 5)
+#define M4U_PORT_SMTO_D2 MTK_M4U_ID(M4U_LARB5_ID, 6)
+#define M4U_PORT_SMTO_D1 MTK_M4U_ID(M4U_LARB5_ID, 7)
+#define M4U_PORT_CRZO_D1 MTK_M4U_ID(M4U_LARB5_ID, 8)
+#define M4U_PORT_IMG3O_D1 MTK_M4U_ID(M4U_LARB5_ID, 9)
+#define M4U_PORT_VIPI_D1 MTK_M4U_ID(M4U_LARB5_ID, 10)
+#define M4U_PORT_WPE_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 11)
+#define M4U_PORT_WPE_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 12)
+#define M4U_PORT_WPE_WDMA MTK_M4U_ID(M4U_LARB5_ID, 13)
+#define M4U_PORT_TIMGO_D1 MTK_M4U_ID(M4U_LARB5_ID, 14)
+#define M4U_PORT_MFB_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 15)
+#define M4U_PORT_MFB_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 16)
+#define M4U_PORT_MFB_RDMA2 MTK_M4U_ID(M4U_LARB5_ID, 17)
+#define M4U_PORT_MFB_RDMA3 MTK_M4U_ID(M4U_LARB5_ID, 18)
+#define M4U_PORT_MFB_WDMA MTK_M4U_ID(M4U_LARB5_ID, 19)
+#define M4U_PORT_RESERVE1 MTK_M4U_ID(M4U_LARB5_ID, 20)
+#define M4U_PORT_RESERVE2 MTK_M4U_ID(M4U_LARB5_ID, 21)
+#define M4U_PORT_RESERVE3 MTK_M4U_ID(M4U_LARB5_ID, 22)
+#define M4U_PORT_RESERVE4 MTK_M4U_ID(M4U_LARB5_ID, 23)
+#define M4U_PORT_RESERVE5 MTK_M4U_ID(M4U_LARB5_ID, 24)
+#define M4U_PORT_RESERVE6 MTK_M4U_ID(M4U_LARB5_ID, 25)
+
+/* larb6-IMG-VPU */
+#define M4U_PORT_IMG_IPUO MTK_M4U_ID(M4U_LARB6_ID, 0)
+#define M4U_PORT_IMG_IPU3O MTK_M4U_ID(M4U_LARB6_ID, 1)
+#define M4U_PORT_IMG_IPUI MTK_M4U_ID(M4U_LARB6_ID, 2)
+
+/* larb7-DVS */
+#define M4U_PORT_DVS_RDMA MTK_M4U_ID(M4U_LARB7_ID, 0)
+#define M4U_PORT_DVS_WDMA MTK_M4U_ID(M4U_LARB7_ID, 1)
+#define M4U_PORT_DVP_RDMA MTK_M4U_ID(M4U_LARB7_ID, 2)
+#define M4U_PORT_DVP_WDMA MTK_M4U_ID(M4U_LARB7_ID, 3)
+
+/* larb8-IPESYS */
+#define M4U_PORT_FDVT_RDA MTK_M4U_ID(M4U_LARB8_ID, 0)
+#define M4U_PORT_FDVT_RDB MTK_M4U_ID(M4U_LARB8_ID, 1)
+#define M4U_PORT_FDVT_WRA MTK_M4U_ID(M4U_LARB8_ID, 2)
+#define M4U_PORT_FDVT_WRB MTK_M4U_ID(M4U_LARB8_ID, 3)
+#define M4U_PORT_FE_RD0 MTK_M4U_ID(M4U_LARB8_ID, 4)
+#define M4U_PORT_FE_RD1 MTK_M4U_ID(M4U_LARB8_ID, 5)
+#define M4U_PORT_FE_WR0 MTK_M4U_ID(M4U_LARB8_ID, 6)
+#define M4U_PORT_FE_WR1 MTK_M4U_ID(M4U_LARB8_ID, 7)
+#define M4U_PORT_RSC_RDMA0 MTK_M4U_ID(M4U_LARB8_ID, 8)
+#define M4U_PORT_RSC_WDMA MTK_M4U_ID(M4U_LARB8_ID, 9)
+
+/* larb9-CAM */
+#define M4U_PORT_CAM_IMGO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 0)
+#define M4U_PORT_CAM_RRZO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 1)
+#define M4U_PORT_CAM_LSCI_R1_C MTK_M4U_ID(M4U_LARB9_ID, 2)
+#define M4U_PORT_CAM_BPCI_R1_C MTK_M4U_ID(M4U_LARB9_ID, 3)
+#define M4U_PORT_CAM_YUVO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 4)
+#define M4U_PORT_CAM_UFDI_R2_C MTK_M4U_ID(M4U_LARB9_ID, 5)
+#define M4U_PORT_CAM_RAWI_R2_C MTK_M4U_ID(M4U_LARB9_ID, 6)
+#define M4U_PORT_CAM_RAWI_R5_C MTK_M4U_ID(M4U_LARB9_ID, 7)
+#define M4U_PORT_CAM_CAMSV_1 MTK_M4U_ID(M4U_LARB9_ID, 8)
+#define M4U_PORT_CAM_CAMSV_2 MTK_M4U_ID(M4U_LARB9_ID, 9)
+#define M4U_PORT_CAM_CAMSV_3 MTK_M4U_ID(M4U_LARB9_ID, 10)
+#define M4U_PORT_CAM_CAMSV_4 MTK_M4U_ID(M4U_LARB9_ID, 11)
+#define M4U_PORT_CAM_CAMSV_5 MTK_M4U_ID(M4U_LARB9_ID, 12)
+#define M4U_PORT_CAM_CAMSV_6 MTK_M4U_ID(M4U_LARB9_ID, 13)
+#define M4U_PORT_CAM_AAO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 14)
+#define M4U_PORT_CAM_AFO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 15)
+#define M4U_PORT_CAM_FLKO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 16)
+#define M4U_PORT_CAM_LCESO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 17)
+#define M4U_PORT_CAM_CRZO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 18)
+#define M4U_PORT_CAM_LTMSO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 19)
+#define M4U_PORT_CAM_RSSO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 20)
+#define M4U_PORT_CAM_CCUI MTK_M4U_ID(M4U_LARB9_ID, 21)
+#define M4U_PORT_CAM_CCUO MTK_M4U_ID(M4U_LARB9_ID, 22)
+#define M4U_PORT_CAM_FAKE MTK_M4U_ID(M4U_LARB9_ID, 23)
+
+/* larb10-CAM_A */
+#define M4U_PORT_CAM_IMGO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 0)
+#define M4U_PORT_CAM_RRZO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 1)
+#define M4U_PORT_CAM_LSCI_R1_A MTK_M4U_ID(M4U_LARB10_ID, 2)
+#define M4U_PORT_CAM_BPCI_R1_A MTK_M4U_ID(M4U_LARB10_ID, 3)
+#define M4U_PORT_CAM_YUVO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 4)
+#define M4U_PORT_CAM_UFDI_R2_A MTK_M4U_ID(M4U_LARB10_ID, 5)
+#define M4U_PORT_CAM_RAWI_R2_A MTK_M4U_ID(M4U_LARB10_ID, 6)
+#define M4U_PORT_CAM_RAWI_R5_A MTK_M4U_ID(M4U_LARB10_ID, 7)
+#define M4U_PORT_CAM_IMGO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 8)
+#define M4U_PORT_CAM_RRZO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 9)
+#define M4U_PORT_CAM_LSCI_R1_B MTK_M4U_ID(M4U_LARB10_ID, 10)
+#define M4U_PORT_CAM_BPCI_R1_B MTK_M4U_ID(M4U_LARB10_ID, 11)
+#define M4U_PORT_CAM_YUVO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 12)
+#define M4U_PORT_CAM_UFDI_R2_B MTK_M4U_ID(M4U_LARB10_ID, 13)
+#define M4U_PORT_CAM_RAWI_R2_B MTK_M4U_ID(M4U_LARB10_ID, 14)
+#define M4U_PORT_CAM_RAWI_R5_B MTK_M4U_ID(M4U_LARB10_ID, 15)
+#define M4U_PORT_CAM_CAMSV_0 MTK_M4U_ID(M4U_LARB10_ID, 16)
+#define M4U_PORT_CAM_AAO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 17)
+#define M4U_PORT_CAM_AFO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 18)
+#define M4U_PORT_CAM_FLKO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 19)
+#define M4U_PORT_CAM_LCESO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 20)
+#define M4U_PORT_CAM_CRZO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 21)
+#define M4U_PORT_CAM_AAO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 22)
+#define M4U_PORT_CAM_AFO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 23)
+#define M4U_PORT_CAM_FLKO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 24)
+#define M4U_PORT_CAM_LCESO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 25)
+#define M4U_PORT_CAM_CRZO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 26)
+#define M4U_PORT_CAM_LTMSO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 27)
+#define M4U_PORT_CAM_RSSO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 28)
+#define M4U_PORT_CAM_LTMSO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 29)
+#define M4U_PORT_CAM_RSSO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 30)
+
+/* larb11-CAM-VPU */
+#define M4U_PORT_CAM_IPUO MTK_M4U_ID(M4U_LARB11_ID, 0)
+#define M4U_PORT_CAM_IPU2O MTK_M4U_ID(M4U_LARB11_ID, 1)
+#define M4U_PORT_CAM_IPU3O MTK_M4U_ID(M4U_LARB11_ID, 2)
+#define M4U_PORT_CAM_IPUI MTK_M4U_ID(M4U_LARB11_ID, 3)
+#define M4U_PORT_CAM_IPU2I MTK_M4U_ID(M4U_LARB11_ID, 4)
+
+#define M4U_PORT_CCU0 MTK_M4U_ID(M4U_LARB12_ID, 0)
+#define M4U_PORT_CCU1 MTK_M4U_ID(M4U_LARB12_ID, 1)
+
+#define M4U_PORT_VPU MTK_M4U_ID(M4U_LARB13_ID, 0)
+#define M4U_PORT_MDLA MTK_M4U_ID(M4U_LARB13_ID, 1)
+#define M4U_PORT_EDMA MTK_M4U_ID(M4U_LARB13_ID, 2)
+
+#endif
--
2.18.0
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^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v2 01/19] dt-bindings: mediatek: Add bindings for MT6779
2020-01-05 10:45 ` [PATCH v2 01/19] dt-bindings: mediatek: Add bindings for MT6779 Chao Hao
@ 2020-01-06 21:57 ` Rob Herring
2020-01-07 11:10 ` chao hao
0 siblings, 1 reply; 22+ messages in thread
From: Rob Herring @ 2020-01-06 21:57 UTC (permalink / raw)
To: Chao Hao
Cc: Anan Sun, devicetree, Jun Yan, wsd_upstream, linux-kernel,
Chao Hao, iommu, linux-mediatek, Matthias Brugger, Cui Zhang,
linux-arm-kernel
On Sun, 5 Jan 2020 18:45:05 +0800, Chao Hao wrote:
> This patch adds description for MT6779 IOMMU.
>
> MT6779 has two iommus, they are MM_IOMMU and APU_IOMMU which
> use ARM Short-Descriptor translation format.
>
> The MT6779 IOMMU hardware diagram is as below, it is only a brief
> diagram about iommu, it don't focus on the part of smi_larb, so
> I don't describe the smi_larb detailedly.
>
> EMI
> |
> --------------------------------------
> | |
> MM_IOMMU APU_IOMMU
> | |
> SMI_COMMOM----------- APU_BUS
> | | |
> SMI_LARB(0~11) SMI_LARB12(FAKE) SMI_LARB13(FAKE)
> | | |
> | | --------------
> | | | | |
> Multimedia engine CCU VPU MDLA EMDA
>
> All the connections are hardware fixed, software can not adjust it.
>
> >From the diagram above, MM_IOMMU provides mapping for multimedia engine,
> but CCU is connected with smi_common directly, we can take them as larb12.
> APU_IOMMU provides mapping for APU engine, we can take them larb13.
> Larb12 and Larb13 are fake larbs.
>
> Signed-off-by: Chao Hao <chao.hao@mediatek.com>
> ---
> .../bindings/iommu/mediatek,iommu.txt | 2 +
> include/dt-bindings/memory/mt6779-larb-port.h | 215 ++++++++++++++++++
> 2 files changed, 217 insertions(+)
> create mode 100644 include/dt-bindings/memory/mt6779-larb-port.h
>
Please add Acked-by/Reviewed-by tags when posting new versions. However,
there's no need to repost patches *only* to add the tags. The upstream
maintainer will do that for acks received on the version they apply.
If a tag was not added on purpose, please state why and what changed.
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 01/19] dt-bindings: mediatek: Add bindings for MT6779
2020-01-06 21:57 ` Rob Herring
@ 2020-01-07 11:10 ` chao hao
0 siblings, 0 replies; 22+ messages in thread
From: chao hao @ 2020-01-07 11:10 UTC (permalink / raw)
To: Rob Herring
Cc: Anan Sun, devicetree, Cui Zhang, Jun Yan, wsd_upstream,
linux-kernel, Chao Hao, iommu, linux-mediatek, Matthias Brugger,
linux-arm-kernel
On Mon, 2020-01-06 at 15:57 -0600, Rob Herring wrote:
> On Sun, 5 Jan 2020 18:45:05 +0800, Chao Hao wrote:
> > This patch adds description for MT6779 IOMMU.
> >
> > MT6779 has two iommus, they are MM_IOMMU and APU_IOMMU which
> > use ARM Short-Descriptor translation format.
> >
> > The MT6779 IOMMU hardware diagram is as below, it is only a brief
> > diagram about iommu, it don't focus on the part of smi_larb, so
> > I don't describe the smi_larb detailedly.
> >
> > EMI
> > |
> > --------------------------------------
> > | |
> > MM_IOMMU APU_IOMMU
> > | |
> > SMI_COMMOM----------- APU_BUS
> > | | |
> > SMI_LARB(0~11) SMI_LARB12(FAKE) SMI_LARB13(FAKE)
> > | | |
> > | | --------------
> > | | | | |
> > Multimedia engine CCU VPU MDLA EMDA
> >
> > All the connections are hardware fixed, software can not adjust it.
> >
> > >From the diagram above, MM_IOMMU provides mapping for multimedia engine,
> > but CCU is connected with smi_common directly, we can take them as larb12.
> > APU_IOMMU provides mapping for APU engine, we can take them larb13.
> > Larb12 and Larb13 are fake larbs.
> >
> > Signed-off-by: Chao Hao <chao.hao@mediatek.com>
> > ---
> > .../bindings/iommu/mediatek,iommu.txt | 2 +
> > include/dt-bindings/memory/mt6779-larb-port.h | 215 ++++++++++++++++++
> > 2 files changed, 217 insertions(+)
> > create mode 100644 include/dt-bindings/memory/mt6779-larb-port.h
> >
>
> Please add Acked-by/Reviewed-by tags when posting new versions. However,
> there's no need to repost patches *only* to add the tags. The upstream
> maintainer will do that for acks received on the version they apply.
>
> If a tag was not added on purpose, please state why and what changed.
Hi Rob,
I am Sorry, this is my first time upstream and not clear for some
details, please forgive me for this mistake.
I put the changed explanation into cover letter([PATCH v2 00/19] MT6779
IOMMU SUPPORT) about this patch. I will pay attention to this problem in
next version.
Change since v1 for this patch
1.Delete M4U_PORT_UNKNOWN define because of not use it.
2.Correct coding format: ex: /*larb3-VENC*/ --> /* larb3-VENC */
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^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v2 02/19] iommu/mediatek: Add m4u1_mask to distinguish m4u_id
2020-01-05 10:45 [PATCH v2 00/19] MT6779 IOMMU SUPPORT Chao Hao
2020-01-05 10:45 ` [PATCH v2 01/19] dt-bindings: mediatek: Add bindings for MT6779 Chao Hao
@ 2020-01-05 10:45 ` Chao Hao
2020-01-05 10:45 ` [PATCH v2 03/19] iommu/mediatek: Extend larb_remap to larb_remap[2] Chao Hao
` (16 subsequent siblings)
18 siblings, 0 replies; 22+ messages in thread
From: Chao Hao @ 2020-01-05 10:45 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger
Cc: Anan Sun, devicetree, Jun Yan, wsd_upstream, linux-kernel,
Chao Hao, iommu, linux-mediatek, Cui Zhang, linux-arm-kernel
For some platforms(ex: later mt6779), it maybe have two IOMMUs,
so we can add m4u_mask variable to distinguish it by different
smi_larb id
Signed-off-by: Chao Hao <chao.hao@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 3 +++
drivers/iommu/mtk_iommu.h | 2 ++
2 files changed, 5 insertions(+)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 6fc1f5ecf91e..09192edef1f7 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -678,6 +678,9 @@ static int mtk_iommu_probe(struct platform_device *pdev)
}
data->larb_imu[id].dev = &plarbdev->dev;
+ if (data->plat_data->m4u1_mask == (1 << id))
+ data->m4u_id = 1;
+
component_match_add_release(dev, &match, release_of,
compare_of, larbnode);
}
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index ea949a324e33..b4bd76548615 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -42,6 +42,7 @@ struct mtk_iommu_plat_data {
bool has_bclk;
bool has_vld_pa_rng;
bool reset_axi;
+ u32 m4u1_mask;
unsigned char larbid_remap[MTK_LARB_NR_MAX];
};
@@ -59,6 +60,7 @@ struct mtk_iommu_data {
bool enable_4GB;
spinlock_t tlb_lock; /* lock for tlb range flush */
+ u32 m4u_id;
struct iommu_device iommu;
const struct mtk_iommu_plat_data *plat_data;
--
2.18.0
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v2 03/19] iommu/mediatek: Extend larb_remap to larb_remap[2]
2020-01-05 10:45 [PATCH v2 00/19] MT6779 IOMMU SUPPORT Chao Hao
2020-01-05 10:45 ` [PATCH v2 01/19] dt-bindings: mediatek: Add bindings for MT6779 Chao Hao
2020-01-05 10:45 ` [PATCH v2 02/19] iommu/mediatek: Add m4u1_mask to distinguish m4u_id Chao Hao
@ 2020-01-05 10:45 ` Chao Hao
2020-01-05 10:45 ` [PATCH v2 04/19] iommu/mediatek: Rename offset=0x48 register Chao Hao
` (15 subsequent siblings)
18 siblings, 0 replies; 22+ messages in thread
From: Chao Hao @ 2020-01-05 10:45 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger
Cc: Anan Sun, devicetree, Jun Yan, wsd_upstream, linux-kernel,
Chao Hao, iommu, linux-mediatek, Cui Zhang, linux-arm-kernel
For more than one IOMMUs, they are corresponding to different
smi_larb id, so we need to extend larb_remap to larb_remap[2]
to distinguish it by index.
Signed-off-by: Chao Hao <chao.hao@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 8 ++++----
drivers/iommu/mtk_iommu.h | 2 +-
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 09192edef1f7..f2d953fc09df 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -245,7 +245,7 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
fault_larb = F_MMU_INT_ID_LARB_ID(regval);
fault_port = F_MMU_INT_ID_PORT_ID(regval);
- fault_larb = data->plat_data->larbid_remap[fault_larb];
+ fault_larb = data->plat_data->larbid_remap[data->m4u_id][fault_larb];
if (report_iommu_fault(&dom->domain, data->dev, fault_iova,
write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) {
@@ -782,7 +782,7 @@ static const struct mtk_iommu_plat_data mt2712_data = {
.has_4gb_mode = true,
.has_bclk = true,
.has_vld_pa_rng = true,
- .larbid_remap = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9},
+ .larbid_remap[0] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9},
};
static const struct mtk_iommu_plat_data mt8173_data = {
@@ -790,13 +790,13 @@ static const struct mtk_iommu_plat_data mt8173_data = {
.has_4gb_mode = true,
.has_bclk = true,
.reset_axi = true,
- .larbid_remap = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */
+ .larbid_remap[0] = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */
};
static const struct mtk_iommu_plat_data mt8183_data = {
.m4u_plat = M4U_MT8183,
.reset_axi = true,
- .larbid_remap = {0, 4, 5, 6, 7, 2, 3, 1},
+ .larbid_remap[0] = {0, 4, 5, 6, 7, 2, 3, 1},
};
static const struct of_device_id mtk_iommu_of_ids[] = {
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index b4bd76548615..c585811a957c 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -43,7 +43,7 @@ struct mtk_iommu_plat_data {
bool has_vld_pa_rng;
bool reset_axi;
u32 m4u1_mask;
- unsigned char larbid_remap[MTK_LARB_NR_MAX];
+ unsigned char larbid_remap[2][MTK_LARB_NR_MAX];
};
struct mtk_iommu_domain;
--
2.18.0
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v2 04/19] iommu/mediatek: Rename offset=0x48 register
2020-01-05 10:45 [PATCH v2 00/19] MT6779 IOMMU SUPPORT Chao Hao
` (2 preceding siblings ...)
2020-01-05 10:45 ` [PATCH v2 03/19] iommu/mediatek: Extend larb_remap to larb_remap[2] Chao Hao
@ 2020-01-05 10:45 ` Chao Hao
2020-01-05 10:45 ` [PATCH v2 05/19] iommu/mediatek: Put inv_sel_reg in the plat_data for preparing add 0x2c support in mt6779 Chao Hao
` (14 subsequent siblings)
18 siblings, 0 replies; 22+ messages in thread
From: Chao Hao @ 2020-01-05 10:45 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger
Cc: Anan Sun, devicetree, Jun Yan, wsd_upstream, linux-kernel,
Chao Hao, iommu, linux-mediatek, Cui Zhang, linux-arm-kernel
For different platforms(ex:later mt6779), offset=0x48 register will
extend more feature by different bits, so we can rename REG_MMU_MISC_CTRL.
Signed-off-by: Chao Hao <chao.hao@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index f2d953fc09df..bffd417f4442 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -41,7 +41,7 @@
#define F_INVLD_EN0 BIT(0)
#define F_INVLD_EN1 BIT(1)
-#define REG_MMU_STANDARD_AXI_MODE 0x048
+#define REG_MMU_MISC_CTRL 0x048
#define REG_MMU_DCM_DIS 0x050
#define REG_MMU_CTRL_REG 0x110
@@ -587,7 +587,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
if (data->plat_data->reset_axi)
- writel_relaxed(0, data->base + REG_MMU_STANDARD_AXI_MODE);
+ writel_relaxed(0, data->base + REG_MMU_MISC_CTRL);
if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
dev_name(data->dev), (void *)data)) {
@@ -735,7 +735,7 @@ static int __maybe_unused mtk_iommu_suspend(struct device *dev)
void __iomem *base = data->base;
reg->standard_axi_mode = readl_relaxed(base +
- REG_MMU_STANDARD_AXI_MODE);
+ REG_MMU_MISC_CTRL);
reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS);
reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0);
@@ -760,7 +760,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
return ret;
}
writel_relaxed(reg->standard_axi_mode,
- base + REG_MMU_STANDARD_AXI_MODE);
+ base + REG_MMU_MISC_CTRL);
writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS);
writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0);
--
2.18.0
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v2 05/19] iommu/mediatek: Put inv_sel_reg in the plat_data for preparing add 0x2c support in mt6779
2020-01-05 10:45 [PATCH v2 00/19] MT6779 IOMMU SUPPORT Chao Hao
` (3 preceding siblings ...)
2020-01-05 10:45 ` [PATCH v2 04/19] iommu/mediatek: Rename offset=0x48 register Chao Hao
@ 2020-01-05 10:45 ` Chao Hao
2020-01-05 10:45 ` [PATCH v2 06/19] iommu/mediatek: Add new flow to get SUB_COMMON ID in translation fault Chao Hao
` (13 subsequent siblings)
18 siblings, 0 replies; 22+ messages in thread
From: Chao Hao @ 2020-01-05 10:45 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger
Cc: Anan Sun, devicetree, Jun Yan, wsd_upstream, linux-kernel,
Chao Hao, iommu, linux-mediatek, Cui Zhang, linux-arm-kernel
For mt6779, MMU_INVLDT_SEL register's offset is changed from 0x38 to 0x2c,
so we can put inv_sel_reg in the plat_data to use it.
Signed-off-by: Chao Hao <chao.hao@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 8 ++++++--
drivers/iommu/mtk_iommu.h | 1 +
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index bffd417f4442..b61785a87764 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -37,6 +37,7 @@
#define REG_MMU_INVLD_START_A 0x024
#define REG_MMU_INVLD_END_A 0x028
+#define REG_MMU_INV_SEL_MT6779 0x02c
#define REG_MMU_INV_SEL 0x038
#define F_INVLD_EN0 BIT(0)
#define F_INVLD_EN1 BIT(1)
@@ -165,7 +166,7 @@ static void mtk_iommu_tlb_flush_all(void *cookie)
for_each_m4u(data) {
writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
- data->base + REG_MMU_INV_SEL);
+ data->base + data->plat_data->inv_sel_reg);
writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
wmb(); /* Make sure the tlb flush all done */
}
@@ -182,7 +183,7 @@ static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size,
for_each_m4u(data) {
spin_lock_irqsave(&data->tlb_lock, flags);
writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
- data->base + REG_MMU_INV_SEL);
+ data->base + data->plat_data->inv_sel_reg);
writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A);
writel_relaxed(iova + size - 1,
@@ -783,6 +784,7 @@ static const struct mtk_iommu_plat_data mt2712_data = {
.has_bclk = true,
.has_vld_pa_rng = true,
.larbid_remap[0] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9},
+ .inv_sel_reg = REG_MMU_INV_SEL,
};
static const struct mtk_iommu_plat_data mt8173_data = {
@@ -791,12 +793,14 @@ static const struct mtk_iommu_plat_data mt8173_data = {
.has_bclk = true,
.reset_axi = true,
.larbid_remap[0] = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */
+ .inv_sel_reg = REG_MMU_INV_SEL,
};
static const struct mtk_iommu_plat_data mt8183_data = {
.m4u_plat = M4U_MT8183,
.reset_axi = true,
.larbid_remap[0] = {0, 4, 5, 6, 7, 2, 3, 1},
+ .inv_sel_reg = REG_MMU_INV_SEL,
};
static const struct of_device_id mtk_iommu_of_ids[] = {
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index c585811a957c..ec3011a50728 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -43,6 +43,7 @@ struct mtk_iommu_plat_data {
bool has_vld_pa_rng;
bool reset_axi;
u32 m4u1_mask;
+ u32 inv_sel_reg;
unsigned char larbid_remap[2][MTK_LARB_NR_MAX];
};
--
2.18.0
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v2 06/19] iommu/mediatek: Add new flow to get SUB_COMMON ID in translation fault
2020-01-05 10:45 [PATCH v2 00/19] MT6779 IOMMU SUPPORT Chao Hao
` (4 preceding siblings ...)
2020-01-05 10:45 ` [PATCH v2 05/19] iommu/mediatek: Put inv_sel_reg in the plat_data for preparing add 0x2c support in mt6779 Chao Hao
@ 2020-01-05 10:45 ` Chao Hao
2020-01-05 10:45 ` [PATCH v2 07/19] iommu/mediatek: Add REG_MMU_WR_LEN reg define prepare for mt6779 Chao Hao
` (12 subsequent siblings)
18 siblings, 0 replies; 22+ messages in thread
From: Chao Hao @ 2020-01-05 10:45 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger
Cc: Anan Sun, devicetree, Jun Yan, wsd_upstream, linux-kernel,
Chao Hao, iommu, linux-mediatek, Cui Zhang, linux-arm-kernel
When the number of smi_larb is more than seven, smi_larb id
will be divided into COMMON_ID(high three bits, bit[11:9]) and
SUB_COMMON_ID(low two bits,bit[8:7]). So we can analyse translation
fault id by SUB_COMMON_ID and COMMON_ID. We can distinguish if
has SUB_COMMON_ID and SUB_COMMON_ID by has_sub_comm variable.
Signed-off-by: Chao Hao <chao.hao@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 16 ++++++++++++----
drivers/iommu/mtk_iommu.h | 1 +
2 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index b61785a87764..5de13ab1094e 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -89,6 +89,8 @@
#define REG_MMU1_INVLD_PA 0x148
#define REG_MMU0_INT_ID 0x150
#define REG_MMU1_INT_ID 0x154
+#define F_MMU_INT_ID_COMM_ID(a) (((a) >> 9) & 0x7)
+#define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3)
#define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7)
#define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f)
@@ -227,7 +229,7 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
struct mtk_iommu_data *data = dev_id;
struct mtk_iommu_domain *dom = data->m4u_dom;
u32 int_state, regval, fault_iova, fault_pa;
- unsigned int fault_larb, fault_port;
+ unsigned int fault_larb, fault_port, sub_comm = 0;
bool layer, write;
/* Read error info from registers */
@@ -243,8 +245,13 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
}
layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT;
write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT;
- fault_larb = F_MMU_INT_ID_LARB_ID(regval);
fault_port = F_MMU_INT_ID_PORT_ID(regval);
+ if (data->plat_data->has_sub_comm[data->m4u_id]) {
+ fault_larb = F_MMU_INT_ID_COMM_ID(regval);
+ sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval);
+ } else {
+ fault_larb = F_MMU_INT_ID_LARB_ID(regval);
+ }
fault_larb = data->plat_data->larbid_remap[data->m4u_id][fault_larb];
@@ -252,8 +259,9 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) {
dev_err_ratelimited(
data->dev,
- "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d layer=%d %s\n",
- int_state, fault_iova, fault_pa, fault_larb, fault_port,
+ "fault type=0x%x iova=0x%x pa=0x%x larb=%d sub_comm=%d port=%d regval=0x%x layer=%d %s\n",
+ int_state, fault_iova, fault_pa, fault_larb,
+ sub_comm, fault_port, regval,
layer, write ? "write" : "read");
}
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index ec3011a50728..d4495230c6e7 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -40,6 +40,7 @@ struct mtk_iommu_plat_data {
/* HW will use the EMI clock if there isn't the "bclk". */
bool has_bclk;
+ bool has_sub_comm[2];
bool has_vld_pa_rng;
bool reset_axi;
u32 m4u1_mask;
--
2.18.0
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v2 07/19] iommu/mediatek: Add REG_MMU_WR_LEN reg define prepare for mt6779
2020-01-05 10:45 [PATCH v2 00/19] MT6779 IOMMU SUPPORT Chao Hao
` (5 preceding siblings ...)
2020-01-05 10:45 ` [PATCH v2 06/19] iommu/mediatek: Add new flow to get SUB_COMMON ID in translation fault Chao Hao
@ 2020-01-05 10:45 ` Chao Hao
2020-01-05 10:45 ` [PATCH v2 08/19] iommu/mediatek: Add mt6779 basic support Chao Hao
` (11 subsequent siblings)
18 siblings, 0 replies; 22+ messages in thread
From: Chao Hao @ 2020-01-05 10:45 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger
Cc: Anan Sun, devicetree, Jun Yan, wsd_upstream, linux-kernel,
Chao Hao, iommu, linux-mediatek, Cui Zhang, linux-arm-kernel
When some platforms(ex:later mt6779) define has_wr_len variable,
we need to set REG_MMU_WR_LEN to improve performance. So we add
REG_MMU_WR_LEN register define in this patch.
Signed-off-by: Chao Hao <chao.hao@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 11 +++++++++++
drivers/iommu/mtk_iommu.h | 2 ++
2 files changed, 13 insertions(+)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 5de13ab1094e..ad5690350d6a 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -44,6 +44,8 @@
#define REG_MMU_MISC_CTRL 0x048
#define REG_MMU_DCM_DIS 0x050
+#define REG_MMU_WR_LEN 0x054
+#define F_MMU_WR_THROT_DIS (BIT(5) | BIT(21))
#define REG_MMU_CTRL_REG 0x110
#define F_MMU_TF_PROT_TO_PROGRAM_ADDR (2 << 4)
@@ -595,6 +597,13 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
}
writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
+ if (data->plat_data->has_wr_len) {
+ /* write command throttling mode */
+ regval = readl_relaxed(data->base + REG_MMU_WR_LEN);
+ regval &= ~F_MMU_WR_THROT_DIS;
+ writel_relaxed(regval, data->base + REG_MMU_WR_LEN);
+ }
+
if (data->plat_data->reset_axi)
writel_relaxed(0, data->base + REG_MMU_MISC_CTRL);
@@ -743,6 +752,7 @@ static int __maybe_unused mtk_iommu_suspend(struct device *dev)
struct mtk_iommu_suspend_reg *reg = &data->reg;
void __iomem *base = data->base;
+ reg->wr_len = readl_relaxed(base + REG_MMU_WR_LEN);
reg->standard_axi_mode = readl_relaxed(base +
REG_MMU_MISC_CTRL);
reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS);
@@ -768,6 +778,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret);
return ret;
}
+ writel_relaxed(reg->wr_len, base + REG_MMU_WR_LEN);
writel_relaxed(reg->standard_axi_mode,
base + REG_MMU_MISC_CTRL);
writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS);
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index d4495230c6e7..0623f199e96f 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -25,6 +25,7 @@ struct mtk_iommu_suspend_reg {
u32 int_main_control;
u32 ivrp_paddr;
u32 vld_pa_rng;
+ u32 wr_len;
};
enum mtk_iommu_plat {
@@ -43,6 +44,7 @@ struct mtk_iommu_plat_data {
bool has_sub_comm[2];
bool has_vld_pa_rng;
bool reset_axi;
+ bool has_wr_len;
u32 m4u1_mask;
u32 inv_sel_reg;
unsigned char larbid_remap[2][MTK_LARB_NR_MAX];
--
2.18.0
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v2 08/19] iommu/mediatek: Add mt6779 basic support
2020-01-05 10:45 [PATCH v2 00/19] MT6779 IOMMU SUPPORT Chao Hao
` (6 preceding siblings ...)
2020-01-05 10:45 ` [PATCH v2 07/19] iommu/mediatek: Add REG_MMU_WR_LEN reg define prepare for mt6779 Chao Hao
@ 2020-01-05 10:45 ` Chao Hao
2020-01-05 10:45 ` [PATCH v2 09/19] iommu/mediatek: Add mtk_iommu_pgtable structure Chao Hao
` (10 subsequent siblings)
18 siblings, 0 replies; 22+ messages in thread
From: Chao Hao @ 2020-01-05 10:45 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger
Cc: Anan Sun, devicetree, Jun Yan, wsd_upstream, linux-kernel,
Chao Hao, iommu, linux-mediatek, Cui Zhang, linux-arm-kernel
1. Add mt6779_data define to support mt6779 IOMMU HW init.
2. For mt6779, there are two IOMMUs, one is MM_IOMMU, the
other is VPU_IOMMU. MM_IOMMU is connected smi_larb to support
multimedia engine to access DRAM, and VPU_IOMMU is connected to
APU_bus to support VPU,MDLA,EDMA to access DRAM. MM_IOMMU and
VPU_IOMMU use the same page table to simplify design by
"mtk_iommu_get_m4u_data".
3. For smi_larb6, it doesn't use MM_IOMMU, so we can distinguish
VPU_IOMMU by it when excutes iommu_probe.
4. For mt6779 APU_IOMMU fault id is irregular, so it was treated specially.
Signed-off-by: Chao Hao <chao.hao@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 46 ++++++++++++++++++++++++++++++++++-----
drivers/iommu/mtk_iommu.h | 2 ++
2 files changed, 42 insertions(+), 6 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index ad5690350d6a..7829d1fd08dd 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -43,7 +43,10 @@
#define F_INVLD_EN1 BIT(1)
#define REG_MMU_MISC_CTRL 0x048
+#define REG_MMU_STANDARD_AXI_MODE_MT6779 (BIT(3) | BIT(19))
+
#define REG_MMU_DCM_DIS 0x050
+
#define REG_MMU_WR_LEN 0x054
#define F_MMU_WR_THROT_DIS (BIT(5) | BIT(21))
@@ -95,8 +98,10 @@
#define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3)
#define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7)
#define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f)
+#define F_MMU_INT_ID_COMM_APU_ID(a) ((a) & 0x3)
+#define F_MMU_INT_ID_SUB_APU_ID(a) (((a) >> 2) & 0x3)
-#define MTK_PROTECT_PA_ALIGN 128
+#define MTK_PROTECT_PA_ALIGN 256
/*
* Get the local arbiter ID and the portid within the larb arbiter
@@ -249,8 +254,15 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT;
fault_port = F_MMU_INT_ID_PORT_ID(regval);
if (data->plat_data->has_sub_comm[data->m4u_id]) {
- fault_larb = F_MMU_INT_ID_COMM_ID(regval);
- sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval);
+ /* m4u1 is VPU in mt6779.*/
+ if (data->m4u_id && data->plat_data->m4u_plat == M4U_MT6779) {
+ fault_larb = F_MMU_INT_ID_COMM_APU_ID(regval);
+ sub_comm = F_MMU_INT_ID_SUB_APU_ID(regval);
+ fault_port = 0; /* for mt6779 APU ID is irregular */
+ } else {
+ fault_larb = F_MMU_INT_ID_COMM_ID(regval);
+ sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval);
+ }
} else {
fault_larb = F_MMU_INT_ID_LARB_ID(regval);
}
@@ -556,11 +568,12 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
return ret;
}
+ regval = readl_relaxed(data->base + REG_MMU_CTRL_REG);
if (data->plat_data->m4u_plat == M4U_MT8173)
- regval = F_MMU_PREFETCH_RT_REPLACE_MOD |
+ regval |= F_MMU_PREFETCH_RT_REPLACE_MOD |
F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173;
else
- regval = F_MMU_TF_PROT_TO_PROGRAM_ADDR;
+ regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR;
writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
regval = F_L2_MULIT_HIT_EN |
@@ -604,8 +617,16 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
writel_relaxed(regval, data->base + REG_MMU_WR_LEN);
}
- if (data->plat_data->reset_axi)
+ if (data->plat_data->has_misc_ctrl[data->m4u_id]) {
+ /* special settings for mmu0 (multimedia iommu) */
+ regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL);
+ /* non-standard AXI mode */
+ regval &= ~REG_MMU_STANDARD_AXI_MODE_MT6779;
+ writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL);
+ } else if (data->plat_data->reset_axi) {
+ /*disable standard axi when it is REG_MMU_STANDARD_AXI_MODE */
writel_relaxed(0, data->base + REG_MMU_MISC_CTRL);
+ }
if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
dev_name(data->dev), (void *)data)) {
@@ -806,6 +827,18 @@ static const struct mtk_iommu_plat_data mt2712_data = {
.inv_sel_reg = REG_MMU_INV_SEL,
};
+static const struct mtk_iommu_plat_data mt6779_data = {
+ .m4u_plat = M4U_MT6779,
+ .larbid_remap[0] = {0, 1, 2, 3, 5, 7, 10, 9},
+ /* vp6a, vp6b, mdla/core2, mdla/edmc*/
+ .larbid_remap[1] = {2, 0, 3, 1},
+ .has_sub_comm = {true, true},
+ .has_wr_len = true,
+ .has_misc_ctrl = {true, false},
+ .inv_sel_reg = REG_MMU_INV_SEL_MT6779,
+ .m4u1_mask = BIT(6),
+};
+
static const struct mtk_iommu_plat_data mt8173_data = {
.m4u_plat = M4U_MT8173,
.has_4gb_mode = true,
@@ -824,6 +857,7 @@ static const struct mtk_iommu_plat_data mt8183_data = {
static const struct of_device_id mtk_iommu_of_ids[] = {
{ .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
+ { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data},
{ .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
{ .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},
{}
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 0623f199e96f..2b207dcadd06 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -31,6 +31,7 @@ struct mtk_iommu_suspend_reg {
enum mtk_iommu_plat {
M4U_MT2701,
M4U_MT2712,
+ M4U_MT6779,
M4U_MT8173,
M4U_MT8183,
};
@@ -45,6 +46,7 @@ struct mtk_iommu_plat_data {
bool has_vld_pa_rng;
bool reset_axi;
bool has_wr_len;
+ bool has_misc_ctrl[2];
u32 m4u1_mask;
u32 inv_sel_reg;
unsigned char larbid_remap[2][MTK_LARB_NR_MAX];
--
2.18.0
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v2 09/19] iommu/mediatek: Add mtk_iommu_pgtable structure
2020-01-05 10:45 [PATCH v2 00/19] MT6779 IOMMU SUPPORT Chao Hao
` (7 preceding siblings ...)
2020-01-05 10:45 ` [PATCH v2 08/19] iommu/mediatek: Add mt6779 basic support Chao Hao
@ 2020-01-05 10:45 ` Chao Hao
2020-01-05 10:45 ` [PATCH v2 10/19] iommu/mediatek: Remove mtk_iommu_domain_finalise Chao Hao
` (9 subsequent siblings)
18 siblings, 0 replies; 22+ messages in thread
From: Chao Hao @ 2020-01-05 10:45 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger
Cc: Anan Sun, devicetree, Jun Yan, wsd_upstream, linux-kernel,
Chao Hao, iommu, linux-mediatek, Cui Zhang, linux-arm-kernel
Start with this patch, we will change the SW architecture
to support multiple domains. SW architecture will has a big change,
so we need to modify a little bit by more than one patch.
The new SW overall architecture is as below:
iommu0 iommu1
| |
-----------
|
mtk_iommu_pgtable
|
------------------------------------------
| | |
mtk_iommu_domain1 mtk_iommu_domain2 mtk_iommu_domain3
| | |
iommu_group1 iommu_group2 iommu_group3
| | |
iommu_domain1 iommu_domain2 iommu_domain3
| | |
iova region1(normal) iova region2(CCU) iova region3(VPU)
For current structure, no matter how many iommus there are,
they use the same page table to simplify the usage of module.
In order to make the software architecture more explicit, this
patch will create a global mtk_iommu_pgtable structure to describe
page table and all the iommus use it.
The diagram is as below:
mtk_iommu_data1(MM) mtk_iommu_data2(APU)
| |
| |
------mtk_iommu_pgtable-----
We need to create global mtk_iommu_pgtable to include all the iova
regions firstly and special iova regions by divided based on it,
so the information of pgtable needs to be created in device_group.
Signed-off-by: Chao Hao <chao.hao@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 84 +++++++++++++++++++++++++++++++++++++++
drivers/iommu/mtk_iommu.h | 1 +
2 files changed, 85 insertions(+)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 7829d1fd08dd..50c6a01eb517 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -117,6 +117,12 @@ struct mtk_iommu_domain {
struct iommu_domain domain;
};
+struct mtk_iommu_pgtable {
+ struct io_pgtable_cfg cfg;
+ struct io_pgtable_ops *iop;
+};
+
+static struct mtk_iommu_pgtable *share_pgtable;
static const struct iommu_ops mtk_iommu_ops;
/*
@@ -164,6 +170,11 @@ static struct mtk_iommu_data *mtk_iommu_get_m4u_data(void)
return NULL;
}
+static struct mtk_iommu_pgtable *mtk_iommu_get_pgtable(void)
+{
+ return share_pgtable;
+}
+
static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom)
{
return container_of(dom, struct mtk_iommu_domain, domain);
@@ -316,6 +327,13 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom)
{
struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
+ if (data->pgtable) {
+ dom->cfg = data->pgtable->cfg;
+ dom->iop = data->pgtable->iop;
+ dom->domain.pgsize_bitmap = data->pgtable->cfg.pgsize_bitmap;
+ return 0;
+ }
+
dom->cfg = (struct io_pgtable_cfg) {
.quirks = IO_PGTABLE_QUIRK_ARM_NS |
IO_PGTABLE_QUIRK_NO_PERMS |
@@ -339,6 +357,61 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom)
return 0;
}
+static struct mtk_iommu_pgtable *create_pgtable(struct mtk_iommu_data *data)
+{
+ struct mtk_iommu_pgtable *pgtable;
+
+ pgtable = kzalloc(sizeof(*pgtable), GFP_KERNEL);
+ if (!pgtable)
+ return ERR_PTR(-ENOMEM);
+
+ pgtable->cfg = (struct io_pgtable_cfg) {
+ .quirks = IO_PGTABLE_QUIRK_ARM_NS |
+ IO_PGTABLE_QUIRK_NO_PERMS |
+ IO_PGTABLE_QUIRK_TLBI_ON_MAP |
+ IO_PGTABLE_QUIRK_ARM_MTK_EXT,
+ .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap,
+ .ias = 32,
+ .oas = 34,
+ .tlb = &mtk_iommu_flush_ops,
+ .iommu_dev = data->dev,
+ };
+
+ pgtable->iop = alloc_io_pgtable_ops(ARM_V7S, &pgtable->cfg, data);
+ if (!pgtable->iop) {
+ dev_err(data->dev, "Failed to alloc io pgtable\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ dev_info(data->dev, "%s create pgtable done\n", __func__);
+
+ return pgtable;
+}
+
+static int mtk_iommu_attach_pgtable(struct mtk_iommu_data *data,
+ struct device *dev)
+{
+ struct mtk_iommu_pgtable *pgtable = mtk_iommu_get_pgtable();
+
+ /* create share pgtable */
+ if (!pgtable) {
+ pgtable = create_pgtable(data);
+ if (IS_ERR(pgtable)) {
+ dev_err(data->dev, "Failed to create pgtable\n");
+ return -ENOMEM;
+ }
+
+ share_pgtable = pgtable;
+ }
+
+ /* binding to pgtable */
+ data->pgtable = pgtable;
+
+ dev_info(data->dev, "m4u%d attach_pgtable done!\n", data->m4u_id);
+
+ return 0;
+}
+
static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
{
struct mtk_iommu_domain *dom;
@@ -502,10 +575,21 @@ static void mtk_iommu_remove_device(struct device *dev)
static struct iommu_group *mtk_iommu_device_group(struct device *dev)
{
struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
+ struct mtk_iommu_pgtable *pgtable;
+ int ret = 0;
if (!data)
return ERR_PTR(-ENODEV);
+ pgtable = data->pgtable;
+ if (!pgtable) {
+ ret = mtk_iommu_attach_pgtable(data, dev);
+ if (ret) {
+ dev_err(data->dev, "Failed to device_group\n");
+ return NULL;
+ }
+ }
+
/* All the client devices are in the same m4u iommu-group */
if (!data->m4u_group) {
data->m4u_group = iommu_group_alloc();
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 2b207dcadd06..a3c598f99ed5 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -61,6 +61,7 @@ struct mtk_iommu_data {
struct clk *bclk;
phys_addr_t protect_base; /* protect memory base */
struct mtk_iommu_suspend_reg reg;
+ struct mtk_iommu_pgtable *pgtable;
struct mtk_iommu_domain *m4u_dom;
struct iommu_group *m4u_group;
bool enable_4GB;
--
2.18.0
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v2 10/19] iommu/mediatek: Remove mtk_iommu_domain_finalise
2020-01-05 10:45 [PATCH v2 00/19] MT6779 IOMMU SUPPORT Chao Hao
` (8 preceding siblings ...)
2020-01-05 10:45 ` [PATCH v2 09/19] iommu/mediatek: Add mtk_iommu_pgtable structure Chao Hao
@ 2020-01-05 10:45 ` Chao Hao
2020-01-05 10:45 ` [PATCH v2 11/19] iommu/mediatek: Remove pgtable info in mtk_iommu_domain Chao Hao
` (8 subsequent siblings)
18 siblings, 0 replies; 22+ messages in thread
From: Chao Hao @ 2020-01-05 10:45 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger
Cc: Anan Sun, devicetree, Jun Yan, wsd_upstream, linux-kernel,
Chao Hao, iommu, linux-mediatek, Cui Zhang, linux-arm-kernel
We already have global mtk_iommu_pgtable structure to describe
page table and create it in group_device, "mtk_iommu_domain_finalise"
is as the same as that, so so we will remove mtk_iommu_domain_finalise.
Signed-off-by: Chao Hao <chao.hao@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 48 ++++++++-------------------------------
1 file changed, 10 insertions(+), 38 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 50c6a01eb517..cfefdd638f1a 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -323,40 +323,6 @@ static void mtk_iommu_config(struct mtk_iommu_data *data,
}
}
-static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom)
-{
- struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
-
- if (data->pgtable) {
- dom->cfg = data->pgtable->cfg;
- dom->iop = data->pgtable->iop;
- dom->domain.pgsize_bitmap = data->pgtable->cfg.pgsize_bitmap;
- return 0;
- }
-
- dom->cfg = (struct io_pgtable_cfg) {
- .quirks = IO_PGTABLE_QUIRK_ARM_NS |
- IO_PGTABLE_QUIRK_NO_PERMS |
- IO_PGTABLE_QUIRK_TLBI_ON_MAP |
- IO_PGTABLE_QUIRK_ARM_MTK_EXT,
- .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap,
- .ias = 32,
- .oas = 34,
- .tlb = &mtk_iommu_flush_ops,
- .iommu_dev = data->dev,
- };
-
- dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data);
- if (!dom->iop) {
- dev_err(data->dev, "Failed to alloc io pgtable\n");
- return -EINVAL;
- }
-
- /* Update our support page sizes bitmap */
- dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap;
- return 0;
-}
-
static struct mtk_iommu_pgtable *create_pgtable(struct mtk_iommu_data *data)
{
struct mtk_iommu_pgtable *pgtable;
@@ -414,11 +380,17 @@ static int mtk_iommu_attach_pgtable(struct mtk_iommu_data *data,
static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
{
+ struct mtk_iommu_pgtable *pgtable = mtk_iommu_get_pgtable();
struct mtk_iommu_domain *dom;
if (type != IOMMU_DOMAIN_DMA)
return NULL;
+ if (!pgtable) {
+ pr_err("%s, pgtable is not ready\n", __func__);
+ return NULL;
+ }
+
dom = kzalloc(sizeof(*dom), GFP_KERNEL);
if (!dom)
return NULL;
@@ -426,8 +398,10 @@ static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
if (iommu_get_dma_cookie(&dom->domain))
goto free_dom;
- if (mtk_iommu_domain_finalise(dom))
- goto put_dma_cookie;
+ dom->cfg = pgtable->cfg;
+ dom->iop = pgtable->iop;
+ /* Update our support page sizes bitmap */
+ dom->domain.pgsize_bitmap = pgtable->cfg.pgsize_bitmap;
dom->domain.geometry.aperture_start = 0;
dom->domain.geometry.aperture_end = DMA_BIT_MASK(32);
@@ -435,8 +409,6 @@ static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
return &dom->domain;
-put_dma_cookie:
- iommu_put_dma_cookie(&dom->domain);
free_dom:
kfree(dom);
return NULL;
--
2.18.0
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v2 11/19] iommu/mediatek: Remove pgtable info in mtk_iommu_domain
2020-01-05 10:45 [PATCH v2 00/19] MT6779 IOMMU SUPPORT Chao Hao
` (9 preceding siblings ...)
2020-01-05 10:45 ` [PATCH v2 10/19] iommu/mediatek: Remove mtk_iommu_domain_finalise Chao Hao
@ 2020-01-05 10:45 ` Chao Hao
2020-01-05 10:45 ` [PATCH v2 12/19] iommu/mediatek: Change get the way of m4u_group Chao Hao
` (7 subsequent siblings)
18 siblings, 0 replies; 22+ messages in thread
From: Chao Hao @ 2020-01-05 10:45 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger
Cc: Anan Sun, devicetree, Jun Yan, wsd_upstream, linux-kernel,
Chao Hao, iommu, linux-mediatek, Cui Zhang, linux-arm-kernel
This patch will use mtk_iommu_pgtable to replace the part
of pgtable in mtk_iommu_domain, so we can remove the information
of pgtable in mtk_iommu_domain.
Signed-off-by: Chao Hao <chao.hao@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 37 +++++++++++++++++--------------------
1 file changed, 17 insertions(+), 20 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index cfefdd638f1a..b34bd3abccf8 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -111,9 +111,6 @@
#define MTK_M4U_TO_PORT(id) ((id) & 0x1f)
struct mtk_iommu_domain {
- struct io_pgtable_cfg cfg;
- struct io_pgtable_ops *iop;
-
struct iommu_domain domain;
};
@@ -373,6 +370,10 @@ static int mtk_iommu_attach_pgtable(struct mtk_iommu_data *data,
/* binding to pgtable */
data->pgtable = pgtable;
+ /* update HW settings */
+ writel(pgtable->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK,
+ data->base + REG_MMU_PT_BASE_ADDR);
+
dev_info(data->dev, "m4u%d attach_pgtable done!\n", data->m4u_id);
return 0;
@@ -398,8 +399,6 @@ static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
if (iommu_get_dma_cookie(&dom->domain))
goto free_dom;
- dom->cfg = pgtable->cfg;
- dom->iop = pgtable->iop;
/* Update our support page sizes bitmap */
dom->domain.pgsize_bitmap = pgtable->cfg.pgsize_bitmap;
@@ -416,11 +415,12 @@ static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
static void mtk_iommu_domain_free(struct iommu_domain *domain)
{
- struct mtk_iommu_domain *dom = to_mtk_domain(domain);
+ struct mtk_iommu_pgtable *pgtable = mtk_iommu_get_pgtable();
- free_io_pgtable_ops(dom->iop);
iommu_put_dma_cookie(domain);
kfree(to_mtk_domain(domain));
+ free_io_pgtable_ops(pgtable->iop);
+ kfree(pgtable);
}
static int mtk_iommu_attach_device(struct iommu_domain *domain,
@@ -433,11 +433,8 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain,
return -ENODEV;
/* Update the pgtable base address register of the M4U HW */
- if (!data->m4u_dom) {
+ if (!data->m4u_dom)
data->m4u_dom = dom;
- writel(dom->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK,
- data->base + REG_MMU_PT_BASE_ADDR);
- }
mtk_iommu_config(data, dev, true);
return 0;
@@ -457,7 +454,7 @@ static void mtk_iommu_detach_device(struct iommu_domain *domain,
static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
phys_addr_t paddr, size_t size, int prot, gfp_t gfp)
{
- struct mtk_iommu_domain *dom = to_mtk_domain(domain);
+ struct mtk_iommu_pgtable *pgtable = mtk_iommu_get_pgtable();
struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
/* The "4GB mode" M4U physically can not use the lower remap of Dram. */
@@ -465,16 +462,16 @@ static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
paddr |= BIT_ULL(32);
/* Synchronize with the tlb_lock */
- return dom->iop->map(dom->iop, iova, paddr, size, prot);
+ return pgtable->iop->map(pgtable->iop, iova, paddr, size, prot);
}
static size_t mtk_iommu_unmap(struct iommu_domain *domain,
unsigned long iova, size_t size,
struct iommu_iotlb_gather *gather)
{
- struct mtk_iommu_domain *dom = to_mtk_domain(domain);
+ struct mtk_iommu_pgtable *pgtable = mtk_iommu_get_pgtable();
- return dom->iop->unmap(dom->iop, iova, size, gather);
+ return pgtable->iop->unmap(pgtable->iop, iova, size, gather);
}
static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain)
@@ -498,11 +495,11 @@ static void mtk_iommu_iotlb_sync(struct iommu_domain *domain,
static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
dma_addr_t iova)
{
- struct mtk_iommu_domain *dom = to_mtk_domain(domain);
+ struct mtk_iommu_pgtable *pgtable = mtk_iommu_get_pgtable();
struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
phys_addr_t pa;
- pa = dom->iop->iova_to_phys(dom->iop, iova);
+ pa = pgtable->iop->iova_to_phys(pgtable->iop, iova);
if (data->enable_4GB && pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE)
pa &= ~BIT_ULL(32);
@@ -845,8 +842,8 @@ static int __maybe_unused mtk_iommu_suspend(struct device *dev)
static int __maybe_unused mtk_iommu_resume(struct device *dev)
{
struct mtk_iommu_data *data = dev_get_drvdata(dev);
+ struct mtk_iommu_pgtable *pgtable = data->pgtable;
struct mtk_iommu_suspend_reg *reg = &data->reg;
- struct mtk_iommu_domain *m4u_dom = data->m4u_dom;
void __iomem *base = data->base;
int ret;
@@ -864,8 +861,8 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL);
writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR);
writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG);
- if (m4u_dom)
- writel(m4u_dom->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK,
+ if (pgtable)
+ writel(pgtable->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK,
base + REG_MMU_PT_BASE_ADDR);
return 0;
}
--
2.18.0
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v2 12/19] iommu/mediatek: Change get the way of m4u_group
2020-01-05 10:45 [PATCH v2 00/19] MT6779 IOMMU SUPPORT Chao Hao
` (10 preceding siblings ...)
2020-01-05 10:45 ` [PATCH v2 11/19] iommu/mediatek: Remove pgtable info in mtk_iommu_domain Chao Hao
@ 2020-01-05 10:45 ` Chao Hao
2020-01-05 10:45 ` [PATCH v2 13/19] iommu/mediatek: Add smi_larb info about device Chao Hao
` (6 subsequent siblings)
18 siblings, 0 replies; 22+ messages in thread
From: Chao Hao @ 2020-01-05 10:45 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger
Cc: Anan Sun, devicetree, Jun Yan, wsd_upstream, linux-kernel,
Chao Hao, iommu, linux-mediatek, Cui Zhang, linux-arm-kernel
1. Redefine mtk_iommu_domain structure, it will include iommu_group
and iommu_domain. Different mtk_iommu_domains can be distinguished by
ID. When we realize multiple mtk_iommu_domains, every mtk_iommu_domain
can describe one iova region.
2. In theory, every device has one iommu_group, so this patch will
get iommu_group by checking device. All the devices belong to the same
m4u_group currently, so they also use the same mtk_iommu_domain(id=0).
Signed-off-by: Chao Hao <chao.hao@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 46 +++++++++++++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index b34bd3abccf8..bf781f4d7364 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -111,12 +111,16 @@
#define MTK_M4U_TO_PORT(id) ((id) & 0x1f)
struct mtk_iommu_domain {
+ u32 id;
struct iommu_domain domain;
+ struct iommu_group *group;
+ struct list_head list;
};
struct mtk_iommu_pgtable {
struct io_pgtable_cfg cfg;
struct io_pgtable_ops *iop;
+ struct list_head m4u_dom_v2;
};
static struct mtk_iommu_pgtable *share_pgtable;
@@ -167,6 +171,41 @@ static struct mtk_iommu_data *mtk_iommu_get_m4u_data(void)
return NULL;
}
+static u32 get_domain_id(void)
+{
+ /* only support one mtk_iommu_domain currently */
+ return 0;
+}
+
+static u32 mtk_iommu_get_domain_id(void)
+{
+ return get_domain_id();
+}
+
+static struct mtk_iommu_domain *get_mtk_domain(struct device *dev)
+{
+ struct mtk_iommu_data *data = dev->iommu_fwspec->iommu_priv;
+ struct mtk_iommu_domain *dom;
+ u32 domain_id = mtk_iommu_get_domain_id();
+
+ list_for_each_entry(dom, &data->pgtable->m4u_dom_v2, list) {
+ if (dom->id == domain_id)
+ return dom;
+ }
+ return NULL;
+}
+
+static struct iommu_group *mtk_iommu_get_group(struct device *dev)
+{
+ struct mtk_iommu_domain *dom;
+
+ dom = get_mtk_domain(dev);
+ if (dom)
+ return dom->group;
+
+ return NULL;
+}
+
static struct mtk_iommu_pgtable *mtk_iommu_get_pgtable(void)
{
return share_pgtable;
@@ -328,6 +367,8 @@ static struct mtk_iommu_pgtable *create_pgtable(struct mtk_iommu_data *data)
if (!pgtable)
return ERR_PTR(-ENOMEM);
+ INIT_LIST_HEAD(&pgtable->m4u_dom_v2);
+
pgtable->cfg = (struct io_pgtable_cfg) {
.quirks = IO_PGTABLE_QUIRK_ARM_NS |
IO_PGTABLE_QUIRK_NO_PERMS |
@@ -382,6 +423,7 @@ static int mtk_iommu_attach_pgtable(struct mtk_iommu_data *data,
static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
{
struct mtk_iommu_pgtable *pgtable = mtk_iommu_get_pgtable();
+ struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
struct mtk_iommu_domain *dom;
if (type != IOMMU_DOMAIN_DMA)
@@ -399,12 +441,15 @@ static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
if (iommu_get_dma_cookie(&dom->domain))
goto free_dom;
+ dom->group = data->m4u_group;
+ dom->id = mtk_iommu_get_domain_id();
/* Update our support page sizes bitmap */
dom->domain.pgsize_bitmap = pgtable->cfg.pgsize_bitmap;
dom->domain.geometry.aperture_start = 0;
dom->domain.geometry.aperture_end = DMA_BIT_MASK(32);
dom->domain.geometry.force_aperture = true;
+ list_add_tail(&dom->list, &pgtable->m4u_dom_v2);
return &dom->domain;
@@ -560,6 +605,7 @@ static struct iommu_group *mtk_iommu_device_group(struct device *dev)
}
/* All the client devices are in the same m4u iommu-group */
+ data->m4u_group = mtk_iommu_get_group(dev);
if (!data->m4u_group) {
data->m4u_group = iommu_group_alloc();
if (IS_ERR(data->m4u_group))
--
2.18.0
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v2 13/19] iommu/mediatek: Add smi_larb info about device
2020-01-05 10:45 [PATCH v2 00/19] MT6779 IOMMU SUPPORT Chao Hao
` (11 preceding siblings ...)
2020-01-05 10:45 ` [PATCH v2 12/19] iommu/mediatek: Change get the way of m4u_group Chao Hao
@ 2020-01-05 10:45 ` Chao Hao
2020-01-05 10:45 ` [PATCH v2 14/19] iommu/mediatek: Add mtk_domain_data structure Chao Hao
` (5 subsequent siblings)
18 siblings, 0 replies; 22+ messages in thread
From: Chao Hao @ 2020-01-05 10:45 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger
Cc: Anan Sun, devicetree, Jun Yan, wsd_upstream, linux-kernel,
Chao Hao, iommu, linux-mediatek, Cui Zhang, linux-arm-kernel
All the devices which used iommu are connected to SMI_larb port,
so when different devices driver execute initialization, iommu
can check larb_id and port_id to distinguish them and then make
them match to iommu_group accordingly. We also add dom_cnt variable
to describe the number of mtk_iommu_domain.
Larb_id and port_id define can refer to "mtxxxx-larb-port.h(ex:
mt6779-larb-port.h)" file
Signed-off-by: Chao Hao <chao.hao@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 50 ++++++++++++++++++++++++++++++++-------
drivers/iommu/mtk_iommu.h | 1 +
2 files changed, 43 insertions(+), 8 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index bf781f4d7364..f2137033ec59 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -120,6 +120,7 @@ struct mtk_iommu_domain {
struct mtk_iommu_pgtable {
struct io_pgtable_cfg cfg;
struct io_pgtable_ops *iop;
+ struct device *init_dev;
struct list_head m4u_dom_v2;
};
@@ -171,22 +172,35 @@ static struct mtk_iommu_data *mtk_iommu_get_m4u_data(void)
return NULL;
}
-static u32 get_domain_id(void)
+static u32 get_domain_id(struct mtk_iommu_data *data, u32 portid)
{
- /* only support one mtk_iommu_domain currently */
- return 0;
+ u32 dom_id = 0;
+ int i;
+
+ /* only support one mtk_iommu_domain currently(dom_cnt = 1) */
+ for (i = 0; i < data->plat_data->dom_cnt; i++)
+ return i;
+
+ return dom_id;
}
-static u32 mtk_iommu_get_domain_id(void)
+static u32 mtk_iommu_get_domain_id(struct device *dev)
{
- return get_domain_id();
+ struct iommu_fwspec *fwspec = dev->iommu_fwspec;
+ struct mtk_iommu_data *data = dev->iommu_fwspec->iommu_priv;
+ u32 portid = fwspec->ids[0];
+
+ return get_domain_id(data, portid);
}
static struct mtk_iommu_domain *get_mtk_domain(struct device *dev)
{
struct mtk_iommu_data *data = dev->iommu_fwspec->iommu_priv;
struct mtk_iommu_domain *dom;
- u32 domain_id = mtk_iommu_get_domain_id();
+ u32 domain_id = mtk_iommu_get_domain_id(dev);
+
+ if (domain_id >= data->plat_data->dom_cnt)
+ return NULL;
list_for_each_entry(dom, &data->pgtable->m4u_dom_v2, list) {
if (dom->id == domain_id)
@@ -425,11 +439,18 @@ static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
struct mtk_iommu_pgtable *pgtable = mtk_iommu_get_pgtable();
struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
struct mtk_iommu_domain *dom;
+ struct device *dev;
if (type != IOMMU_DOMAIN_DMA)
return NULL;
- if (!pgtable) {
+ if (pgtable) {
+ dev = pgtable->init_dev;
+ if (!data->m4u_group) {
+ pr_err("%s, find m4u_group failed\n", __func__);
+ return NULL;
+ }
+ } else {
pr_err("%s, pgtable is not ready\n", __func__);
return NULL;
}
@@ -441,8 +462,11 @@ static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
if (iommu_get_dma_cookie(&dom->domain))
goto free_dom;
+ dom->id = mtk_iommu_get_domain_id(dev);
+ if (dom->id >= data->plat_data->dom_cnt)
+ goto put_dma_cookie;
+
dom->group = data->m4u_group;
- dom->id = mtk_iommu_get_domain_id();
/* Update our support page sizes bitmap */
dom->domain.pgsize_bitmap = pgtable->cfg.pgsize_bitmap;
@@ -453,6 +477,8 @@ static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
return &dom->domain;
+put_dma_cookie:
+ iommu_put_dma_cookie(&dom->domain);
free_dom:
kfree(dom);
return NULL;
@@ -613,6 +639,10 @@ static struct iommu_group *mtk_iommu_device_group(struct device *dev)
} else {
iommu_group_ref_get(data->m4u_group);
}
+
+ /* save the latest init device */
+ pgtable->init_dev = dev;
+
return data->m4u_group;
}
@@ -922,12 +952,14 @@ static const struct mtk_iommu_plat_data mt2712_data = {
.has_4gb_mode = true,
.has_bclk = true,
.has_vld_pa_rng = true,
+ .dom_cnt = 1,
.larbid_remap[0] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9},
.inv_sel_reg = REG_MMU_INV_SEL,
};
static const struct mtk_iommu_plat_data mt6779_data = {
.m4u_plat = M4U_MT6779,
+ .dom_cnt = 1,
.larbid_remap[0] = {0, 1, 2, 3, 5, 7, 10, 9},
/* vp6a, vp6b, mdla/core2, mdla/edmc*/
.larbid_remap[1] = {2, 0, 3, 1},
@@ -943,6 +975,7 @@ static const struct mtk_iommu_plat_data mt8173_data = {
.has_4gb_mode = true,
.has_bclk = true,
.reset_axi = true,
+ .dom_cnt = 1,
.larbid_remap[0] = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */
.inv_sel_reg = REG_MMU_INV_SEL,
};
@@ -950,6 +983,7 @@ static const struct mtk_iommu_plat_data mt8173_data = {
static const struct mtk_iommu_plat_data mt8183_data = {
.m4u_plat = M4U_MT8183,
.reset_axi = true,
+ .dom_cnt = 1,
.larbid_remap[0] = {0, 4, 5, 6, 7, 2, 3, 1},
.inv_sel_reg = REG_MMU_INV_SEL,
};
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index a3c598f99ed5..3a1c79222d09 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -47,6 +47,7 @@ struct mtk_iommu_plat_data {
bool reset_axi;
bool has_wr_len;
bool has_misc_ctrl[2];
+ u32 dom_cnt;
u32 m4u1_mask;
u32 inv_sel_reg;
unsigned char larbid_remap[2][MTK_LARB_NR_MAX];
--
2.18.0
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v2 14/19] iommu/mediatek: Add mtk_domain_data structure
2020-01-05 10:45 [PATCH v2 00/19] MT6779 IOMMU SUPPORT Chao Hao
` (12 preceding siblings ...)
2020-01-05 10:45 ` [PATCH v2 13/19] iommu/mediatek: Add smi_larb info about device Chao Hao
@ 2020-01-05 10:45 ` Chao Hao
2020-01-05 10:45 ` [PATCH v2 15/19] iommu/mediatek: Remove the usage of m4u_dom variable Chao Hao
` (4 subsequent siblings)
18 siblings, 0 replies; 22+ messages in thread
From: Chao Hao @ 2020-01-05 10:45 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger
Cc: Anan Sun, devicetree, Jun Yan, wsd_upstream, linux-kernel,
Chao Hao, iommu, linux-mediatek, Cui Zhang, linux-arm-kernel
Add mtk_domain_data structure to describe how many iova regions
there are and the relevant the start and end address of each
iova region. The number of iova region is equal to the number
of mtk_iommu_domain. So we will use mtk_domain_data to initialize
the start and end iova of mtk_iommu_domain.
Signed-off-by: Chao Hao <chao.hao@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 17 +++++++++++++++--
drivers/iommu/mtk_iommu.h | 17 +++++++++++++++++
2 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index f2137033ec59..b1ce0a2df583 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -122,6 +122,12 @@ struct mtk_iommu_pgtable {
struct io_pgtable_ops *iop;
struct device *init_dev;
struct list_head m4u_dom_v2;
+ const struct mtk_domain_data *dom_region;
+};
+
+const struct mtk_domain_data single_dom = {
+ .min_iova = 0x0,
+ .max_iova = DMA_BIT_MASK(32)
};
static struct mtk_iommu_pgtable *share_pgtable;
@@ -400,6 +406,7 @@ static struct mtk_iommu_pgtable *create_pgtable(struct mtk_iommu_data *data)
dev_err(data->dev, "Failed to alloc io pgtable\n");
return ERR_PTR(-EINVAL);
}
+ pgtable->dom_region = data->plat_data->dom_data;
dev_info(data->dev, "%s create pgtable done\n", __func__);
@@ -470,8 +477,10 @@ static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
/* Update our support page sizes bitmap */
dom->domain.pgsize_bitmap = pgtable->cfg.pgsize_bitmap;
- dom->domain.geometry.aperture_start = 0;
- dom->domain.geometry.aperture_end = DMA_BIT_MASK(32);
+ dom->domain.geometry.aperture_start =
+ pgtable->dom_region->min_iova;
+ dom->domain.geometry.aperture_end =
+ pgtable->dom_region->max_iova;
dom->domain.geometry.force_aperture = true;
list_add_tail(&dom->list, &pgtable->m4u_dom_v2);
@@ -953,6 +962,7 @@ static const struct mtk_iommu_plat_data mt2712_data = {
.has_bclk = true,
.has_vld_pa_rng = true,
.dom_cnt = 1,
+ .dom_data = &single_dom,
.larbid_remap[0] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9},
.inv_sel_reg = REG_MMU_INV_SEL,
};
@@ -960,6 +970,7 @@ static const struct mtk_iommu_plat_data mt2712_data = {
static const struct mtk_iommu_plat_data mt6779_data = {
.m4u_plat = M4U_MT6779,
.dom_cnt = 1,
+ .dom_data = &single_dom,
.larbid_remap[0] = {0, 1, 2, 3, 5, 7, 10, 9},
/* vp6a, vp6b, mdla/core2, mdla/edmc*/
.larbid_remap[1] = {2, 0, 3, 1},
@@ -976,6 +987,7 @@ static const struct mtk_iommu_plat_data mt8173_data = {
.has_bclk = true,
.reset_axi = true,
.dom_cnt = 1,
+ .dom_data = &single_dom,
.larbid_remap[0] = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */
.inv_sel_reg = REG_MMU_INV_SEL,
};
@@ -984,6 +996,7 @@ static const struct mtk_iommu_plat_data mt8183_data = {
.m4u_plat = M4U_MT8183,
.reset_axi = true,
.dom_cnt = 1,
+ .dom_data = &single_dom,
.larbid_remap[0] = {0, 4, 5, 6, 7, 2, 3, 1},
.inv_sel_reg = REG_MMU_INV_SEL,
};
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 3a1c79222d09..a38b26018abe 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -36,6 +36,22 @@ enum mtk_iommu_plat {
M4U_MT8183,
};
+/*
+ * reserved IOVA Domain for IOMMU users of HW limitation.
+ */
+
+/*
+ * struct mtk_domain_data: domain configuration
+ * @min_iova: Start address of iova
+ * @max_iova: End address of iova
+ * Note: one user can only belong to one domain
+ */
+
+struct mtk_domain_data {
+ dma_addr_t min_iova;
+ dma_addr_t max_iova;
+};
+
struct mtk_iommu_plat_data {
enum mtk_iommu_plat m4u_plat;
bool has_4gb_mode;
@@ -51,6 +67,7 @@ struct mtk_iommu_plat_data {
u32 m4u1_mask;
u32 inv_sel_reg;
unsigned char larbid_remap[2][MTK_LARB_NR_MAX];
+ const struct mtk_domain_data *dom_data;
};
struct mtk_iommu_domain;
--
2.18.0
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https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v2 15/19] iommu/mediatek: Remove the usage of m4u_dom variable
2020-01-05 10:45 [PATCH v2 00/19] MT6779 IOMMU SUPPORT Chao Hao
` (13 preceding siblings ...)
2020-01-05 10:45 ` [PATCH v2 14/19] iommu/mediatek: Add mtk_domain_data structure Chao Hao
@ 2020-01-05 10:45 ` Chao Hao
2020-01-05 10:45 ` [PATCH v2 16/19] iommu/mediatek: Remove mtk_iommu_get_m4u_data api Chao Hao
` (3 subsequent siblings)
18 siblings, 0 replies; 22+ messages in thread
From: Chao Hao @ 2020-01-05 10:45 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger
Cc: Anan Sun, devicetree, Jun Yan, wsd_upstream, linux-kernel,
Chao Hao, iommu, linux-mediatek, Cui Zhang, linux-arm-kernel
This patch will remove the usage of the m4u_dom variable.
We have already redefined mtk_iommu_domain structure and it
includes iommu_domain, so m4u_dom variable will not be used.
Signed-off-by: Chao Hao <chao.hao@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 27 ++++++++++++++++++++-------
1 file changed, 20 insertions(+), 7 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index b1ce0a2df583..bfb1831afae9 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -107,6 +107,7 @@
* Get the local arbiter ID and the portid within the larb arbiter
* from mtk_m4u_id which is defined by MTK_M4U_ID.
*/
+#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port))
#define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0xf)
#define MTK_M4U_TO_PORT(id) ((id) & 0x1f)
@@ -199,6 +200,22 @@ static u32 mtk_iommu_get_domain_id(struct device *dev)
return get_domain_id(data, portid);
}
+static struct iommu_domain *_get_mtk_domain(struct mtk_iommu_data *data,
+ u32 larbid, u32 portid)
+{
+ u32 domain_id;
+ u32 port_mask = MTK_M4U_ID(larbid, portid);
+ struct mtk_iommu_domain *dom;
+
+ domain_id = get_domain_id(data, port_mask);
+
+ list_for_each_entry(dom, &data->pgtable->m4u_dom_v2, list) {
+ if (dom->id == domain_id)
+ return &dom->domain;
+ }
+ return NULL;
+}
+
static struct mtk_iommu_domain *get_mtk_domain(struct device *dev)
{
struct mtk_iommu_data *data = dev->iommu_fwspec->iommu_priv;
@@ -301,7 +318,7 @@ static const struct iommu_flush_ops mtk_iommu_flush_ops = {
static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
{
struct mtk_iommu_data *data = dev_id;
- struct mtk_iommu_domain *dom = data->m4u_dom;
+ struct iommu_domain *domain;
u32 int_state, regval, fault_iova, fault_pa;
unsigned int fault_larb, fault_port, sub_comm = 0;
bool layer, write;
@@ -336,7 +353,8 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
fault_larb = data->plat_data->larbid_remap[data->m4u_id][fault_larb];
- if (report_iommu_fault(&dom->domain, data->dev, fault_iova,
+ domain = _get_mtk_domain(data, fault_larb, fault_port);
+ if (report_iommu_fault(domain, data->dev, fault_iova,
write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) {
dev_err_ratelimited(
data->dev,
@@ -506,16 +524,11 @@ static void mtk_iommu_domain_free(struct iommu_domain *domain)
static int mtk_iommu_attach_device(struct iommu_domain *domain,
struct device *dev)
{
- struct mtk_iommu_domain *dom = to_mtk_domain(domain);
struct mtk_iommu_data *data = dev_iommu_fwspec_get(dev)->iommu_priv;
if (!data)
return -ENODEV;
- /* Update the pgtable base address register of the M4U HW */
- if (!data->m4u_dom)
- data->m4u_dom = dom;
-
mtk_iommu_config(data, dev, true);
return 0;
}
--
2.18.0
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v2 16/19] iommu/mediatek: Remove mtk_iommu_get_m4u_data api
2020-01-05 10:45 [PATCH v2 00/19] MT6779 IOMMU SUPPORT Chao Hao
` (14 preceding siblings ...)
2020-01-05 10:45 ` [PATCH v2 15/19] iommu/mediatek: Remove the usage of m4u_dom variable Chao Hao
@ 2020-01-05 10:45 ` Chao Hao
2020-01-05 10:45 ` [PATCH v2 17/19] iommu/mediatek: Add iova reserved function Chao Hao
` (2 subsequent siblings)
18 siblings, 0 replies; 22+ messages in thread
From: Chao Hao @ 2020-01-05 10:45 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger
Cc: Anan Sun, devicetree, Jun Yan, wsd_upstream, linux-kernel,
Chao Hao, iommu, linux-mediatek, Cui Zhang, linux-arm-kernel
Based on previous modifications in the patchset, A mtk_iommu_data
structure represent a iommu, we will add mtk_iommu_data to mtk_iommu_domain
to show the iommu which mtk_iommu_domain belongs to, so we can get
mtk_iommu_data by mtk_iommu_domain, don't use to "mtk_iommu_get_m4u_data"
any more.
Besides, there is a small SW adjustment, we will move alloc iommu_group
into "create_iommu_group"
Signed-off-by: Chao Hao <chao.hao@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 74 +++++++++++++++++++--------------------
1 file changed, 37 insertions(+), 37 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index bfb1831afae9..9a7f2a388e3e 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -115,6 +115,7 @@ struct mtk_iommu_domain {
u32 id;
struct iommu_domain domain;
struct iommu_group *group;
+ struct mtk_iommu_data *data;
struct list_head list;
};
@@ -162,23 +163,6 @@ static LIST_HEAD(m4ulist); /* List all the M4U HWs */
#define for_each_m4u(data) list_for_each_entry(data, &m4ulist, list)
-/*
- * There may be 1 or 2 M4U HWs, But we always expect they are in the same domain
- * for the performance.
- *
- * Here always return the mtk_iommu_data of the first probed M4U where the
- * iommu domain information is recorded.
- */
-static struct mtk_iommu_data *mtk_iommu_get_m4u_data(void)
-{
- struct mtk_iommu_data *data;
-
- for_each_m4u(data)
- return data;
-
- return NULL;
-}
-
static u32 get_domain_id(struct mtk_iommu_data *data, u32 portid)
{
u32 dom_id = 0;
@@ -397,6 +381,27 @@ static void mtk_iommu_config(struct mtk_iommu_data *data,
}
}
+static struct iommu_group *create_iommu_group(struct mtk_iommu_data *data,
+ struct device *dev)
+{
+ struct mtk_iommu_pgtable *pgtable = mtk_iommu_get_pgtable();
+
+ /* Prepare for allocate mtk_iommu_domain */
+ data->m4u_group = mtk_iommu_get_group(dev);
+ if (!data->m4u_group) {
+ data->m4u_group = iommu_group_alloc();
+ if (IS_ERR(data->m4u_group))
+ dev_err(dev, "Failed to allocate M4U IOMMU group\n");
+ } else {
+ iommu_group_ref_get(data->m4u_group);
+ }
+
+ /* save the latest init device */
+ pgtable->init_dev = dev;
+
+ return data->m4u_group;
+}
+
static struct mtk_iommu_pgtable *create_pgtable(struct mtk_iommu_data *data)
{
struct mtk_iommu_pgtable *pgtable;
@@ -462,7 +467,7 @@ static int mtk_iommu_attach_pgtable(struct mtk_iommu_data *data,
static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
{
struct mtk_iommu_pgtable *pgtable = mtk_iommu_get_pgtable();
- struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
+ struct mtk_iommu_data *data;
struct mtk_iommu_domain *dom;
struct device *dev;
@@ -471,6 +476,7 @@ static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
if (pgtable) {
dev = pgtable->init_dev;
+ data = dev_iommu_fwspec_get(dev)->iommu_priv;
if (!data->m4u_group) {
pr_err("%s, find m4u_group failed\n", __func__);
return NULL;
@@ -491,6 +497,7 @@ static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
if (dom->id >= data->plat_data->dom_cnt)
goto put_dma_cookie;
+ dom->data = data;
dom->group = data->m4u_group;
/* Update our support page sizes bitmap */
dom->domain.pgsize_bitmap = pgtable->cfg.pgsize_bitmap;
@@ -548,7 +555,8 @@ static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
phys_addr_t paddr, size_t size, int prot, gfp_t gfp)
{
struct mtk_iommu_pgtable *pgtable = mtk_iommu_get_pgtable();
- struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
+ struct mtk_iommu_domain *dom = to_mtk_domain(domain);
+ struct mtk_iommu_data *data = dom->data;
/* The "4GB mode" M4U physically can not use the lower remap of Dram. */
if (data->enable_4GB)
@@ -569,27 +577,30 @@ static size_t mtk_iommu_unmap(struct iommu_domain *domain,
static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain)
{
- mtk_iommu_tlb_flush_all(mtk_iommu_get_m4u_data());
+ struct mtk_iommu_domain *dom = to_mtk_domain(domain);
+
+ mtk_iommu_tlb_flush_all(dom->data);
}
static void mtk_iommu_iotlb_sync(struct iommu_domain *domain,
struct iommu_iotlb_gather *gather)
{
- struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
+ struct mtk_iommu_domain *dom = to_mtk_domain(domain);
size_t length = gather->end - gather->start;
if (gather->start == ULONG_MAX)
return;
mtk_iommu_tlb_flush_range_sync(gather->start, length, gather->pgsize,
- data);
+ dom->data);
}
static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
dma_addr_t iova)
{
struct mtk_iommu_pgtable *pgtable = mtk_iommu_get_pgtable();
- struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
+ struct mtk_iommu_domain *dom = to_mtk_domain(domain);
+ struct mtk_iommu_data *data = dom->data;
phys_addr_t pa;
pa = pgtable->iop->iova_to_phys(pgtable->iop, iova);
@@ -636,7 +647,7 @@ static void mtk_iommu_remove_device(struct device *dev)
static struct iommu_group *mtk_iommu_device_group(struct device *dev)
{
- struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
+ struct mtk_iommu_data *data = dev->iommu_fwspec->iommu_priv;
struct mtk_iommu_pgtable *pgtable;
int ret = 0;
@@ -652,20 +663,9 @@ static struct iommu_group *mtk_iommu_device_group(struct device *dev)
}
}
- /* All the client devices are in the same m4u iommu-group */
- data->m4u_group = mtk_iommu_get_group(dev);
- if (!data->m4u_group) {
- data->m4u_group = iommu_group_alloc();
- if (IS_ERR(data->m4u_group))
- dev_err(dev, "Failed to allocate M4U IOMMU group\n");
- } else {
- iommu_group_ref_get(data->m4u_group);
- }
+ dev_info(data->dev, "%s, init data:%d\n", __func__, data->m4u_id);
- /* save the latest init device */
- pgtable->init_dev = dev;
-
- return data->m4u_group;
+ return create_iommu_group(data, dev);
}
static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
--
2.18.0
_______________________________________________
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iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v2 17/19] iommu/mediatek: Add iova reserved function
2020-01-05 10:45 [PATCH v2 00/19] MT6779 IOMMU SUPPORT Chao Hao
` (15 preceding siblings ...)
2020-01-05 10:45 ` [PATCH v2 16/19] iommu/mediatek: Remove mtk_iommu_get_m4u_data api Chao Hao
@ 2020-01-05 10:45 ` Chao Hao
2020-01-05 10:45 ` [PATCH v2 18/19] iommu/mediatek: Change single domain to multiple domains Chao Hao
2020-01-05 10:45 ` [PATCH v2 19/19] iommu/mediatek: Add multiple mtk_iommu_domain support for mt6779 Chao Hao
18 siblings, 0 replies; 22+ messages in thread
From: Chao Hao @ 2020-01-05 10:45 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger
Cc: Anan Sun, devicetree, Jun Yan, wsd_upstream, linux-kernel,
Chao Hao, iommu, linux-mediatek, Cui Zhang, linux-arm-kernel
For multiple iommu_domains, we need to reserve some iova
regions, so we will add mtk_iommu_resv_iova_region structure.
It includes the start address and size of iova and iommu_resv_type.
Based on the function, we will realize multiple mtk_iommu_domains
Signed-off-by: Anan Sun <anan.sun@mediatek.com>
Signed-off-by: Chao Hao <chao.hao@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 47 +++++++++++++++++++++++++++++++++++++++
drivers/iommu/mtk_iommu.h | 12 ++++++++++
2 files changed, 59 insertions(+)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 9a7f2a388e3e..ac658fa16136 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -691,6 +691,51 @@ static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
return iommu_fwspec_add_ids(dev, args->args, 1);
}
+/* reserve/dir-map iova region */
+static void mtk_iommu_get_resv_regions(struct device *dev,
+ struct list_head *head)
+{
+ struct mtk_iommu_data *data = dev_iommu_fwspec_get(dev)->iommu_priv;
+ unsigned int i, total_cnt = data->plat_data->resv_cnt;
+ const struct mtk_iommu_resv_iova_region *resv_data;
+ struct iommu_resv_region *region;
+ unsigned long base = 0;
+ size_t size = 0;
+ int prot = IOMMU_WRITE | IOMMU_READ;
+
+ resv_data = data->plat_data->resv_region;
+
+ for (i = 0; i < total_cnt; i++) {
+ size = 0;
+ if (resv_data[i].iova_size) {
+ base = (unsigned long)resv_data[i].iova_base;
+ size = resv_data[i].iova_size;
+ }
+ if (!size)
+ continue;
+
+ region = iommu_alloc_resv_region(base, size, prot,
+ resv_data[i].type);
+ if (!region)
+ return;
+
+ list_add_tail(®ion->list, head);
+
+ dev_dbg(data->dev, "%s iova 0x%x ~ 0x%x\n",
+ (resv_data[i].type == IOMMU_RESV_DIRECT) ? "dm" : "rsv",
+ (unsigned int)base, (unsigned int)(base + size - 1));
+ }
+}
+
+static void mtk_iommu_put_resv_regions(struct device *dev,
+ struct list_head *head)
+{
+ struct iommu_resv_region *entry, *next;
+
+ list_for_each_entry_safe(entry, next, head, list)
+ kfree(entry);
+}
+
static const struct iommu_ops mtk_iommu_ops = {
.domain_alloc = mtk_iommu_domain_alloc,
.domain_free = mtk_iommu_domain_free,
@@ -705,6 +750,8 @@ static const struct iommu_ops mtk_iommu_ops = {
.remove_device = mtk_iommu_remove_device,
.device_group = mtk_iommu_device_group,
.of_xlate = mtk_iommu_of_xlate,
+ .get_resv_regions = mtk_iommu_get_resv_regions,
+ .put_resv_regions = mtk_iommu_put_resv_regions,
.pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M,
};
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index a38b26018abe..7f4d498ec5f6 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -36,6 +36,12 @@ enum mtk_iommu_plat {
M4U_MT8183,
};
+struct mtk_iommu_resv_iova_region {
+ dma_addr_t iova_base;
+ size_t iova_size;
+ enum iommu_resv_type type;
+};
+
/*
* reserved IOVA Domain for IOMMU users of HW limitation.
*/
@@ -68,6 +74,12 @@ struct mtk_iommu_plat_data {
u32 inv_sel_reg;
unsigned char larbid_remap[2][MTK_LARB_NR_MAX];
const struct mtk_domain_data *dom_data;
+ /*
+ * reserve/dir-mapping iova region data
+ * todo: for different reserve needs on multiple iommu domains
+ */
+ const unsigned int resv_cnt;
+ const struct mtk_iommu_resv_iova_region *resv_region;
};
struct mtk_iommu_domain;
--
2.18.0
_______________________________________________
iommu mailing list
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v2 18/19] iommu/mediatek: Change single domain to multiple domains
2020-01-05 10:45 [PATCH v2 00/19] MT6779 IOMMU SUPPORT Chao Hao
` (16 preceding siblings ...)
2020-01-05 10:45 ` [PATCH v2 17/19] iommu/mediatek: Add iova reserved function Chao Hao
@ 2020-01-05 10:45 ` Chao Hao
2020-01-05 10:45 ` [PATCH v2 19/19] iommu/mediatek: Add multiple mtk_iommu_domain support for mt6779 Chao Hao
18 siblings, 0 replies; 22+ messages in thread
From: Chao Hao @ 2020-01-05 10:45 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger
Cc: Anan Sun, devicetree, Jun Yan, wsd_upstream, linux-kernel,
Chao Hao, iommu, linux-mediatek, Cui Zhang, linux-arm-kernel
Based on one mtk_iommu_domain, this patch supports multiple
mtk_iommu_domains to realize different iova regions.
Every module has one smi_larb port, so we can create different
mtk_iommu_domains by smi_larb port define. So we will add port_mask
variable to mtk_domain_data, if some modules need special iova regions,
they can write smi_larb port which corresponding to themselves to
post_mask variable and specify the start and end address of iova region.
The form of port_mask can use "MTK_M4U_ID(larb, port)", larb and port can
refer to "mtxxxx-larb-port.h(ex: mt6779-larb-port.h)" file.
The architecture diagram is as below:
mtk_iommu_pgtable
|
mtk_domain_data
|
-------------------------------------------------
| | |
mtk_iommu_domain1 mtk_iommu_domain2 mtk_iommu_domain3
Signed-off-by: Chao Hao <chao.hao@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 48 +++++++++++++++++++++++++++++++++------
drivers/iommu/mtk_iommu.h | 11 ++++++++-
2 files changed, 51 insertions(+), 8 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index ac658fa16136..ab09f435d437 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -124,6 +124,8 @@ struct mtk_iommu_pgtable {
struct io_pgtable_ops *iop;
struct device *init_dev;
struct list_head m4u_dom_v2;
+ spinlock_t domain_lock; /* lock for domain count */
+ u32 domain_count;
const struct mtk_domain_data *dom_region;
};
@@ -166,11 +168,15 @@ static LIST_HEAD(m4ulist); /* List all the M4U HWs */
static u32 get_domain_id(struct mtk_iommu_data *data, u32 portid)
{
u32 dom_id = 0;
- int i;
+ const struct mtk_domain_data *mtk_dom_array = data->plat_data->dom_data;
+ int i, j;
- /* only support one mtk_iommu_domain currently(dom_cnt = 1) */
- for (i = 0; i < data->plat_data->dom_cnt; i++)
- return i;
+ for (i = 0; i < data->plat_data->dom_cnt; i++) {
+ for (j = 0; j < MTK_MAX_PORT_NUM; j++) {
+ if (portid == mtk_dom_array[i].port_mask[j])
+ return i;
+ }
+ }
return dom_id;
}
@@ -410,6 +416,8 @@ static struct mtk_iommu_pgtable *create_pgtable(struct mtk_iommu_data *data)
if (!pgtable)
return ERR_PTR(-ENOMEM);
+ spin_lock_init(&pgtable->domain_lock);
+ pgtable->domain_count = 0;
INIT_LIST_HEAD(&pgtable->m4u_dom_v2);
pgtable->cfg = (struct io_pgtable_cfg) {
@@ -470,6 +478,7 @@ static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
struct mtk_iommu_data *data;
struct mtk_iommu_domain *dom;
struct device *dev;
+ unsigned long flags;
if (type != IOMMU_DOMAIN_DMA)
return NULL;
@@ -497,18 +506,34 @@ static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
if (dom->id >= data->plat_data->dom_cnt)
goto put_dma_cookie;
+ spin_lock_irqsave(&pgtable->domain_lock, flags);
+ if (pgtable->domain_count >= data->plat_data->dom_cnt) {
+ spin_unlock_irqrestore(&pgtable->domain_lock, flags);
+ dev_err(dev, "%s, too many domain, count=%u\n",
+ __func__, pgtable->domain_count);
+ goto put_dma_cookie;
+ }
+ pgtable->domain_count++;
+ spin_unlock_irqrestore(&pgtable->domain_lock, flags);
dom->data = data;
dom->group = data->m4u_group;
+
/* Update our support page sizes bitmap */
dom->domain.pgsize_bitmap = pgtable->cfg.pgsize_bitmap;
dom->domain.geometry.aperture_start =
- pgtable->dom_region->min_iova;
+ pgtable->dom_region[dom->id].min_iova;
dom->domain.geometry.aperture_end =
- pgtable->dom_region->max_iova;
+ pgtable->dom_region[dom->id].max_iova;
dom->domain.geometry.force_aperture = true;
list_add_tail(&dom->list, &pgtable->m4u_dom_v2);
+ dev_info(dev, "%s: dom_id:%u, start:%pa, end:%pa, dom_cnt:%u\n",
+ __func__, dom->id,
+ &dom->domain.geometry.aperture_start,
+ &dom->domain.geometry.aperture_end,
+ pgtable->domain_count);
+
return &dom->domain;
put_dma_cookie:
@@ -521,9 +546,17 @@ static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
static void mtk_iommu_domain_free(struct iommu_domain *domain)
{
struct mtk_iommu_pgtable *pgtable = mtk_iommu_get_pgtable();
+ unsigned long flags;
iommu_put_dma_cookie(domain);
kfree(to_mtk_domain(domain));
+ spin_lock_irqsave(&pgtable->domain_lock, flags);
+ pgtable->domain_count--;
+ if (pgtable->domain_count > 0) {
+ spin_unlock_irqrestore(&pgtable->domain_lock, flags);
+ return;
+ }
+ spin_unlock_irqrestore(&pgtable->domain_lock, flags);
free_io_pgtable_ops(pgtable->iop);
kfree(pgtable);
}
@@ -697,6 +730,7 @@ static void mtk_iommu_get_resv_regions(struct device *dev,
{
struct mtk_iommu_data *data = dev_iommu_fwspec_get(dev)->iommu_priv;
unsigned int i, total_cnt = data->plat_data->resv_cnt;
+ u32 dom_id = mtk_iommu_get_domain_id(dev);
const struct mtk_iommu_resv_iova_region *resv_data;
struct iommu_resv_region *region;
unsigned long base = 0;
@@ -711,7 +745,7 @@ static void mtk_iommu_get_resv_regions(struct device *dev,
base = (unsigned long)resv_data[i].iova_base;
size = resv_data[i].iova_size;
}
- if (!size)
+ if (!size || resv_data[i].dom_id != dom_id)
continue;
region = iommu_alloc_resv_region(base, size, prot,
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 7f4d498ec5f6..3f6236c0416e 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -37,6 +37,7 @@ enum mtk_iommu_plat {
};
struct mtk_iommu_resv_iova_region {
+ u32 dom_id;
dma_addr_t iova_base;
size_t iova_size;
enum iommu_resv_type type;
@@ -50,12 +51,20 @@ struct mtk_iommu_resv_iova_region {
* struct mtk_domain_data: domain configuration
* @min_iova: Start address of iova
* @max_iova: End address of iova
- * Note: one user can only belong to one domain
+ * @port_mask: User can specify mtk_iommu_domain by smi larb and port.
+ * Different mtk_iommu_domain have different iova space,
+ * port_mask is made up of larb_id and port_id.
+ * The format of larb and port can refer to mtxxxx-larb-port.h.
+ * bit[4:0] = port_id bit[11:5] = larb_id.
+ * Note: one user can only belong to one domain,
+ * the port mask is in unit of SMI larb.
*/
+#define MTK_MAX_PORT_NUM 5
struct mtk_domain_data {
dma_addr_t min_iova;
dma_addr_t max_iova;
+ u32 port_mask[MTK_MAX_PORT_NUM];
};
struct mtk_iommu_plat_data {
--
2.18.0
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v2 19/19] iommu/mediatek: Add multiple mtk_iommu_domain support for mt6779
2020-01-05 10:45 [PATCH v2 00/19] MT6779 IOMMU SUPPORT Chao Hao
` (17 preceding siblings ...)
2020-01-05 10:45 ` [PATCH v2 18/19] iommu/mediatek: Change single domain to multiple domains Chao Hao
@ 2020-01-05 10:45 ` Chao Hao
18 siblings, 0 replies; 22+ messages in thread
From: Chao Hao @ 2020-01-05 10:45 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger
Cc: Anan Sun, devicetree, Jun Yan, wsd_upstream, linux-kernel,
Chao Hao, iommu, linux-mediatek, Cui Zhang, linux-arm-kernel
For mt6779, it need to support three mtk_iommu_domains, every
mtk_iommu_domain's iova space is different.
Three mtk_iommu_domains is as below:
1. Normal mtk_iommu_domain exclude 0x4000_0000~0x47ff_ffff and
0x7da0_0000~7fbf_ffff.
2. CCU mtk_iommu_domain include 0x4000_0000~0x47ff_ffff.
3. VPU mtk_iommu_domain 0x7da0_0000~0x7fbf_ffff.
Signed-off-by: Chao Hao <chao.hao@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 45 +++++++++++++++++++++++++++++++++++++--
1 file changed, 43 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index ab09f435d437..d56254883541 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -134,6 +134,30 @@ const struct mtk_domain_data single_dom = {
.max_iova = DMA_BIT_MASK(32)
};
+/*
+ * related file: mt6779-larb-port.h
+ */
+const struct mtk_domain_data mt6779_multi_dom[] = {
+ /* normal domain */
+ {
+ .min_iova = 0x0,
+ .max_iova = DMA_BIT_MASK(32),
+ },
+ /* ccu domain */
+ {
+ .min_iova = 0x40000000,
+ .max_iova = 0x48000000 - 1,
+ .port_mask = {MTK_M4U_ID(9, 21), MTK_M4U_ID(9, 22),
+ MTK_M4U_ID(12, 0), MTK_M4U_ID(12, 1)}
+ },
+ /* vpu domain */
+ {
+ .min_iova = 0x7da00000,
+ .max_iova = 0x7fc00000 - 1,
+ .port_mask = {MTK_M4U_ID(13, 0)}
+ }
+};
+
static struct mtk_iommu_pgtable *share_pgtable;
static const struct iommu_ops mtk_iommu_ops;
@@ -1050,6 +1074,21 @@ static const struct dev_pm_ops mtk_iommu_pm_ops = {
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume)
};
+static const struct mtk_iommu_resv_iova_region mt6779_iommu_rsv_list[] = {
+ {
+ .dom_id = 0,
+ .iova_base = 0x40000000, /* CCU */
+ .iova_size = 0x8000000,
+ .type = IOMMU_RESV_RESERVED,
+ },
+ {
+ .dom_id = 0,
+ .iova_base = 0x7da00000, /* VPU/MDLA */
+ .iova_size = 0x2700000,
+ .type = IOMMU_RESV_RESERVED,
+ },
+};
+
static const struct mtk_iommu_plat_data mt2712_data = {
.m4u_plat = M4U_MT2712,
.has_4gb_mode = true,
@@ -1063,8 +1102,10 @@ static const struct mtk_iommu_plat_data mt2712_data = {
static const struct mtk_iommu_plat_data mt6779_data = {
.m4u_plat = M4U_MT6779,
- .dom_cnt = 1,
- .dom_data = &single_dom,
+ .resv_cnt = ARRAY_SIZE(mt6779_iommu_rsv_list),
+ .resv_region = mt6779_iommu_rsv_list,
+ .dom_cnt = ARRAY_SIZE(mt6779_multi_dom),
+ .dom_data = mt6779_multi_dom,
.larbid_remap[0] = {0, 1, 2, 3, 5, 7, 10, 9},
/* vp6a, vp6b, mdla/core2, mdla/edmc*/
.larbid_remap[1] = {2, 0, 3, 1},
--
2.18.0
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https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 22+ messages in thread