[PATCH 0/5] iommu/vt-d: Several minor adjustments

[PATCH 0/5] iommu/vt-d: Several minor adjustments

[Lu Baolu]

Hi,

This series includes some adjustments for Intel IOMMU which I have
been suggested. Please help to review.

- Enable Intel IOMMU scalable mode by default
- Preset A/D bits for user space DMA usage
- Disallow SVA if devices don't support 64-bit address
- Allow devices to have more than 32 outstanding PRs

Best regards,
baolu

Lu Baolu (5):
  iommu/vt-d: Refactor Kconfig a bit
  iommu/vt-d: Enable Intel IOMMU scalable mode by default
  iommu/vt-d: Preset A/D bits for user space DMA usage
  iommu/vt-d: Disallow SVA if devices don't support 64-bit address
  iommu/vt-d: Allow devices to have more than 32 outstanding PRs

 .../admin-guide/kernel-parameters.txt         | 11 +++---
 include/linux/intel-svm.h                     |  5 +++
 drivers/iommu/intel/iommu.c                   | 34 ++++++++-----------
 drivers/iommu/intel/svm.c                     |  4 ---
 drivers/iommu/intel/Kconfig                   | 19 ++++++-----
 5 files changed, 36 insertions(+), 37 deletions(-)

-- 
2.25.1

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[PATCH 1/5] iommu/vt-d: Refactor Kconfig a bit

[Lu Baolu]

Put all sub-options inside a "if INTEL_IOMMU" so that they don't need to
always depend on INTEL_IOMMU. Use IS_ENABLED() instead of #ifdef as well.

Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
---
 drivers/iommu/intel/iommu.c | 13 ++-----------
 drivers/iommu/intel/Kconfig | 18 ++++++++++--------
 2 files changed, 12 insertions(+), 19 deletions(-)

diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index 8c116fe071a2..0440a1850b63 100644
--- a/drivers/iommu/intel/iommu.c
+++ b/drivers/iommu/intel/iommu.c
@@ -327,17 +327,8 @@ static int intel_iommu_attach_device(struct iommu_domain *domain,
 static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
 					    dma_addr_t iova);
 
-#ifdef CONFIG_INTEL_IOMMU_DEFAULT_ON
-int dmar_disabled = 0;
-#else
-int dmar_disabled = 1;
-#endif /* CONFIG_INTEL_IOMMU_DEFAULT_ON */
-
-#ifdef CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON
-int intel_iommu_sm = 1;
-#else
-int intel_iommu_sm;
-#endif /* CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON */
+int dmar_disabled = !IS_ENABLED(CONFIG_INTEL_IOMMU_DEFAULT_ON);
+int intel_iommu_sm = IS_ENABLED(CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON);
 
 int intel_iommu_enabled = 0;
 EXPORT_SYMBOL_GPL(intel_iommu_enabled);
diff --git a/drivers/iommu/intel/Kconfig b/drivers/iommu/intel/Kconfig
index 43ebd8af11c5..c1a92c3049d0 100644
--- a/drivers/iommu/intel/Kconfig
+++ b/drivers/iommu/intel/Kconfig
@@ -25,9 +25,11 @@ config INTEL_IOMMU
 	  and include PCI device scope covered by these DMA
 	  remapping devices.
 
+if INTEL_IOMMU
+
 config INTEL_IOMMU_DEBUGFS
 	bool "Export Intel IOMMU internals in Debugfs"
-	depends on INTEL_IOMMU && IOMMU_DEBUGFS
+	depends on IOMMU_DEBUGFS
 	select DMAR_PERF
 	help
 	  !!!WARNING!!!
@@ -41,7 +43,7 @@ config INTEL_IOMMU_DEBUGFS
 
 config INTEL_IOMMU_SVM
 	bool "Support for Shared Virtual Memory with Intel IOMMU"
-	depends on INTEL_IOMMU && X86_64
+	depends on X86_64
 	select PCI_PASID
 	select PCI_PRI
 	select MMU_NOTIFIER
@@ -53,9 +55,8 @@ config INTEL_IOMMU_SVM
 	  means of a Process Address Space ID (PASID).
 
 config INTEL_IOMMU_DEFAULT_ON
-	def_bool y
-	prompt "Enable Intel DMA Remapping Devices by default"
-	depends on INTEL_IOMMU
+	bool "Enable Intel DMA Remapping Devices by default"
+	default y
 	help
 	  Selecting this option will enable a DMAR device at boot time if
 	  one is found. If this option is not selected, DMAR support can
@@ -63,7 +64,7 @@ config INTEL_IOMMU_DEFAULT_ON
 
 config INTEL_IOMMU_BROKEN_GFX_WA
 	bool "Workaround broken graphics drivers (going away soon)"
-	depends on INTEL_IOMMU && BROKEN && X86
+	depends on BROKEN && X86
 	help
 	  Current Graphics drivers tend to use physical address
 	  for DMA and avoid using DMA APIs. Setting this config
@@ -74,7 +75,7 @@ config INTEL_IOMMU_BROKEN_GFX_WA
 
 config INTEL_IOMMU_FLOPPY_WA
 	def_bool y
-	depends on INTEL_IOMMU && X86
+	depends on X86
 	help
 	  Floppy disk drivers are known to bypass DMA API calls
 	  thereby failing to work when IOMMU is enabled. This
@@ -83,7 +84,6 @@ config INTEL_IOMMU_FLOPPY_WA
 
 config INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON
 	bool "Enable Intel IOMMU scalable mode by default"
-	depends on INTEL_IOMMU
 	help
 	  Selecting this option will enable by default the scalable mode if
 	  hardware presents the capability. The scalable mode is defined in
@@ -92,3 +92,5 @@ config INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON
 	  is not selected, scalable mode support could also be enabled by
 	  passing intel_iommu=sm_on to the kernel. If not sure, please use
 	  the default value.
+
+endif # INTEL_IOMMU
-- 
2.25.1

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[PATCH 2/5] iommu/vt-d: Enable Intel IOMMU scalable mode by default

[Lu Baolu]

The commit 8950dcd83ae7d ("iommu/vt-d: Leave scalable mode default off")
leaves the scalable mode default off and end users could turn it on with
"intel_iommu=sm_on". Using the Intel IOMMU scalable mode for kernel DMA,
user-level device access and Shared Virtual Address have been enabled.
This enables the scalable mode by default if the hardware advertises the
support and adds kernel options of "intel_iommu=sm_on/sm_off" for end
users to configure it through the kernel parameters.

Suggested-by: Ashok Raj <ashok.raj@intel.com>
Suggested-by: Sanjay Kumar <sanjay.k.kumar@intel.com>
Cc: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
---
 Documentation/admin-guide/kernel-parameters.txt | 11 ++++++-----
 drivers/iommu/intel/iommu.c                     |  5 ++++-
 drivers/iommu/intel/Kconfig                     |  1 +
 3 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index bdb22006f713..388eaf40fbe5 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -1951,11 +1951,12 @@
 			By default, super page will be supported if Intel IOMMU
 			has the capability. With this option, super page will
 			not be supported.
-		sm_on [Default Off]
-			By default, scalable mode will be disabled even if the
-			hardware advertises that it has support for the scalable
-			mode translation. With this option set, scalable mode
-			will be used on hardware which claims to support it.
+		sm_on
+			Enable the Intel IOMMU scalable mode if the hardware
+			advertises that it has support for the scalable mode
+			translation.
+		sm_off
+			Disallow use of the Intel IOMMU scalable mode.
 		tboot_noforce [Default Off]
 			Do not force the Intel IOMMU enabled under tboot.
 			By default, tboot will force Intel IOMMU on, which
diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index 0440a1850b63..1131b8efb050 100644
--- a/drivers/iommu/intel/iommu.c
+++ b/drivers/iommu/intel/iommu.c
@@ -433,8 +433,11 @@ static int __init intel_iommu_setup(char *str)
 			pr_info("Disable supported super page\n");
 			intel_iommu_superpage = 0;
 		} else if (!strncmp(str, "sm_on", 5)) {
-			pr_info("Intel-IOMMU: scalable mode supported\n");
+			pr_info("Enable scalable mode if hardware supports\n");
 			intel_iommu_sm = 1;
+		} else if (!strncmp(str, "sm_off", 6)) {
+			pr_info("Scalable mode is disallowed\n");
+			intel_iommu_sm = 0;
 		} else if (!strncmp(str, "tboot_noforce", 13)) {
 			pr_info("Intel-IOMMU: not forcing on after tboot. This could expose security risk for tboot\n");
 			intel_iommu_tboot_noforce = 1;
diff --git a/drivers/iommu/intel/Kconfig b/drivers/iommu/intel/Kconfig
index c1a92c3049d0..0ddb77115be7 100644
--- a/drivers/iommu/intel/Kconfig
+++ b/drivers/iommu/intel/Kconfig
@@ -84,6 +84,7 @@ config INTEL_IOMMU_FLOPPY_WA
 
 config INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON
 	bool "Enable Intel IOMMU scalable mode by default"
+	default y
 	help
 	  Selecting this option will enable by default the scalable mode if
 	  hardware presents the capability. The scalable mode is defined in
-- 
2.25.1

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[PATCH 3/5] iommu/vt-d: Preset A/D bits for user space DMA usage

[Lu Baolu]

We preset the access and dirty bits for IOVA over first level usage only
for the kernel DMA (i.e., when domain type is IOMMU_DOMAIN_DMA). We should
also preset the FL A/D for user space DMA usage. The idea is that even the
user space A/D bit memory write is unnecessary. We should avoid it to
minimize the overhead.

Suggested-by: Sanjay Kumar <sanjay.k.kumar@intel.com>
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
---
 drivers/iommu/intel/iommu.c | 10 +++-------
 1 file changed, 3 insertions(+), 7 deletions(-)

diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index 1131b8efb050..f45c80ce2381 100644
--- a/drivers/iommu/intel/iommu.c
+++ b/drivers/iommu/intel/iommu.c
@@ -2339,13 +2339,9 @@ __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
 	attr = prot & (DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP);
 	attr |= DMA_FL_PTE_PRESENT;
 	if (domain_use_first_level(domain)) {
-		attr |= DMA_FL_PTE_XD | DMA_FL_PTE_US;
-
-		if (domain->domain.type == IOMMU_DOMAIN_DMA) {
-			attr |= DMA_FL_PTE_ACCESS;
-			if (prot & DMA_PTE_WRITE)
-				attr |= DMA_FL_PTE_DIRTY;
-		}
+		attr |= DMA_FL_PTE_XD | DMA_FL_PTE_US | DMA_FL_PTE_ACCESS;
+		if (prot & DMA_PTE_WRITE)
+			attr |= DMA_FL_PTE_DIRTY;
 	}
 
 	pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | attr;
-- 
2.25.1

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[PATCH 4/5] iommu/vt-d: Disallow SVA if devices don't support 64-bit address

[Lu Baolu]

When the device and CPU share an address space (such as SVA), the device
must support the same addressing capability as the CPU. The CPU does not
consider the addressing ability of any device when managing the page table
of a process, so the device must have enough addressing ability to bind
the page table of the process.

Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
---
 drivers/iommu/intel/iommu.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index f45c80ce2381..f3cca1dd384d 100644
--- a/drivers/iommu/intel/iommu.c
+++ b/drivers/iommu/intel/iommu.c
@@ -5372,6 +5372,9 @@ static int intel_iommu_enable_sva(struct device *dev)
 	if (!(iommu->flags & VTD_FLAG_SVM_CAPABLE))
 		return -ENODEV;
 
+	if (!dev->dma_mask || *dev->dma_mask != DMA_BIT_MASK(64))
+		return -ENODEV;
+
 	if (intel_iommu_enable_pasid(iommu, dev))
 		return -ENODEV;
 
-- 
2.25.1

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Re: [PATCH 4/5] iommu/vt-d: Disallow SVA if devices don't support 64-bit address

[Robin Murphy]

On 2021-07-20 02:38, Lu Baolu wrote:
> When the device and CPU share an address space (such as SVA), the device
> must support the same addressing capability as the CPU. The CPU does not
> consider the addressing ability of any device when managing the page table
> of a process, so the device must have enough addressing ability to bind
> the page table of the process.
> 
> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
> ---
>   drivers/iommu/intel/iommu.c | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
> index f45c80ce2381..f3cca1dd384d 100644
> --- a/drivers/iommu/intel/iommu.c
> +++ b/drivers/iommu/intel/iommu.c
> @@ -5372,6 +5372,9 @@ static int intel_iommu_enable_sva(struct device *dev)
>   	if (!(iommu->flags & VTD_FLAG_SVM_CAPABLE))
>   		return -ENODEV;
>   
> +	if (!dev->dma_mask || *dev->dma_mask != DMA_BIT_MASK(64))

Careful - VFIO doesn't set DMA masks (since it doesn't use the DMA API), 
so this appears to be relying on another driver having bound previously, 
otherwise the mask would still be the default 32-bit one from 
pci_setup_device(). I'm not sure that's an entirely robust assumption.

Robin.

> +		return -ENODEV;
> +
>   	if (intel_iommu_enable_pasid(iommu, dev))
>   		return -ENODEV;
>   
> 
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Re: [PATCH 4/5] iommu/vt-d: Disallow SVA if devices don't support 64-bit address

[Lu Baolu]

Hi Robin,

Thanks a lot for reviewing my patch!

On 7/20/21 5:27 PM, Robin Murphy wrote:
> On 2021-07-20 02:38, Lu Baolu wrote:
>> When the device and CPU share an address space (such as SVA), the device
>> must support the same addressing capability as the CPU. The CPU does not
>> consider the addressing ability of any device when managing the page 
>> table
>> of a process, so the device must have enough addressing ability to bind
>> the page table of the process.
>>
>> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
>> ---
>>   drivers/iommu/intel/iommu.c | 3 +++
>>   1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
>> index f45c80ce2381..f3cca1dd384d 100644
>> --- a/drivers/iommu/intel/iommu.c
>> +++ b/drivers/iommu/intel/iommu.c
>> @@ -5372,6 +5372,9 @@ static int intel_iommu_enable_sva(struct device 
>> *dev)
>>       if (!(iommu->flags & VTD_FLAG_SVM_CAPABLE))
>>           return -ENODEV;
>> +    if (!dev->dma_mask || *dev->dma_mask != DMA_BIT_MASK(64))
> 
> Careful - VFIO doesn't set DMA masks (since it doesn't use the DMA API),

SVA doesn't work through the VFIO framework.

> so this appears to be relying on another driver having bound previously,

Yes. You are right.

> otherwise the mask would still be the default 32-bit one from 
> pci_setup_device(). I'm not sure that's an entirely robust assumption.

Currently SVA implementation always requires a native kernel driver. The
assumption is that the drivers should check and set 64-bit addressing
capability before calling iommu_sva_xxx() APIs.

>
> Robin.
> 
>> +        return -ENODEV;
>> +
>>       if (intel_iommu_enable_pasid(iommu, dev))
>>           return -ENODEV;
>>

Best regards,
baolu
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Re: [PATCH 4/5] iommu/vt-d: Disallow SVA if devices don't support 64-bit address

[Robin Murphy]

On 2021-07-21 02:50, Lu Baolu wrote:
> Hi Robin,
> 
> Thanks a lot for reviewing my patch!
> 
> On 7/20/21 5:27 PM, Robin Murphy wrote:
>> On 2021-07-20 02:38, Lu Baolu wrote:
>>> When the device and CPU share an address space (such as SVA), the device
>>> must support the same addressing capability as the CPU. The CPU does not
>>> consider the addressing ability of any device when managing the page 
>>> table
>>> of a process, so the device must have enough addressing ability to bind
>>> the page table of the process.
>>>
>>> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
>>> ---
>>>   drivers/iommu/intel/iommu.c | 3 +++
>>>   1 file changed, 3 insertions(+)
>>>
>>> diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
>>> index f45c80ce2381..f3cca1dd384d 100644
>>> --- a/drivers/iommu/intel/iommu.c
>>> +++ b/drivers/iommu/intel/iommu.c
>>> @@ -5372,6 +5372,9 @@ static int intel_iommu_enable_sva(struct device 
>>> *dev)
>>>       if (!(iommu->flags & VTD_FLAG_SVM_CAPABLE))
>>>           return -ENODEV;
>>> +    if (!dev->dma_mask || *dev->dma_mask != DMA_BIT_MASK(64))
>>
>> Careful - VFIO doesn't set DMA masks (since it doesn't use the DMA API),
> 
> SVA doesn't work through the VFIO framework.

Did anyone say it does? My point is that, as far as I understand, the 
SVA UAPI is very much intended to work *with* VFIO, and even if the 
finer details are still mired in the /dev/ioasid discussion today we 
should definitely expect to see VFIO-like use-cases at some point. I 
certainly don't see why any of the guest SVA stuff exists already if not 
for VFIO-assigned devices?

>> so this appears to be relying on another driver having bound previously,
> 
> Yes. You are right.
> 
>> otherwise the mask would still be the default 32-bit one from 
>> pci_setup_device(). I'm not sure that's an entirely robust assumption.
> 
> Currently SVA implementation always requires a native kernel driver. The
> assumption is that the drivers should check and set 64-bit addressing
> capability before calling iommu_sva_xxx() APIs.

...and given that that is not a documented requirement, and certainly 
not a technical one (even a self-contained kernel driver could choose to 
only use SVA contexts and not touch the DMA API), it's an inherently 
fragile assumption which I'm confident *will* be broken eventually :)

Robin.

>>> +        return -ENODEV;
>>> +
>>>       if (intel_iommu_enable_pasid(iommu, dev))
>>>           return -ENODEV;
>>>
> 
> Best regards,
> baolu
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Re: [PATCH 4/5] iommu/vt-d: Disallow SVA if devices don't support 64-bit address

[Lu Baolu]

On 2021/7/21 19:12, Robin Murphy wrote:
> On 2021-07-21 02:50, Lu Baolu wrote:
>> Hi Robin,
>>
>> Thanks a lot for reviewing my patch!
>>
>> On 7/20/21 5:27 PM, Robin Murphy wrote:
>>> On 2021-07-20 02:38, Lu Baolu wrote:
>>>> When the device and CPU share an address space (such as SVA), the 
>>>> device
>>>> must support the same addressing capability as the CPU. The CPU does 
>>>> not
>>>> consider the addressing ability of any device when managing the page 
>>>> table
>>>> of a process, so the device must have enough addressing ability to bind
>>>> the page table of the process.
>>>>
>>>> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
>>>> ---
>>>>   drivers/iommu/intel/iommu.c | 3 +++
>>>>   1 file changed, 3 insertions(+)
>>>>
>>>> diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
>>>> index f45c80ce2381..f3cca1dd384d 100644
>>>> --- a/drivers/iommu/intel/iommu.c
>>>> +++ b/drivers/iommu/intel/iommu.c
>>>> @@ -5372,6 +5372,9 @@ static int intel_iommu_enable_sva(struct 
>>>> device *dev)
>>>>       if (!(iommu->flags & VTD_FLAG_SVM_CAPABLE))
>>>>           return -ENODEV;
>>>> +    if (!dev->dma_mask || *dev->dma_mask != DMA_BIT_MASK(64))
>>>
>>> Careful - VFIO doesn't set DMA masks (since it doesn't use the DMA API),
>>
>> SVA doesn't work through the VFIO framework.
> 
> Did anyone say it does? My point is that, as far as I understand, the 
> SVA UAPI is very much intended to work *with* VFIO, and even if the 
> finer details are still mired in the /dev/ioasid discussion today we 
> should definitely expect to see VFIO-like use-cases at some point. I 
> certainly don't see why any of the guest SVA stuff exists already if not 
> for VFIO-assigned devices?

Agreed. From /dev/ioasid design point of view, it's possible to have
VFIO-like use case of SVA. Perhaps the device addressing capability
could be included in GET_DEV_INFO of /dev/ioasid UAPI.

> 
>>> so this appears to be relying on another driver having bound previously,
>>
>> Yes. You are right.
>>
>>> otherwise the mask would still be the default 32-bit one from 
>>> pci_setup_device(). I'm not sure that's an entirely robust assumption.
>>
>> Currently SVA implementation always requires a native kernel driver. The
>> assumption is that the drivers should check and set 64-bit addressing
>> capability before calling iommu_sva_xxx() APIs.
> 
> ...and given that that is not a documented requirement, and certainly 
> not a technical one (even a self-contained kernel driver could choose to 
> only use SVA contexts and not touch the DMA API), it's an inherently 
> fragile assumption which I'm confident *will* be broken eventually :)
> 

Fair enough. I will drop this patch.

Thanks a lot for the comments.

Best regards,
baolu

> Robin.
> 
>>>> +        return -ENODEV;
>>>> +
>>>>       if (intel_iommu_enable_pasid(iommu, dev))
>>>>           return -ENODEV;
>>>>
>>
>> Best regards,
>> baolu
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[PATCH 5/5] iommu/vt-d: Allow devices to have more than 32 outstanding PRs

[Lu Baolu]

The minimum per-IOMMU PRQ queue size is one 4K page, this is more entries
than the hardcoded limit of 32 in the current VT-d code. Some devices can
support up to 512 outstanding PRQs but underutilized by this limit of 32.
Although, 32 gives some rough fairness when multiple devices share the same
IOMMU PRQ queue, but far from optimal for customized use case. This extends
the per-IOMMU PRQ queue size to four 4K pages and let the devices have as
many outstanding page requests as they can.

Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
---
 include/linux/intel-svm.h   | 5 +++++
 drivers/iommu/intel/iommu.c | 3 ++-
 drivers/iommu/intel/svm.c   | 4 ----
 3 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/include/linux/intel-svm.h b/include/linux/intel-svm.h
index 10fa80eef13a..57cceecbe37f 100644
--- a/include/linux/intel-svm.h
+++ b/include/linux/intel-svm.h
@@ -14,6 +14,11 @@
 #define SVM_REQ_EXEC	(1<<1)
 #define SVM_REQ_PRIV	(1<<0)
 
+/* Page Request Queue depth */
+#define PRQ_ORDER	2
+#define PRQ_RING_MASK	((0x1000 << PRQ_ORDER) - 0x20)
+#define PRQ_DEPTH	((0x1000 << PRQ_ORDER) >> 5)
+
 /*
  * The SVM_FLAG_SUPERVISOR_MODE flag requests a PASID which can be used only
  * for access to kernel addresses. No IOTLB flushes are automatically done
diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index f3cca1dd384d..97d65839236c 100644
--- a/drivers/iommu/intel/iommu.c
+++ b/drivers/iommu/intel/iommu.c
@@ -33,6 +33,7 @@
 #include <linux/iommu.h>
 #include <linux/dma-iommu.h>
 #include <linux/intel-iommu.h>
+#include <linux/intel-svm.h>
 #include <linux/syscore_ops.h>
 #include <linux/tboot.h>
 #include <linux/dmi.h>
@@ -1542,7 +1543,7 @@ static void iommu_enable_dev_iotlb(struct device_domain_info *info)
 
 	if (info->pri_supported &&
 	    (info->pasid_enabled ? pci_prg_resp_pasid_required(pdev) : 1)  &&
-	    !pci_reset_pri(pdev) && !pci_enable_pri(pdev, 32))
+	    !pci_reset_pri(pdev) && !pci_enable_pri(pdev, PRQ_DEPTH))
 		info->pri_enabled = 1;
 #endif
 	if (info->ats_supported && pci_ats_page_aligned(pdev) &&
diff --git a/drivers/iommu/intel/svm.c b/drivers/iommu/intel/svm.c
index 9b0f22bc0514..813438a07b62 100644
--- a/drivers/iommu/intel/svm.c
+++ b/drivers/iommu/intel/svm.c
@@ -31,8 +31,6 @@ static irqreturn_t prq_event_thread(int irq, void *d);
 static void intel_svm_drain_prq(struct device *dev, u32 pasid);
 #define to_intel_svm_dev(handle) container_of(handle, struct intel_svm_dev, sva)
 
-#define PRQ_ORDER 0
-
 static DEFINE_XARRAY_ALLOC(pasid_private_array);
 static int pasid_private_add(ioasid_t pasid, void *priv)
 {
@@ -724,8 +722,6 @@ struct page_req_dsc {
 	u64 priv_data[2];
 };
 
-#define PRQ_RING_MASK	((0x1000 << PRQ_ORDER) - 0x20)
-
 static bool is_canonical_address(u64 addr)
 {
 	int shift = 64 - (__VIRTUAL_MASK_SHIFT + 1);
-- 
2.25.1

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