iommu.lists.linux-foundation.org archive mirror
 help / color / mirror / Atom feed
* [PATCH 1/2] iommu/amd: Use BIT/BIT_ULL macro to define bit fields
@ 2023-06-09  9:06 Vasant Hegde
  2023-06-09  9:06 ` [PATCH 2/2] iommu/amd: Remove extern from function prototypes Vasant Hegde
                   ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: Vasant Hegde @ 2023-06-09  9:06 UTC (permalink / raw)
  To: iommu, joro; +Cc: suravee.suthikulpanit, Vasant Hegde, Yazen Ghannam

Make use of BIT macro when defining bitfields which makes it easy to read.

No functional change intended.

Suggested-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
---
 drivers/iommu/amd/amd_iommu_types.h | 76 ++++++++++++++---------------
 1 file changed, 38 insertions(+), 38 deletions(-)

diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
index ae0edeb379d4..a49cc2258a76 100644
--- a/drivers/iommu/amd/amd_iommu_types.h
+++ b/drivers/iommu/amd/amd_iommu_types.h
@@ -84,21 +84,21 @@
 
 
 /* Extended Feature Bits */
-#define FEATURE_PREFETCH	(1ULL<<0)
-#define FEATURE_PPR		(1ULL<<1)
-#define FEATURE_X2APIC		(1ULL<<2)
-#define FEATURE_NX		(1ULL<<3)
-#define FEATURE_GT		(1ULL<<4)
-#define FEATURE_IA		(1ULL<<6)
-#define FEATURE_GA		(1ULL<<7)
-#define FEATURE_HE		(1ULL<<8)
-#define FEATURE_PC		(1ULL<<9)
+#define FEATURE_PREFETCH	BIT_ULL(0)
+#define FEATURE_PPR		BIT_ULL(1)
+#define FEATURE_X2APIC		BIT_ULL(2)
+#define FEATURE_NX		BIT_ULL(3)
+#define FEATURE_GT		BIT_ULL(4)
+#define FEATURE_IA		BIT_ULL(6)
+#define FEATURE_GA		BIT_ULL(7)
+#define FEATURE_HE		BIT_ULL(8)
+#define FEATURE_PC		BIT_ULL(9)
 #define FEATURE_GATS_SHIFT	(12)
 #define FEATURE_GATS_MASK	(3ULL)
-#define FEATURE_GAM_VAPIC	(1ULL<<21)
-#define FEATURE_GIOSUP		(1ULL<<48)
-#define FEATURE_EPHSUP		(1ULL<<50)
-#define FEATURE_SNP		(1ULL<<63)
+#define FEATURE_GAM_VAPIC	BIT_ULL(21)
+#define FEATURE_GIOSUP		BIT_ULL(48)
+#define FEATURE_EPHSUP		BIT_ULL(50)
+#define FEATURE_SNP		BIT_ULL(63)
 
 #define FEATURE_PASID_SHIFT	32
 #define FEATURE_PASID_MASK	(0x1fULL << FEATURE_PASID_SHIFT)
@@ -120,13 +120,13 @@
 #define PASID_MASK		0x0000ffff
 
 /* MMIO status bits */
-#define MMIO_STATUS_EVT_OVERFLOW_INT_MASK	(1 << 0)
-#define MMIO_STATUS_EVT_INT_MASK	(1 << 1)
-#define MMIO_STATUS_COM_WAIT_INT_MASK	(1 << 2)
-#define MMIO_STATUS_PPR_INT_MASK	(1 << 6)
-#define MMIO_STATUS_GALOG_RUN_MASK	(1 << 8)
-#define MMIO_STATUS_GALOG_OVERFLOW_MASK	(1 << 9)
-#define MMIO_STATUS_GALOG_INT_MASK	(1 << 10)
+#define MMIO_STATUS_EVT_OVERFLOW_INT_MASK	BIT(0)
+#define MMIO_STATUS_EVT_INT_MASK		BIT(1)
+#define MMIO_STATUS_COM_WAIT_INT_MASK		BIT(2)
+#define MMIO_STATUS_PPR_INT_MASK		BIT(6)
+#define MMIO_STATUS_GALOG_RUN_MASK		BIT(8)
+#define MMIO_STATUS_GALOG_OVERFLOW_MASK		BIT(9)
+#define MMIO_STATUS_GALOG_INT_MASK		BIT(10)
 
 /* event logging constants */
 #define EVENT_ENTRY_SIZE	0x10
@@ -369,23 +369,23 @@
 /*
  * Bit value definition for I/O PTE fields
  */
-#define IOMMU_PTE_PR (1ULL << 0)
-#define IOMMU_PTE_U  (1ULL << 59)
-#define IOMMU_PTE_FC (1ULL << 60)
-#define IOMMU_PTE_IR (1ULL << 61)
-#define IOMMU_PTE_IW (1ULL << 62)
+#define IOMMU_PTE_PR	BIT_ULL(0)
+#define IOMMU_PTE_U	BIT_ULL(59)
+#define IOMMU_PTE_FC	BIT_ULL(60)
+#define IOMMU_PTE_IR	BIT_ULL(61)
+#define IOMMU_PTE_IW	BIT_ULL(62)
 
 /*
  * Bit value definition for DTE fields
  */
-#define DTE_FLAG_V  (1ULL << 0)
-#define DTE_FLAG_TV (1ULL << 1)
-#define DTE_FLAG_IR (1ULL << 61)
-#define DTE_FLAG_IW (1ULL << 62)
-
-#define DTE_FLAG_IOTLB	(1ULL << 32)
-#define DTE_FLAG_GIOV	(1ULL << 54)
-#define DTE_FLAG_GV	(1ULL << 55)
+#define DTE_FLAG_V	BIT_ULL(0)
+#define DTE_FLAG_TV	BIT_ULL(1)
+#define DTE_FLAG_IR	BIT_ULL(61)
+#define DTE_FLAG_IW	BIT_ULL(62)
+
+#define DTE_FLAG_IOTLB	BIT_ULL(32)
+#define DTE_FLAG_GIOV	BIT_ULL(54)
+#define DTE_FLAG_GV	BIT_ULL(55)
 #define DTE_FLAG_MASK	(0x3ffULL << 32)
 #define DTE_GLX_SHIFT	(56)
 #define DTE_GLX_MASK	(3)
@@ -439,13 +439,13 @@
 #define MAX_DOMAIN_ID 65536
 
 /* Protection domain flags */
-#define PD_DMA_OPS_MASK		(1UL << 0) /* domain used for dma_ops */
-#define PD_DEFAULT_MASK		(1UL << 1) /* domain is a default dma_ops
+#define PD_DMA_OPS_MASK		BIT(0) /* domain used for dma_ops */
+#define PD_DEFAULT_MASK		BIT(1) /* domain is a default dma_ops
 					      domain for an IOMMU */
-#define PD_PASSTHROUGH_MASK	(1UL << 2) /* domain has no page
+#define PD_PASSTHROUGH_MASK	BIT(2) /* domain has no page
 					      translation */
-#define PD_IOMMUV2_MASK		(1UL << 3) /* domain has gcr3 table */
-#define PD_GIOV_MASK		(1UL << 4) /* domain enable GIOV support */
+#define PD_IOMMUV2_MASK		BIT(3) /* domain has gcr3 table */
+#define PD_GIOV_MASK		BIT(4) /* domain enable GIOV support */
 
 extern bool amd_iommu_dump;
 #define DUMP_printk(format, arg...)				\
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [PATCH 2/2] iommu/amd: Remove extern from function prototypes
  2023-06-09  9:06 [PATCH 1/2] iommu/amd: Use BIT/BIT_ULL macro to define bit fields Vasant Hegde
@ 2023-06-09  9:06 ` Vasant Hegde
  2023-06-12 18:58   ` Jerry Snitselaar
  2023-06-12 18:55 ` [PATCH 1/2] iommu/amd: Use BIT/BIT_ULL macro to define bit fields Jerry Snitselaar
  2023-06-16 14:34 ` Joerg Roedel
  2 siblings, 1 reply; 6+ messages in thread
From: Vasant Hegde @ 2023-06-09  9:06 UTC (permalink / raw)
  To: iommu, joro; +Cc: suravee.suthikulpanit, Vasant Hegde, Yazen Ghannam

The kernel coding style does not require 'extern' in function prototypes.
Hence remove them from header file.

No functional change intended.

Suggested-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
---
 drivers/iommu/amd/amd_iommu.h       | 88 ++++++++++++++---------------
 drivers/iommu/amd/amd_iommu_types.h |  2 +-
 2 files changed, 44 insertions(+), 46 deletions(-)

diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h
index 9beeceb9d825..317d5c26c614 100644
--- a/drivers/iommu/amd/amd_iommu.h
+++ b/drivers/iommu/amd/amd_iommu.h
@@ -11,12 +11,12 @@
 
 #include "amd_iommu_types.h"
 
-extern irqreturn_t amd_iommu_int_thread(int irq, void *data);
-extern irqreturn_t amd_iommu_int_handler(int irq, void *data);
-extern void amd_iommu_apply_erratum_63(struct amd_iommu *iommu, u16 devid);
-extern void amd_iommu_restart_event_logging(struct amd_iommu *iommu);
-extern void amd_iommu_restart_ga_log(struct amd_iommu *iommu);
-extern void amd_iommu_set_rlookup_table(struct amd_iommu *iommu, u16 devid);
+irqreturn_t amd_iommu_int_thread(int irq, void *data);
+irqreturn_t amd_iommu_int_handler(int irq, void *data);
+void amd_iommu_apply_erratum_63(struct amd_iommu *iommu, u16 devid);
+void amd_iommu_restart_event_logging(struct amd_iommu *iommu);
+void amd_iommu_restart_ga_log(struct amd_iommu *iommu);
+void amd_iommu_set_rlookup_table(struct amd_iommu *iommu, u16 devid);
 
 #ifdef CONFIG_AMD_IOMMU_DEBUGFS
 void amd_iommu_debugfs_setup(struct amd_iommu *iommu);
@@ -25,11 +25,11 @@ static inline void amd_iommu_debugfs_setup(struct amd_iommu *iommu) {}
 #endif
 
 /* Needed for interrupt remapping */
-extern int amd_iommu_prepare(void);
-extern int amd_iommu_enable(void);
-extern void amd_iommu_disable(void);
-extern int amd_iommu_reenable(int);
-extern int amd_iommu_enable_faulting(void);
+int amd_iommu_prepare(void);
+int amd_iommu_enable(void);
+void amd_iommu_disable(void);
+int amd_iommu_reenable(int mode);
+int amd_iommu_enable_faulting(void);
 extern int amd_iommu_guest_ir;
 extern enum io_pgtable_fmt amd_iommu_pgtable;
 extern int amd_iommu_gpt_level;
@@ -37,33 +37,32 @@ extern int amd_iommu_gpt_level;
 /* IOMMUv2 specific functions */
 struct iommu_domain;
 
-extern bool amd_iommu_v2_supported(void);
-extern struct amd_iommu *get_amd_iommu(unsigned int idx);
-extern u8 amd_iommu_pc_get_max_banks(unsigned int idx);
-extern bool amd_iommu_pc_supported(void);
-extern u8 amd_iommu_pc_get_max_counters(unsigned int idx);
-extern int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
-				u8 fxn, u64 *value);
-extern int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
-				u8 fxn, u64 *value);
-
-extern int amd_iommu_register_ppr_notifier(struct notifier_block *nb);
-extern int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb);
-extern void amd_iommu_domain_direct_map(struct iommu_domain *dom);
-extern int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids);
-extern int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid,
-				u64 address);
-extern void amd_iommu_update_and_flush_device_table(struct protection_domain *domain);
-extern void amd_iommu_domain_update(struct protection_domain *domain);
-extern void amd_iommu_domain_flush_complete(struct protection_domain *domain);
-extern void amd_iommu_domain_flush_tlb_pde(struct protection_domain *domain);
-extern int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid);
-extern int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid,
-				     unsigned long cr3);
-extern int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid);
+bool amd_iommu_v2_supported(void);
+struct amd_iommu *get_amd_iommu(unsigned int idx);
+u8 amd_iommu_pc_get_max_banks(unsigned int idx);
+bool amd_iommu_pc_supported(void);
+u8 amd_iommu_pc_get_max_counters(unsigned int idx);
+int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
+			 u8 fxn, u64 *value);
+int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
+			 u8 fxn, u64 *value);
+
+int amd_iommu_register_ppr_notifier(struct notifier_block *nb);
+int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb);
+void amd_iommu_domain_direct_map(struct iommu_domain *dom);
+int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids);
+int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid, u64 address);
+void amd_iommu_update_and_flush_device_table(struct protection_domain *domain);
+void amd_iommu_domain_update(struct protection_domain *domain);
+void amd_iommu_domain_flush_complete(struct protection_domain *domain);
+void amd_iommu_domain_flush_tlb_pde(struct protection_domain *domain);
+int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid);
+int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid,
+			      unsigned long cr3);
+int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid);
 
 #ifdef CONFIG_IRQ_REMAP
-extern int amd_iommu_create_irq_domain(struct amd_iommu *iommu);
+int amd_iommu_create_irq_domain(struct amd_iommu *iommu);
 #else
 static inline int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
 {
@@ -75,8 +74,8 @@ static inline int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
 #define PPR_INVALID			0x1
 #define PPR_FAILURE			0xf
 
-extern int amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid,
-				  int status, int tag);
+int amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid,
+			   int status, int tag);
 
 static inline bool is_rd890_iommu(struct pci_dev *pdev)
 {
@@ -129,10 +128,9 @@ static inline void *alloc_pgtable_page(int nid, gfp_t gfp)
 	return page ? page_address(page) : NULL;
 }
 
-extern bool translation_pre_enabled(struct amd_iommu *iommu);
-extern bool amd_iommu_is_attach_deferred(struct device *dev);
-extern int __init add_special_device(u8 type, u8 id, u32 *devid,
-				     bool cmd_line);
+bool translation_pre_enabled(struct amd_iommu *iommu);
+bool amd_iommu_is_attach_deferred(struct device *dev);
+int __init add_special_device(u8 type, u8 id, u32 *devid, bool cmd_line);
 
 #ifdef CONFIG_DMI
 void amd_iommu_apply_ivrs_quirks(void);
@@ -140,9 +138,9 @@ void amd_iommu_apply_ivrs_quirks(void);
 static inline void amd_iommu_apply_ivrs_quirks(void) { }
 #endif
 
-extern void amd_iommu_domain_set_pgtable(struct protection_domain *domain,
-					 u64 *root, int mode);
-extern struct dev_table_entry *get_dev_table(struct amd_iommu *iommu);
+void amd_iommu_domain_set_pgtable(struct protection_domain *domain,
+				  u64 *root, int mode);
+struct dev_table_entry *get_dev_table(struct amd_iommu *iommu);
 
 extern u64 amd_iommu_efr;
 extern u64 amd_iommu_efr2;
diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
index a49cc2258a76..364fdaa52e74 100644
--- a/drivers/iommu/amd/amd_iommu_types.h
+++ b/drivers/iommu/amd/amd_iommu_types.h
@@ -882,7 +882,7 @@ extern int amd_iommu_max_glx_val;
  * This function flushes all internal caches of
  * the IOMMU used by this driver.
  */
-extern void iommu_flush_all_caches(struct amd_iommu *iommu);
+void iommu_flush_all_caches(struct amd_iommu *iommu);
 
 static inline int get_ioapic_devid(int id)
 {
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] iommu/amd: Use BIT/BIT_ULL macro to define bit fields
  2023-06-09  9:06 [PATCH 1/2] iommu/amd: Use BIT/BIT_ULL macro to define bit fields Vasant Hegde
  2023-06-09  9:06 ` [PATCH 2/2] iommu/amd: Remove extern from function prototypes Vasant Hegde
@ 2023-06-12 18:55 ` Jerry Snitselaar
  2023-06-14  9:45   ` Vasant Hegde
  2023-06-16 14:34 ` Joerg Roedel
  2 siblings, 1 reply; 6+ messages in thread
From: Jerry Snitselaar @ 2023-06-12 18:55 UTC (permalink / raw)
  To: Vasant Hegde; +Cc: iommu, joro, suravee.suthikulpanit, Yazen Ghannam

On Fri, Jun 09, 2023 at 09:06:30AM +0000, Vasant Hegde wrote:
> Make use of BIT macro when defining bitfields which makes it easy to read.
> 
> No functional change intended.
> 
> Suggested-by: Yazen Ghannam <yazen.ghannam@amd.com>
> Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
> ---
>  drivers/iommu/amd/amd_iommu_types.h | 76 ++++++++++++++---------------
>  1 file changed, 38 insertions(+), 38 deletions(-)
> 
> diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
> index ae0edeb379d4..a49cc2258a76 100644
> --- a/drivers/iommu/amd/amd_iommu_types.h
> +++ b/drivers/iommu/amd/amd_iommu_types.h
> @@ -84,21 +84,21 @@
>  
>  
>  /* Extended Feature Bits */
> -#define FEATURE_PREFETCH	(1ULL<<0)
> -#define FEATURE_PPR		(1ULL<<1)
> -#define FEATURE_X2APIC		(1ULL<<2)
> -#define FEATURE_NX		(1ULL<<3)
> -#define FEATURE_GT		(1ULL<<4)
> -#define FEATURE_IA		(1ULL<<6)
> -#define FEATURE_GA		(1ULL<<7)
> -#define FEATURE_HE		(1ULL<<8)
> -#define FEATURE_PC		(1ULL<<9)
> +#define FEATURE_PREFETCH	BIT_ULL(0)
> +#define FEATURE_PPR		BIT_ULL(1)
> +#define FEATURE_X2APIC		BIT_ULL(2)
> +#define FEATURE_NX		BIT_ULL(3)
> +#define FEATURE_GT		BIT_ULL(4)
> +#define FEATURE_IA		BIT_ULL(6)
> +#define FEATURE_GA		BIT_ULL(7)
> +#define FEATURE_HE		BIT_ULL(8)
> +#define FEATURE_PC		BIT_ULL(9)
>  #define FEATURE_GATS_SHIFT	(12)
>  #define FEATURE_GATS_MASK	(3ULL)
> -#define FEATURE_GAM_VAPIC	(1ULL<<21)
> -#define FEATURE_GIOSUP		(1ULL<<48)
> -#define FEATURE_EPHSUP		(1ULL<<50)
> -#define FEATURE_SNP		(1ULL<<63)
> +#define FEATURE_GAM_VAPIC	BIT_ULL(21)
> +#define FEATURE_GIOSUP		BIT_ULL(48)
> +#define FEATURE_EPHSUP		BIT_ULL(50)
> +#define FEATURE_SNP		BIT_ULL(63)
>  
>  #define FEATURE_PASID_SHIFT	32
>  #define FEATURE_PASID_MASK	(0x1fULL << FEATURE_PASID_SHIFT)
> @@ -120,13 +120,13 @@
>  #define PASID_MASK		0x0000ffff
>  
>  /* MMIO status bits */
> -#define MMIO_STATUS_EVT_OVERFLOW_INT_MASK	(1 << 0)
> -#define MMIO_STATUS_EVT_INT_MASK	(1 << 1)
> -#define MMIO_STATUS_COM_WAIT_INT_MASK	(1 << 2)
> -#define MMIO_STATUS_PPR_INT_MASK	(1 << 6)
> -#define MMIO_STATUS_GALOG_RUN_MASK	(1 << 8)
> -#define MMIO_STATUS_GALOG_OVERFLOW_MASK	(1 << 9)
> -#define MMIO_STATUS_GALOG_INT_MASK	(1 << 10)
> +#define MMIO_STATUS_EVT_OVERFLOW_INT_MASK	BIT(0)
> +#define MMIO_STATUS_EVT_INT_MASK		BIT(1)
> +#define MMIO_STATUS_COM_WAIT_INT_MASK		BIT(2)
> +#define MMIO_STATUS_PPR_INT_MASK		BIT(6)
> +#define MMIO_STATUS_GALOG_RUN_MASK		BIT(8)
> +#define MMIO_STATUS_GALOG_OVERFLOW_MASK		BIT(9)
> +#define MMIO_STATUS_GALOG_INT_MASK		BIT(10)
>  
>  /* event logging constants */
>  #define EVENT_ENTRY_SIZE	0x10
> @@ -369,23 +369,23 @@
>  /*
>   * Bit value definition for I/O PTE fields
>   */
> -#define IOMMU_PTE_PR (1ULL << 0)
> -#define IOMMU_PTE_U  (1ULL << 59)
> -#define IOMMU_PTE_FC (1ULL << 60)
> -#define IOMMU_PTE_IR (1ULL << 61)
> -#define IOMMU_PTE_IW (1ULL << 62)
> +#define IOMMU_PTE_PR	BIT_ULL(0)
> +#define IOMMU_PTE_U	BIT_ULL(59)
> +#define IOMMU_PTE_FC	BIT_ULL(60)
> +#define IOMMU_PTE_IR	BIT_ULL(61)
> +#define IOMMU_PTE_IW	BIT_ULL(62)
>  
>  /*
>   * Bit value definition for DTE fields
>   */
> -#define DTE_FLAG_V  (1ULL << 0)
> -#define DTE_FLAG_TV (1ULL << 1)
> -#define DTE_FLAG_IR (1ULL << 61)
> -#define DTE_FLAG_IW (1ULL << 62)
> -
> -#define DTE_FLAG_IOTLB	(1ULL << 32)
> -#define DTE_FLAG_GIOV	(1ULL << 54)
> -#define DTE_FLAG_GV	(1ULL << 55)
> +#define DTE_FLAG_V	BIT_ULL(0)
> +#define DTE_FLAG_TV	BIT_ULL(1)
> +#define DTE_FLAG_IR	BIT_ULL(61)
> +#define DTE_FLAG_IW	BIT_ULL(62)
> +
> +#define DTE_FLAG_IOTLB	BIT_ULL(32)
> +#define DTE_FLAG_GIOV	BIT_ULL(54)
> +#define DTE_FLAG_GV	BIT_ULL(55)

Minor thing, but would it make sense to group these according
to which 64-bit word they are in? DTE_FLAG_IOTLB is in the
second 64-bit word of the DTE, and the rest are in the first.

Regards,
Jerry

>  #define DTE_FLAG_MASK	(0x3ffULL << 32)
>  #define DTE_GLX_SHIFT	(56)
>  #define DTE_GLX_MASK	(3)
> @@ -439,13 +439,13 @@
>  #define MAX_DOMAIN_ID 65536
>  
>  /* Protection domain flags */
> -#define PD_DMA_OPS_MASK		(1UL << 0) /* domain used for dma_ops */
> -#define PD_DEFAULT_MASK		(1UL << 1) /* domain is a default dma_ops
> +#define PD_DMA_OPS_MASK		BIT(0) /* domain used for dma_ops */
> +#define PD_DEFAULT_MASK		BIT(1) /* domain is a default dma_ops
>  					      domain for an IOMMU */
> -#define PD_PASSTHROUGH_MASK	(1UL << 2) /* domain has no page
> +#define PD_PASSTHROUGH_MASK	BIT(2) /* domain has no page
>  					      translation */
> -#define PD_IOMMUV2_MASK		(1UL << 3) /* domain has gcr3 table */
> -#define PD_GIOV_MASK		(1UL << 4) /* domain enable GIOV support */
> +#define PD_IOMMUV2_MASK		BIT(3) /* domain has gcr3 table */
> +#define PD_GIOV_MASK		BIT(4) /* domain enable GIOV support */
>  
>  extern bool amd_iommu_dump;
>  #define DUMP_printk(format, arg...)				\
> -- 
> 2.31.1
> 


^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] iommu/amd: Remove extern from function prototypes
  2023-06-09  9:06 ` [PATCH 2/2] iommu/amd: Remove extern from function prototypes Vasant Hegde
@ 2023-06-12 18:58   ` Jerry Snitselaar
  0 siblings, 0 replies; 6+ messages in thread
From: Jerry Snitselaar @ 2023-06-12 18:58 UTC (permalink / raw)
  To: Vasant Hegde; +Cc: iommu, joro, suravee.suthikulpanit, Yazen Ghannam

On Fri, Jun 09, 2023 at 09:06:31AM +0000, Vasant Hegde wrote:
> The kernel coding style does not require 'extern' in function prototypes.
> Hence remove them from header file.
> 
> No functional change intended.
> 
> Suggested-by: Yazen Ghannam <yazen.ghannam@amd.com>
> Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>

Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com>

> ---
>  drivers/iommu/amd/amd_iommu.h       | 88 ++++++++++++++---------------
>  drivers/iommu/amd/amd_iommu_types.h |  2 +-
>  2 files changed, 44 insertions(+), 46 deletions(-)
> 
> diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h
> index 9beeceb9d825..317d5c26c614 100644
> --- a/drivers/iommu/amd/amd_iommu.h
> +++ b/drivers/iommu/amd/amd_iommu.h
> @@ -11,12 +11,12 @@
>  
>  #include "amd_iommu_types.h"
>  
> -extern irqreturn_t amd_iommu_int_thread(int irq, void *data);
> -extern irqreturn_t amd_iommu_int_handler(int irq, void *data);
> -extern void amd_iommu_apply_erratum_63(struct amd_iommu *iommu, u16 devid);
> -extern void amd_iommu_restart_event_logging(struct amd_iommu *iommu);
> -extern void amd_iommu_restart_ga_log(struct amd_iommu *iommu);
> -extern void amd_iommu_set_rlookup_table(struct amd_iommu *iommu, u16 devid);
> +irqreturn_t amd_iommu_int_thread(int irq, void *data);
> +irqreturn_t amd_iommu_int_handler(int irq, void *data);
> +void amd_iommu_apply_erratum_63(struct amd_iommu *iommu, u16 devid);
> +void amd_iommu_restart_event_logging(struct amd_iommu *iommu);
> +void amd_iommu_restart_ga_log(struct amd_iommu *iommu);
> +void amd_iommu_set_rlookup_table(struct amd_iommu *iommu, u16 devid);
>  
>  #ifdef CONFIG_AMD_IOMMU_DEBUGFS
>  void amd_iommu_debugfs_setup(struct amd_iommu *iommu);
> @@ -25,11 +25,11 @@ static inline void amd_iommu_debugfs_setup(struct amd_iommu *iommu) {}
>  #endif
>  
>  /* Needed for interrupt remapping */
> -extern int amd_iommu_prepare(void);
> -extern int amd_iommu_enable(void);
> -extern void amd_iommu_disable(void);
> -extern int amd_iommu_reenable(int);
> -extern int amd_iommu_enable_faulting(void);
> +int amd_iommu_prepare(void);
> +int amd_iommu_enable(void);
> +void amd_iommu_disable(void);
> +int amd_iommu_reenable(int mode);
> +int amd_iommu_enable_faulting(void);
>  extern int amd_iommu_guest_ir;
>  extern enum io_pgtable_fmt amd_iommu_pgtable;
>  extern int amd_iommu_gpt_level;
> @@ -37,33 +37,32 @@ extern int amd_iommu_gpt_level;
>  /* IOMMUv2 specific functions */
>  struct iommu_domain;
>  
> -extern bool amd_iommu_v2_supported(void);
> -extern struct amd_iommu *get_amd_iommu(unsigned int idx);
> -extern u8 amd_iommu_pc_get_max_banks(unsigned int idx);
> -extern bool amd_iommu_pc_supported(void);
> -extern u8 amd_iommu_pc_get_max_counters(unsigned int idx);
> -extern int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
> -				u8 fxn, u64 *value);
> -extern int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
> -				u8 fxn, u64 *value);
> -
> -extern int amd_iommu_register_ppr_notifier(struct notifier_block *nb);
> -extern int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb);
> -extern void amd_iommu_domain_direct_map(struct iommu_domain *dom);
> -extern int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids);
> -extern int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid,
> -				u64 address);
> -extern void amd_iommu_update_and_flush_device_table(struct protection_domain *domain);
> -extern void amd_iommu_domain_update(struct protection_domain *domain);
> -extern void amd_iommu_domain_flush_complete(struct protection_domain *domain);
> -extern void amd_iommu_domain_flush_tlb_pde(struct protection_domain *domain);
> -extern int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid);
> -extern int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid,
> -				     unsigned long cr3);
> -extern int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid);
> +bool amd_iommu_v2_supported(void);
> +struct amd_iommu *get_amd_iommu(unsigned int idx);
> +u8 amd_iommu_pc_get_max_banks(unsigned int idx);
> +bool amd_iommu_pc_supported(void);
> +u8 amd_iommu_pc_get_max_counters(unsigned int idx);
> +int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
> +			 u8 fxn, u64 *value);
> +int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
> +			 u8 fxn, u64 *value);
> +
> +int amd_iommu_register_ppr_notifier(struct notifier_block *nb);
> +int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb);
> +void amd_iommu_domain_direct_map(struct iommu_domain *dom);
> +int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids);
> +int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid, u64 address);
> +void amd_iommu_update_and_flush_device_table(struct protection_domain *domain);
> +void amd_iommu_domain_update(struct protection_domain *domain);
> +void amd_iommu_domain_flush_complete(struct protection_domain *domain);
> +void amd_iommu_domain_flush_tlb_pde(struct protection_domain *domain);
> +int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid);
> +int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid,
> +			      unsigned long cr3);
> +int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid);
>  
>  #ifdef CONFIG_IRQ_REMAP
> -extern int amd_iommu_create_irq_domain(struct amd_iommu *iommu);
> +int amd_iommu_create_irq_domain(struct amd_iommu *iommu);
>  #else
>  static inline int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
>  {
> @@ -75,8 +74,8 @@ static inline int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
>  #define PPR_INVALID			0x1
>  #define PPR_FAILURE			0xf
>  
> -extern int amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid,
> -				  int status, int tag);
> +int amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid,
> +			   int status, int tag);
>  
>  static inline bool is_rd890_iommu(struct pci_dev *pdev)
>  {
> @@ -129,10 +128,9 @@ static inline void *alloc_pgtable_page(int nid, gfp_t gfp)
>  	return page ? page_address(page) : NULL;
>  }
>  
> -extern bool translation_pre_enabled(struct amd_iommu *iommu);
> -extern bool amd_iommu_is_attach_deferred(struct device *dev);
> -extern int __init add_special_device(u8 type, u8 id, u32 *devid,
> -				     bool cmd_line);
> +bool translation_pre_enabled(struct amd_iommu *iommu);
> +bool amd_iommu_is_attach_deferred(struct device *dev);
> +int __init add_special_device(u8 type, u8 id, u32 *devid, bool cmd_line);
>  
>  #ifdef CONFIG_DMI
>  void amd_iommu_apply_ivrs_quirks(void);
> @@ -140,9 +138,9 @@ void amd_iommu_apply_ivrs_quirks(void);
>  static inline void amd_iommu_apply_ivrs_quirks(void) { }
>  #endif
>  
> -extern void amd_iommu_domain_set_pgtable(struct protection_domain *domain,
> -					 u64 *root, int mode);
> -extern struct dev_table_entry *get_dev_table(struct amd_iommu *iommu);
> +void amd_iommu_domain_set_pgtable(struct protection_domain *domain,
> +				  u64 *root, int mode);
> +struct dev_table_entry *get_dev_table(struct amd_iommu *iommu);
>  
>  extern u64 amd_iommu_efr;
>  extern u64 amd_iommu_efr2;
> diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
> index a49cc2258a76..364fdaa52e74 100644
> --- a/drivers/iommu/amd/amd_iommu_types.h
> +++ b/drivers/iommu/amd/amd_iommu_types.h
> @@ -882,7 +882,7 @@ extern int amd_iommu_max_glx_val;
>   * This function flushes all internal caches of
>   * the IOMMU used by this driver.
>   */
> -extern void iommu_flush_all_caches(struct amd_iommu *iommu);
> +void iommu_flush_all_caches(struct amd_iommu *iommu);
>  
>  static inline int get_ioapic_devid(int id)
>  {
> -- 
> 2.31.1
> 


^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] iommu/amd: Use BIT/BIT_ULL macro to define bit fields
  2023-06-12 18:55 ` [PATCH 1/2] iommu/amd: Use BIT/BIT_ULL macro to define bit fields Jerry Snitselaar
@ 2023-06-14  9:45   ` Vasant Hegde
  0 siblings, 0 replies; 6+ messages in thread
From: Vasant Hegde @ 2023-06-14  9:45 UTC (permalink / raw)
  To: Jerry Snitselaar; +Cc: iommu, joro, suravee.suthikulpanit, Yazen Ghannam

Jerry,


On 6/13/2023 12:25 AM, Jerry Snitselaar wrote:
> On Fri, Jun 09, 2023 at 09:06:30AM +0000, Vasant Hegde wrote:
>> Make use of BIT macro when defining bitfields which makes it easy to read.
>>
>> No functional change intended.
>>
>> Suggested-by: Yazen Ghannam <yazen.ghannam@amd.com>
>> Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
>> ---
>>  drivers/iommu/amd/amd_iommu_types.h | 76 ++++++++++++++---------------
>>  1 file changed, 38 insertions(+), 38 deletions(-)
>>
>> diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
>> index ae0edeb379d4..a49cc2258a76 100644
>> --- a/drivers/iommu/amd/amd_iommu_types.h
>> +++ b/drivers/iommu/amd/amd_iommu_types.h
>> @@ -84,21 +84,21 @@
>>  


.../...

>>  /*
>>   * Bit value definition for DTE fields
>>   */
>> -#define DTE_FLAG_V  (1ULL << 0)
>> -#define DTE_FLAG_TV (1ULL << 1)
>> -#define DTE_FLAG_IR (1ULL << 61)
>> -#define DTE_FLAG_IW (1ULL << 62)
>> -
>> -#define DTE_FLAG_IOTLB	(1ULL << 32)
>> -#define DTE_FLAG_GIOV	(1ULL << 54)
>> -#define DTE_FLAG_GV	(1ULL << 55)
>> +#define DTE_FLAG_V	BIT_ULL(0)
>> +#define DTE_FLAG_TV	BIT_ULL(1)
>> +#define DTE_FLAG_IR	BIT_ULL(61)
>> +#define DTE_FLAG_IW	BIT_ULL(62)
>> +
>> +#define DTE_FLAG_IOTLB	BIT_ULL(32)
>> +#define DTE_FLAG_GIOV	BIT_ULL(54)
>> +#define DTE_FLAG_GV	BIT_ULL(55)
> 
> Minor thing, but would it make sense to group these according
> to which 64-bit word they are in? DTE_FLAG_IOTLB is in the
> second 64-bit word of the DTE, and the rest are in the first.

Sure. I will fix it in next version.

-Vasant


^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] iommu/amd: Use BIT/BIT_ULL macro to define bit fields
  2023-06-09  9:06 [PATCH 1/2] iommu/amd: Use BIT/BIT_ULL macro to define bit fields Vasant Hegde
  2023-06-09  9:06 ` [PATCH 2/2] iommu/amd: Remove extern from function prototypes Vasant Hegde
  2023-06-12 18:55 ` [PATCH 1/2] iommu/amd: Use BIT/BIT_ULL macro to define bit fields Jerry Snitselaar
@ 2023-06-16 14:34 ` Joerg Roedel
  2 siblings, 0 replies; 6+ messages in thread
From: Joerg Roedel @ 2023-06-16 14:34 UTC (permalink / raw)
  To: Vasant Hegde; +Cc: iommu, suravee.suthikulpanit, Yazen Ghannam

On Fri, Jun 09, 2023 at 09:06:30AM +0000, Vasant Hegde wrote:
> Make use of BIT macro when defining bitfields which makes it easy to read.
> 
> No functional change intended.
> 
> Suggested-by: Yazen Ghannam <yazen.ghannam@amd.com>
> Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
> ---
>  drivers/iommu/amd/amd_iommu_types.h | 76 ++++++++++++++---------------
>  1 file changed, 38 insertions(+), 38 deletions(-)

Applied both, thanks.


^ permalink raw reply	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-06-16 14:35 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-06-09  9:06 [PATCH 1/2] iommu/amd: Use BIT/BIT_ULL macro to define bit fields Vasant Hegde
2023-06-09  9:06 ` [PATCH 2/2] iommu/amd: Remove extern from function prototypes Vasant Hegde
2023-06-12 18:58   ` Jerry Snitselaar
2023-06-12 18:55 ` [PATCH 1/2] iommu/amd: Use BIT/BIT_ULL macro to define bit fields Jerry Snitselaar
2023-06-14  9:45   ` Vasant Hegde
2023-06-16 14:34 ` Joerg Roedel

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).