[PATCH] dt-bndings: iommu: renesas, ipmmu-vmsa: convert to json-schema

[PATCH] dt-bndings: iommu: renesas, ipmmu-vmsa: convert to json-schema

[Yoshihiro Shimoda]

Convert Renesas VMSA-Compatible IOMMU bindings documentation
to json-schema.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 .../bindings/iommu/renesas,ipmmu-vmsa.txt          | 73 ------------------
 .../bindings/iommu/renesas,ipmmu-vmsa.yaml         | 90 ++++++++++++++++++++++
 2 files changed, 90 insertions(+), 73 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt
 create mode 100644 Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml

diff --git a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt
deleted file mode 100644
index 020d6f2..00000000
--- a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt
+++ /dev/null
@@ -1,73 +0,0 @@
-* Renesas VMSA-Compatible IOMMU
-
-The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables.
-It provides address translation for bus masters outside of the CPU, each
-connected to the IPMMU through a port called micro-TLB.
-
-
-Required Properties:
-
-  - compatible: Must contain SoC-specific and generic entry below in case
-    the device is compatible with the R-Car Gen2 VMSA-compatible IPMMU.
-
-    - "renesas,ipmmu-r8a73a4" for the R8A73A4 (R-Mobile APE6) IPMMU.
-    - "renesas,ipmmu-r8a7743" for the R8A7743 (RZ/G1M) IPMMU.
-    - "renesas,ipmmu-r8a7744" for the R8A7744 (RZ/G1N) IPMMU.
-    - "renesas,ipmmu-r8a7745" for the R8A7745 (RZ/G1E) IPMMU.
-    - "renesas,ipmmu-r8a774a1" for the R8A774A1 (RZ/G2M) IPMMU.
-    - "renesas,ipmmu-r8a774b1" for the R8A774B1 (RZ/G2N) IPMMU.
-    - "renesas,ipmmu-r8a774c0" for the R8A774C0 (RZ/G2E) IPMMU.
-    - "renesas,ipmmu-r8a7790" for the R8A7790 (R-Car H2) IPMMU.
-    - "renesas,ipmmu-r8a7791" for the R8A7791 (R-Car M2-W) IPMMU.
-    - "renesas,ipmmu-r8a7793" for the R8A7793 (R-Car M2-N) IPMMU.
-    - "renesas,ipmmu-r8a7794" for the R8A7794 (R-Car E2) IPMMU.
-    - "renesas,ipmmu-r8a7795" for the R8A7795 (R-Car H3) IPMMU.
-    - "renesas,ipmmu-r8a7796" for the R8A7796 (R-Car M3-W) IPMMU.
-    - "renesas,ipmmu-r8a77965" for the R8A77965 (R-Car M3-N) IPMMU.
-    - "renesas,ipmmu-r8a77970" for the R8A77970 (R-Car V3M) IPMMU.
-    - "renesas,ipmmu-r8a77980" for the R8A77980 (R-Car V3H) IPMMU.
-    - "renesas,ipmmu-r8a77990" for the R8A77990 (R-Car E3) IPMMU.
-    - "renesas,ipmmu-r8a77995" for the R8A77995 (R-Car D3) IPMMU.
-    - "renesas,ipmmu-vmsa" for generic R-Car Gen2 or RZ/G1 VMSA-compatible
-			   IPMMU.
-
-  - reg: Base address and size of the IPMMU registers.
-  - interrupts: Specifiers for the MMU fault interrupts. For instances that
-    support secure mode two interrupts must be specified, for non-secure and
-    secure mode, in that order. For instances that don't support secure mode a
-    single interrupt must be specified. Not required for cache IPMMUs.
-
-  - #iommu-cells: Must be 1.
-
-Optional properties:
-
-  - renesas,ipmmu-main: reference to the main IPMMU instance in two cells.
-    The first cell is a phandle to the main IPMMU and the second cell is
-    the interrupt bit number associated with the particular cache IPMMU device.
-    The interrupt bit number needs to match the main IPMMU IMSSTR register.
-    Only used by cache IPMMU instances.
-
-
-Each bus master connected to an IPMMU must reference the IPMMU in its device
-node with the following property:
-
-  - iommus: A reference to the IPMMU in two cells. The first cell is a phandle
-    to the IPMMU and the second cell the number of the micro-TLB that the
-    device is connected to.
-
-
-Example: R8A7791 IPMMU-MX and VSP1-D0 bus master
-
-	ipmmu_mx: mmu@fe951000 {
-		compatible = "renasas,ipmmu-r8a7791", "renasas,ipmmu-vmsa";
-		reg = <0 0xfe951000 0 0x1000>;
-		interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 221 IRQ_TYPE_LEVEL_HIGH>;
-		#iommu-cells = <1>;
-	};
-
-	vsp@fe928000 {
-		...
-		iommus = <&ipmmu_mx 13>;
-		...
-	};
diff --git a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
new file mode 100644
index 00000000..3820b10
--- /dev/null
+++ b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iommu/renesas,ipmmu-vmsa.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas VMSA-Compatible IOMMU
+
+maintainers:
+  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+
+description:
+  The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables.
+  It provides address translation for bus masters outside of the CPU, each
+  connected to the IPMMU through a port called micro-TLB.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - renesas,ipmmu-r8a7743  # RZ/G1M
+              - renesas,ipmmu-r8a7744  # RZ/G1N
+              - renesas,ipmmu-r8a7745  # RZ/G1E
+              - renesas,ipmmu-r8a7790  # R-Car H2
+              - renesas,ipmmu-r8a7791  # R-Car M2-W
+              - renesas,ipmmu-r8a7793  # R-Car M2-N
+              - renesas,ipmmu-r8a7794  # R-Car E2
+              - renesas,ipmmu-r8a7795  # R-Car H3
+          - const: renesas,ipmmu-vmsa  # R-Car Gen2 or RZ/G1
+      - items:
+          - enum:
+              - renesas,ipmmu-r8a73a4  # R-Mobile APE6
+              - renesas,ipmmu-r8a774a1 # RZ/G2M
+              - renesas,ipmmu-r8a774b1 # RZ/G2N
+              - renesas,ipmmu-r8a774c0 # RZ/G2E
+              - renesas,ipmmu-r8a7796  # R-Car M3-W
+              - renesas,ipmmu-r8a77965 # R-Car M3-N
+              - renesas,ipmmu-r8a77970 # R-Car V3M
+              - renesas,ipmmu-r8a77980 # R-Car V3H
+              - renesas,ipmmu-r8a77990 # R-Car E3
+              - renesas,ipmmu-r8a77995 # R-Car D3
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    minItems: 1
+    maxItems: 2
+    description:
+      Specifiers for the MMU fault interrupts. For instances that support
+      secure mode two interrupts must be specified, for non-secure and secure
+      mode, in that order. For instances that don't support secure mode a
+      single interrupt must be specified. Not required for cache IPMMUs.
+
+  '#iommu-cells':
+    const: 1
+
+  power-domains:
+    maxItems: 1
+
+  renesas,ipmmu-main:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    description:
+      Reference to the main IPMMU instance in two cells. The first cell is
+      a phandle to the main IPMMU and the second cell is the interrupt bit
+      number associated with the particular cache IPMMU device. The interrupt
+      bit number needs to match the main IPMMU IMSSTR register. Only used by
+      cache IPMMU instances.
+
+required:
+  - compatible
+  - reg
+  - '#iommu-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/power/r8a7791-sysc.h>
+
+    ipmmu_mx: mmu@fe951000 {
+        compatible = "renasas,ipmmu-r8a7791", "renasas,ipmmu-vmsa";
+        reg = <0xfe951000 0x1000>;
+        interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+        #iommu-cells = <1>;
+    };
-- 
2.7.4

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Re: [PATCH] dt-bndings: iommu: renesas, ipmmu-vmsa: convert to json-schema

[Robin Murphy]

On 2020-04-13 11:25 am, Yoshihiro Shimoda wrote:
[...]
> -Each bus master connected to an IPMMU must reference the IPMMU in its device
> -node with the following property:
> -
> -  - iommus: A reference to the IPMMU in two cells. The first cell is a phandle
> -    to the IPMMU and the second cell the number of the micro-TLB that the
> -    device is connected to.

This definition of what the phandle argument means...

[...]
> +  '#iommu-cells':
> +    const: 1
 > +

...deserves to be captured in a description here.

Robin.
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RE: [PATCH] dt-bndings: iommu: renesas, ipmmu-vmsa: convert to json-schema

[Yoshihiro Shimoda]

Hi Robin,

> From: Robin Murphy, Sent: Wednesday, April 15, 2020 2:16 AM
> 
> On 2020-04-13 11:25 am, Yoshihiro Shimoda wrote:
> [...]
> > -Each bus master connected to an IPMMU must reference the IPMMU in its device
> > -node with the following property:
> > -
> > -  - iommus: A reference to the IPMMU in two cells. The first cell is a phandle
> > -    to the IPMMU and the second cell the number of the micro-TLB that the
> > -    device is connected to.
> 
> This definition of what the phandle argument means...
> 
> [...]
> > +  '#iommu-cells':
> > +    const: 1
>  > +
> 
> ...deserves to be captured in a description here.

Thank you for the comment! I'll fix this.

Best regards,
Yoshihiro Shimoda

> Robin.
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Re: [PATCH] dt-bndings: iommu: renesas, ipmmu-vmsa: convert to json-schema

[Geert Uytterhoeven]

Hi Shimoda-san,

On Tue, Apr 14, 2020 at 2:26 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Convert Renesas VMSA-Compatible IOMMU bindings documentation
> to json-schema.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
> @@ -0,0 +1,90 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/iommu/renesas,ipmmu-vmsa.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas VMSA-Compatible IOMMU
> +
> +maintainers:
> +  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> +
> +description:
> +  The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables.
> +  It provides address translation for bus masters outside of the CPU, each
> +  connected to the IPMMU through a port called micro-TLB.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - enum:
> +              - renesas,ipmmu-r8a7743  # RZ/G1M
> +              - renesas,ipmmu-r8a7744  # RZ/G1N
> +              - renesas,ipmmu-r8a7745  # RZ/G1E
> +              - renesas,ipmmu-r8a7790  # R-Car H2
> +              - renesas,ipmmu-r8a7791  # R-Car M2-W
> +              - renesas,ipmmu-r8a7793  # R-Car M2-N
> +              - renesas,ipmmu-r8a7794  # R-Car E2
> +              - renesas,ipmmu-r8a7795  # R-Car H3
> +          - const: renesas,ipmmu-vmsa  # R-Car Gen2 or RZ/G1
> +      - items:
> +          - enum:
> +              - renesas,ipmmu-r8a73a4  # R-Mobile APE6

I believe the R-Mobile APE6 IPMMU is similar to the R-Car Gen2 IPMMU,
and thus belongs in the section above instead.

> +              - renesas,ipmmu-r8a774a1 # RZ/G2M
> +              - renesas,ipmmu-r8a774b1 # RZ/G2N
> +              - renesas,ipmmu-r8a774c0 # RZ/G2E
> +              - renesas,ipmmu-r8a7796  # R-Car M3-W
> +              - renesas,ipmmu-r8a77965 # R-Car M3-N
> +              - renesas,ipmmu-r8a77970 # R-Car V3M
> +              - renesas,ipmmu-r8a77980 # R-Car V3H
> +              - renesas,ipmmu-r8a77990 # R-Car E3
> +              - renesas,ipmmu-r8a77995 # R-Car D3
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    minItems: 1
> +    maxItems: 2
> +    description:
> +      Specifiers for the MMU fault interrupts. For instances that support
> +      secure mode two interrupts must be specified, for non-secure and secure
> +      mode, in that order. For instances that don't support secure mode a
> +      single interrupt must be specified. Not required for cache IPMMUs.

    items:
      - description: <non-secure ...>
      - description: <secure ...>

> +
> +  '#iommu-cells':
> +    const: 1
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  renesas,ipmmu-main:
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    description:
> +      Reference to the main IPMMU instance in two cells. The first cell is
> +      a phandle to the main IPMMU and the second cell is the interrupt bit
> +      number associated with the particular cache IPMMU device. The interrupt
> +      bit number needs to match the main IPMMU IMSSTR register. Only used by
> +      cache IPMMU instances.

This property is not valid only on R-Car Gen2 and R-Mobile APE6.

(untested)

oneOf:
  - properties:
      contains:
        const: renesas,ipmmu-vmsa
  - properties:
      renesas,ipmmu-main:
        $ref: /schemas/types.yaml#/definitions/phandle-array
        description:
          [...]

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
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RE: [PATCH] dt-bndings: iommu: renesas,ipmmu-vmsa: convert to json-schema

[Yoshihiro Shimoda]

Hi Geert-san,

Thank you for your review!

> From: Geert Uytterhoeven, Sent: Wednesday, April 15, 2020 11:21 PM
> 
> Hi Shimoda-san,
> 
> On Tue, Apr 14, 2020 at 2:26 AM Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
> > Convert Renesas VMSA-Compatible IOMMU bindings documentation
> > to json-schema.
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> 
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
> > @@ -0,0 +1,90 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/iommu/renesas,ipmmu-vmsa.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Renesas VMSA-Compatible IOMMU
> > +
> > +maintainers:
> > +  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > +
> > +description:
> > +  The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables.
> > +  It provides address translation for bus masters outside of the CPU, each
> > +  connected to the IPMMU through a port called micro-TLB.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - enum:
> > +              - renesas,ipmmu-r8a7743  # RZ/G1M
> > +              - renesas,ipmmu-r8a7744  # RZ/G1N
> > +              - renesas,ipmmu-r8a7745  # RZ/G1E
> > +              - renesas,ipmmu-r8a7790  # R-Car H2
> > +              - renesas,ipmmu-r8a7791  # R-Car M2-W
> > +              - renesas,ipmmu-r8a7793  # R-Car M2-N
> > +              - renesas,ipmmu-r8a7794  # R-Car E2
> > +              - renesas,ipmmu-r8a7795  # R-Car H3
> > +          - const: renesas,ipmmu-vmsa  # R-Car Gen2 or RZ/G1
> > +      - items:
> > +          - enum:
> > +              - renesas,ipmmu-r8a73a4  # R-Mobile APE6
> 
> I believe the R-Mobile APE6 IPMMU is similar to the R-Car Gen2 IPMMU,
> and thus belongs in the section above instead.

I think so.
Since the original document doesn't mention about R-Mobile APE6,
I wrote this here. But, I also think R-Mobile APE6 IPMMU is similar to
the R-Car Gen2 IPMMU. So, I'll change renesas,ipmmu-r8a73a4
to the above section and fix comment of renesas,ipmmu-vmsa

> > +              - renesas,ipmmu-r8a774a1 # RZ/G2M
> > +              - renesas,ipmmu-r8a774b1 # RZ/G2N
> > +              - renesas,ipmmu-r8a774c0 # RZ/G2E
> > +              - renesas,ipmmu-r8a7796  # R-Car M3-W
> > +              - renesas,ipmmu-r8a77965 # R-Car M3-N
> > +              - renesas,ipmmu-r8a77970 # R-Car V3M
> > +              - renesas,ipmmu-r8a77980 # R-Car V3H
> > +              - renesas,ipmmu-r8a77990 # R-Car E3
> > +              - renesas,ipmmu-r8a77995 # R-Car D3
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    minItems: 1
> > +    maxItems: 2
> > +    description:
> > +      Specifiers for the MMU fault interrupts. For instances that support
> > +      secure mode two interrupts must be specified, for non-secure and secure
> > +      mode, in that order. For instances that don't support secure mode a
> > +      single interrupt must be specified. Not required for cache IPMMUs.
> 
>     items:
>       - description: <non-secure ...>
>       - description: <secure ...>

I got it. I'll add items.

> > +
> > +  '#iommu-cells':
> > +    const: 1
> > +
> > +  power-domains:
> > +    maxItems: 1
> > +
> > +  renesas,ipmmu-main:
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    description:
> > +      Reference to the main IPMMU instance in two cells. The first cell is
> > +      a phandle to the main IPMMU and the second cell is the interrupt bit
> > +      number associated with the particular cache IPMMU device. The interrupt
> > +      bit number needs to match the main IPMMU IMSSTR register. Only used by
> > +      cache IPMMU instances.
> 
> This property is not valid only on R-Car Gen2 and R-Mobile APE6.

That sounds good. But, since ipmmu_mm on R-Car Gen3 also is not valid,
we cannot use compatible property for detecting it.

However, I realized renesas,ipmmu-main is only used by "cache IPMMU"
and "cache IPMMU" doesn't have interrupts property. So,
I described the following schema and then it seems success.
--
if:
  properties:
    interrupts: false
then:
  required:
    - renesas,ipmmu-main
--

Especially, I could find missing renesas,ipmmu-main property on r8a77980.dtsi
like below :)  So, I'll make and submit a fixing r8a77980.dtsi patch later (maybe tomorrow).

  CHECK   arch/arm64/boot/dts/renesas/r8a77980-condor.dt.yaml
/opt/home/shimoda/workdir/json-schema/arch/arm64/boot/dts/renesas/r8a77980-condor.dt.yaml: mmu@e7b00000: 'renesas,ipmmu-main' is a required property
/opt/home/shimoda/workdir/json-schema/arch/arm64/boot/dts/renesas/r8a77980-condor.dt.yaml: mmu@e7960000: 'renesas,ipmmu-main' is a required property

Best regards,
Yoshihiro Shimoda

> (untested)
> 
> oneOf:
>   - properties:
>       contains:
>         const: renesas,ipmmu-vmsa
>   - properties:
>       renesas,ipmmu-main:
>         $ref: /schemas/types.yaml#/definitions/phandle-array
>         description:
>           [...]
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds
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Re: [PATCH] dt-bndings: iommu: renesas, ipmmu-vmsa: convert to json-schema

[Geert Uytterhoeven]

Hi Shimoda-san,

On Thu, Apr 16, 2020 at 11:56 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> > From: Geert Uytterhoeven, Sent: Wednesday, April 15, 2020 11:21 PM
> > On Tue, Apr 14, 2020 at 2:26 AM Yoshihiro Shimoda
> > <yoshihiro.shimoda.uh@renesas.com> wrote:
> > > Convert Renesas VMSA-Compatible IOMMU bindings documentation
> > > to json-schema.
> > >
> > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> >
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml

> > > +  renesas,ipmmu-main:
> > > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > > +    description:
> > > +      Reference to the main IPMMU instance in two cells. The first cell is
> > > +      a phandle to the main IPMMU and the second cell is the interrupt bit
> > > +      number associated with the particular cache IPMMU device. The interrupt
> > > +      bit number needs to match the main IPMMU IMSSTR register. Only used by
> > > +      cache IPMMU instances.
> >
> > This property is not valid only on R-Car Gen2 and R-Mobile APE6.
>
> That sounds good. But, since ipmmu_mm on R-Car Gen3 also is not valid,
> we cannot use compatible property for detecting it.

What do you mean by "ipmmu_mm is not valid"?

> However, I realized renesas,ipmmu-main is only used by "cache IPMMU"
> and "cache IPMMU" doesn't have interrupts property. So,
> I described the following schema and then it seems success.
> --
> if:
>   properties:
>     interrupts: false
> then:
>   required:
>     - renesas,ipmmu-main

But all other nodes should have interrupts properties, right?
So they are mutually exclusive:

  oneOf:
     - required:
         - interrupts
    - required:
        - renesas,ipmmu-main

> Especially, I could find missing renesas,ipmmu-main property on r8a77980.dtsi
> like below :)  So, I'll make and submit a fixing r8a77980.dtsi patch later (maybe tomorrow).

Good! ;-)

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
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RE: [PATCH] dt-bndings: iommu: renesas,ipmmu-vmsa: convert to json-schema

[Yoshihiro Shimoda]

Hi Geert-san,

> From: Geert Uytterhoeven, Sent: Thursday, April 16, 2020 7:06 PM
<snip>
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
> 
> > > > +  renesas,ipmmu-main:
> > > > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > > > +    description:
> > > > +      Reference to the main IPMMU instance in two cells. The first cell is
> > > > +      a phandle to the main IPMMU and the second cell is the interrupt bit
> > > > +      number associated with the particular cache IPMMU device. The interrupt
> > > > +      bit number needs to match the main IPMMU IMSSTR register. Only used by
> > > > +      cache IPMMU instances.
> > >
> > > This property is not valid only on R-Car Gen2 and R-Mobile APE6.
> >
> > That sounds good. But, since ipmmu_mm on R-Car Gen3 also is not valid,
> > we cannot use compatible property for detecting it.
> 
> What do you mean by "ipmmu_mm is not valid"?

I just wanted to say that ipmmu_mm node on R-Car Gen3 cannot have
this renesas,ipmmu-main property.

> > However, I realized renesas,ipmmu-main is only used by "cache IPMMU"
> > and "cache IPMMU" doesn't have interrupts property. So,
> > I described the following schema and then it seems success.
> > --
> > if:
> >   properties:
> >     interrupts: false
> > then:
> >   required:
> >     - renesas,ipmmu-main
> 
> But all other nodes should have interrupts properties, right?

Yes, that's right.

> So they are mutually exclusive:
> 
>   oneOf:
>      - required:
>          - interrupts
>     - required:
>         - renesas,ipmmu-main

Thank you! Now I understood it and such the schema is better than mine.
I'll fix it.

> > Especially, I could find missing renesas,ipmmu-main property on r8a77980.dtsi
> > like below :)  So, I'll make and submit a fixing r8a77980.dtsi patch later (maybe tomorrow).
> 
> Good! ;-)

:)

Best regards,
Yoshihiro Shimoda

> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds
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Re: [PATCH] dt-bndings: iommu: renesas,ipmmu-vmsa: convert to json-schema

[Rob Herring]

On Mon, Apr 13, 2020 at 07:25:33PM +0900, Yoshihiro Shimoda wrote:
> Convert Renesas VMSA-Compatible IOMMU bindings documentation
> to json-schema.
> 
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> ---
>  .../bindings/iommu/renesas,ipmmu-vmsa.txt          | 73 ------------------
>  .../bindings/iommu/renesas,ipmmu-vmsa.yaml         | 90 ++++++++++++++++++++++
>  2 files changed, 90 insertions(+), 73 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt
>  create mode 100644 Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
> 
> diff --git a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt
> deleted file mode 100644
> index 020d6f2..00000000
> --- a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt
> +++ /dev/null
> @@ -1,73 +0,0 @@
> -* Renesas VMSA-Compatible IOMMU
> -
> -The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables.
> -It provides address translation for bus masters outside of the CPU, each
> -connected to the IPMMU through a port called micro-TLB.
> -
> -
> -Required Properties:
> -
> -  - compatible: Must contain SoC-specific and generic entry below in case
> -    the device is compatible with the R-Car Gen2 VMSA-compatible IPMMU.
> -
> -    - "renesas,ipmmu-r8a73a4" for the R8A73A4 (R-Mobile APE6) IPMMU.
> -    - "renesas,ipmmu-r8a7743" for the R8A7743 (RZ/G1M) IPMMU.
> -    - "renesas,ipmmu-r8a7744" for the R8A7744 (RZ/G1N) IPMMU.
> -    - "renesas,ipmmu-r8a7745" for the R8A7745 (RZ/G1E) IPMMU.
> -    - "renesas,ipmmu-r8a774a1" for the R8A774A1 (RZ/G2M) IPMMU.
> -    - "renesas,ipmmu-r8a774b1" for the R8A774B1 (RZ/G2N) IPMMU.
> -    - "renesas,ipmmu-r8a774c0" for the R8A774C0 (RZ/G2E) IPMMU.
> -    - "renesas,ipmmu-r8a7790" for the R8A7790 (R-Car H2) IPMMU.
> -    - "renesas,ipmmu-r8a7791" for the R8A7791 (R-Car M2-W) IPMMU.
> -    - "renesas,ipmmu-r8a7793" for the R8A7793 (R-Car M2-N) IPMMU.
> -    - "renesas,ipmmu-r8a7794" for the R8A7794 (R-Car E2) IPMMU.
> -    - "renesas,ipmmu-r8a7795" for the R8A7795 (R-Car H3) IPMMU.
> -    - "renesas,ipmmu-r8a7796" for the R8A7796 (R-Car M3-W) IPMMU.
> -    - "renesas,ipmmu-r8a77965" for the R8A77965 (R-Car M3-N) IPMMU.
> -    - "renesas,ipmmu-r8a77970" for the R8A77970 (R-Car V3M) IPMMU.
> -    - "renesas,ipmmu-r8a77980" for the R8A77980 (R-Car V3H) IPMMU.
> -    - "renesas,ipmmu-r8a77990" for the R8A77990 (R-Car E3) IPMMU.
> -    - "renesas,ipmmu-r8a77995" for the R8A77995 (R-Car D3) IPMMU.
> -    - "renesas,ipmmu-vmsa" for generic R-Car Gen2 or RZ/G1 VMSA-compatible
> -			   IPMMU.
> -
> -  - reg: Base address and size of the IPMMU registers.
> -  - interrupts: Specifiers for the MMU fault interrupts. For instances that
> -    support secure mode two interrupts must be specified, for non-secure and
> -    secure mode, in that order. For instances that don't support secure mode a
> -    single interrupt must be specified. Not required for cache IPMMUs.
> -
> -  - #iommu-cells: Must be 1.
> -
> -Optional properties:
> -
> -  - renesas,ipmmu-main: reference to the main IPMMU instance in two cells.
> -    The first cell is a phandle to the main IPMMU and the second cell is
> -    the interrupt bit number associated with the particular cache IPMMU device.
> -    The interrupt bit number needs to match the main IPMMU IMSSTR register.
> -    Only used by cache IPMMU instances.
> -
> -
> -Each bus master connected to an IPMMU must reference the IPMMU in its device
> -node with the following property:
> -
> -  - iommus: A reference to the IPMMU in two cells. The first cell is a phandle
> -    to the IPMMU and the second cell the number of the micro-TLB that the
> -    device is connected to.
> -
> -
> -Example: R8A7791 IPMMU-MX and VSP1-D0 bus master
> -
> -	ipmmu_mx: mmu@fe951000 {
> -		compatible = "renasas,ipmmu-r8a7791", "renasas,ipmmu-vmsa";
> -		reg = <0 0xfe951000 0 0x1000>;
> -		interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
> -			     <0 221 IRQ_TYPE_LEVEL_HIGH>;
> -		#iommu-cells = <1>;
> -	};
> -
> -	vsp@fe928000 {
> -		...
> -		iommus = <&ipmmu_mx 13>;
> -		...
> -	};
> diff --git a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
> new file mode 100644
> index 00000000..3820b10
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
> @@ -0,0 +1,90 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/iommu/renesas,ipmmu-vmsa.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas VMSA-Compatible IOMMU
> +
> +maintainers:
> +  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> +
> +description:
> +  The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables.
> +  It provides address translation for bus masters outside of the CPU, each
> +  connected to the IPMMU through a port called micro-TLB.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - enum:
> +              - renesas,ipmmu-r8a7743  # RZ/G1M
> +              - renesas,ipmmu-r8a7744  # RZ/G1N
> +              - renesas,ipmmu-r8a7745  # RZ/G1E
> +              - renesas,ipmmu-r8a7790  # R-Car H2
> +              - renesas,ipmmu-r8a7791  # R-Car M2-W
> +              - renesas,ipmmu-r8a7793  # R-Car M2-N
> +              - renesas,ipmmu-r8a7794  # R-Car E2
> +              - renesas,ipmmu-r8a7795  # R-Car H3
> +          - const: renesas,ipmmu-vmsa  # R-Car Gen2 or RZ/G1
> +      - items:
> +          - enum:
> +              - renesas,ipmmu-r8a73a4  # R-Mobile APE6
> +              - renesas,ipmmu-r8a774a1 # RZ/G2M
> +              - renesas,ipmmu-r8a774b1 # RZ/G2N
> +              - renesas,ipmmu-r8a774c0 # RZ/G2E
> +              - renesas,ipmmu-r8a7796  # R-Car M3-W
> +              - renesas,ipmmu-r8a77965 # R-Car M3-N
> +              - renesas,ipmmu-r8a77970 # R-Car V3M
> +              - renesas,ipmmu-r8a77980 # R-Car V3H
> +              - renesas,ipmmu-r8a77990 # R-Car E3
> +              - renesas,ipmmu-r8a77995 # R-Car D3
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    minItems: 1
> +    maxItems: 2
> +    description:
> +      Specifiers for the MMU fault interrupts. For instances that support
> +      secure mode two interrupts must be specified, for non-secure and secure
> +      mode, in that order. For instances that don't support secure mode a
> +      single interrupt must be specified. Not required for cache IPMMUs.
> +
> +  '#iommu-cells':
> +    const: 1
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  renesas,ipmmu-main:
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    description:
> +      Reference to the main IPMMU instance in two cells. The first cell is
> +      a phandle to the main IPMMU and the second cell is the interrupt bit

The cell counting is wrong here. We don't count the phandle as a cell. 
It's a 'phandle plus 1 cell'.

Same goes for 'iommus'.

> +      number associated with the particular cache IPMMU device. The interrupt
> +      bit number needs to match the main IPMMU IMSSTR register. Only used by
> +      cache IPMMU instances.
> +
> +required:
> +  - compatible
> +  - reg
> +  - '#iommu-cells'
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/power/r8a7791-sysc.h>
> +
> +    ipmmu_mx: mmu@fe951000 {

iommu@...

> +        compatible = "renasas,ipmmu-r8a7791", "renasas,ipmmu-vmsa";
> +        reg = <0xfe951000 0x1000>;
> +        interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
> +        #iommu-cells = <1>;
> +    };
> -- 
> 2.7.4
> 
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RE: [PATCH] dt-bndings: iommu: renesas,ipmmu-vmsa: convert to json-schema

[Yoshihiro Shimoda]

Hi Rob,

Thank you for the review!

> From: Rob Herring, Sent: Tuesday, April 21, 2020 4:27 AM
> 
> On Mon, Apr 13, 2020 at 07:25:33PM +0900, Yoshihiro Shimoda wrote:
> > Convert Renesas VMSA-Compatible IOMMU bindings documentation
> > to json-schema.
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
<snip>
> > diff --git a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
> b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
> > new file mode 100644
> > index 00000000..3820b10
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
> > @@ -0,0 +1,90 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/iommu/renesas,ipmmu-vmsa.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Renesas VMSA-Compatible IOMMU
> > +
> > +maintainers:
> > +  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > +
> > +description:
> > +  The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables.
> > +  It provides address translation for bus masters outside of the CPU, each
> > +  connected to the IPMMU through a port called micro-TLB.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - enum:
> > +              - renesas,ipmmu-r8a7743  # RZ/G1M
> > +              - renesas,ipmmu-r8a7744  # RZ/G1N
> > +              - renesas,ipmmu-r8a7745  # RZ/G1E
> > +              - renesas,ipmmu-r8a7790  # R-Car H2
> > +              - renesas,ipmmu-r8a7791  # R-Car M2-W
> > +              - renesas,ipmmu-r8a7793  # R-Car M2-N
> > +              - renesas,ipmmu-r8a7794  # R-Car E2
> > +              - renesas,ipmmu-r8a7795  # R-Car H3
> > +          - const: renesas,ipmmu-vmsa  # R-Car Gen2 or RZ/G1
> > +      - items:
> > +          - enum:
> > +              - renesas,ipmmu-r8a73a4  # R-Mobile APE6
> > +              - renesas,ipmmu-r8a774a1 # RZ/G2M
> > +              - renesas,ipmmu-r8a774b1 # RZ/G2N
> > +              - renesas,ipmmu-r8a774c0 # RZ/G2E
> > +              - renesas,ipmmu-r8a7796  # R-Car M3-W
> > +              - renesas,ipmmu-r8a77965 # R-Car M3-N
> > +              - renesas,ipmmu-r8a77970 # R-Car V3M
> > +              - renesas,ipmmu-r8a77980 # R-Car V3H
> > +              - renesas,ipmmu-r8a77990 # R-Car E3
> > +              - renesas,ipmmu-r8a77995 # R-Car D3
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    minItems: 1
> > +    maxItems: 2
> > +    description:
> > +      Specifiers for the MMU fault interrupts. For instances that support
> > +      secure mode two interrupts must be specified, for non-secure and secure
> > +      mode, in that order. For instances that don't support secure mode a
> > +      single interrupt must be specified. Not required for cache IPMMUs.
> > +
> > +  '#iommu-cells':
> > +    const: 1
> > +
> > +  power-domains:
> > +    maxItems: 1
> > +
> > +  renesas,ipmmu-main:
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    description:
> > +      Reference to the main IPMMU instance in two cells. The first cell is
> > +      a phandle to the main IPMMU and the second cell is the interrupt bit
> 
> The cell counting is wrong here. We don't count the phandle as a cell.
> It's a 'phandle plus 1 cell'.

I got it. I'll fix it.

> Same goes for 'iommus'.

I understood it. I'll also fix '#iommu-cells' description.

> > +      number associated with the particular cache IPMMU device. The interrupt
> > +      bit number needs to match the main IPMMU IMSSTR register. Only used by
> > +      cache IPMMU instances.
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - '#iommu-cells'
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
> > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +    #include <dt-bindings/power/r8a7791-sysc.h>
> > +
> > +    ipmmu_mx: mmu@fe951000 {
> 
> iommu@...

I got it.

BTW, all Renesas related dts files are described as "mmu" now.
So, I'll also fix dts files later. Thank you for the pointed it out!

Best regards,
Yoshihiro Shimoda

> > +        compatible = "renasas,ipmmu-r8a7791", "renasas,ipmmu-vmsa";
> > +        reg = <0xfe951000 0x1000>;
> > +        interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
> > +                     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
> > +        #iommu-cells = <1>;
> > +    };
> > --
> > 2.7.4
> >
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