iommu.lists.linux-foundation.org archive mirror
 help / color / mirror / Atom feed
* [PATCH 0/2] iommu/vt-d: Fixes for v6.0-rc7
@ 2022-09-21  2:40 Lu Baolu
  2022-09-21  2:40 ` [PATCH 1/2] Revert "iommu/vt-d: Fix possible recursive locking in intel_iommu_init()" Lu Baolu
                   ` (2 more replies)
  0 siblings, 3 replies; 4+ messages in thread
From: Lu Baolu @ 2022-09-21  2:40 UTC (permalink / raw)
  To: Joerg Roedel
  Cc: Kevin Tian, Yi Liu, Robin Murphy, George Hilliard, iommu, iommu

Hi Joerg,

Below fixes are queued for v6.0. They aim to fix:

- Check the right capability bit for 5-level page table support.
- Revert a previous patch to avoid regression.

Please consider it for the iommu/fix branch.

Best regards,
Lu Baolu

Lu Baolu (1):
  Revert "iommu/vt-d: Fix possible recursive locking in
    intel_iommu_init()"

Yi Liu (1):
  iommu/vt-d: Check correct capability for sagaw determination

 include/linux/dmar.h        |  4 +---
 drivers/iommu/intel/dmar.c  |  7 -------
 drivers/iommu/intel/iommu.c | 29 ++++++++++++++++++++++++++---
 3 files changed, 27 insertions(+), 13 deletions(-)

-- 
2.34.1


^ permalink raw reply	[flat|nested] 4+ messages in thread

* [PATCH 1/2] Revert "iommu/vt-d: Fix possible recursive locking in intel_iommu_init()"
  2022-09-21  2:40 [PATCH 0/2] iommu/vt-d: Fixes for v6.0-rc7 Lu Baolu
@ 2022-09-21  2:40 ` Lu Baolu
  2022-09-21  2:40 ` [PATCH 2/2] iommu/vt-d: Check correct capability for sagaw determination Lu Baolu
  2022-09-21  8:23 ` [PATCH 0/2] iommu/vt-d: Fixes for v6.0-rc7 Joerg Roedel
  2 siblings, 0 replies; 4+ messages in thread
From: Lu Baolu @ 2022-09-21  2:40 UTC (permalink / raw)
  To: Joerg Roedel
  Cc: Kevin Tian, Yi Liu, Robin Murphy, George Hilliard, iommu, iommu

This reverts commit 9cd4f1434479f1ac25c440c421fbf52069079914.

Some issues were reported on the original commit. Some thunderbolt devices
don't work anymore due to the following DMA fault.

DMAR: DRHD: handling fault status reg 2
DMAR: [INTR-REMAP] Request device [09:00.0] fault index 0x8080
      [fault reason 0x25]
      Blocked a compatibility format interrupt request

Bring it back for now to avoid functional regression.

Fixes: 9cd4f1434479f ("iommu/vt-d: Fix possible recursive locking in intel_iommu_init()")
Link: https://lore.kernel.org/linux-iommu/485A6EA5-6D58-42EA-B298-8571E97422DE@getmailspring.com/
Link: https://bugzilla.kernel.org/show_bug.cgi?id=216497
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: <stable@vger.kernel.org> # 5.19.x
Reported-and-tested-by: George Hilliard <thirtythreeforty@gmail.com>
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Link: https://lore.kernel.org/r/20220920081701.3453504-1-baolu.lu@linux.intel.com
---
 include/linux/dmar.h        |  4 +---
 drivers/iommu/intel/dmar.c  |  7 -------
 drivers/iommu/intel/iommu.c | 27 +++++++++++++++++++++++++--
 3 files changed, 26 insertions(+), 12 deletions(-)

diff --git a/include/linux/dmar.h b/include/linux/dmar.h
index 8917a32173c4..d81a51978d01 100644
--- a/include/linux/dmar.h
+++ b/include/linux/dmar.h
@@ -65,7 +65,6 @@ struct dmar_pci_notify_info {
 
 extern struct rw_semaphore dmar_global_lock;
 extern struct list_head dmar_drhd_units;
-extern int intel_iommu_enabled;
 
 #define for_each_drhd_unit(drhd)					\
 	list_for_each_entry_rcu(drhd, &dmar_drhd_units, list,		\
@@ -89,8 +88,7 @@ extern int intel_iommu_enabled;
 static inline bool dmar_rcu_check(void)
 {
 	return rwsem_is_locked(&dmar_global_lock) ||
-	       system_state == SYSTEM_BOOTING ||
-	       (IS_ENABLED(CONFIG_INTEL_IOMMU) && !intel_iommu_enabled);
+	       system_state == SYSTEM_BOOTING;
 }
 
 #define	dmar_rcu_dereference(p)	rcu_dereference_check((p), dmar_rcu_check())
diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c
index 497c912ad9e1..5a8f780e7ffd 100644
--- a/drivers/iommu/intel/dmar.c
+++ b/drivers/iommu/intel/dmar.c
@@ -2349,13 +2349,6 @@ static int dmar_device_hotplug(acpi_handle handle, bool insert)
 	if (!dmar_in_use())
 		return 0;
 
-	/*
-	 * It's unlikely that any I/O board is hot added before the IOMMU
-	 * subsystem is initialized.
-	 */
-	if (IS_ENABLED(CONFIG_INTEL_IOMMU) && !intel_iommu_enabled)
-		return -EOPNOTSUPP;
-
 	if (dmar_detect_dsm(handle, DMAR_DSM_FUNC_DRHD)) {
 		tmp = handle;
 	} else {
diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index 1f2cd43cf9bc..64d30895a4c8 100644
--- a/drivers/iommu/intel/iommu.c
+++ b/drivers/iommu/intel/iommu.c
@@ -3019,7 +3019,13 @@ static int __init init_dmars(void)
 
 #ifdef CONFIG_INTEL_IOMMU_SVM
 		if (pasid_supported(iommu) && ecap_prs(iommu->ecap)) {
+			/*
+			 * Call dmar_alloc_hwirq() with dmar_global_lock held,
+			 * could cause possible lock race condition.
+			 */
+			up_write(&dmar_global_lock);
 			ret = intel_svm_enable_prq(iommu);
+			down_write(&dmar_global_lock);
 			if (ret)
 				goto free_iommu;
 		}
@@ -3932,6 +3938,7 @@ int __init intel_iommu_init(void)
 	force_on = (!intel_iommu_tboot_noforce && tboot_force_iommu()) ||
 		    platform_optin_force_iommu();
 
+	down_write(&dmar_global_lock);
 	if (dmar_table_init()) {
 		if (force_on)
 			panic("tboot: Failed to initialize DMAR table\n");
@@ -3944,6 +3951,16 @@ int __init intel_iommu_init(void)
 		goto out_free_dmar;
 	}
 
+	up_write(&dmar_global_lock);
+
+	/*
+	 * The bus notifier takes the dmar_global_lock, so lockdep will
+	 * complain later when we register it under the lock.
+	 */
+	dmar_register_bus_notifier();
+
+	down_write(&dmar_global_lock);
+
 	if (!no_iommu)
 		intel_iommu_debugfs_init();
 
@@ -3988,9 +4005,11 @@ int __init intel_iommu_init(void)
 		pr_err("Initialization failed\n");
 		goto out_free_dmar;
 	}
+	up_write(&dmar_global_lock);
 
 	init_iommu_pm_ops();
 
+	down_read(&dmar_global_lock);
 	for_each_active_iommu(iommu, drhd) {
 		/*
 		 * The flush queue implementation does not perform
@@ -4008,11 +4027,13 @@ int __init intel_iommu_init(void)
 				       "%s", iommu->name);
 		iommu_device_register(&iommu->iommu, &intel_iommu_ops, NULL);
 	}
+	up_read(&dmar_global_lock);
 
 	bus_set_iommu(&pci_bus_type, &intel_iommu_ops);
 	if (si_domain && !hw_pass_through)
 		register_memory_notifier(&intel_iommu_memory_nb);
 
+	down_read(&dmar_global_lock);
 	if (probe_acpi_namespace_devices())
 		pr_warn("ACPI name space devices didn't probe correctly\n");
 
@@ -4023,15 +4044,17 @@ int __init intel_iommu_init(void)
 
 		iommu_disable_protect_mem_regions(iommu);
 	}
+	up_read(&dmar_global_lock);
 
-	intel_iommu_enabled = 1;
-	dmar_register_bus_notifier();
 	pr_info("Intel(R) Virtualization Technology for Directed I/O\n");
 
+	intel_iommu_enabled = 1;
+
 	return 0;
 
 out_free_dmar:
 	intel_iommu_free_dmars();
+	up_write(&dmar_global_lock);
 	return ret;
 }
 
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 4+ messages in thread

* [PATCH 2/2] iommu/vt-d: Check correct capability for sagaw determination
  2022-09-21  2:40 [PATCH 0/2] iommu/vt-d: Fixes for v6.0-rc7 Lu Baolu
  2022-09-21  2:40 ` [PATCH 1/2] Revert "iommu/vt-d: Fix possible recursive locking in intel_iommu_init()" Lu Baolu
@ 2022-09-21  2:40 ` Lu Baolu
  2022-09-21  8:23 ` [PATCH 0/2] iommu/vt-d: Fixes for v6.0-rc7 Joerg Roedel
  2 siblings, 0 replies; 4+ messages in thread
From: Lu Baolu @ 2022-09-21  2:40 UTC (permalink / raw)
  To: Joerg Roedel
  Cc: Kevin Tian, Yi Liu, Robin Murphy, George Hilliard, iommu, iommu

From: Yi Liu <yi.l.liu@intel.com>

Check 5-level paging capability for 57 bits address width instead of
checking 1GB large page capability.

Fixes: 53fc7ad6edf2 ("iommu/vt-d: Correctly calculate sagaw value of IOMMU")
Cc: stable@vger.kernel.org
Reported-by: Raghunathan Srinivasan <raghunathan.srinivasan@intel.com>
Signed-off-by: Yi Liu <yi.l.liu@intel.com>
Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Reviewed-by: Raghunathan Srinivasan <raghunathan.srinivasan@intel.com>
Link: https://lore.kernel.org/r/20220916071212.2223869-2-yi.l.liu@intel.com
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
---
 drivers/iommu/intel/iommu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index 64d30895a4c8..31bc50e538a3 100644
--- a/drivers/iommu/intel/iommu.c
+++ b/drivers/iommu/intel/iommu.c
@@ -399,7 +399,7 @@ static unsigned long __iommu_calculate_sagaw(struct intel_iommu *iommu)
 {
 	unsigned long fl_sagaw, sl_sagaw;
 
-	fl_sagaw = BIT(2) | (cap_fl1gp_support(iommu->cap) ? BIT(3) : 0);
+	fl_sagaw = BIT(2) | (cap_5lp_support(iommu->cap) ? BIT(3) : 0);
 	sl_sagaw = cap_sagaw(iommu->cap);
 
 	/* Second level only. */
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 4+ messages in thread

* Re: [PATCH 0/2] iommu/vt-d: Fixes for v6.0-rc7
  2022-09-21  2:40 [PATCH 0/2] iommu/vt-d: Fixes for v6.0-rc7 Lu Baolu
  2022-09-21  2:40 ` [PATCH 1/2] Revert "iommu/vt-d: Fix possible recursive locking in intel_iommu_init()" Lu Baolu
  2022-09-21  2:40 ` [PATCH 2/2] iommu/vt-d: Check correct capability for sagaw determination Lu Baolu
@ 2022-09-21  8:23 ` Joerg Roedel
  2 siblings, 0 replies; 4+ messages in thread
From: Joerg Roedel @ 2022-09-21  8:23 UTC (permalink / raw)
  To: Lu Baolu; +Cc: Kevin Tian, Yi Liu, Robin Murphy, George Hilliard, iommu, iommu

On Wed, Sep 21, 2022 at 10:40:52AM +0800, Lu Baolu wrote:
> Lu Baolu (1):
>   Revert "iommu/vt-d: Fix possible recursive locking in
>     intel_iommu_init()"
> 
> Yi Liu (1):
>   iommu/vt-d: Check correct capability for sagaw determination

Applied, thanks Baolu.

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2022-09-21  8:23 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-21  2:40 [PATCH 0/2] iommu/vt-d: Fixes for v6.0-rc7 Lu Baolu
2022-09-21  2:40 ` [PATCH 1/2] Revert "iommu/vt-d: Fix possible recursive locking in intel_iommu_init()" Lu Baolu
2022-09-21  2:40 ` [PATCH 2/2] iommu/vt-d: Check correct capability for sagaw determination Lu Baolu
2022-09-21  8:23 ` [PATCH 0/2] iommu/vt-d: Fixes for v6.0-rc7 Joerg Roedel

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).