From: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Rohit Agarwal <quic_rohiagar@quicinc.com>,
agross@kernel.org, andersson@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
rafael@kernel.org, viresh.kumar@linaro.org, tglx@linutronix.de,
maz@kernel.org, will@kernel.org, robin.murphy@arm.com,
joro@8bytes.org, mani@kernel.org, robimarko@gmail.com
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev
Subject: Re: [PATCH v2 10/10] arm64: dts: qcom: Add the support of cpufreq on SDX75
Date: Mon, 5 Jun 2023 20:21:39 +0200 [thread overview]
Message-ID: <c4f34ad1-bea7-c5cf-dca8-9ededeafa4b4@linaro.org> (raw)
In-Reply-To: <1685982557-28326-11-git-send-email-quic_rohiagar@quicinc.com>
On 5.06.2023 18:29, Rohit Agarwal wrote:
> Add the support of cpufreq to enable the cpufreq scaling
> on SDX75 SoC. Also add CPU specific information to build
> energy model for EAS.
>
> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/sdx75.dtsi | 30 ++++++++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi
> index 47170ae..e1887a4 100644
> --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi
> @@ -47,10 +47,14 @@
> device_type = "cpu";
> compatible = "arm,cortex-a55";
> reg = <0x0 0x0>;
> + clocks = <&cpufreq_hw 0>;
> enable-method = "psci";
> power-domains = <&CPU_PD0>;
> power-domain-names = "psci";
> next-level-cache = <&L2_0>;
> + qcom,freq-domain = <&cpufreq_hw 0>;
> + capacity-dmips-mhz = <1024>;
> + dynamic-power-coefficient = <100>;
> L2_0: l2-cache {
> compatible = "cache";
> next-level-cache = <&L3_0>;
> @@ -64,10 +68,14 @@
> device_type = "cpu";
> compatible = "arm,cortex-a55";
> reg = <0x0 0x100>;
> + clocks = <&cpufreq_hw 0>;
> enable-method = "psci";
> power-domains = <&CPU_PD1>;
> power-domain-names = "psci";
> next-level-cache = <&L2_100>;
> + qcom,freq-domain = <&cpufreq_hw 0>;
> + capacity-dmips-mhz = <1024>;
> + dynamic-power-coefficient = <100>;
> L2_100: l2-cache {
> compatible = "cache";
> next-level-cache = <&L3_0>;
> @@ -78,10 +86,14 @@
> device_type = "cpu";
> compatible = "arm,cortex-a55";
> reg = <0x0 0x200>;
> + clocks = <&cpufreq_hw 0>;
> enable-method = "psci";
> power-domains = <&CPU_PD2>;
> power-domain-names = "psci";
> next-level-cache = <&L2_200>;
> + qcom,freq-domain = <&cpufreq_hw 0>;
> + capacity-dmips-mhz = <1024>;
> + dynamic-power-coefficient = <100>;
> L2_200: l2-cache {
> compatible = "cache";
> next-level-cache = <&L3_0>;
> @@ -92,10 +104,14 @@
> device_type = "cpu";
> compatible = "arm,cortex-a55";
> reg = <0x0 0x300>;
> + clocks = <&cpufreq_hw 0>;
> enable-method = "psci";
> power-domains = <&CPU_PD3>;
> power-domain-names = "psci";
> next-level-cache = <&L2_300>;
> + qcom,freq-domain = <&cpufreq_hw 0>;
> + capacity-dmips-mhz = <1024>;
That sounds a bit bogus.. Thinking about it, it sounds bogus on most
platforms we have support for! I guess SM8250 big cores aren't *really*
equally as powerful..
> + dynamic-power-coefficient = <100>;
> L2_300: l2-cache {
> compatible = "cache";
> next-level-cache = <&L3_0>;
> @@ -605,6 +621,20 @@
> };
>
> };
> +
> + cpufreq_hw: cpufreq@17d91000 {
> + compatible = "qcom,sdx75-cpufreq-epss", "qcom,cpufreq-epss";
> + reg = <0 0x17d91000 0 0x1000>;
You used 0x0 instead of 0 everywhere else, please do so here as well
to keep things consistent.
With that:
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> + reg-names = "freq-domain0";
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GPLL0>;
> + clock-names = "xo",
> + "alternate";
> + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "dcvsh-irq-0";
> + #freq-domain-cells = <1>;
> + #clock-cells = <1>;
> + };
> };
>
> timer {
next prev parent reply other threads:[~2023-06-05 18:21 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-05 16:29 [PATCH v2 00/10] Add devicetree support for SDX75 Modem and IDP Rohit Agarwal
2023-06-05 16:29 ` [PATCH v2 01/10] dt-bindings: arm: qcom: Document SDX75 platform and boards Rohit Agarwal
2023-06-05 16:29 ` [PATCH v2 02/10] dt-bindings: firmware: scm: Add compatible for SDX75 Rohit Agarwal
2023-06-05 16:29 ` [PATCH v2 03/10] dt-bindings: interrupt-controller: Add SDX75 PDC compatible Rohit Agarwal
2023-06-05 16:29 ` [PATCH v2 04/10] dt-bindings: arm-smmu: Add SDX75 SMMU compatible Rohit Agarwal
2023-06-05 16:29 ` [PATCH v2 05/10] dt-bindings: cpufreq: cpufreq-qcom-hw: Add SDX75 compatible Rohit Agarwal
2023-06-06 5:09 ` Viresh Kumar
2023-06-06 6:04 ` Krzysztof Kozlowski
2023-06-05 16:29 ` [PATCH v2 06/10] arm64: dts: qcom: Add SDX75 platform and IDP board support Rohit Agarwal
2023-06-05 18:15 ` Konrad Dybcio
2023-06-06 8:04 ` Rohit Agarwal
2023-06-06 9:36 ` Konrad Dybcio
2023-06-06 11:42 ` Rohit Agarwal
2023-06-06 12:18 ` Konrad Dybcio
2023-06-07 7:01 ` Rohit Agarwal
[not found] ` <ffaa2700-27d1-f406-bcef-ac042ad1af61@quicinc.com>
2023-06-07 8:43 ` Konrad Dybcio
2023-06-07 8:51 ` Rohit Agarwal
2023-06-05 16:29 ` [PATCH v2 07/10] arm64: dts: qcom: Add support for GCC and RPMHCC for SDX75 Rohit Agarwal
2023-06-05 18:16 ` Konrad Dybcio
2023-06-05 18:30 ` Dmitry Baryshkov
2023-06-06 6:45 ` Rohit Agarwal
2023-06-05 16:29 ` [PATCH v2 08/10] arm64: dts: qcom: Add QUPv3 UART console node " Rohit Agarwal
2023-06-05 18:17 ` Konrad Dybcio
2023-06-06 8:06 ` Rohit Agarwal
2023-06-06 6:06 ` Krzysztof Kozlowski
2023-06-06 6:33 ` Rohit Agarwal
2023-06-05 16:29 ` [PATCH v2 09/10] arm64: dts: qcom: Enable the QUPv3 UART console " Rohit Agarwal
2023-06-06 6:06 ` Krzysztof Kozlowski
2023-06-05 16:29 ` [PATCH v2 10/10] arm64: dts: qcom: Add the support of cpufreq on SDX75 Rohit Agarwal
2023-06-05 18:21 ` Konrad Dybcio [this message]
2023-06-06 9:32 ` Pavan Kondeti
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=c4f34ad1-bea7-c5cf-dca8-9ededeafa4b4@linaro.org \
--to=konrad.dybcio@linaro.org \
--cc=agross@kernel.org \
--cc=andersson@kernel.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=iommu@lists.linux.dev \
--cc=joro@8bytes.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pm@vger.kernel.org \
--cc=mani@kernel.org \
--cc=maz@kernel.org \
--cc=quic_rohiagar@quicinc.com \
--cc=rafael@kernel.org \
--cc=robh+dt@kernel.org \
--cc=robimarko@gmail.com \
--cc=robin.murphy@arm.com \
--cc=tglx@linutronix.de \
--cc=viresh.kumar@linaro.org \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).