* [PATCH v6 01/12] dt-bindings: display/msm: dsi-controller-main: Add SM6350
2023-06-06 12:43 [PATCH v6 00/12] SM63(50|75) DPU support Konrad Dybcio
@ 2023-06-06 12:43 ` Konrad Dybcio
2023-06-06 12:43 ` [PATCH v6 02/12] dt-bindings: display/msm: dsi-controller-main: Add SM6375 Konrad Dybcio
` (12 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Konrad Dybcio @ 2023-06-06 12:43 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
Conor Dooley
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio,
Rob Herring
Add the DSI host found on SM6350.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
index 660e0f496826..8081ced7b297 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
@@ -27,6 +27,7 @@ properties:
- qcom,sdm660-dsi-ctrl
- qcom,sdm845-dsi-ctrl
- qcom,sm6115-dsi-ctrl
+ - qcom,sm6350-dsi-ctrl
- qcom,sm8150-dsi-ctrl
- qcom,sm8250-dsi-ctrl
- qcom,sm8350-dsi-ctrl
@@ -299,6 +300,7 @@ allOf:
contains:
enum:
- qcom,msm8998-dsi-ctrl
+ - qcom,sm6350-dsi-ctrl
then:
properties:
clocks:
--
2.40.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v6 02/12] dt-bindings: display/msm: dsi-controller-main: Add SM6375
2023-06-06 12:43 [PATCH v6 00/12] SM63(50|75) DPU support Konrad Dybcio
2023-06-06 12:43 ` [PATCH v6 01/12] dt-bindings: display/msm: dsi-controller-main: Add SM6350 Konrad Dybcio
@ 2023-06-06 12:43 ` Konrad Dybcio
2023-06-06 12:43 ` [PATCH v6 03/12] dt-bindings: display/msm: sc7180-dpu: Describe SM6350 and SM6375 Konrad Dybcio
` (11 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Konrad Dybcio @ 2023-06-06 12:43 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
Conor Dooley
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio,
Rob Herring
Add the DSI host found on SM6375.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
index 8081ced7b297..01848bdd5873 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
@@ -28,6 +28,7 @@ properties:
- qcom,sdm845-dsi-ctrl
- qcom,sm6115-dsi-ctrl
- qcom,sm6350-dsi-ctrl
+ - qcom,sm6375-dsi-ctrl
- qcom,sm8150-dsi-ctrl
- qcom,sm8250-dsi-ctrl
- qcom,sm8350-dsi-ctrl
@@ -368,6 +369,7 @@ allOf:
enum:
- qcom,sdm845-dsi-ctrl
- qcom,sm6115-dsi-ctrl
+ - qcom,sm6375-dsi-ctrl
then:
properties:
clocks:
--
2.40.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v6 03/12] dt-bindings: display/msm: sc7180-dpu: Describe SM6350 and SM6375
2023-06-06 12:43 [PATCH v6 00/12] SM63(50|75) DPU support Konrad Dybcio
2023-06-06 12:43 ` [PATCH v6 01/12] dt-bindings: display/msm: dsi-controller-main: Add SM6350 Konrad Dybcio
2023-06-06 12:43 ` [PATCH v6 02/12] dt-bindings: display/msm: dsi-controller-main: Add SM6375 Konrad Dybcio
@ 2023-06-06 12:43 ` Konrad Dybcio
2023-06-06 12:43 ` [PATCH v6 04/12] dt-bindings: display/msm: Add SM6350 MDSS Konrad Dybcio
` (10 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Konrad Dybcio @ 2023-06-06 12:43 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
Conor Dooley
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio,
Krzysztof Kozlowski
SC7180, SM6350 and SM6375 use a rather similar hw setup for DPU, with
the main exception being that the last one requires an additional
throttle clock.
It is not well understood yet, but failing to toggle it on makes the
display hardware stall and not output any frames.
Document SM6350 and SM6375 DPU.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../bindings/display/msm/qcom,sc7180-dpu.yaml | 23 +++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml
index 1fb8321d9ee8..630b11480496 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml
@@ -13,7 +13,10 @@ $ref: /schemas/display/msm/dpu-common.yaml#
properties:
compatible:
- const: qcom,sc7180-dpu
+ enum:
+ - qcom,sc7180-dpu
+ - qcom,sm6350-dpu
+ - qcom,sm6375-dpu
reg:
items:
@@ -26,6 +29,7 @@ properties:
- const: vbif
clocks:
+ minItems: 6
items:
- description: Display hf axi clock
- description: Display ahb clock
@@ -33,8 +37,10 @@ properties:
- description: Display lut clock
- description: Display core clock
- description: Display vsync clock
+ - description: Display core throttle clock
clock-names:
+ minItems: 6
items:
- const: bus
- const: iface
@@ -42,6 +48,7 @@ properties:
- const: lut
- const: core
- const: vsync
+ - const: throttle
required:
- compatible
@@ -52,6 +59,20 @@ required:
unevaluatedProperties: false
+allOf:
+ - if:
+ properties:
+ compatible:
+ const: qcom,sm6375-dpu
+
+ then:
+ properties:
+ clocks:
+ minItems: 7
+
+ clock-names:
+ minItems: 7
+
examples:
- |
#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
--
2.40.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v6 04/12] dt-bindings: display/msm: Add SM6350 MDSS
2023-06-06 12:43 [PATCH v6 00/12] SM63(50|75) DPU support Konrad Dybcio
` (2 preceding siblings ...)
2023-06-06 12:43 ` [PATCH v6 03/12] dt-bindings: display/msm: sc7180-dpu: Describe SM6350 and SM6375 Konrad Dybcio
@ 2023-06-06 12:43 ` Konrad Dybcio
2023-06-07 18:11 ` Krzysztof Kozlowski
2023-06-06 12:43 ` [PATCH v6 05/12] dt-bindings: display/msm: Add SM6375 MDSS Konrad Dybcio
` (9 subsequent siblings)
13 siblings, 1 reply; 20+ messages in thread
From: Konrad Dybcio @ 2023-06-06 12:43 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
Conor Dooley
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
Document the SM6350 MDSS.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../bindings/display/msm/qcom,sm6350-mdss.yaml | 213 +++++++++++++++++++++
1 file changed, 213 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml
new file mode 100644
index 000000000000..ed0ad194d4ce
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml
@@ -0,0 +1,213 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm6350-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM6350 Display MDSS
+
+maintainers:
+ - Krishna Manikandan <quic_mkrishn@quicinc.com>
+
+description:
+ SM6350 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
+ like DPU display controller, DSI and DP interfaces etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+ const: qcom,sm6350-mdss
+
+ clocks:
+ items:
+ - description: Display AHB clock from gcc
+ - description: Display AXI clock from gcc
+ - description: Display core clock
+
+ clock-names:
+ items:
+ - const: iface
+ - const: bus
+ - const: core
+
+ iommus:
+ maxItems: 1
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ maxItems: 2
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,sm6350-dpu
+
+ "^dsi@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ items:
+ - const: qcom,sm6350-dsi-ctrl
+ - const: qcom,mdss-dsi-ctrl
+
+ "^phy@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,dsi-phy-10nm
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dispcc-sm6350.h>
+ #include <dt-bindings/clock/qcom,gcc-sm6350.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ display-subsystem@ae00000 {
+ compatible = "qcom,sm6350-mdss";
+ reg = <0x0ae00000 0x1000>;
+ reg-names = "mdss";
+
+ power-domains = <&dispcc MDSS_GDSC>;
+
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&gcc GCC_DISP_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "bus", "core";
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x800 0x2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ display-controller@ae01000 {
+ compatible = "qcom,sm6350-dpu";
+ reg = <0x0ae01000 0x8f000>,
+ <0x0aeb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus", "iface", "rot", "lut", "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>;
+ assigned-clock-rates = <300000000>,
+ <19200000>,
+ <19200000>,
+ <19200000>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmhpd SM6350_CX>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf2_out: endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+ };
+
+ dsi@ae94000 {
+ compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0x0ae94000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd SM6350_MX>;
+
+ phys = <&dsi0_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ dsi0_phy: phy@ae94400 {
+ compatible = "qcom,dsi-phy-10nm";
+ reg = <0x0ae94400 0x200>,
+ <0x0ae94600 0x280>,
+ <0x0ae94a00 0x1e0>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+ };
+ };
+...
--
2.40.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH v6 04/12] dt-bindings: display/msm: Add SM6350 MDSS
2023-06-06 12:43 ` [PATCH v6 04/12] dt-bindings: display/msm: Add SM6350 MDSS Konrad Dybcio
@ 2023-06-07 18:11 ` Krzysztof Kozlowski
0 siblings, 0 replies; 20+ messages in thread
From: Krzysztof Kozlowski @ 2023-06-07 18:11 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, Abhinav Kumar, Dmitry Baryshkov,
Sean Paul, David Airlie, Daniel Vetter, Rob Herring,
Krzysztof Kozlowski, Krishna Manikandan, Will Deacon,
Robin Murphy, Joerg Roedel, Conor Dooley
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu
On 06/06/2023 14:43, Konrad Dybcio wrote:
> Document the SM6350 MDSS.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../bindings/display/msm/qcom,sm6350-mdss.yaml | 213 +++++++++++++++++++++
> 1 file changed, 213 insertions(+)
>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v6 05/12] dt-bindings: display/msm: Add SM6375 MDSS
2023-06-06 12:43 [PATCH v6 00/12] SM63(50|75) DPU support Konrad Dybcio
` (3 preceding siblings ...)
2023-06-06 12:43 ` [PATCH v6 04/12] dt-bindings: display/msm: Add SM6350 MDSS Konrad Dybcio
@ 2023-06-06 12:43 ` Konrad Dybcio
2023-06-07 18:11 ` Krzysztof Kozlowski
2023-06-06 12:43 ` [PATCH v6 06/12] drm/msm/dpu: Add SM6350 support Konrad Dybcio
` (8 subsequent siblings)
13 siblings, 1 reply; 20+ messages in thread
From: Konrad Dybcio @ 2023-06-06 12:43 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
Conor Dooley
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
Document the SM6375 MDSS.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../bindings/display/msm/qcom,sm6375-mdss.yaml | 215 +++++++++++++++++++++
1 file changed, 215 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml
new file mode 100644
index 000000000000..76369a4f7c4d
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml
@@ -0,0 +1,215 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm6375-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM6375 Display MDSS
+
+maintainers:
+ - Konrad Dybcio <konrad.dybcio@linaro.org>
+
+description:
+ SM6375 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
+ like DPU display controller, DSI and DP interfaces etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+ const: qcom,sm6375-mdss
+
+ clocks:
+ items:
+ - description: Display AHB clock from gcc
+ - description: Display AHB clock
+ - description: Display core clock
+
+ clock-names:
+ items:
+ - const: iface
+ - const: ahb
+ - const: core
+
+ iommus:
+ maxItems: 1
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ maxItems: 2
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,sm6375-dpu
+
+ "^dsi@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ items:
+ - const: qcom,sm6375-dsi-ctrl
+ - const: qcom,mdss-dsi-ctrl
+
+ "^phy@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,sm6375-dsi-phy-7nm
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmcc.h>
+ #include <dt-bindings/clock/qcom,sm6375-gcc.h>
+ #include <dt-bindings/clock/qcom,sm6375-dispcc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ display-subsystem@5e00000 {
+ compatible = "qcom,sm6375-mdss";
+ reg = <0x05e00000 0x1000>;
+ reg-names = "mdss";
+
+ power-domains = <&dispcc MDSS_GDSC>;
+
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "ahb", "core";
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x820 0x2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ display-controller@5e01000 {
+ compatible = "qcom,sm6375-dpu";
+ reg = <0x05e01000 0x8e030>,
+ <0x05eb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
+ <&gcc GCC_DISP_THROTTLE_CORE_CLK>;
+ clock-names = "bus",
+ "iface",
+ "rot",
+ "lut",
+ "core",
+ "vsync",
+ "throttle";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmpd SM6375_VDDCX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf2_out: endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+ };
+
+ dsi@5e94000 {
+ compatible = "qcom,sm6375-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0x05e94000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmpd SM6375_VDDMX>;
+
+ phys = <&mdss_dsi0_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss_dsi0_phy: phy@5e94400 {
+ compatible = "qcom,sm6375-dsi-phy-7nm";
+ reg = <0x05e94400 0x200>,
+ <0x05e94600 0x280>,
+ <0x05e94900 0x264>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "iface", "ref";
+ };
+ };
+...
--
2.40.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH v6 05/12] dt-bindings: display/msm: Add SM6375 MDSS
2023-06-06 12:43 ` [PATCH v6 05/12] dt-bindings: display/msm: Add SM6375 MDSS Konrad Dybcio
@ 2023-06-07 18:11 ` Krzysztof Kozlowski
0 siblings, 0 replies; 20+ messages in thread
From: Krzysztof Kozlowski @ 2023-06-07 18:11 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, Abhinav Kumar, Dmitry Baryshkov,
Sean Paul, David Airlie, Daniel Vetter, Rob Herring,
Krzysztof Kozlowski, Krishna Manikandan, Will Deacon,
Robin Murphy, Joerg Roedel, Conor Dooley
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu
On 06/06/2023 14:43, Konrad Dybcio wrote:
> Document the SM6375 MDSS.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../bindings/display/msm/qcom,sm6375-mdss.yaml | 215 +++++++++++++++++++++
> 1 file changed, 215 insertions(+)
>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v6 06/12] drm/msm/dpu: Add SM6350 support
2023-06-06 12:43 [PATCH v6 00/12] SM63(50|75) DPU support Konrad Dybcio
` (4 preceding siblings ...)
2023-06-06 12:43 ` [PATCH v6 05/12] dt-bindings: display/msm: Add SM6375 MDSS Konrad Dybcio
@ 2023-06-06 12:43 ` Konrad Dybcio
2023-06-06 12:43 ` [PATCH v6 07/12] drm/msm: mdss: " Konrad Dybcio
` (7 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Konrad Dybcio @ 2023-06-06 12:43 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
Conor Dooley
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio,
Konrad Dybcio
Add SM6350 support to the DPU1 driver to enable display output.
It's worth noting that one entry dpu_qos_lut_entry was trimmed off:
{.fl = 0, .lut = 0x0011223344556677 },
due to the lack of support for selecting between portrait and landscape
LUT settings (for danger and safe LUTs) and no full support for
qseed/non-qseed usescases (for QoS LUT).
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 173 +++++++++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 5 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
4 files changed, 180 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
new file mode 100644
index 000000000000..06eba23b0236
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -0,0 +1,173 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef _DPU_6_4_SM6350_H
+#define _DPU_6_4_SM6350_H
+
+static const struct dpu_caps sm6350_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0x7,
+ .qseed_type = DPU_SSPP_SCALER_QSEED4,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
+static const struct dpu_ubwc_cfg sm6350_ubwc_cfg = {
+ .ubwc_version = DPU_HW_UBWC_VER_20,
+ .ubwc_swizzle = 6,
+ .highest_bank_bit = 1,
+};
+
+static const struct dpu_mdp_cfg sm6350_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x494,
+ .features = 0,
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
+ },
+};
+
+static const struct dpu_ctl_cfg sm6350_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+ {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x1200, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ },
+ {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x1400, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ },
+ {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x1600, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ },
+};
+
+static const struct dpu_sspp_cfg sm6350_sspp[] = {
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
+ sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
+ sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
+ SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
+ sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
+ SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
+ sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
+};
+
+static const struct dpu_lm_cfg sm6350_lm[] = {
+ LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
+ &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
+ LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
+ &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
+};
+
+static const struct dpu_dspp_cfg sm6350_dspp[] = {
+ DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
+ &sm8150_dspp_sblk),
+};
+
+static struct dpu_pingpong_cfg sm6350_pp[] = {
+ PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ -1),
+ PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+ -1),
+};
+
+static const struct dpu_dsc_cfg sm6350_dsc[] = {
+ DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)),
+};
+
+static const struct dpu_intf_cfg sm6350_intf[] = {
+ INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 35, INTF_SC7180_MASK,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
+ INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 35, INTF_SC7180_MASK,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+ DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
+};
+
+static const struct dpu_perf_cfg sm6350_perf_data = {
+ .max_bw_low = 4200000,
+ .max_bw_high = 5100000,
+ .min_core_ib = 2500000,
+ .min_llcc_ib = 0,
+ .min_dram_ib = 1600000,
+ .min_prefill_lines = 35,
+ /* TODO: confirm danger_lut_tbl */
+ .danger_lut_tbl = {0xffff, 0xffff, 0x0},
+ .safe_lut_tbl = {0xff00, 0xff00, 0xffff},
+ .qos_lut_tbl = {
+ {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
+ .entries = sm6350_qos_linear_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
+ .entries = sm6350_qos_linear_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
+ .entries = sc7180_qos_nrt
+ },
+ },
+ .cdp_cfg = {
+ {.rd_enable = 1, .wr_enable = 1},
+ {.rd_enable = 1, .wr_enable = 0}
+ },
+ .clk_inefficiency_factor = 105,
+ .bw_inefficiency_factor = 120,
+};
+
+const struct dpu_mdss_cfg dpu_sm6350_cfg = {
+ .caps = &sm6350_dpu_caps,
+ .ubwc = &sm6350_ubwc_cfg,
+ .mdp_count = ARRAY_SIZE(sm6350_mdp),
+ .mdp = sm6350_mdp,
+ .ctl_count = ARRAY_SIZE(sm6350_ctl),
+ .ctl = sm6350_ctl,
+ .sspp_count = ARRAY_SIZE(sm6350_sspp),
+ .sspp = sm6350_sspp,
+ .mixer_count = ARRAY_SIZE(sm6350_lm),
+ .mixer = sm6350_lm,
+ .dspp_count = ARRAY_SIZE(sm6350_dspp),
+ .dspp = sm6350_dspp,
+ .dsc_count = ARRAY_SIZE(sm6350_dsc),
+ .dsc = sm6350_dsc,
+ .pingpong_count = ARRAY_SIZE(sm6350_pp),
+ .pingpong = sm6350_pp,
+ .intf_count = ARRAY_SIZE(sm6350_intf),
+ .intf = sm6350_intf,
+ .vbif_count = ARRAY_SIZE(sdm845_vbif),
+ .vbif = sdm845_vbif,
+ .perf = &sm6350_perf_data,
+ .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
+ BIT(MDP_SSPP_TOP0_INTR2) | \
+ BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+ BIT(MDP_INTF0_INTR) | \
+ BIT(MDP_INTF1_INTR) | \
+ BIT(MDP_INTF1_TEAR_INTR),
+};
+
+#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index f07eab738008..8bf6562f39e8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -689,6 +689,10 @@ static const struct dpu_qos_lut_entry sc7180_qos_linear[] = {
{.fl = 0, .lut = 0x0011222222335777},
};
+static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
+ {.fl = 0, .lut = 0x0011223445566777 },
+};
+
static const struct dpu_qos_lut_entry sm8150_qos_linear[] = {
{.fl = 0, .lut = 0x0011222222223357 },
};
@@ -744,6 +748,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
#include "catalog/dpu_6_0_sm8250.h"
#include "catalog/dpu_6_2_sc7180.h"
#include "catalog/dpu_6_3_sm6115.h"
+#include "catalog/dpu_6_4_sm6350.h"
#include "catalog/dpu_6_5_qcm2290.h"
#include "catalog/dpu_7_0_sm8350.h"
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index d59a9027c4b6..e89edbe0ab98 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -832,6 +832,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;
extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
+extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 613384b8ca0e..190345e94178 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1305,6 +1305,7 @@ static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
{ .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
{ .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
+ { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
{ .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
{ .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
{ .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
--
2.40.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v6 07/12] drm/msm: mdss: Add SM6350 support
2023-06-06 12:43 [PATCH v6 00/12] SM63(50|75) DPU support Konrad Dybcio
` (5 preceding siblings ...)
2023-06-06 12:43 ` [PATCH v6 06/12] drm/msm/dpu: Add SM6350 support Konrad Dybcio
@ 2023-06-06 12:43 ` Konrad Dybcio
2023-06-06 12:43 ` [PATCH v6 08/12] drm/msm/dpu: Add SM6375 support Konrad Dybcio
` (6 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Konrad Dybcio @ 2023-06-06 12:43 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
Conor Dooley
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
Add support for MDSS on SM6350.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/gpu/drm/msm/msm_mdss.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index e8c93731aaa1..4e3a5f0c303c 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -538,6 +538,14 @@ static const struct msm_mdss_data sdm845_data = {
.highest_bank_bit = 2,
};
+static const struct msm_mdss_data sm6350_data = {
+ .ubwc_version = UBWC_2_0,
+ .ubwc_dec_version = UBWC_2_0,
+ .ubwc_swizzle = 6,
+ .ubwc_static = 0x1e,
+ .highest_bank_bit = 1,
+};
+
static const struct msm_mdss_data sm8150_data = {
.ubwc_version = UBWC_3_0,
.ubwc_dec_version = UBWC_3_0,
@@ -571,6 +579,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,sc8180x-mdss", .data = &sc8180x_data },
{ .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data },
{ .compatible = "qcom,sm6115-mdss", .data = &sm6115_data },
+ { .compatible = "qcom,sm6350-mdss", .data = &sm6350_data },
{ .compatible = "qcom,sm8150-mdss", .data = &sm8150_data },
{ .compatible = "qcom,sm8250-mdss", .data = &sm8250_data },
{ .compatible = "qcom,sm8350-mdss", .data = &sm8250_data },
--
2.40.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v6 08/12] drm/msm/dpu: Add SM6375 support
2023-06-06 12:43 [PATCH v6 00/12] SM63(50|75) DPU support Konrad Dybcio
` (6 preceding siblings ...)
2023-06-06 12:43 ` [PATCH v6 07/12] drm/msm: mdss: " Konrad Dybcio
@ 2023-06-06 12:43 ` Konrad Dybcio
2023-06-06 12:44 ` [PATCH v6 09/12] drm/msm: mdss: " Konrad Dybcio
` (5 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Konrad Dybcio @ 2023-06-06 12:43 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
Conor Dooley
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
Add basic SM6375 support to the DPU1 driver to enable display output.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 139 +++++++++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
4 files changed, 142 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
new file mode 100644
index 000000000000..d7aae45e3e66
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
@@ -0,0 +1,139 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef _DPU_6_9_SM6375_H
+#define _DPU_6_9_SM6375_H
+
+static const struct dpu_caps sm6375_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
+ .max_mixer_blendstages = 0x4,
+ .qseed_type = DPU_SSPP_SCALER_QSEED4,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .max_linewidth = 2160,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
+static const struct dpu_ubwc_cfg sm6375_ubwc_cfg = {
+ .ubwc_version = DPU_HW_UBWC_VER_20,
+ .ubwc_swizzle = 6,
+ .highest_bank_bit = 1,
+};
+
+static const struct dpu_mdp_cfg sm6375_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x494,
+ .features = 0,
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ },
+};
+
+static const struct dpu_ctl_cfg sm6375_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+};
+
+static const struct dpu_sspp_cfg sm6375_sspp[] = {
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
+ sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
+ sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
+};
+
+static const struct dpu_lm_cfg sm6375_lm[] = {
+ LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
+ &qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0),
+};
+
+static const struct dpu_dspp_cfg sm6375_dspp[] = {
+ DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
+ &sm8150_dspp_sblk),
+};
+
+static const struct dpu_pingpong_cfg sm6375_pp[] = {
+ PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ -1),
+};
+
+static const struct dpu_dsc_cfg sm6375_dsc[] = {
+ DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)),
+};
+
+static const struct dpu_intf_cfg sm6375_intf[] = {
+ INTF_BLK("intf_0", INTF_0, 0x00000, 0x280, INTF_NONE, 0, 0, 0, 0, 0),
+ INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+ DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
+};
+
+static const struct dpu_perf_cfg sm6375_perf_data = {
+ .max_bw_low = 5200000,
+ .max_bw_high = 6200000,
+ .min_core_ib = 2500000,
+ .min_llcc_ib = 0, /* No LLCC on this SoC */
+ .min_dram_ib = 1600000,
+ .min_prefill_lines = 24,
+ /* TODO: confirm danger_lut_tbl */
+ .danger_lut_tbl = {0xffff, 0xffff, 0x0},
+ .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
+ .qos_lut_tbl = {
+ {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
+ .entries = sm6350_qos_linear_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
+ .entries = sm6350_qos_linear_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
+ .entries = sc7180_qos_nrt
+ },
+ },
+ .cdp_cfg = {
+ {.rd_enable = 1, .wr_enable = 1},
+ {.rd_enable = 1, .wr_enable = 0}
+ },
+ .clk_inefficiency_factor = 105,
+ .bw_inefficiency_factor = 120,
+};
+
+const struct dpu_mdss_cfg dpu_sm6375_cfg = {
+ .caps = &sm6375_dpu_caps,
+ .ubwc = &sm6375_ubwc_cfg,
+ .mdp_count = ARRAY_SIZE(sm6375_mdp),
+ .mdp = sm6375_mdp,
+ .ctl_count = ARRAY_SIZE(sm6375_ctl),
+ .ctl = sm6375_ctl,
+ .sspp_count = ARRAY_SIZE(sm6375_sspp),
+ .sspp = sm6375_sspp,
+ .mixer_count = ARRAY_SIZE(sm6375_lm),
+ .mixer = sm6375_lm,
+ .dspp_count = ARRAY_SIZE(sm6375_dspp),
+ .dspp = sm6375_dspp,
+ .dsc_count = ARRAY_SIZE(sm6375_dsc),
+ .dsc = sm6375_dsc,
+ .pingpong_count = ARRAY_SIZE(sm6375_pp),
+ .pingpong = sm6375_pp,
+ .intf_count = ARRAY_SIZE(sm6375_intf),
+ .intf = sm6375_intf,
+ .vbif_count = ARRAY_SIZE(sdm845_vbif),
+ .vbif = sdm845_vbif,
+ .perf = &sm6375_perf_data,
+ .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
+ BIT(MDP_SSPP_TOP0_INTR2) | \
+ BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+ BIT(MDP_INTF1_INTR) | \
+ BIT(MDP_INTF1_TEAR_INTR),
+};
+
+#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 8bf6562f39e8..b9f1d58a6cac 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -750,6 +750,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
#include "catalog/dpu_6_3_sm6115.h"
#include "catalog/dpu_6_4_sm6350.h"
#include "catalog/dpu_6_5_qcm2290.h"
+#include "catalog/dpu_6_9_sm6375.h"
#include "catalog/dpu_7_0_sm8350.h"
#include "catalog/dpu_7_2_sc7280.h"
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index e89edbe0ab98..ac4a9e73705c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -834,6 +834,7 @@ extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
+extern const struct dpu_mdss_cfg dpu_sm6375_cfg;
extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 190345e94178..aa8499de1b9f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1306,6 +1306,7 @@ static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
{ .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
{ .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
+ { .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, },
{ .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
{ .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
{ .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
--
2.40.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v6 09/12] drm/msm: mdss: Add SM6375 support
2023-06-06 12:43 [PATCH v6 00/12] SM63(50|75) DPU support Konrad Dybcio
` (7 preceding siblings ...)
2023-06-06 12:43 ` [PATCH v6 08/12] drm/msm/dpu: Add SM6375 support Konrad Dybcio
@ 2023-06-06 12:44 ` Konrad Dybcio
2023-06-06 12:44 ` [PATCH v6 10/12] iommu/arm-smmu-qcom: Sort the compatible list alphabetically Konrad Dybcio
` (4 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Konrad Dybcio @ 2023-06-06 12:44 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
Conor Dooley
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
Add support for MDSS on SM6375.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/gpu/drm/msm/msm_mdss.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 4e3a5f0c303c..05648c910c68 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -580,6 +580,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data },
{ .compatible = "qcom,sm6115-mdss", .data = &sm6115_data },
{ .compatible = "qcom,sm6350-mdss", .data = &sm6350_data },
+ { .compatible = "qcom,sm6375-mdss", .data = &sm6350_data },
{ .compatible = "qcom,sm8150-mdss", .data = &sm8150_data },
{ .compatible = "qcom,sm8250-mdss", .data = &sm8250_data },
{ .compatible = "qcom,sm8350-mdss", .data = &sm8250_data },
--
2.40.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v6 10/12] iommu/arm-smmu-qcom: Sort the compatible list alphabetically
2023-06-06 12:43 [PATCH v6 00/12] SM63(50|75) DPU support Konrad Dybcio
` (8 preceding siblings ...)
2023-06-06 12:44 ` [PATCH v6 09/12] drm/msm: mdss: " Konrad Dybcio
@ 2023-06-06 12:44 ` Konrad Dybcio
2023-06-08 21:02 ` Will Deacon
2023-06-06 12:44 ` [PATCH v6 11/12] iommu/arm-smmu-qcom: Add SM6375 DPU compatible Konrad Dybcio
` (3 subsequent siblings)
13 siblings, 1 reply; 20+ messages in thread
From: Konrad Dybcio @ 2023-06-06 12:44 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
Conor Dooley
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
It got broken at some point, fix it up.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index c71afda79d64..3800ab478216 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -251,10 +251,10 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
{ .compatible = "qcom,sc7280-mss-pil" },
{ .compatible = "qcom,sc8180x-mdss" },
{ .compatible = "qcom,sc8280xp-mdss" },
- { .compatible = "qcom,sm8150-mdss" },
- { .compatible = "qcom,sm8250-mdss" },
{ .compatible = "qcom,sdm845-mdss" },
{ .compatible = "qcom,sdm845-mss-pil" },
+ { .compatible = "qcom,sm8150-mdss" },
+ { .compatible = "qcom,sm8250-mdss" },
{ }
};
--
2.40.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH v6 10/12] iommu/arm-smmu-qcom: Sort the compatible list alphabetically
2023-06-06 12:44 ` [PATCH v6 10/12] iommu/arm-smmu-qcom: Sort the compatible list alphabetically Konrad Dybcio
@ 2023-06-08 21:02 ` Will Deacon
0 siblings, 0 replies; 20+ messages in thread
From: Will Deacon @ 2023-06-08 21:02 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Robin Murphy, Joerg Roedel, Conor Dooley,
Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu
On Tue, Jun 06, 2023 at 02:44:01PM +0200, Konrad Dybcio wrote:
> It got broken at some point, fix it up.
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> index c71afda79d64..3800ab478216 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> @@ -251,10 +251,10 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
> { .compatible = "qcom,sc7280-mss-pil" },
> { .compatible = "qcom,sc8180x-mdss" },
> { .compatible = "qcom,sc8280xp-mdss" },
> - { .compatible = "qcom,sm8150-mdss" },
> - { .compatible = "qcom,sm8250-mdss" },
> { .compatible = "qcom,sdm845-mdss" },
> { .compatible = "qcom,sdm845-mss-pil" },
> + { .compatible = "qcom,sm8150-mdss" },
> + { .compatible = "qcom,sm8250-mdss" },
> { }
> };
Acked-by: Will Deacon <will@kernel.org>
Will
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v6 11/12] iommu/arm-smmu-qcom: Add SM6375 DPU compatible
2023-06-06 12:43 [PATCH v6 00/12] SM63(50|75) DPU support Konrad Dybcio
` (9 preceding siblings ...)
2023-06-06 12:44 ` [PATCH v6 10/12] iommu/arm-smmu-qcom: Sort the compatible list alphabetically Konrad Dybcio
@ 2023-06-06 12:44 ` Konrad Dybcio
2023-06-08 21:02 ` Will Deacon
2023-06-06 12:44 ` [PATCH v6 12/12] iommu/arm-smmu-qcom: Add SM6350 " Konrad Dybcio
` (2 subsequent siblings)
13 siblings, 1 reply; 20+ messages in thread
From: Konrad Dybcio @ 2023-06-06 12:44 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
Conor Dooley
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
Add the SM6375 DPU compatible to clients compatible list, as it also
needs the workarounds.
Acked-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 3800ab478216..cc574928c707 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -253,6 +253,7 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
{ .compatible = "qcom,sc8280xp-mdss" },
{ .compatible = "qcom,sdm845-mdss" },
{ .compatible = "qcom,sdm845-mss-pil" },
+ { .compatible = "qcom,sm6375-mdss" },
{ .compatible = "qcom,sm8150-mdss" },
{ .compatible = "qcom,sm8250-mdss" },
{ }
--
2.40.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH v6 11/12] iommu/arm-smmu-qcom: Add SM6375 DPU compatible
2023-06-06 12:44 ` [PATCH v6 11/12] iommu/arm-smmu-qcom: Add SM6375 DPU compatible Konrad Dybcio
@ 2023-06-08 21:02 ` Will Deacon
0 siblings, 0 replies; 20+ messages in thread
From: Will Deacon @ 2023-06-08 21:02 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Robin Murphy, Joerg Roedel, Conor Dooley,
Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu
On Tue, Jun 06, 2023 at 02:44:02PM +0200, Konrad Dybcio wrote:
> Add the SM6375 DPU compatible to clients compatible list, as it also
> needs the workarounds.
>
> Acked-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> index 3800ab478216..cc574928c707 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> @@ -253,6 +253,7 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
> { .compatible = "qcom,sc8280xp-mdss" },
> { .compatible = "qcom,sdm845-mdss" },
> { .compatible = "qcom,sdm845-mss-pil" },
> + { .compatible = "qcom,sm6375-mdss" },
> { .compatible = "qcom,sm8150-mdss" },
> { .compatible = "qcom,sm8250-mdss" },
> { }
Acked-by: Will Deacon <will@kernel.org>
Will
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v6 12/12] iommu/arm-smmu-qcom: Add SM6350 DPU compatible
2023-06-06 12:43 [PATCH v6 00/12] SM63(50|75) DPU support Konrad Dybcio
` (10 preceding siblings ...)
2023-06-06 12:44 ` [PATCH v6 11/12] iommu/arm-smmu-qcom: Add SM6375 DPU compatible Konrad Dybcio
@ 2023-06-06 12:44 ` Konrad Dybcio
2023-06-08 21:03 ` Will Deacon
2023-06-07 23:20 ` [PATCH v6 00/12] SM63(50|75) DPU support Dmitry Baryshkov
2023-06-07 23:39 ` Dmitry Baryshkov
13 siblings, 1 reply; 20+ messages in thread
From: Konrad Dybcio @ 2023-06-06 12:44 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
Conor Dooley
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio,
Konrad Dybcio
From: Konrad Dybcio <konrad.dybcio@somainline.org>
Add the SM6350 DPU compatible to clients compatible list, as it also
needs the workarounds.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Acked-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index cc574928c707..bdeb587552c0 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -253,6 +253,7 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
{ .compatible = "qcom,sc8280xp-mdss" },
{ .compatible = "qcom,sdm845-mdss" },
{ .compatible = "qcom,sdm845-mss-pil" },
+ { .compatible = "qcom,sm6350-mdss" },
{ .compatible = "qcom,sm6375-mdss" },
{ .compatible = "qcom,sm8150-mdss" },
{ .compatible = "qcom,sm8250-mdss" },
--
2.40.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH v6 12/12] iommu/arm-smmu-qcom: Add SM6350 DPU compatible
2023-06-06 12:44 ` [PATCH v6 12/12] iommu/arm-smmu-qcom: Add SM6350 " Konrad Dybcio
@ 2023-06-08 21:03 ` Will Deacon
0 siblings, 0 replies; 20+ messages in thread
From: Will Deacon @ 2023-06-08 21:03 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Robin Murphy, Joerg Roedel, Conor Dooley,
Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Konrad Dybcio
On Tue, Jun 06, 2023 at 02:44:03PM +0200, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@somainline.org>
>
> Add the SM6350 DPU compatible to clients compatible list, as it also
> needs the workarounds.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> Acked-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> index cc574928c707..bdeb587552c0 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> @@ -253,6 +253,7 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
> { .compatible = "qcom,sc8280xp-mdss" },
> { .compatible = "qcom,sdm845-mdss" },
> { .compatible = "qcom,sdm845-mss-pil" },
> + { .compatible = "qcom,sm6350-mdss" },
> { .compatible = "qcom,sm6375-mdss" },
> { .compatible = "qcom,sm8150-mdss" },
> { .compatible = "qcom,sm8250-mdss" },
Acked-by: Will Deacon <will@kernel.org>
Will
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v6 00/12] SM63(50|75) DPU support
2023-06-06 12:43 [PATCH v6 00/12] SM63(50|75) DPU support Konrad Dybcio
` (11 preceding siblings ...)
2023-06-06 12:44 ` [PATCH v6 12/12] iommu/arm-smmu-qcom: Add SM6350 " Konrad Dybcio
@ 2023-06-07 23:20 ` Dmitry Baryshkov
2023-06-07 23:39 ` Dmitry Baryshkov
13 siblings, 0 replies; 20+ messages in thread
From: Dmitry Baryshkov @ 2023-06-07 23:20 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Sean Paul, David Airlie, Daniel Vetter,
Rob Herring, Krzysztof Kozlowski, Krishna Manikandan,
Will Deacon, Robin Murphy, Joerg Roedel, Conor Dooley,
Konrad Dybcio
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Rob Herring,
Krzysztof Kozlowski, Konrad Dybcio
On Tue, 06 Jun 2023 14:43:51 +0200, Konrad Dybcio wrote:
> v5 -> v6:
> - Drop unnecessary items: level in bindings
> - Use INTF_SC7180_MASK for 6375 to avoid enabling DPU_INTF_DATA_COMPRESS on DPU6
> - Pick up tags
>
> v5: https://lore.kernel.org/r/20230411-topic-straitlagoon_mdss-v5-0-998b4d2f7dd1@linaro.org
>
> [...]
Applied, thanks!
[01/12] dt-bindings: display/msm: dsi-controller-main: Add SM6350
https://gitlab.freedesktop.org/lumag/msm/-/commit/e99b2d0670a7
[02/12] dt-bindings: display/msm: dsi-controller-main: Add SM6375
https://gitlab.freedesktop.org/lumag/msm/-/commit/27a869221bb7
[03/12] dt-bindings: display/msm: sc7180-dpu: Describe SM6350 and SM6375
https://gitlab.freedesktop.org/lumag/msm/-/commit/ed41005f5b7c
[04/12] dt-bindings: display/msm: Add SM6350 MDSS
https://gitlab.freedesktop.org/lumag/msm/-/commit/3b7502b0c205
[05/12] dt-bindings: display/msm: Add SM6375 MDSS
https://gitlab.freedesktop.org/lumag/msm/-/commit/2a5c1021bc77
[06/12] drm/msm/dpu: Add SM6350 support
https://gitlab.freedesktop.org/lumag/msm/-/commit/3186acba5cdc
[07/12] drm/msm: mdss: Add SM6350 support
https://gitlab.freedesktop.org/lumag/msm/-/commit/c2c1217e61bd
[08/12] drm/msm/dpu: Add SM6375 support
https://gitlab.freedesktop.org/lumag/msm/-/commit/27f0df03f3ff
[09/12] drm/msm: mdss: Add SM6375 support
https://gitlab.freedesktop.org/lumag/msm/-/commit/5ff3d3a0a09e
Best regards,
--
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v6 00/12] SM63(50|75) DPU support
2023-06-06 12:43 [PATCH v6 00/12] SM63(50|75) DPU support Konrad Dybcio
` (12 preceding siblings ...)
2023-06-07 23:20 ` [PATCH v6 00/12] SM63(50|75) DPU support Dmitry Baryshkov
@ 2023-06-07 23:39 ` Dmitry Baryshkov
13 siblings, 0 replies; 20+ messages in thread
From: Dmitry Baryshkov @ 2023-06-07 23:39 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Krishna Manikandan, Will Deacon, Robin Murphy, Joerg Roedel,
Conor Dooley
Cc: Marijn Suijten, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-arm-kernel, iommu, Rob Herring,
Krzysztof Kozlowski, Konrad Dybcio
On 06/06/2023 15:43, Konrad Dybcio wrote:
[skipped the changelog]
> ---
> Konrad Dybcio (12):
> dt-bindings: display/msm: dsi-controller-main: Add SM6350
> dt-bindings: display/msm: dsi-controller-main: Add SM6375
> dt-bindings: display/msm: sc7180-dpu: Describe SM6350 and SM6375
> dt-bindings: display/msm: Add SM6350 MDSS
> dt-bindings: display/msm: Add SM6375 MDSS
> drm/msm/dpu: Add SM6350 support
> drm/msm: mdss: Add SM6350 support
> drm/msm/dpu: Add SM6375 support
> drm/msm: mdss: Add SM6375 support
Will, we have finally picked up the display related patches. Could you
please pick up the IOMMU patches if they look fine to you.
> iommu/arm-smmu-qcom: Sort the compatible list alphabetically
> iommu/arm-smmu-qcom: Add SM6375 DPU compatible
> iommu/arm-smmu-qcom: Add SM6350 DPU compatible
>
> .../bindings/display/msm/dsi-controller-main.yaml | 4 +
> .../bindings/display/msm/qcom,sc7180-dpu.yaml | 23 ++-
> .../bindings/display/msm/qcom,sm6350-mdss.yaml | 213 ++++++++++++++++++++
> .../bindings/display/msm/qcom,sm6375-mdss.yaml | 215 +++++++++++++++++++++
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 173 +++++++++++++++++
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 139 +++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +
> drivers/gpu/drm/msm/msm_mdss.c | 10 +
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 6 +-
> 11 files changed, 790 insertions(+), 3 deletions(-)
> ---
> base-commit: 6db29e14f4fb7bce9eb5290288e71b05c2b0d118
> change-id: 20230411-topic-straitlagoon_mdss-8f34cacd5e26
>
> Best regards,
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 20+ messages in thread