* [PATCH] crypto: hisilicon/hpre - delete ECC 1bit error reported threshold
@ 2021-01-18 8:15 Hui Tang
2021-01-29 5:10 ` Herbert Xu
0 siblings, 1 reply; 2+ messages in thread
From: Hui Tang @ 2021-01-18 8:15 UTC (permalink / raw)
To: herbert, davem; +Cc: linux-crypto, xuzaibo, wangzhou1, tanghui20, linux-kernel
Delete 'HPRE_RAS_ECC1BIT_TH' register setting of hpre,
since register 'QM_RAS_CE_THRESHOLD' of qm has done this work.
Signed-off-by: Hui Tang <tanghui20@huawei.com>
Reviewed-by: Zaibo Xu <xuzaibo@huawei.com>
---
drivers/crypto/hisilicon/hpre/hpre_main.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/crypto/hisilicon/hpre/hpre_main.c b/drivers/crypto/hisilicon/hpre/hpre_main.c
index ad8b691..bf1fa08 100644
--- a/drivers/crypto/hisilicon/hpre/hpre_main.c
+++ b/drivers/crypto/hisilicon/hpre/hpre_main.c
@@ -36,7 +36,6 @@
#define HPRE_INT_STATUS 0x301800
#define HPRE_CORE_INT_ENABLE 0
#define HPRE_CORE_INT_DISABLE 0x003fffff
-#define HPRE_RAS_ECC_1BIT_TH 0x30140c
#define HPRE_RDCHN_INI_ST 0x301a00
#define HPRE_CLSTR_BASE 0x302000
#define HPRE_CORE_EN_OFFSET 0x04
@@ -312,7 +311,6 @@ static int hpre_set_user_domain_and_cache(struct hisi_qm *qm)
writel(HPRE_QM_VFG_AX_MASK, HPRE_ADDR(qm, HPRE_VFG_AXCACHE));
writel(0x0, HPRE_ADDR(qm, HPRE_BD_ENDIAN));
writel(0x0, HPRE_ADDR(qm, HPRE_INT_MASK));
- writel(0x0, HPRE_ADDR(qm, HPRE_RAS_ECC_1BIT_TH));
writel(0x0, HPRE_ADDR(qm, HPRE_POISON_BYPASS));
writel(0x0, HPRE_ADDR(qm, HPRE_COMM_CNT_CLR_CE));
writel(0x0, HPRE_ADDR(qm, HPRE_ECC_BYPASS));
--
2.8.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] crypto: hisilicon/hpre - delete ECC 1bit error reported threshold
2021-01-18 8:15 [PATCH] crypto: hisilicon/hpre - delete ECC 1bit error reported threshold Hui Tang
@ 2021-01-29 5:10 ` Herbert Xu
0 siblings, 0 replies; 2+ messages in thread
From: Herbert Xu @ 2021-01-29 5:10 UTC (permalink / raw)
To: Hui Tang; +Cc: davem, linux-crypto, xuzaibo, wangzhou1, linux-kernel
On Mon, Jan 18, 2021 at 04:15:40PM +0800, Hui Tang wrote:
> Delete 'HPRE_RAS_ECC1BIT_TH' register setting of hpre,
> since register 'QM_RAS_CE_THRESHOLD' of qm has done this work.
>
> Signed-off-by: Hui Tang <tanghui20@huawei.com>
> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com>
> ---
> drivers/crypto/hisilicon/hpre/hpre_main.c | 2 --
> 1 file changed, 2 deletions(-)
Patch applied. Thanks.
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply [flat|nested] 2+ messages in thread
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2021-01-29 5:10 ` Herbert Xu
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