* [PATCH] riscv: fix misalgned trap vector base address
@ 2021-10-18 5:22 Chen Lu
2021-10-18 5:31 ` Anup Patel
2021-10-27 21:22 ` Palmer Dabbelt
0 siblings, 2 replies; 3+ messages in thread
From: Chen Lu @ 2021-10-18 5:22 UTC (permalink / raw)
To: palmer
Cc: paul.walmsley, aou, alex, vitaly.wool, anup, seanga2,
wangkefeng.wang, linux-riscv, linux-kernel, yuzihao, Chen Lu
* The trap vector marked by label .Lsecondary_park should align on a
4-byte boundary. If not, CSR_TVEC may be set to an incorrect address.
* This bug is introduced at commit e011995e826f8 ("RISC-V: Move relocate
and few other functions out of __init").
* This bug is exposed with an educational emualtor.
Signed-off-by: Chen Lu <181250012@smail.nju.edu.cn>
---
arch/riscv/kernel/head.S | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index fce5184b22c3..52c5ff9804c5 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -193,6 +193,7 @@ setup_trap_vector:
csrw CSR_SCRATCH, zero
ret
+.align 2
.Lsecondary_park:
/* We lack SMP support or have too many harts, so park this hart */
wfi
--
2.30.2
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] riscv: fix misalgned trap vector base address
2021-10-18 5:22 [PATCH] riscv: fix misalgned trap vector base address Chen Lu
@ 2021-10-18 5:31 ` Anup Patel
2021-10-27 21:22 ` Palmer Dabbelt
1 sibling, 0 replies; 3+ messages in thread
From: Anup Patel @ 2021-10-18 5:31 UTC (permalink / raw)
To: Chen Lu
Cc: Palmer Dabbelt, Paul Walmsley, Albert Ou, Alexandre Ghiti,
Vitaly Wool, Sean Anderson, Kefeng Wang, linux-riscv,
linux-kernel@vger.kernel.org List, Zihao Yu
On Mon, Oct 18, 2021 at 10:52 AM Chen Lu <181250012@smail.nju.edu.cn> wrote:
>
> * The trap vector marked by label .Lsecondary_park should align on a
> 4-byte boundary. If not, CSR_TVEC may be set to an incorrect address.
> * This bug is introduced at commit e011995e826f8 ("RISC-V: Move relocate
> and few other functions out of __init").
> * This bug is exposed with an educational emualtor.
>
Please add "Fixes:" line here.
> Signed-off-by: Chen Lu <181250012@smail.nju.edu.cn>
Otherwise it looks good to me.
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Regards,
Anup
> ---
> arch/riscv/kernel/head.S | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index fce5184b22c3..52c5ff9804c5 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -193,6 +193,7 @@ setup_trap_vector:
> csrw CSR_SCRATCH, zero
> ret
>
> +.align 2
> .Lsecondary_park:
> /* We lack SMP support or have too many harts, so park this hart */
> wfi
> --
> 2.30.2
>
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] riscv: fix misalgned trap vector base address
2021-10-18 5:22 [PATCH] riscv: fix misalgned trap vector base address Chen Lu
2021-10-18 5:31 ` Anup Patel
@ 2021-10-27 21:22 ` Palmer Dabbelt
1 sibling, 0 replies; 3+ messages in thread
From: Palmer Dabbelt @ 2021-10-27 21:22 UTC (permalink / raw)
To: 181250012
Cc: Paul Walmsley, aou, alex, vitaly.wool, anup, seanga2,
wangkefeng.wang, linux-riscv, linux-kernel, yuzihao, 181250012
On Sun, 17 Oct 2021 22:22:38 PDT (-0700), 181250012@smail.nju.edu.cn wrote:
> * The trap vector marked by label .Lsecondary_park should align on a
> 4-byte boundary. If not, CSR_TVEC may be set to an incorrect address.
> * This bug is introduced at commit e011995e826f8 ("RISC-V: Move relocate
> and few other functions out of __init").
> * This bug is exposed with an educational emualtor.
>
> Signed-off-by: Chen Lu <181250012@smail.nju.edu.cn>
> ---
> arch/riscv/kernel/head.S | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index fce5184b22c3..52c5ff9804c5 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -193,6 +193,7 @@ setup_trap_vector:
> csrw CSR_SCRATCH, zero
> ret
>
> +.align 2
> .Lsecondary_park:
> /* We lack SMP support or have too many harts, so park this hart */
> wfi
Thanks, this is on fixes (with some commit message cleanups).
^ permalink raw reply [flat|nested] 3+ messages in thread
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2021-10-18 5:31 ` Anup Patel
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