* [PATCH v1 1/6] arm64/hwcap: Add support for FEAT_CSSC
2022-10-17 15:25 [PATCH v1 0/6] arm64: Support for 2022 data processing instructions Mark Brown
@ 2022-10-17 15:25 ` Mark Brown
2022-11-09 17:29 ` Catalin Marinas
2022-10-17 15:25 ` [PATCH v1 2/6] kselftest/arm64: Add FEAT_CSSC to the hwcap selftest Mark Brown
` (5 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Mark Brown @ 2022-10-17 15:25 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Shuah Khan, Shuah Khan
Cc: linux-arm-kernel, linux-kselftest, Mark Brown
FEAT_CSSC adds a number of new instructions usable to optimise common short
sequences of instructions, add a hwcap indicating that the feature is
available and can be used by userspace.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
Documentation/arm64/elf_hwcaps.rst | 3 +++
arch/arm64/include/asm/hwcap.h | 1 +
arch/arm64/include/uapi/asm/hwcap.h | 1 +
arch/arm64/kernel/cpufeature.c | 2 ++
arch/arm64/kernel/cpuinfo.c | 1 +
arch/arm64/tools/sysreg | 7 ++++++-
6 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/Documentation/arm64/elf_hwcaps.rst b/Documentation/arm64/elf_hwcaps.rst
index bb34287c8e01..58197e9ccb6d 100644
--- a/Documentation/arm64/elf_hwcaps.rst
+++ b/Documentation/arm64/elf_hwcaps.rst
@@ -275,6 +275,9 @@ HWCAP2_EBF16
HWCAP2_SVE_EBF16
Functionality implied by ID_AA64ZFR0_EL1.BF16 == 0b0010.
+HWCAP2_CSSC
+ Functionality implied by ID_AA64ISAR2_EL1.CSSC == 0b0001.
+
4. Unused AT_HWCAP bits
-----------------------
diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h
index 298b386d3ebe..a0e080df9a62 100644
--- a/arch/arm64/include/asm/hwcap.h
+++ b/arch/arm64/include/asm/hwcap.h
@@ -120,6 +120,7 @@
#define KERNEL_HWCAP_WFXT __khwcap2_feature(WFXT)
#define KERNEL_HWCAP_EBF16 __khwcap2_feature(EBF16)
#define KERNEL_HWCAP_SVE_EBF16 __khwcap2_feature(SVE_EBF16)
+#define KERNEL_HWCAP_CSSC __khwcap2_feature(CSSC)
/*
* This yields a mask that user programs can use to figure out what
diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h
index 9b245da6f507..a43dddd94b4a 100644
--- a/arch/arm64/include/uapi/asm/hwcap.h
+++ b/arch/arm64/include/uapi/asm/hwcap.h
@@ -93,5 +93,6 @@
#define HWCAP2_WFXT (1UL << 31)
#define HWCAP2_EBF16 (1UL << 32)
#define HWCAP2_SVE_EBF16 (1UL << 33)
+#define HWCAP2_CSSC (1UL << 34)
#endif /* _UAPI__ASM_HWCAP_H */
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 6062454a9067..130cc9127dde 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -212,6 +212,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
};
static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0),
@@ -2774,6 +2775,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
#endif /* CONFIG_ARM64_MTE */
HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV),
HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP),
+ HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_CSSC_IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC),
HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES),
HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_WFxT_IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT),
#ifdef CONFIG_ARM64_SME
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index 28d4f442b0bc..3160550c0cc9 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -116,6 +116,7 @@ static const char *const hwcap_str[] = {
[KERNEL_HWCAP_WFXT] = "wfxt",
[KERNEL_HWCAP_EBF16] = "ebf16",
[KERNEL_HWCAP_SVE_EBF16] = "sveebf16",
+ [KERNEL_HWCAP_CSSC] = "cssc",
};
#ifdef CONFIG_COMPAT
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 384757a7eda9..629d119151bf 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -484,7 +484,12 @@ EndEnum
EndSysreg
Sysreg ID_AA64ISAR2_EL1 3 0 0 6 2
-Res0 63:28
+Res0 63:56
+Enum 55:52 CSSC
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Res0 51:28
Enum 27:24 PAC_frac
0b0000 NI
0b0001 IMP
--
2.30.2
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v1 2/6] kselftest/arm64: Add FEAT_CSSC to the hwcap selftest
2022-10-17 15:25 [PATCH v1 0/6] arm64: Support for 2022 data processing instructions Mark Brown
2022-10-17 15:25 ` [PATCH v1 1/6] arm64/hwcap: Add support for FEAT_CSSC Mark Brown
@ 2022-10-17 15:25 ` Mark Brown
2022-11-09 17:30 ` Catalin Marinas
2022-10-17 15:25 ` [PATCH v1 3/6] arm64/hwcap: Add support for FEAT_RPRFM Mark Brown
` (4 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Mark Brown @ 2022-10-17 15:25 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Shuah Khan, Shuah Khan
Cc: linux-arm-kernel, linux-kselftest, Mark Brown
Add FEAT_CSSC to the set of features checked by the hwcap selftest.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
tools/testing/selftests/arm64/abi/hwcap.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/tools/testing/selftests/arm64/abi/hwcap.c b/tools/testing/selftests/arm64/abi/hwcap.c
index 9f1a7b5c6193..c7a6b327a7d0 100644
--- a/tools/testing/selftests/arm64/abi/hwcap.c
+++ b/tools/testing/selftests/arm64/abi/hwcap.c
@@ -33,6 +33,12 @@
*/
typedef void (*sigill_fn)(void);
+static void cssc_sigill(void)
+{
+ /* CNT x0, x0 */
+ asm volatile(".inst 0xdac01c00" : : : "x0");
+}
+
static void rng_sigill(void)
{
asm volatile("mrs x0, S3_3_C2_C4_0" : : : "x0");
@@ -118,6 +124,13 @@ static const struct hwcap_data {
sigill_fn sigill_fn;
bool sigill_reliable;
} hwcaps[] = {
+ {
+ .name = "CSSC",
+ .at_hwcap = AT_HWCAP2,
+ .hwcap_bit = HWCAP2_CSSC,
+ .cpuinfo = "cssc",
+ .sigill_fn = cssc_sigill,
+ },
{
.name = "RNG",
.at_hwcap = AT_HWCAP2,
--
2.30.2
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v1 3/6] arm64/hwcap: Add support for FEAT_RPRFM
2022-10-17 15:25 [PATCH v1 0/6] arm64: Support for 2022 data processing instructions Mark Brown
2022-10-17 15:25 ` [PATCH v1 1/6] arm64/hwcap: Add support for FEAT_CSSC Mark Brown
2022-10-17 15:25 ` [PATCH v1 2/6] kselftest/arm64: Add FEAT_CSSC to the hwcap selftest Mark Brown
@ 2022-10-17 15:25 ` Mark Brown
2022-11-09 17:30 ` Catalin Marinas
2022-10-17 15:25 ` [PATCH v1 4/6] kselftest/arm64: Add FEAT_RPRFM to the hwcap test Mark Brown
` (3 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Mark Brown @ 2022-10-17 15:25 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Shuah Khan, Shuah Khan
Cc: linux-arm-kernel, linux-kselftest, Mark Brown
FEAT_RPRFM adds a new range prefetch hint within the existing PRFM space
for range prefetch hinting. Add a new hwcap to allow userspace to discover
support for the new instruction.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
Documentation/arm64/elf_hwcaps.rst | 3 +++
arch/arm64/include/asm/hwcap.h | 1 +
arch/arm64/include/uapi/asm/hwcap.h | 1 +
arch/arm64/kernel/cpufeature.c | 2 ++
arch/arm64/kernel/cpuinfo.c | 1 +
arch/arm64/tools/sysreg | 6 +++++-
6 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/Documentation/arm64/elf_hwcaps.rst b/Documentation/arm64/elf_hwcaps.rst
index 58197e9ccb6d..a82b2cdff680 100644
--- a/Documentation/arm64/elf_hwcaps.rst
+++ b/Documentation/arm64/elf_hwcaps.rst
@@ -278,6 +278,9 @@ HWCAP2_SVE_EBF16
HWCAP2_CSSC
Functionality implied by ID_AA64ISAR2_EL1.CSSC == 0b0001.
+HWCAP2_RPRFM
+ Functionality implied by ID_AA64ISAR2_EL1.RPRFM == 0b0001.
+
4. Unused AT_HWCAP bits
-----------------------
diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h
index a0e080df9a62..605ec55cee70 100644
--- a/arch/arm64/include/asm/hwcap.h
+++ b/arch/arm64/include/asm/hwcap.h
@@ -121,6 +121,7 @@
#define KERNEL_HWCAP_EBF16 __khwcap2_feature(EBF16)
#define KERNEL_HWCAP_SVE_EBF16 __khwcap2_feature(SVE_EBF16)
#define KERNEL_HWCAP_CSSC __khwcap2_feature(CSSC)
+#define KERNEL_HWCAP_RPRFM __khwcap2_feature(RPRFM)
/*
* This yields a mask that user programs can use to figure out what
diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h
index a43dddd94b4a..063cc6ea560f 100644
--- a/arch/arm64/include/uapi/asm/hwcap.h
+++ b/arch/arm64/include/uapi/asm/hwcap.h
@@ -94,5 +94,6 @@
#define HWCAP2_EBF16 (1UL << 32)
#define HWCAP2_SVE_EBF16 (1UL << 33)
#define HWCAP2_CSSC (1UL << 34)
+#define HWCAP2_RPRFM (1UL << 35)
#endif /* _UAPI__ASM_HWCAP_H */
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 130cc9127dde..01bd72ff9617 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -213,6 +213,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0),
@@ -2776,6 +2777,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV),
HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP),
HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_CSSC_IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC),
+ HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_RPRFM_IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM),
HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES),
HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_WFxT_IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT),
#ifdef CONFIG_ARM64_SME
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index 3160550c0cc9..85108832d86e 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -117,6 +117,7 @@ static const char *const hwcap_str[] = {
[KERNEL_HWCAP_EBF16] = "ebf16",
[KERNEL_HWCAP_SVE_EBF16] = "sveebf16",
[KERNEL_HWCAP_CSSC] = "cssc",
+ [KERNEL_HWCAP_RPRFM] = "rprfm",
};
#ifdef CONFIG_COMPAT
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 629d119151bf..a2b2e4c1c3f2 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -489,7 +489,11 @@ Enum 55:52 CSSC
0b0000 NI
0b0001 IMP
EndEnum
-Res0 51:28
+Enum 51:48 RPRFM
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Res0 47:28
Enum 27:24 PAC_frac
0b0000 NI
0b0001 IMP
--
2.30.2
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v1 4/6] kselftest/arm64: Add FEAT_RPRFM to the hwcap test
2022-10-17 15:25 [PATCH v1 0/6] arm64: Support for 2022 data processing instructions Mark Brown
` (2 preceding siblings ...)
2022-10-17 15:25 ` [PATCH v1 3/6] arm64/hwcap: Add support for FEAT_RPRFM Mark Brown
@ 2022-10-17 15:25 ` Mark Brown
2022-11-09 17:31 ` Catalin Marinas
2022-10-17 15:25 ` [PATCH v1 5/6] arm64/hwcap: Add support for SVE 2.1 Mark Brown
` (2 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Mark Brown @ 2022-10-17 15:25 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Shuah Khan, Shuah Khan
Cc: linux-arm-kernel, linux-kselftest, Mark Brown
Since the newly added instruction is in the HINT space we can't reasonably
test for it actually being present.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
tools/testing/selftests/arm64/abi/hwcap.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/tools/testing/selftests/arm64/abi/hwcap.c b/tools/testing/selftests/arm64/abi/hwcap.c
index c7a6b327a7d0..30f87dfd634e 100644
--- a/tools/testing/selftests/arm64/abi/hwcap.c
+++ b/tools/testing/selftests/arm64/abi/hwcap.c
@@ -138,6 +138,12 @@ static const struct hwcap_data {
.cpuinfo = "rng",
.sigill_fn = rng_sigill,
},
+ {
+ .name = "RPRFM",
+ .at_hwcap = AT_HWCAP2,
+ .hwcap_bit = HWCAP2_RPRFM,
+ .cpuinfo = "rprfm",
+ },
{
.name = "SME",
.at_hwcap = AT_HWCAP2,
--
2.30.2
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v1 5/6] arm64/hwcap: Add support for SVE 2.1
2022-10-17 15:25 [PATCH v1 0/6] arm64: Support for 2022 data processing instructions Mark Brown
` (3 preceding siblings ...)
2022-10-17 15:25 ` [PATCH v1 4/6] kselftest/arm64: Add FEAT_RPRFM to the hwcap test Mark Brown
@ 2022-10-17 15:25 ` Mark Brown
2022-11-09 17:35 ` Catalin Marinas
2022-10-17 15:25 ` [PATCH v1 6/6] kselftest/arm64: Add SVE 2.1 to hwcap test Mark Brown
2022-11-09 19:13 ` [PATCH v1 0/6] arm64: Support for 2022 data processing instructions Will Deacon
6 siblings, 1 reply; 14+ messages in thread
From: Mark Brown @ 2022-10-17 15:25 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Shuah Khan, Shuah Khan
Cc: linux-arm-kernel, linux-kselftest, Mark Brown
FEAT_SVE2p1 introduces a number of new SVE instructions. Since there is no
new architectural state added kernel support is simply a new hwcap which
lets userspace know that the feature is supported.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
Documentation/arm64/elf_hwcaps.rst | 3 +++
Documentation/arm64/sve.rst | 1 +
arch/arm64/include/asm/hwcap.h | 1 +
arch/arm64/include/uapi/asm/hwcap.h | 1 +
arch/arm64/kernel/cpufeature.c | 1 +
arch/arm64/kernel/cpuinfo.c | 1 +
arch/arm64/tools/sysreg | 1 +
7 files changed, 9 insertions(+)
diff --git a/Documentation/arm64/elf_hwcaps.rst b/Documentation/arm64/elf_hwcaps.rst
index a82b2cdff680..6fed84f935df 100644
--- a/Documentation/arm64/elf_hwcaps.rst
+++ b/Documentation/arm64/elf_hwcaps.rst
@@ -281,6 +281,9 @@ HWCAP2_CSSC
HWCAP2_RPRFM
Functionality implied by ID_AA64ISAR2_EL1.RPRFM == 0b0001.
+HWCAP2_SVE2P1
+ Functionality implied by ID_AA64ZFR0_EL1.SVEver == 0b0010.
+
4. Unused AT_HWCAP bits
-----------------------
diff --git a/Documentation/arm64/sve.rst b/Documentation/arm64/sve.rst
index f338ee2df46d..c7a356bf4e8f 100644
--- a/Documentation/arm64/sve.rst
+++ b/Documentation/arm64/sve.rst
@@ -52,6 +52,7 @@ model features for SVE is included in Appendix A.
HWCAP2_SVEBITPERM
HWCAP2_SVESHA3
HWCAP2_SVESM4
+ HWCAP2_SVE2P1
This list may be extended over time as the SVE architecture evolves.
diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h
index 605ec55cee70..06dd12c514e6 100644
--- a/arch/arm64/include/asm/hwcap.h
+++ b/arch/arm64/include/asm/hwcap.h
@@ -122,6 +122,7 @@
#define KERNEL_HWCAP_SVE_EBF16 __khwcap2_feature(SVE_EBF16)
#define KERNEL_HWCAP_CSSC __khwcap2_feature(CSSC)
#define KERNEL_HWCAP_RPRFM __khwcap2_feature(RPRFM)
+#define KERNEL_HWCAP_SVE2P1 __khwcap2_feature(SVE2P1)
/*
* This yields a mask that user programs can use to figure out what
diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h
index 063cc6ea560f..b713d30544f1 100644
--- a/arch/arm64/include/uapi/asm/hwcap.h
+++ b/arch/arm64/include/uapi/asm/hwcap.h
@@ -95,5 +95,6 @@
#define HWCAP2_SVE_EBF16 (1UL << 33)
#define HWCAP2_CSSC (1UL << 34)
#define HWCAP2_RPRFM (1UL << 35)
+#define HWCAP2_SVE2P1 (1UL << 36)
#endif /* _UAPI__ASM_HWCAP_H */
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 01bd72ff9617..bb1ef8cf7d04 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2750,6 +2750,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_EL1_AT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),
#ifdef CONFIG_ARM64_SVE
HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_SVE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR0_EL1_SVE_IMP, CAP_HWCAP, KERNEL_HWCAP_SVE),
+ HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SVEver_SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1),
HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SVEver_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_AES_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_AES_PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index 85108832d86e..379695262b77 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -118,6 +118,7 @@ static const char *const hwcap_str[] = {
[KERNEL_HWCAP_SVE_EBF16] = "sveebf16",
[KERNEL_HWCAP_CSSC] = "cssc",
[KERNEL_HWCAP_RPRFM] = "rprfm",
+ [KERNEL_HWCAP_SVE2P1] = "sve2p1",
};
#ifdef CONFIG_COMPAT
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index a2b2e4c1c3f2..b2782b8faa01 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -210,6 +210,7 @@ EndEnum
Enum 3:0 SVEver
0b0000 IMP
0b0001 SVE2
+ 0b0010 SVE2p1
EndEnum
EndSysreg
--
2.30.2
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v1 5/6] arm64/hwcap: Add support for SVE 2.1
2022-10-17 15:25 ` [PATCH v1 5/6] arm64/hwcap: Add support for SVE 2.1 Mark Brown
@ 2022-11-09 17:35 ` Catalin Marinas
0 siblings, 0 replies; 14+ messages in thread
From: Catalin Marinas @ 2022-11-09 17:35 UTC (permalink / raw)
To: Mark Brown
Cc: Will Deacon, Shuah Khan, Shuah Khan, linux-arm-kernel, linux-kselftest
On Mon, Oct 17, 2022 at 04:25:19PM +0100, Mark Brown wrote:
> FEAT_SVE2p1 introduces a number of new SVE instructions. Since there is no
> new architectural state added kernel support is simply a new hwcap which
> lets userspace know that the feature is supported.
>
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
> Documentation/arm64/elf_hwcaps.rst | 3 +++
> Documentation/arm64/sve.rst | 1 +
> arch/arm64/include/asm/hwcap.h | 1 +
> arch/arm64/include/uapi/asm/hwcap.h | 1 +
> arch/arm64/kernel/cpufeature.c | 1 +
> arch/arm64/kernel/cpuinfo.c | 1 +
> arch/arm64/tools/sysreg | 1 +
> 7 files changed, 9 insertions(+)
>
> diff --git a/Documentation/arm64/elf_hwcaps.rst b/Documentation/arm64/elf_hwcaps.rst
> index a82b2cdff680..6fed84f935df 100644
> --- a/Documentation/arm64/elf_hwcaps.rst
> +++ b/Documentation/arm64/elf_hwcaps.rst
> @@ -281,6 +281,9 @@ HWCAP2_CSSC
> HWCAP2_RPRFM
> Functionality implied by ID_AA64ISAR2_EL1.RPRFM == 0b0001.
>
> +HWCAP2_SVE2P1
> + Functionality implied by ID_AA64ZFR0_EL1.SVEver == 0b0010.
It looks like our architect ran out of meaningful names. I guess we
should just follow them in the kernel.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v1 6/6] kselftest/arm64: Add SVE 2.1 to hwcap test
2022-10-17 15:25 [PATCH v1 0/6] arm64: Support for 2022 data processing instructions Mark Brown
` (4 preceding siblings ...)
2022-10-17 15:25 ` [PATCH v1 5/6] arm64/hwcap: Add support for SVE 2.1 Mark Brown
@ 2022-10-17 15:25 ` Mark Brown
2022-11-09 17:35 ` Catalin Marinas
2022-11-09 19:13 ` [PATCH v1 0/6] arm64: Support for 2022 data processing instructions Will Deacon
6 siblings, 1 reply; 14+ messages in thread
From: Mark Brown @ 2022-10-17 15:25 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Shuah Khan, Shuah Khan
Cc: linux-arm-kernel, linux-kselftest, Mark Brown
Add coverage for FEAT_SVE2p1.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
tools/testing/selftests/arm64/abi/hwcap.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/tools/testing/selftests/arm64/abi/hwcap.c b/tools/testing/selftests/arm64/abi/hwcap.c
index 30f87dfd634e..9f255bc5f31c 100644
--- a/tools/testing/selftests/arm64/abi/hwcap.c
+++ b/tools/testing/selftests/arm64/abi/hwcap.c
@@ -62,6 +62,12 @@ static void sve2_sigill(void)
asm volatile(".inst 0x4408A000" : : : "z0");
}
+static void sve2p1_sigill(void)
+{
+ /* BFADD Z0.H, Z0.H, Z0.H */
+ asm volatile(".inst 0x65000000" : : : "z0");
+}
+
static void sveaes_sigill(void)
{
/* AESD z0.b, z0.b, z0.b */
@@ -167,6 +173,13 @@ static const struct hwcap_data {
.cpuinfo = "sve2",
.sigill_fn = sve2_sigill,
},
+ {
+ .name = "SVE 2.1",
+ .at_hwcap = AT_HWCAP2,
+ .hwcap_bit = HWCAP2_SVE2P1,
+ .cpuinfo = "sve2p1",
+ .sigill_fn = sve2p1_sigill,
+ },
{
.name = "SVE AES",
.at_hwcap = AT_HWCAP2,
--
2.30.2
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v1 0/6] arm64: Support for 2022 data processing instructions
2022-10-17 15:25 [PATCH v1 0/6] arm64: Support for 2022 data processing instructions Mark Brown
` (5 preceding siblings ...)
2022-10-17 15:25 ` [PATCH v1 6/6] kselftest/arm64: Add SVE 2.1 to hwcap test Mark Brown
@ 2022-11-09 19:13 ` Will Deacon
6 siblings, 0 replies; 14+ messages in thread
From: Will Deacon @ 2022-11-09 19:13 UTC (permalink / raw)
To: Mark Brown, Shuah Khan, Catalin Marinas, Shuah Khan
Cc: kernel-team, Will Deacon, linux-arm-kernel, linux-kselftest
On Mon, 17 Oct 2022 16:25:14 +0100, Mark Brown wrote:
> The 2022 update to the Arm architecture includes a number of additions
> of generic data processing features, covering the base architecture, SVE
> and SME. Other than SME these are all simple features which introduce no
> architectural state so we simply need to expose hwcaps for them. This
> series covers these simple features. Since the SME updates do introduce
> new architectural state for which we must add new ABI they will be
> handled in a separate series.
>
> [...]
Applied to arm64 (for-next/cpufeature), thanks!
[1/6] arm64/hwcap: Add support for FEAT_CSSC
https://git.kernel.org/arm64/c/95aa6860d608
[2/6] kselftest/arm64: Add FEAT_CSSC to the hwcap selftest
https://git.kernel.org/arm64/c/b0ab73a5479f
[3/6] arm64/hwcap: Add support for FEAT_RPRFM
https://git.kernel.org/arm64/c/939e4649d4fd
[4/6] kselftest/arm64: Add FEAT_RPRFM to the hwcap test
https://git.kernel.org/arm64/c/989d37fc3d97
[5/6] arm64/hwcap: Add support for SVE 2.1
https://git.kernel.org/arm64/c/d12aada8dfb0
[6/6] kselftest/arm64: Add SVE 2.1 to hwcap test
https://git.kernel.org/arm64/c/c5195b027d29
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
^ permalink raw reply [flat|nested] 14+ messages in thread