* [PATCH v2 0/5] ColdFire PCI bus support
@ 2012-07-16 12:27 gerg
2012-07-16 12:27 ` [PATCH v2 1/5] m68k: common PCI support definitions and code gerg
` (4 more replies)
0 siblings, 5 replies; 10+ messages in thread
From: gerg @ 2012-07-16 12:27 UTC (permalink / raw)
To: linux-m68k
This is version 2 of the ColdFire PCI bus support.
The following patch series adds support for the PCI bus on the ColdFire
M54[78]x family of parts.
Changes since the last version:
. change to drivers/pci/Makefile sent to linux-pci email list separately
. header file changes broken out into a separate patch (for easier review)
. IO barriers added within PCI config space access functions
---
arch/m68k/Kconfig.bus | 7
arch/m68k/include/asm/dma.h | 4
arch/m68k/include/asm/io_mm.h | 50 +++++
arch/m68k/include/asm/m54xxpci.h | 138 ++++++++++++++
arch/m68k/include/asm/m54xxsim.h | 3
arch/m68k/include/asm/pci.h | 6
arch/m68k/kernel/Makefile | 1
arch/m68k/kernel/pcibios.c | 109 +++++++++++
arch/m68k/platform/coldfire/Makefile | 2
arch/m68k/platform/coldfire/pci.c | 327 +++++++++++++++++++++++++++++++++++
10 files changed, 646 insertions(+), 1 deletion(-)
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH v2 1/5] m68k: common PCI support definitions and code 2012-07-16 12:27 [PATCH v2 0/5] ColdFire PCI bus support gerg @ 2012-07-16 12:27 ` gerg 2021-06-28 7:44 ` Geert Uytterhoeven 2012-07-16 12:27 ` [PATCH v2 2/5] m68k: add PCI bus support definitions for the ColdFire M54xx SoC family gerg ` (3 subsequent siblings) 4 siblings, 1 reply; 10+ messages in thread From: gerg @ 2012-07-16 12:27 UTC (permalink / raw) To: linux-m68k; +Cc: Greg Ungerer From: Greg Ungerer <gerg@uclinux.org> Basic set of definitions and support code required to turn on CONFIG_PCI for the m68k architecture. Nothing specific to any PCI implementation in any m68k class CPU hardware yet. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> --- arch/m68k/include/asm/dma.h | 4 ++ arch/m68k/include/asm/io_mm.h | 2 + arch/m68k/include/asm/pci.h | 6 ++ arch/m68k/kernel/Makefile | 1 + arch/m68k/kernel/pcibios.c | 109 +++++++++++++++++++++++++++++++++++++++++ 5 files changed, 122 insertions(+), 0 deletions(-) create mode 100644 arch/m68k/kernel/pcibios.c diff --git a/arch/m68k/include/asm/dma.h b/arch/m68k/include/asm/dma.h index 6fbdfe8..7a59439 100644 --- a/arch/m68k/include/asm/dma.h +++ b/arch/m68k/include/asm/dma.h @@ -486,6 +486,10 @@ static __inline__ int get_dma_residue(unsigned int dmanr) extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */ extern void free_dma(unsigned int dmanr); /* release it again */ +#ifdef CONFIG_PCI +extern int isa_dma_bridge_buggy; +#else #define isa_dma_bridge_buggy (0) +#endif #endif /* _M68K_DMA_H */ diff --git a/arch/m68k/include/asm/io_mm.h b/arch/m68k/include/asm/io_mm.h index fa4324b..b85dbef 100644 --- a/arch/m68k/include/asm/io_mm.h +++ b/arch/m68k/include/asm/io_mm.h @@ -340,4 +340,6 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int */ #define xlate_dev_kmem_ptr(p) p +#define ioport_map(port, nr) ((void __iomem *)(port)) + #endif /* _IO_H */ diff --git a/arch/m68k/include/asm/pci.h b/arch/m68k/include/asm/pci.h index 4ad0aea..848c3df 100644 --- a/arch/m68k/include/asm/pci.h +++ b/arch/m68k/include/asm/pci.h @@ -2,6 +2,7 @@ #define _ASM_M68K_PCI_H #include <asm-generic/pci-dma-compat.h> +#include <asm-generic/pci.h> /* The PCI address space does equal the physical memory * address space. The networking and block device layers use @@ -9,4 +10,9 @@ */ #define PCI_DMA_BUS_IS_PHYS (1) +#define pcibios_assign_all_busses() 1 + +#define PCIBIOS_MIN_IO 0x00000100 +#define PCIBIOS_MIN_MEM 0x02000000 + #endif /* _ASM_M68K_PCI_H */ diff --git a/arch/m68k/kernel/Makefile b/arch/m68k/kernel/Makefile index 5c7070e..068ad49 100644 --- a/arch/m68k/kernel/Makefile +++ b/arch/m68k/kernel/Makefile @@ -18,6 +18,7 @@ obj-y += setup.o signal.o sys_m68k.o syscalltable.o time.o traps.o obj-$(CONFIG_MMU_MOTOROLA) += ints.o vectors.o obj-$(CONFIG_MMU_SUN3) += ints.o vectors.o +obj-$(CONFIG_PCI) += pcibios.o ifndef CONFIG_MMU_SUN3 obj-y += dma.o diff --git a/arch/m68k/kernel/pcibios.c b/arch/m68k/kernel/pcibios.c new file mode 100644 index 0000000..b2988aa --- /dev/null +++ b/arch/m68k/kernel/pcibios.c @@ -0,0 +1,109 @@ +/* + * pci.c -- basic PCI support code + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org> + */ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/mm.h> +#include <linux/init.h> +#include <linux/pci.h> + +/* + * From arch/i386/kernel/pci-i386.c: + * + * We need to avoid collisions with `mirrored' VGA ports + * and other strange ISA hardware, so we always want the + * addresses to be allocated in the 0x000-0x0ff region + * modulo 0x400. + * + * Why? Because some silly external IO cards only decode + * the low 10 bits of the IO address. The 0x00-0xff region + * is reserved for motherboard devices that decode all 16 + * bits, so it's ok to allocate at, say, 0x2800-0x28ff, + * but we want to try to avoid allocating at 0x2900-0x2bff + * which might be mirrored at 0x0100-0x03ff.. + */ +resource_size_t pcibios_align_resource(void *data, const struct resource *res, + resource_size_t size, resource_size_t align) +{ + resource_size_t start = res->start; + + if ((res->flags & IORESOURCE_IO) && (start & 0x300)) + start = (start + 0x3ff) & ~0x3ff; + + start = (start + align - 1) & ~(align - 1); + + return start; +} + +/* + * This is taken from the ARM code for this. + */ +int pcibios_enable_device(struct pci_dev *dev, int mask) +{ + struct resource *r; + u16 cmd, newcmd; + int idx; + + pci_read_config_word(dev, PCI_COMMAND, &cmd); + newcmd = cmd; + + for (idx = 0; idx < 6; idx++) { + /* Only set up the requested stuff */ + if (!(mask & (1 << idx))) + continue; + + r = dev->resource + idx; + if (!r->start && r->end) { + pr_err(KERN_ERR "PCI: Device %s not available because of resource collisions\n", + pci_name(dev)); + return -EINVAL; + } + if (r->flags & IORESOURCE_IO) + newcmd |= PCI_COMMAND_IO; + if (r->flags & IORESOURCE_MEM) + newcmd |= PCI_COMMAND_MEMORY; + } + + /* + * Bridges (eg, cardbus bridges) need to be fully enabled + */ + if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) + newcmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY; + + + if (newcmd != cmd) { + pr_info("PCI: enabling device %s (0x%04x -> 0x%04x)\n", + pci_name(dev), cmd, newcmd); + pci_write_config_word(dev, PCI_COMMAND, newcmd); + } + return 0; +} + +void pcibios_update_irq(struct pci_dev *dev, int irq) +{ + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); +} + +void __devinit pcibios_fixup_bus(struct pci_bus *bus) +{ + struct pci_dev *dev; + + list_for_each_entry(dev, &bus->devices, bus_list) { + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8); + pci_write_config_byte(dev, PCI_LATENCY_TIMER, 32); + } +} + +char __devinit *pcibios_setup(char *str) +{ + return str; +} + -- 1.7.0.4 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v2 1/5] m68k: common PCI support definitions and code 2012-07-16 12:27 ` [PATCH v2 1/5] m68k: common PCI support definitions and code gerg @ 2021-06-28 7:44 ` Geert Uytterhoeven 2021-06-28 13:23 ` Greg Ungerer 0 siblings, 1 reply; 10+ messages in thread From: Geert Uytterhoeven @ 2021-06-28 7:44 UTC (permalink / raw) To: Greg Ungerer; +Cc: Linux/m68k Hi Greg, On Mon, Jul 16, 2012 at 2:25 PM <gerg@snapgear.com> wrote: > From: Greg Ungerer <gerg@uclinux.org> > > Basic set of definitions and support code required to turn on CONFIG_PCI > for the m68k architecture. Nothing specific to any PCI implementation in > any m68k class CPU hardware yet. > > Signed-off-by: Greg Ungerer <gerg@uclinux.org> > --- a/arch/m68k/include/asm/io_mm.h > +++ b/arch/m68k/include/asm/io_mm.h > @@ -340,4 +340,6 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int > */ > #define xlate_dev_kmem_ptr(p) p > > +#define ioport_map(port, nr) ((void __iomem *)(port)) So should we dop: config NO_IOPORT_MAP def_bool y Triggered by seeing CONFIG_GPIO_TQMX86 being removed from allmodconfig builds due to commit c6414e1a2bd26b00 ("gpio: AMD8111 and TQMX86 require HAS_IOPORT_MAP"). Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 1/5] m68k: common PCI support definitions and code 2021-06-28 7:44 ` Geert Uytterhoeven @ 2021-06-28 13:23 ` Greg Ungerer 2021-06-28 13:29 ` Geert Uytterhoeven 0 siblings, 1 reply; 10+ messages in thread From: Greg Ungerer @ 2021-06-28 13:23 UTC (permalink / raw) To: Geert Uytterhoeven; +Cc: Linux/m68k Hi Geert, On 28/6/21 5:44 pm, Geert Uytterhoeven wrote: > Hi Greg, > > On Mon, Jul 16, 2012 at 2:25 PM <gerg@snapgear.com> wrote: >> From: Greg Ungerer <gerg@uclinux.org> >> >> Basic set of definitions and support code required to turn on CONFIG_PCI >> for the m68k architecture. Nothing specific to any PCI implementation in >> any m68k class CPU hardware yet. >> >> Signed-off-by: Greg Ungerer <gerg@uclinux.org> > >> --- a/arch/m68k/include/asm/io_mm.h >> +++ b/arch/m68k/include/asm/io_mm.h >> @@ -340,4 +340,6 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int >> */ >> #define xlate_dev_kmem_ptr(p) p >> >> +#define ioport_map(port, nr) ((void __iomem *)(port)) > > So should we dop: > > config NO_IOPORT_MAP > def_bool y > > Triggered by seeing CONFIG_GPIO_TQMX86 being removed from allmodconfig > builds due to commit c6414e1a2bd26b00 ("gpio: AMD8111 and TQMX86 > require HAS_IOPORT_MAP"). I guess we could. But we would have to remove the iomap/iounmap definitions in kmap.h too right? Regards Greg ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 1/5] m68k: common PCI support definitions and code 2021-06-28 13:23 ` Greg Ungerer @ 2021-06-28 13:29 ` Geert Uytterhoeven 2021-06-28 13:58 ` Greg Ungerer 0 siblings, 1 reply; 10+ messages in thread From: Geert Uytterhoeven @ 2021-06-28 13:29 UTC (permalink / raw) To: Greg Ungerer; +Cc: Linux/m68k Hi Greg, On Mon, Jun 28, 2021 at 3:23 PM Greg Ungerer <gerg@linux-m68k.org> wrote: > On 28/6/21 5:44 pm, Geert Uytterhoeven wrote: > > On Mon, Jul 16, 2012 at 2:25 PM <gerg@snapgear.com> wrote: > >> From: Greg Ungerer <gerg@uclinux.org> > >> > >> Basic set of definitions and support code required to turn on CONFIG_PCI > >> for the m68k architecture. Nothing specific to any PCI implementation in > >> any m68k class CPU hardware yet. > >> > >> Signed-off-by: Greg Ungerer <gerg@uclinux.org> > > > >> --- a/arch/m68k/include/asm/io_mm.h > >> +++ b/arch/m68k/include/asm/io_mm.h > >> @@ -340,4 +340,6 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int > >> */ > >> #define xlate_dev_kmem_ptr(p) p > >> > >> +#define ioport_map(port, nr) ((void __iomem *)(port)) > > > > So should we dop: > > > > config NO_IOPORT_MAP > > def_bool y > > > > Triggered by seeing CONFIG_GPIO_TQMX86 being removed from allmodconfig > > builds due to commit c6414e1a2bd26b00 ("gpio: AMD8111 and TQMX86 > > require HAS_IOPORT_MAP"). > > I guess we could. > But we would have to remove the iomap/iounmap definitions in kmap.h too right? Why? Do I need more coffee? Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 1/5] m68k: common PCI support definitions and code 2021-06-28 13:29 ` Geert Uytterhoeven @ 2021-06-28 13:58 ` Greg Ungerer 0 siblings, 0 replies; 10+ messages in thread From: Greg Ungerer @ 2021-06-28 13:58 UTC (permalink / raw) To: Geert Uytterhoeven; +Cc: Linux/m68k Hi Geert, On 28/6/21 11:29 pm, Geert Uytterhoeven wrote: > Hi Greg, > > On Mon, Jun 28, 2021 at 3:23 PM Greg Ungerer <gerg@linux-m68k.org> wrote: >> On 28/6/21 5:44 pm, Geert Uytterhoeven wrote: >>> On Mon, Jul 16, 2012 at 2:25 PM <gerg@snapgear.com> wrote: >>>> From: Greg Ungerer <gerg@uclinux.org> >>>> >>>> Basic set of definitions and support code required to turn on CONFIG_PCI >>>> for the m68k architecture. Nothing specific to any PCI implementation in >>>> any m68k class CPU hardware yet. >>>> >>>> Signed-off-by: Greg Ungerer <gerg@uclinux.org> >>> >>>> --- a/arch/m68k/include/asm/io_mm.h >>>> +++ b/arch/m68k/include/asm/io_mm.h >>>> @@ -340,4 +340,6 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int >>>> */ >>>> #define xlate_dev_kmem_ptr(p) p >>>> >>>> +#define ioport_map(port, nr) ((void __iomem *)(port)) >>> >>> So should we dop: >>> >>> config NO_IOPORT_MAP >>> def_bool y >>> >>> Triggered by seeing CONFIG_GPIO_TQMX86 being removed from allmodconfig >>> builds due to commit c6414e1a2bd26b00 ("gpio: AMD8111 and TQMX86 >>> require HAS_IOPORT_MAP"). >> >> I guess we could. >> But we would have to remove the iomap/iounmap definitions in kmap.h too right? > > Why? Do I need more coffee? If you do this: diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index 372e4e69c43a..a6d4b2b1fe5a 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -59,9 +59,6 @@ config TIME_LOW_RES bool default y -config NO_IOPORT_MAP - def_bool y - config ZONE_DMA bool default y And the compile for an M5475 target for example you get this: CC lib/strncpy_from_user.o In file included from ./arch/m68k/include/asm/io_no.h:134, from ./arch/m68k/include/asm/io.h:6, from ./include/linux/io.h:13, from ./include/linux/irq.h:20, from ./include/asm-generic/hardirq.h:17, from ./arch/m68k/include/generated/asm/hardirq.h:1, from ./include/linux/hardirq.h:11, from ./include/linux/interrupt.h:11, from ./include/linux/pci.h:38, from lib/iomap.c:7: ./arch/m68k/include/asm/kmap.h:61:20: error: redefinition of ‘ioport_map’ #define ioport_map ioport_map ^~~~~~~~~~ lib/iomap.c:362:15: note: in expansion of macro ‘ioport_map’ void __iomem *ioport_map(unsigned long port, unsigned int nr) ^~~~~~~~~~ ./arch/m68k/include/asm/kmap.h:61:20: note: previous definition of ‘ioport_map’ was here #define ioport_map ioport_map ^~~~~~~~~~ ./arch/m68k/include/asm/kmap.h:62:29: note: in expansion of macro ‘ioport_map’ static inline void __iomem *ioport_map(unsigned long port, unsigned int nr) ^~~~~~~~~~ ./arch/m68k/include/asm/kmap.h:67:22: error: redefinition of ‘ioport_unmap’ #define ioport_unmap ioport_unmap ^~~~~~~~~~~~ lib/iomap.c:369:6: note: in expansion of macro ‘ioport_unmap’ void ioport_unmap(void __iomem *addr) ^~~~~~~~~~~~ ./arch/m68k/include/asm/kmap.h:67:22: note: previous definition of ‘ioport_unmap’ was here #define ioport_unmap ioport_unmap ^~~~~~~~~~~~ ./arch/m68k/include/asm/kmap.h:68:20: note: in expansion of macro ‘ioport_unmap’ static inline void ioport_unmap(void __iomem *p) ^~~~~~~~~~~~ Regards Greg ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 2/5] m68k: add PCI bus support definitions for the ColdFire M54xx SoC family 2012-07-16 12:27 [PATCH v2 0/5] ColdFire PCI bus support gerg 2012-07-16 12:27 ` [PATCH v2 1/5] m68k: common PCI support definitions and code gerg @ 2012-07-16 12:27 ` gerg 2012-07-16 12:27 ` [PATCH v2 3/5] m68k: add IO access definitions to support PCI on ColdFire platforms gerg ` (2 subsequent siblings) 4 siblings, 0 replies; 10+ messages in thread From: gerg @ 2012-07-16 12:27 UTC (permalink / raw) To: linux-m68k; +Cc: Greg Ungerer From: Greg Ungerer <gerg@uclinux.org> Add all the required definitoins to support the ColdFire M54xx SoC PCI hardware unit. These are strait out of the MCF5475 Reference Manual. Signed-off-by: Greg Ungerer <gerg@uclinux.org> --- arch/m68k/include/asm/m54xxpci.h | 138 ++++++++++++++++++++++++++++++++++++++ arch/m68k/include/asm/m54xxsim.h | 3 + 2 files changed, 141 insertions(+), 0 deletions(-) create mode 100644 arch/m68k/include/asm/m54xxpci.h diff --git a/arch/m68k/include/asm/m54xxpci.h b/arch/m68k/include/asm/m54xxpci.h new file mode 100644 index 0000000..6fbf54f --- /dev/null +++ b/arch/m68k/include/asm/m54xxpci.h @@ -0,0 +1,138 @@ +/****************************************************************************/ + +/* + * m54xxpci.h -- ColdFire 547x and 548x PCI bus support + * + * (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org> + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +/****************************************************************************/ +#ifndef M54XXPCI_H +#define M54XXPCI_H +/****************************************************************************/ + +/* + * The core set of PCI support registers are mapped into the MBAR region. + */ +#define PCIIDR (CONFIG_MBAR + 0xb00) /* PCI device/vendor ID */ +#define PCISCR (CONFIG_MBAR + 0xb04) /* PCI status/command */ +#define PCICCRIR (CONFIG_MBAR + 0xb08) /* PCI class/revision */ +#define PCICR1 (CONFIG_MBAR + 0xb0c) /* PCI configuration 1 */ +#define PCIBAR0 (CONFIG_MBAR + 0xb10) /* PCI base address 0 */ +#define PCIBAR1 (CONFIG_MBAR + 0xb14) /* PCI base address 1 */ +#define PCICCPR (CONFIG_MBAR + 0xb28) /* PCI cardbus CIS pointer */ +#define PCISID (CONFIG_MBAR + 0xb2c) /* PCI subsystem IDs */ +#define PCIERBAR (CONFIG_MBAR + 0xb30) /* PCI expansion ROM */ +#define PCICPR (CONFIG_MBAR + 0xb34) /* PCI capabilities pointer */ +#define PCICR2 (CONFIG_MBAR + 0xb3c) /* PCI configuration 2 */ + +#define PCIGSCR (CONFIG_MBAR + 0xb60) /* Global status/control */ +#define PCITBATR0 (CONFIG_MBAR + 0xb64) /* Target base translation 0 */ +#define PCITBATR1 (CONFIG_MBAR + 0xb68) /* Target base translation 1 */ +#define PCITCR (CONFIG_MBAR + 0xb6c) /* Target control */ +#define PCIIW0BTAR (CONFIG_MBAR + 0xb70) /* Initiator window 0 */ +#define PCIIW1BTAR (CONFIG_MBAR + 0xb74) /* Initiator window 1 */ +#define PCIIW2BTAR (CONFIG_MBAR + 0xb78) /* Initiator window 2 */ +#define PCIIWCR (CONFIG_MBAR + 0xb80) /* Initiator window config */ +#define PCIICR (CONFIG_MBAR + 0xb84) /* Initiator control */ +#define PCIISR (CONFIG_MBAR + 0xb88) /* Initiator status */ +#define PCICAR (CONFIG_MBAR + 0xbf8) /* Configuration address */ + +#define PCITPSR (CONFIG_MBAR + 0x8400) /* TX packet size */ +#define PCITSAR (CONFIG_MBAR + 0x8404) /* TX start address */ +#define PCITTCR (CONFIG_MBAR + 0x8408) /* TX transaction control */ +#define PCITER (CONFIG_MBAR + 0x840c) /* TX enables */ +#define PCITNAR (CONFIG_MBAR + 0x8410) /* TX next address */ +#define PCITLWR (CONFIG_MBAR + 0x8414) /* TX last word */ +#define PCITDCR (CONFIG_MBAR + 0x8418) /* TX done counts */ +#define PCITSR (CONFIG_MBAR + 0x841c) /* TX status */ +#define PCITFDR (CONFIG_MBAR + 0x8440) /* TX FIFO data */ +#define PCITFSR (CONFIG_MBAR + 0x8444) /* TX FIFO status */ +#define PCITFCR (CONFIG_MBAR + 0x8448) /* TX FIFO control */ +#define PCITFAR (CONFIG_MBAR + 0x844c) /* TX FIFO alarm */ +#define PCITFRPR (CONFIG_MBAR + 0x8450) /* TX FIFO read pointer */ +#define PCITFWPR (CONFIG_MBAR + 0x8454) /* TX FIFO write pointer */ + +#define PCIRPSR (CONFIG_MBAR + 0x8480) /* RX packet size */ +#define PCIRSAR (CONFIG_MBAR + 0x8484) /* RX start address */ +#define PCIRTCR (CONFIG_MBAR + 0x8488) /* RX transaction control */ +#define PCIRER (CONFIG_MBAR + 0x848c) /* RX enables */ +#define PCIRNAR (CONFIG_MBAR + 0x8490) /* RX next address */ +#define PCIRDCR (CONFIG_MBAR + 0x8498) /* RX done counts */ +#define PCIRSR (CONFIG_MBAR + 0x849c) /* RX status */ +#define PCIRFDR (CONFIG_MBAR + 0x84c0) /* RX FIFO data */ +#define PCIRFSR (CONFIG_MBAR + 0x84c4) /* RX FIFO status */ +#define PCIRFCR (CONFIG_MBAR + 0x84c8) /* RX FIFO control */ +#define PCIRFAR (CONFIG_MBAR + 0x84cc) /* RX FIFO alarm */ +#define PCIRFRPR (CONFIG_MBAR + 0x84d0) /* RX FIFO read pointer */ +#define PCIRFWPR (CONFIG_MBAR + 0x84d4) /* RX FIFO write pointer */ + +#define PACR (CONFIG_MBAR + 0xc00) /* PCI arbiter control */ +#define PASR (COFNIG_MBAR + 0xc04) /* PCI arbiter status */ + +/* + * Definitions for the Global status and control register. + */ +#define PCIGSCR_PE 0x20000000 /* Parity error detected */ +#define PCIGSCR_SE 0x10000000 /* System error detected */ +#define PCIGSCR_XCLKBIN 0x07000000 /* XLB2CLKIN mask */ +#define PCIGSCR_PEE 0x00002000 /* Parity error intr enable */ +#define PCIGSCR_SEE 0x00001000 /* System error intr enable */ +#define PCIGSCR_RESET 0x00000001 /* Reset bit */ + +/* + * Bit definitions for the PCICAR configuration address register. + */ +#define PCICAR_E 0x80000000 /* Enable config space */ +#define PCICAR_BUSN 16 /* Move bus bits */ +#define PCICAR_DEVFNN 8 /* Move devfn bits */ +#define PCICAR_DWORDN 0 /* Move dword bits */ + +/* + * The initiator windows hold the memory and IO mapping information. + * This macro creates the register values from the desired addresses. + */ +#define WXBTAR(hostaddr, pciaddr, size) \ + (((hostaddr) & 0xff000000) | \ + ((((size) - 1) & 0xff000000) >> 8) | \ + (((pciaddr) & 0xff000000) >> 16)) + +#define PCIIWCR_W0_MEM 0x00000000 /* Window 0 is memory */ +#define PCIIWCR_W0_IO 0x08000000 /* Window 0 is IO */ +#define PCIIWCR_W0_MRD 0x00000000 /* Window 0 memory read */ +#define PCIIWCR_W0_MRDL 0x02000000 /* Window 0 memory read line */ +#define PCIIWCR_W0_MRDM 0x04000000 /* Window 0 memory read mult */ +#define PCIIWCR_W0_E 0x01000000 /* Window 0 enable */ + +#define PCIIWCR_W1_MEM 0x00000000 /* Window 0 is memory */ +#define PCIIWCR_W1_IO 0x00080000 /* Window 0 is IO */ +#define PCIIWCR_W1_MRD 0x00000000 /* Window 0 memory read */ +#define PCIIWCR_W1_MRDL 0x00020000 /* Window 0 memory read line */ +#define PCIIWCR_W1_MRDM 0x00040000 /* Window 0 memory read mult */ +#define PCIIWCR_W1_E 0x00010000 /* Window 0 enable */ + +/* + * Bit definitions for the PCIBATR registers. + */ +#define PCITBATR0_E 0x00000001 /* Enable window 0 */ +#define PCITBATR1_E 0x00000001 /* Enable window 1 */ + +/* + * PCI arbiter support definitions and macros. + */ +#define PACR_INTMPRI 0x00000001 +#define PACR_EXTMPRI(x) (((x) & 0x1f) << 1) +#define PACR_INTMINTE 0x00010000 +#define PACR_EXTMINTE(x) (((x) & 0x1f) << 17) +#define PACR_PKMD 0x40000000 +#define PACR_DS 0x80000000 + +#define PCICR1_CL(x) ((x) & 0xf) /* Cacheline size field */ +#define PCICR1_LT(x) (((x) & 0xff) << 8) /* Latency timer field */ + +/****************************************************************************/ +#endif /* M54XXPCI_H */ diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h index ae56b88..d3c5e0d 100644 --- a/arch/m68k/include/asm/m54xxsim.h +++ b/arch/m68k/include/asm/m54xxsim.h @@ -81,4 +81,7 @@ #define MCF_PAR_PSC_RTS_RTS (0x30) #define MCF_PAR_PSC_CANRX (0x40) +#define MCF_PAR_PCIBG (CONFIG_MBAR + 0xa48) /* PCI bus grant */ +#define MCF_PAR_PCIBR (CONFIG_MBAR + 0xa4a) /* PCI */ + #endif /* m54xxsim_h */ -- 1.7.0.4 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 3/5] m68k: add IO access definitions to support PCI on ColdFire platforms 2012-07-16 12:27 [PATCH v2 0/5] ColdFire PCI bus support gerg 2012-07-16 12:27 ` [PATCH v2 1/5] m68k: common PCI support definitions and code gerg 2012-07-16 12:27 ` [PATCH v2 2/5] m68k: add PCI bus support definitions for the ColdFire M54xx SoC family gerg @ 2012-07-16 12:27 ` gerg 2012-07-16 12:27 ` [PATCH v2 4/5] m68k: add PCI bus code support for the ColdFire M54xx SoC family gerg 2012-07-16 12:27 ` [PATCH v2 5/5] m68k: allow PCI bus to be enabled for ColdFire m54xx CPUs gerg 4 siblings, 0 replies; 10+ messages in thread From: gerg @ 2012-07-16 12:27 UTC (permalink / raw) To: linux-m68k; +Cc: Greg Ungerer From: Greg Ungerer <gerg@uclinux.org> Define the usual memory access functions (readb/writeb/...) and I/O space functions (inb/outb/...) for PCI bus support on ColdFire CPU based platforms. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> --- arch/m68k/include/asm/io_mm.h | 48 ++++++++++++++++++++++++++++++++++++++++- 1 files changed, 47 insertions(+), 1 deletions(-) diff --git a/arch/m68k/include/asm/io_mm.h b/arch/m68k/include/asm/io_mm.h index b85dbef..a6686d2 100644 --- a/arch/m68k/include/asm/io_mm.h +++ b/arch/m68k/include/asm/io_mm.h @@ -65,7 +65,53 @@ -#ifdef CONFIG_ISA +#if defined(CONFIG_PCI) && defined(CONFIG_COLDFIRE) + +#define HAVE_ARCH_PIO_SIZE +#define PIO_OFFSET 0 +#define PIO_MASK 0xffff +#define PIO_RESERVED 0x10000 + +u8 mcf_pci_inb(u32 addr); +u16 mcf_pci_inw(u32 addr); +u32 mcf_pci_inl(u32 addr); +void mcf_pci_insb(u32 addr, u8 *buf, u32 len); +void mcf_pci_insw(u32 addr, u16 *buf, u32 len); +void mcf_pci_insl(u32 addr, u32 *buf, u32 len); + +void mcf_pci_outb(u8 v, u32 addr); +void mcf_pci_outw(u16 v, u32 addr); +void mcf_pci_outl(u32 v, u32 addr); +void mcf_pci_outsb(u32 addr, const u8 *buf, u32 len); +void mcf_pci_outsw(u32 addr, const u16 *buf, u32 len); +void mcf_pci_outsl(u32 addr, const u32 *buf, u32 len); + +#define inb mcf_pci_inb +#define inb_p mcf_pci_inb +#define inw mcf_pci_inw +#define inw_p mcf_pci_inw +#define inl mcf_pci_inl +#define inl_p mcf_pci_inl +#define insb mcf_pci_insb +#define insw mcf_pci_insw +#define insl mcf_pci_insl + +#define outb mcf_pci_outb +#define outb_p mcf_pci_outb +#define outw mcf_pci_outw +#define outw_p mcf_pci_outw +#define outl mcf_pci_outl +#define outl_p mcf_pci_outl +#define outsb mcf_pci_outsb +#define outsw mcf_pci_outsw +#define outsl mcf_pci_outsl + +#define readb(addr) in_8(addr) +#define writeb(v, addr) out_8((addr), (v)) +#define readw(addr) in_le16(addr) +#define writew(v, addr) out_le16((addr), (v)) + +#elif defined(CONFIG_ISA) #if MULTI_ISA == 0 #undef MULTI_ISA -- 1.7.0.4 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 4/5] m68k: add PCI bus code support for the ColdFire M54xx SoC family 2012-07-16 12:27 [PATCH v2 0/5] ColdFire PCI bus support gerg ` (2 preceding siblings ...) 2012-07-16 12:27 ` [PATCH v2 3/5] m68k: add IO access definitions to support PCI on ColdFire platforms gerg @ 2012-07-16 12:27 ` gerg 2012-07-16 12:27 ` [PATCH v2 5/5] m68k: allow PCI bus to be enabled for ColdFire m54xx CPUs gerg 4 siblings, 0 replies; 10+ messages in thread From: gerg @ 2012-07-16 12:27 UTC (permalink / raw) To: linux-m68k; +Cc: Greg Ungerer From: Greg Ungerer <gerg@uclinux.org> The ColdFire M54xx SoC family have a traditional PCI bus interface. Add the core support code to access and use this bus on these parts. This code provides all the config space access functions and IO access functions. It also carries out the PCI bus initialization and hooks into the kernel PCI subsystem. Signed-off-by: Greg Ungerer <gerg@uclinux.org> --- arch/m68k/platform/coldfire/Makefile | 2 + arch/m68k/platform/coldfire/pci.c | 327 ++++++++++++++++++++++++++++++++++ 2 files changed, 329 insertions(+), 0 deletions(-) create mode 100644 arch/m68k/platform/coldfire/pci.c diff --git a/arch/m68k/platform/coldfire/Makefile b/arch/m68k/platform/coldfire/Makefile index 76d389d..8d72a38 100644 --- a/arch/m68k/platform/coldfire/Makefile +++ b/arch/m68k/platform/coldfire/Makefile @@ -32,5 +32,7 @@ obj-$(CONFIG_NETtel) += nettel.o obj-$(CONFIG_CLEOPATRA) += nettel.o obj-$(CONFIG_FIREBEE) += firebee.o +obj-$(CONFIG_PCI) += pci.o + obj-y += pinmux.o gpio.o extra-y := head.o diff --git a/arch/m68k/platform/coldfire/pci.c b/arch/m68k/platform/coldfire/pci.c new file mode 100644 index 0000000..553210d --- /dev/null +++ b/arch/m68k/platform/coldfire/pci.c @@ -0,0 +1,327 @@ +/* + * pci.c -- PCI bus support for ColdFire processors + * + * (C) Copyright 2012, Greg Ungerer <gerg@uclinux.com> + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include <linux/types.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <linux/pci.h> +#include <linux/delay.h> +#include <asm/coldfire.h> +#include <asm/mcfsim.h> +#include <asm/m54xxpci.h> + +/* + * Memory and IO mappings. We use a 1:1 mapping for local host memory to + * PCI bus memory (no reason not to really). IO space doesn't matter, we + * always use access functions for that. The device configuration space is + * mapped over the IO map space when we enable it in the PCICAR register. + */ +#define PCI_MEM_PA 0xf0000000 /* Host physical address */ +#define PCI_MEM_BA 0xf0000000 /* Bus physical address */ +#define PCI_MEM_SIZE 0x08000000 /* 128 MB */ +#define PCI_MEM_MASK (PCI_MEM_SIZE - 1) + +#define PCI_IO_PA 0xf8000000 /* Host physical address */ +#define PCI_IO_BA 0x00000000 /* Bus physical address */ +#define PCI_IO_SIZE 0x00010000 /* 64k */ +#define PCI_IO_MASK (PCI_IO_SIZE - 1) + +static struct pci_bus *rootbus; +static unsigned long iospace; + +/* + * We need to be carefull probing on bus 0 (directly connected to host + * bridge). We should only acccess the well defined possible devices in + * use, ignore aliases and the like. + */ +static unsigned char mcf_host_slot2sid[32] = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 1, 2, 0, 3, 4, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, +}; + +static unsigned char mcf_host_irq[] = { + 0, 69, 69, 71, 71, +}; + + +static inline void syncio(void) +{ + /* The ColdFire "nop" instruction waits for all bus IO to complete */ + __asm__ __volatile__ ("nop"); +} + +/* + * Configuration space access functions. Configuration space access is + * through the IO mapping window, enabling it via the PCICAR register. + */ +static unsigned long mcf_mk_pcicar(int bus, unsigned int devfn, int where) +{ + return (bus << PCICAR_BUSN) | (devfn << PCICAR_DEVFNN) | (where & 0xfc); +} + +static int mcf_pci_readconfig(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *value) +{ + unsigned long addr; + + *value = 0xffffffff; + + if (bus->number == 0) { + if (mcf_host_slot2sid[PCI_SLOT(devfn)] == 0) + return PCIBIOS_SUCCESSFUL; + } + + syncio(); + addr = mcf_mk_pcicar(bus->number, devfn, where); + __raw_writel(PCICAR_E | addr, PCICAR); + addr = iospace + (where & 0x3); + + switch (size) { + case 1: + *value = __raw_readb(addr); + break; + case 2: + *value = le16_to_cpu(__raw_readw(addr)); + break; + default: + *value = le32_to_cpu(__raw_readl(addr)); + break; + } + + syncio(); + __raw_writel(0, PCICAR); + return PCIBIOS_SUCCESSFUL; +} + +static int mcf_pci_writeconfig(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 value) +{ + unsigned long addr; + + if (bus->number == 0) { + if (mcf_host_slot2sid[PCI_SLOT(devfn)] == 0) + return PCIBIOS_SUCCESSFUL; + } + + syncio(); + addr = mcf_mk_pcicar(bus->number, devfn, where); + __raw_writel(PCICAR_E | addr, PCICAR); + addr = iospace + (where & 0x3); + + switch (size) { + case 1: + __raw_writeb(value, addr); + break; + case 2: + __raw_writew(cpu_to_le16(value), addr); + break; + default: + __raw_writel(cpu_to_le32(value), addr); + break; + } + + syncio(); + __raw_writel(0, PCICAR); + return PCIBIOS_SUCCESSFUL; +} + +static struct pci_ops mcf_pci_ops = { + .read = mcf_pci_readconfig, + .write = mcf_pci_writeconfig, +}; + +/* + * IO address space access functions. Pretty strait forward, these are + * directly mapped in to the IO mapping window. And that is mapped into + * virtual address space. + */ +u8 mcf_pci_inb(u32 addr) +{ + return __raw_readb(iospace + (addr & PCI_IO_MASK)); +} +EXPORT_SYMBOL(mcf_pci_inb); + +u16 mcf_pci_inw(u32 addr) +{ + return le16_to_cpu(__raw_readw(iospace + (addr & PCI_IO_MASK))); +} +EXPORT_SYMBOL(mcf_pci_inw); + +u32 mcf_pci_inl(u32 addr) +{ + return le32_to_cpu(__raw_readl(iospace + (addr & PCI_IO_MASK))); +} +EXPORT_SYMBOL(mcf_pci_inl); + +void mcf_pci_insb(u32 addr, u8 *buf, u32 len) +{ + for (; len; len--) + *buf++ = mcf_pci_inb(addr); +} +EXPORT_SYMBOL(mcf_pci_insb); + +void mcf_pci_insw(u32 addr, u16 *buf, u32 len) +{ + for (; len; len--) + *buf++ = mcf_pci_inw(addr); +} +EXPORT_SYMBOL(mcf_pci_insw); + +void mcf_pci_insl(u32 addr, u32 *buf, u32 len) +{ + for (; len; len--) + *buf++ = mcf_pci_inl(addr); +} +EXPORT_SYMBOL(mcf_pci_insl); + +void mcf_pci_outb(u8 v, u32 addr) +{ + __raw_writeb(v, iospace + (addr & PCI_IO_MASK)); +} +EXPORT_SYMBOL(mcf_pci_outb); + +void mcf_pci_outw(u16 v, u32 addr) +{ + __raw_writew(cpu_to_le16(v), iospace + (addr & PCI_IO_MASK)); +} +EXPORT_SYMBOL(mcf_pci_outw); + +void mcf_pci_outl(u32 v, u32 addr) +{ + __raw_writel(cpu_to_le32(v), iospace + (addr & PCI_IO_MASK)); +} +EXPORT_SYMBOL(mcf_pci_outl); + +void mcf_pci_outsb(u32 addr, const u8 *buf, u32 len) +{ + for (; len; len--) + mcf_pci_outb(*buf++, addr); +} +EXPORT_SYMBOL(mcf_pci_outsb); + +void mcf_pci_outsw(u32 addr, const u16 *buf, u32 len) +{ + for (; len; len--) + mcf_pci_outw(*buf++, addr); +} +EXPORT_SYMBOL(mcf_pci_outsw); + +void mcf_pci_outsl(u32 addr, const u32 *buf, u32 len) +{ + for (; len; len--) + mcf_pci_outl(*buf++, addr); +} +EXPORT_SYMBOL(mcf_pci_outsl); + +/* + * Initialize the PCI bus registers, and scan the bus. + */ +static struct resource mcf_pci_mem = { + .name = "PCI Memory space", + .start = PCI_MEM_PA, + .end = PCI_MEM_PA + PCI_MEM_SIZE - 1, + .flags = IORESOURCE_MEM, +}; + +static struct resource mcf_pci_io = { + .name = "PCI IO space", + .start = 0x400, + .end = 0x10000 - 1, + .flags = IORESOURCE_IO, +}; + +/* + * Interrupt mapping and setting. + */ +static int mcf_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + int sid; + + sid = mcf_host_slot2sid[slot]; + if (sid) + return mcf_host_irq[sid]; + return 0; +} + +static int __init mcf_pci_init(void) +{ + pr_info("ColdFire: PCI bus initialization...\n"); + + /* Reset the external PCI bus */ + __raw_writel(PCIGSCR_RESET, PCIGSCR); + __raw_writel(0, PCITCR); + + request_resource(&iomem_resource, &mcf_pci_mem); + request_resource(&iomem_resource, &mcf_pci_io); + + /* Configure PCI arbiter */ + __raw_writel(PACR_INTMPRI | PACR_INTMINTE | PACR_EXTMPRI(0x1f) | + PACR_EXTMINTE(0x1f), PACR); + + /* Set required multi-function pins for PCI bus use */ + __raw_writew(0x3ff, MCF_PAR_PCIBG); + __raw_writew(0x3ff, MCF_PAR_PCIBR); + + /* Set up config space for local host bus controller */ + __raw_writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | + PCI_COMMAND_INVALIDATE, PCISCR); + __raw_writel(PCICR1_LT(32) | PCICR1_CL(8), PCICR1); + __raw_writel(0, PCICR2); + + /* + * Set up the initiator windows for memory and IO mapping. + * These give the CPU bus access onto the PCI bus. One for each of + * PCI memory and IO address spaces. + */ + __raw_writel(WXBTAR(PCI_MEM_PA, PCI_MEM_BA, PCI_MEM_SIZE), + PCIIW0BTAR); + __raw_writel(WXBTAR(PCI_IO_PA, PCI_IO_BA, PCI_IO_SIZE), + PCIIW1BTAR); + __raw_writel(PCIIWCR_W0_MEM /*| PCIIWCR_W0_MRDL*/ | PCIIWCR_W0_E | + PCIIWCR_W1_IO | PCIIWCR_W1_E, PCIIWCR); + + /* + * Set up the target windows for access from the PCI bus back to the + * CPU bus. All we need is access to system RAM (for mastering). + */ + __raw_writel(CONFIG_RAMBASE, PCIBAR1); + __raw_writel(CONFIG_RAMBASE | PCITBATR1_E, PCITBATR1); + + /* Keep a virtual mapping to IO/config space active */ + iospace = (unsigned long) ioremap(PCI_IO_PA, PCI_IO_SIZE); + if (iospace == 0) + return -ENODEV; + pr_info("Coldfire: PCI IO/config window mapped to 0x%x\n", + (u32) iospace); + + /* Turn of PCI reset, and wait for devices to settle */ + __raw_writel(0, PCIGSCR); + set_current_state(TASK_UNINTERRUPTIBLE); + schedule_timeout(msecs_to_jiffies(200)); + + rootbus = pci_scan_bus(0, &mcf_pci_ops, NULL); + rootbus->resource[0] = &mcf_pci_io; + rootbus->resource[1] = &mcf_pci_mem; + + pci_fixup_irqs(pci_common_swizzle, mcf_pci_map_irq); + pci_bus_size_bridges(rootbus); + pci_bus_assign_resources(rootbus); + pci_enable_bridges(rootbus); + pci_bus_add_devices(rootbus); + return 0; +} + +subsys_initcall(mcf_pci_init); -- 1.7.0.4 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 5/5] m68k: allow PCI bus to be enabled for ColdFire m54xx CPUs 2012-07-16 12:27 [PATCH v2 0/5] ColdFire PCI bus support gerg ` (3 preceding siblings ...) 2012-07-16 12:27 ` [PATCH v2 4/5] m68k: add PCI bus code support for the ColdFire M54xx SoC family gerg @ 2012-07-16 12:27 ` gerg 4 siblings, 0 replies; 10+ messages in thread From: gerg @ 2012-07-16 12:27 UTC (permalink / raw) To: linux-m68k; +Cc: Greg Ungerer From: Greg Ungerer <gerg@uclinux.org> All support code for the PCI bus hardware on the ColdFire 547x and 548x CPUs is now in. Allow enabling of CONFIG_PCI for them. Signed-off-by: Greg Ungerer <gerg@uclinux.org> --- arch/m68k/Kconfig.bus | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/arch/m68k/Kconfig.bus b/arch/m68k/Kconfig.bus index 3adb499..ffc0601 100644 --- a/arch/m68k/Kconfig.bus +++ b/arch/m68k/Kconfig.bus @@ -48,6 +48,13 @@ config ISA config GENERIC_ISA_DMA def_bool ISA +config PCI + bool "PCI support" + depends on M54xx + help + Enable the PCI bus. Support for the PCI bus hardware built into the + ColdFire 547x and 548x processors. + source "drivers/pci/Kconfig" source "drivers/zorro/Kconfig" -- 1.7.0.4 ^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2021-06-28 13:58 UTC | newest] Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2012-07-16 12:27 [PATCH v2 0/5] ColdFire PCI bus support gerg 2012-07-16 12:27 ` [PATCH v2 1/5] m68k: common PCI support definitions and code gerg 2021-06-28 7:44 ` Geert Uytterhoeven 2021-06-28 13:23 ` Greg Ungerer 2021-06-28 13:29 ` Geert Uytterhoeven 2021-06-28 13:58 ` Greg Ungerer 2012-07-16 12:27 ` [PATCH v2 2/5] m68k: add PCI bus support definitions for the ColdFire M54xx SoC family gerg 2012-07-16 12:27 ` [PATCH v2 3/5] m68k: add IO access definitions to support PCI on ColdFire platforms gerg 2012-07-16 12:27 ` [PATCH v2 4/5] m68k: add PCI bus code support for the ColdFire M54xx SoC family gerg 2012-07-16 12:27 ` [PATCH v2 5/5] m68k: allow PCI bus to be enabled for ColdFire m54xx CPUs gerg
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