[RFC v3 00/13] Exynos5 IS driver

[RFC v3 00/13] Exynos5 IS driver

[Arun Kumar K]

The patch series add support for Exynos5 camera subsystem. It
re-uses mipi-csis and fimc-lite from exynos4-is and adds a new
media device and fimc-is device drivers for exynos5.
The media device supports asynchronos subdev registration for the
fimc-is sensors and is based on the patch series from Sylwester
for exynos4-is [1].

[1] http://www.mail-archive.com/linux-media@vger.kernel.org/msg64653.html

Changes from v2
---------------
- Added exynos5 media device driver from Shaik to this series
- Added ISP pipeline support in media device driver
- Based on Sylwester's latest exynos4-is development
- Asynchronos registration of sensor subdevs
- Made independent IS-sensor support
- Add s5k4e5 sensor driver
- Addressed review comments from Sylwester, Hans, Andrzej, Sachin

Changes from v1
---------------
- Addressed all review comments from Sylwester
- Made sensor subdevs as independent i2c devices
- Lots of cleanup
- Debugfs support added
- Removed PMU global register access

Arun Kumar K (12):
  [media] exynos5-fimc-is: Add Exynos5 FIMC-IS device tree bindings
    documentation
  [media] exynos5-fimc-is: Add driver core files
  [media] exynos5-fimc-is: Add common driver header files
  [media] exynos5-fimc-is: Add register definition and context header
  [media] exynos5-fimc-is: Add isp subdev
  [media] exynos5-fimc-is: Add scaler subdev
  [media] exynos5-fimc-is: Add sensor interface
  [media] exynos5-fimc-is: Add the hardware pipeline control
  [media] exynos5-fimc-is: Add the hardware interface module
  [media] exynos5-is: Add Kconfig and Makefile
  V4L: s5k6a3: Change sensor min/max resolutions
  V4L: Add driver for s5k4e5 image sensor

Shaik Ameer Basha (1):
  [media] exynos5-is: Adding media device driver for exynos5

 .../devicetree/bindings/media/exynos5-fimc-is.txt  |   52 +
 .../devicetree/bindings/media/exynos5-mdev.txt     |  153 ++
 drivers/media/i2c/Kconfig                          |    8 +
 drivers/media/i2c/Makefile                         |    1 +
 drivers/media/i2c/s5k4e5.c                         |  362 ++++
 drivers/media/i2c/s5k6a3.c                         |   14 +-
 drivers/media/platform/Kconfig                     |    1 +
 drivers/media/platform/Makefile                    |    1 +
 drivers/media/platform/exynos5-is/Kconfig          |   19 +
 drivers/media/platform/exynos5-is/Makefile         |    7 +
 drivers/media/platform/exynos5-is/exynos5-mdev.c   | 1471 +++++++++++++++
 drivers/media/platform/exynos5-is/exynos5-mdev.h   |  199 ++
 drivers/media/platform/exynos5-is/fimc-is-cmd.h    |  187 ++
 drivers/media/platform/exynos5-is/fimc-is-core.c   |  394 ++++
 drivers/media/platform/exynos5-is/fimc-is-core.h   |  122 ++
 drivers/media/platform/exynos5-is/fimc-is-err.h    |  257 +++
 .../media/platform/exynos5-is/fimc-is-interface.c  |  861 +++++++++
 .../media/platform/exynos5-is/fimc-is-interface.h  |  128 ++
 drivers/media/platform/exynos5-is/fimc-is-isp.c    |  509 +++++
 drivers/media/platform/exynos5-is/fimc-is-isp.h    |   93 +
 .../media/platform/exynos5-is/fimc-is-metadata.h   |  767 ++++++++
 drivers/media/platform/exynos5-is/fimc-is-param.h  | 1212 ++++++++++++
 .../media/platform/exynos5-is/fimc-is-pipeline.c   | 1961 ++++++++++++++++++++
 .../media/platform/exynos5-is/fimc-is-pipeline.h   |  129 ++
 drivers/media/platform/exynos5-is/fimc-is-regs.h   |  105 ++
 drivers/media/platform/exynos5-is/fimc-is-scaler.c |  458 +++++
 drivers/media/platform/exynos5-is/fimc-is-scaler.h |  112 ++
 drivers/media/platform/exynos5-is/fimc-is-sensor.c |   46 +
 drivers/media/platform/exynos5-is/fimc-is-sensor.h |   69 +
 drivers/media/platform/exynos5-is/fimc-is.h        |  153 ++
 30 files changed, 9847 insertions(+), 4 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
 create mode 100644 Documentation/devicetree/bindings/media/exynos5-mdev.txt
 create mode 100644 drivers/media/i2c/s5k4e5.c
 create mode 100644 drivers/media/platform/exynos5-is/Kconfig
 create mode 100644 drivers/media/platform/exynos5-is/Makefile
 create mode 100644 drivers/media/platform/exynos5-is/exynos5-mdev.c
 create mode 100644 drivers/media/platform/exynos5-is/exynos5-mdev.h
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-cmd.h
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.c
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.h
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-err.h
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-interface.c
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-interface.h
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-isp.c
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-isp.h
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-metadata.h
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-param.h
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-pipeline.c
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-pipeline.h
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-regs.h
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-scaler.c
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-scaler.h
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-sensor.c
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-sensor.h
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is.h

-- 
1.7.9.5

[RFC v3 01/13] [media] exynos5-is: Adding media device driver for exynos5

[Arun Kumar K]

From: Shaik Ameer Basha <shaik.ameer@samsung.com>

This patch adds support for media device for EXYNOS5 SoCs.
The current media device supports the following ips to connect
through the media controller framework.

* MIPI-CSIS
  Support interconnection(subdev interface) between devices

* FIMC-LITE
  Support capture interface from device(Sensor, MIPI-CSIS) to memory
  Support interconnection(subdev interface) between devices

* FIMC-IS
  Camera post-processing IP having multiple sub-nodes.

G-Scaler will be added later to the current media device.

The media device creates two kinds of pipelines for connecting
the above mentioned IPs.
The pipeline0 is uses Sensor, MIPI-CSIS and FIMC-LITE which captures
image data and dumps to memory.
Pipeline1 uses FIMC-IS components for doing post-processing
operations on the captured image and give scaled YUV output.

Pipeline0
  +--------+     +-----------+     +-----------+     +--------+
  | Sensor | --> | MIPI-CSIS | --> | FIMC-LITE | --> | Memory |
  +--------+     +-----------+     +-----------+     +--------+

Pipeline1
 +--------+      +--------+     +-----------+     +-----------+
 | Memory | -->  |  ISP   | --> |    SCC    | --> |    SCP    |
 +--------+      +--------+     +-----------+     +-----------+

Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
---
 .../devicetree/bindings/media/exynos5-mdev.txt     |  153 ++
 drivers/media/platform/exynos5-is/exynos5-mdev.c   | 1471 ++++++++++++++++++++
 drivers/media/platform/exynos5-is/exynos5-mdev.h   |  199 +++
 3 files changed, 1823 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/exynos5-mdev.txt
 create mode 100644 drivers/media/platform/exynos5-is/exynos5-mdev.c
 create mode 100644 drivers/media/platform/exynos5-is/exynos5-mdev.h

diff --git a/Documentation/devicetree/bindings/media/exynos5-mdev.txt b/Documentation/devicetree/bindings/media/exynos5-mdev.txt
new file mode 100644
index 0000000..d7d419b
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/exynos5-mdev.txt
@@ -0,0 +1,153 @@
+Samsung EXYNOS5 SoC Camera Subsystem (FIMC)
+----------------------------------------------
+
+The Exynos5 SoC Camera subsystem comprises of multiple sub-devices
+represented by separate device tree nodes. Currently this includes: FIMC-LITE,
+MIPI CSIS and FIMC-IS.
+
+The sub-subdevices are defined as child nodes of the common 'camera' node which
+also includes common properties of the whole subsystem not really specific to
+any single sub-device, like common camera port pins or the CAMCLK clock outputs
+for external image sensors attached to an SoC.
+
+Common 'camera' node
+--------------------
+
+Required properties:
+
+- compatible	: must be "samsung,exynos5-fimc", "simple-bus"
+- clocks	: list of clock specifiers, corresponding to entries in
+		  the clock-names property;
+- clock-names	: must contain "sclk_cam0", "sclk_cam1" entries,
+		  matching entries in the clocks property.
+
+The pinctrl bindings defined in ../pinctrl/pinctrl-bindings.txt must be used
+to define a required pinctrl state named "default" and optional pinctrl states:
+"idle", "active-a", active-b". These optional states can be used to switch the
+camera port pinmux at runtime. The "idle" state should configure both the camera
+ports A and B into high impedance state, especially the CAMCLK clock output
+should be inactive. For the "active-a" state the camera port A must be activated
+and the port B deactivated and for the state "active-b" it should be the other
+way around.
+
+The 'camera' node must include at least one 'fimc-lite' child node.
+
+'parallel-ports' node
+---------------------
+
+This node should contain child 'port' nodes specifying active parallel video
+input ports. It includes camera A and camera B inputs. 'reg' property in the
+port nodes specifies data input - 0, 1 indicates input A, B respectively.
+
+Optional properties
+
+- samsung,camclk-out : specifies clock output for remote sensor,
+		       0 - CAM_A_CLKOUT, 1 - CAM_B_CLKOUT;
+
+Image sensor nodes
+------------------
+
+The sensor device nodes should be added to their control bus controller (e.g.
+I2C0) nodes and linked to a port node in the csis or the parallel-ports node,
+using the common video interfaces bindings, defined in video-interfaces.txt.
+The implementation of this bindings requires clock-frequency property to be
+present in the sensor device nodes.
+
+Example:
+
+	aliases {
+		fimc-lite0 = &fimc_lite_0
+	};
+
+	/* Parallel bus IF sensor */
+	i2c_0: i2c@13860000 {
+		s5k6aa: sensor@3c {
+			compatible = "samsung,s5k6aafx";
+			reg = <0x3c>;
+			vddio-supply = <...>;
+
+			clock-frequency = <24000000>;
+			clocks = <...>;
+			clock-names = "mclk";
+
+			port {
+				s5k6aa_ep: endpoint {
+					remote-endpoint = <&fimc0_ep>;
+					bus-width = <8>;
+					hsync-active = <0>;
+					vsync-active = <1>;
+					pclk-sample = <1>;
+				};
+			};
+		};
+	};
+
+	/* MIPI CSI-2 bus IF sensor */
+	s5c73m3: sensor@0x1a {
+		compatible = "samsung,s5c73m3";
+		reg = <0x1a>;
+		vddio-supply = <...>;
+
+		clock-frequency = <24000000>;
+		clocks = <...>;
+		clock-names = "mclk";
+
+		port {
+			s5c73m3_1: endpoint {
+				data-lanes = <1 2 3 4>;
+				remote-endpoint = <&csis0_ep>;
+			};
+		};
+	};
+
+	camera {
+		compatible = "samsung,exynos5-fimc", "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		status = "okay";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&cam_port_a_clk_active>;
+
+		/* parallel camera ports */
+		parallel-ports {
+			/* camera A input */
+			port@0 {
+				reg = <0>;
+				fimc0_ep: endpoint {
+					remote-endpoint = <&s5k6aa_ep>;
+					bus-width = <8>;
+					hsync-active = <0>;
+					vsync-active = <1>;
+					pclk-sample = <1>;
+				};
+			};
+		};
+
+		fimc_lite_0: fimc-lite@13C00000 {
+			compatible = "samsung,exynos5250-fimc-lite";
+			reg = <0x13C00000 0x1000>;
+			interrupts = <0 126 0>;
+			clocks = <&clock 129>;
+			clock-names = "flite";
+			status = "okay";
+		};
+
+		csis_0: csis@11880000 {
+			compatible = "samsung,exynos4210-csis";
+			reg = <0x11880000 0x1000>;
+			interrupts = <0 78 0>;
+			/* camera C input */
+			port@3 {
+				reg = <3>;
+				csis0_ep: endpoint {
+					remote-endpoint = <&s5c73m3_ep>;
+					data-lanes = <1 2 3 4>;
+					samsung,csis-hs-settle = <12>;
+				};
+			};
+		};
+	};
+
+MIPI-CSIS device binding is defined in samsung-mipi-csis.txt and FIMC-LITE
+device binding is defined in exynos-fimc-lite.txt.
diff --git a/drivers/media/platform/exynos5-is/exynos5-mdev.c b/drivers/media/platform/exynos5-is/exynos5-mdev.c
new file mode 100644
index 0000000..b59738f
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/exynos5-mdev.c
@@ -0,0 +1,1471 @@
+/*
+ * EXYNOS5 SoC series camera host interface media device driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Shaik Ameer Basha <shaik.ameer@samsung.com>
+ * Arun Kumar K <arun.kk@samsung.com>
+ *
+ * This driver is based on exynos4-is media device driver developed by
+ * Sylwester Nawrocki <s.nawrocki@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published
+ * by the Free Software Foundation, either version 2 of the License,
+ * or (at your option) any later version.
+ */
+
+#include <linux/bug.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/i2c.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/of_device.h>
+#include <linux/of_i2c.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <media/v4l2-async.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-of.h>
+#include <media/media-device.h>
+#include <media/s5p_fimc.h>
+
+#include "exynos5-mdev.h"
+#include "fimc-is.h"
+
+#define dbg(fmt, args...) \
+	pr_debug("%s:%d: " fmt "\n", __func__, __LINE__, ##args)
+
+static int __fimc_md_set_camclk(struct fimc_md *fmd,
+				struct fimc_source_info *si,
+				bool on);
+
+/**
+ * fimc_pipeline_prepare - update pipeline information with subdevice pointers
+ * @me: media entity terminating the pipeline
+ *
+ * Caller holds the graph mutex.
+ */
+static void fimc_pipeline_prepare(struct fimc_pipeline *p,
+				  struct media_entity *me)
+{
+	struct v4l2_subdev *sd;
+	int i;
+
+	for (i = 0; i < IDX_MAX; i++)
+		p->subdevs[i] = NULL;
+
+	while (1) {
+		struct media_pad *pad = NULL;
+
+		/* Find remote source pad */
+		for (i = 0; i < me->num_pads; i++) {
+			struct media_pad *spad = &me->pads[i];
+			if (!(spad->flags & MEDIA_PAD_FL_SINK))
+				continue;
+			pad = media_entity_remote_pad(spad);
+			if (pad)
+				break;
+		}
+
+		if (pad == NULL ||
+		    media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV) {
+			break;
+		}
+		sd = media_entity_to_v4l2_subdev(pad->entity);
+
+		switch (sd->grp_id) {
+		case GRP_ID_FIMC_IS_SENSOR:
+		case GRP_ID_SENSOR:
+			p->subdevs[IDX_SENSOR] = sd;
+			break;
+		case GRP_ID_CSIS:
+			p->subdevs[IDX_CSIS] = sd;
+			break;
+		case GRP_ID_FLITE:
+			p->subdevs[IDX_FLITE] = sd;
+			break;
+		default:
+			pr_warn("%s: Unknown subdev grp_id: %#x\n",
+				__func__, sd->grp_id);
+		}
+		me = &sd->entity;
+		if (me->num_pads == 1)
+			break;
+	}
+
+	/* For using FIMC-IS firmware controlled sensors, ISP subdev
+	 * has to be initialized along with pipeline0 devices.
+	 * So an ISP subdev from a free ISP pipeline is assigned to
+	 * this pipeline
+	 */
+	if (p->subdevs[IDX_SENSOR]->grp_id == GRP_ID_FIMC_IS_SENSOR) {
+		struct fimc_pipeline_isp *p_isp;
+
+		list_for_each_entry(p_isp, p->isp_pipelines, list) {
+			if (!p_isp->in_use) {
+				p->subdevs[IDX_FIMC_IS] =
+					p_isp->subdevs[IDX_ISP];
+				p_isp->in_use = true;
+				break;
+			}
+		}
+	}
+}
+
+/**
+ * __subdev_set_power - change power state of a single subdev
+ * @sd: subdevice to change power state for
+ * @on: 1 to enable power or 0 to disable
+ *
+ * Return result of s_power subdev operation or -ENXIO if sd argument
+ * is NULL. Return 0 if the subdevice does not implement s_power.
+ */
+static int __subdev_set_power(struct v4l2_subdev *sd, int on)
+{
+	int *use_count;
+	int ret;
+
+	if (sd == NULL)
+		return -ENXIO;
+
+	use_count = &sd->entity.use_count;
+	if (on && (*use_count)++ > 0)
+		return 0;
+	else if (!on && (*use_count == 0 || --(*use_count) > 0))
+		return 0;
+	ret = v4l2_subdev_call(sd, core, s_power, on);
+
+	return ret != -ENOIOCTLCMD ? ret : 0;
+}
+
+/**
+ * fimc_pipeline_s_power - change power state of all pipeline subdevs
+ * @fimc: fimc device terminating the pipeline
+ * @state: true to power on, false to power off
+ *
+ * Needs to be called with the graph mutex held.
+ */
+static int fimc_pipeline_s_power(struct fimc_pipeline *p, bool state)
+{
+	unsigned int i;
+	int ret;
+	struct fimc_is_isp *isp_dev;
+
+	if (p->subdevs[IDX_SENSOR] == NULL)
+		return -ENXIO;
+
+	/* If sensor is firmware controlled IS-sensor,
+	 * set sensor sd to isp context
+	 */
+	if (p->subdevs[IDX_FIMC_IS]) {
+		isp_dev = v4l2_get_subdevdata(p->subdevs[IDX_FIMC_IS]);
+		isp_dev->sensor_sd = p->subdevs[IDX_SENSOR];
+	}
+
+	for (i = 0; i < IDX_MAX; i++) {
+		unsigned int idx = state ? i : (IDX_MAX - 1) - i;
+
+		ret = __subdev_set_power(p->subdevs[idx], state);
+		if (ret < 0 && ret != -ENXIO)
+			return ret;
+	}
+
+	return 0;
+}
+
+/**
+ * fimc_md_set_camclk - peripheral sensor clock setup
+ * @sd: sensor subdev to configure sclk_cam clock for
+ * @on: 1 to enable or 0 to disable the clock
+ *
+ * There are 2 separate clock outputs available in the SoC for external
+ * image processors. These clocks are shared between all registered FIMC
+ * devices to which sensors can be attached, either directly or through
+ * the MIPI CSI receiver. The clock is allowed here to be used by
+ * multiple sensors concurrently if they use same frequency.
+ * This function should only be called when the graph mutex is held.
+ */
+static int fimc_md_set_camclk(struct v4l2_subdev *sd, bool on)
+{
+	struct fimc_source_info *si = v4l2_get_subdev_hostdata(sd);
+	struct fimc_md *fmd = entity_to_fimc_mdev(&sd->entity);
+
+	return __fimc_md_set_camclk(fmd, si, on);
+}
+
+/**
+ * __fimc_pipeline_open - update the pipeline information, enable power
+ *                        of all pipeline subdevs and the sensor clock
+ * @me: media entity to start graph walk with
+ * @prepare: true to walk the current pipeline and acquire all subdevs
+ *
+ * Called with the graph mutex held.
+ */
+static int __fimc_pipeline_open(struct exynos_media_pipeline *ep,
+				struct media_entity *me, bool prepare)
+{
+	struct fimc_pipeline *p = to_fimc_pipeline(ep);
+	struct v4l2_subdev *sd;
+	int ret;
+
+	if (WARN_ON(p == NULL || me == NULL))
+		return -EINVAL;
+
+	if (prepare)
+		fimc_pipeline_prepare(p, me);
+
+	sd = p->subdevs[IDX_SENSOR];
+	if (sd == NULL)
+		return -EINVAL;
+
+	ret = fimc_md_set_camclk(sd, true);
+	if (ret < 0)
+		return ret;
+
+	ret = fimc_pipeline_s_power(p, 1);
+	if (!ret)
+		return 0;
+
+	fimc_md_set_camclk(sd, false);
+	return ret;
+}
+
+/**
+ * __fimc_pipeline_close - disable the sensor clock and pipeline power
+ * @fimc: fimc device terminating the pipeline
+ *
+ * Disable power of all subdevs and turn the external sensor clock off.
+ */
+static int __fimc_pipeline_close(struct exynos_media_pipeline *ep)
+{
+	struct fimc_pipeline *p = to_fimc_pipeline(ep);
+	struct v4l2_subdev *sd = p ? p->subdevs[IDX_SENSOR] : NULL;
+	int ret = 0;
+
+	if (WARN_ON(sd == NULL))
+		return -EINVAL;
+
+	if (p->subdevs[IDX_SENSOR]) {
+		ret = fimc_pipeline_s_power(p, 0);
+		fimc_md_set_camclk(sd, false);
+	}
+
+	if (p->subdevs[IDX_SENSOR]->grp_id == GRP_ID_FIMC_IS_SENSOR) {
+		struct fimc_pipeline_isp *p_isp;
+
+		list_for_each_entry(p_isp, p->isp_pipelines, list) {
+			if (p_isp->subdevs[IDX_ISP] ==
+					p->subdevs[IDX_FIMC_IS]) {
+				p->subdevs[IDX_FIMC_IS] = NULL;
+				p_isp->in_use = false;
+				break;
+			}
+		}
+	}
+	return ret == -ENXIO ? 0 : ret;
+}
+
+/**
+ * __fimc_pipeline_s_stream - call s_stream() on pipeline subdevs
+ * @pipeline: video pipeline structure
+ * @on: passed as the s_stream() callback argument
+ */
+static int __fimc_pipeline_s_stream(struct exynos_media_pipeline *ep, bool on)
+{
+	struct fimc_pipeline *p = to_fimc_pipeline(ep);
+	int i, ret;
+
+	if (p->subdevs[IDX_SENSOR] == NULL)
+		return -ENODEV;
+
+	for (i = 0; i < IDX_MAX; i++) {
+		unsigned int idx = on ? i : (IDX_MAX - 1) - i;
+
+		ret = v4l2_subdev_call(p->subdevs[idx], video, s_stream, on);
+
+		if (ret < 0 && ret != -ENOIOCTLCMD && ret != -ENODEV)
+			return ret;
+	}
+	return 0;
+}
+
+/* Media pipeline operations for the FIMC/FIMC-LITE video device driver */
+static const struct exynos_media_pipeline_ops exynos5_pipeline0_ops = {
+	.open		= __fimc_pipeline_open,
+	.close		= __fimc_pipeline_close,
+	.set_stream	= __fimc_pipeline_s_stream,
+};
+
+static struct exynos_media_pipeline *fimc_md_pipeline_create(
+						struct fimc_md *fmd)
+{
+	struct fimc_pipeline *p;
+
+	p = kzalloc(sizeof(*p), GFP_KERNEL);
+	if (!p)
+		return NULL;
+
+	list_add_tail(&p->list, &fmd->pipelines);
+
+	p->isp_pipelines = &fmd->isp_pipelines;
+	p->ep.ops = &exynos5_pipeline0_ops;
+	return &p->ep;
+}
+
+static struct exynos_media_pipeline *fimc_md_isp_pipeline_create(
+						struct fimc_md *fmd)
+{
+	struct fimc_pipeline_isp *p;
+
+	p = kzalloc(sizeof(*p), GFP_KERNEL);
+	if (!p)
+		return NULL;
+
+	list_add_tail(&p->list, &fmd->isp_pipelines);
+
+	p->in_use = false;
+	return &p->ep;
+}
+
+static void fimc_md_pipelines_free(struct fimc_md *fmd)
+{
+	while (!list_empty(&fmd->pipelines)) {
+		struct fimc_pipeline *p;
+
+		p = list_entry(fmd->pipelines.next, typeof(*p), list);
+		list_del(&p->list);
+		kfree(p);
+	}
+	while (!list_empty(&fmd->isp_pipelines)) {
+		struct fimc_pipeline_isp *p;
+
+		p = list_entry(fmd->isp_pipelines.next, typeof(*p), list);
+		list_del(&p->list);
+		kfree(p);
+	}
+}
+
+/*
+ * Sensor subdevice helper functions
+ */
+static void fimc_md_unregister_sensor(struct v4l2_subdev *sd)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct i2c_adapter *adapter;
+
+	if (!client)
+		return;
+
+	v4l2_device_unregister_subdev(sd);
+
+	if (!client->dev.of_node) {
+		adapter = client->adapter;
+		i2c_unregister_device(client);
+		if (adapter)
+			i2c_put_adapter(adapter);
+	}
+}
+
+#ifdef CONFIG_OF
+/* Parse port node and register as a sub-device any sensor specified there. */
+static int fimc_md_parse_port_node(struct fimc_md *fmd,
+				   struct device_node *port,
+				   unsigned int index)
+{
+	struct device_node *rem, *ep, *np;
+	struct fimc_source_info *pd;
+	struct v4l2_of_endpoint endpoint;
+	u32 val;
+
+	pd = &fmd->sensor[index].pdata;
+
+	/* Assume here a port node can have only one endpoint node. */
+	ep = of_get_next_child(port, NULL);
+	if (!ep)
+		return 0;
+
+	v4l2_of_parse_endpoint(ep, &endpoint);
+	if (WARN_ON(endpoint.port == 0) || index >= FIMC_MAX_SENSORS)
+		return -EINVAL;
+
+	pd->mux_id = (endpoint.port - 1) & 0x1;
+
+	rem = v4l2_of_get_remote_port_parent(ep);
+	of_node_put(ep);
+	if (rem == NULL) {
+		v4l2_info(&fmd->v4l2_dev, "Remote device at %s not found\n",
+							ep->full_name);
+		return 0;
+	}
+	if (!of_property_read_u32(rem, "samsung,camclk-out", &val))
+		pd->clk_id = val;
+
+	if (!of_property_read_u32(rem, "clock-frequency", &val))
+		pd->clk_frequency = val;
+
+	if (pd->clk_frequency == 0) {
+		v4l2_err(&fmd->v4l2_dev, "Wrong clock frequency at node %s\n",
+			 rem->full_name);
+		of_node_put(rem);
+		return -EINVAL;
+	}
+
+	if (fimc_input_is_parallel(endpoint.port)) {
+		if (endpoint.bus_type == V4L2_MBUS_PARALLEL)
+			pd->sensor_bus_type = FIMC_BUS_TYPE_ITU_601;
+		else
+			pd->sensor_bus_type = FIMC_BUS_TYPE_ITU_656;
+		pd->flags = endpoint.bus.parallel.flags;
+	} else if (fimc_input_is_mipi_csi(endpoint.port)) {
+		/*
+		 * MIPI CSI-2: only input mux selection and
+		 * the sensor's clock frequency is needed.
+		 */
+		pd->sensor_bus_type = FIMC_BUS_TYPE_MIPI_CSI2;
+	} else {
+		v4l2_err(&fmd->v4l2_dev, "Wrong port id (%u) at node %s\n",
+			 endpoint.port, rem->full_name);
+	}
+
+	np = of_get_parent(rem);
+
+	if (np && !of_node_cmp(np->name, "i2c-isp"))
+		pd->fimc_bus_type = FIMC_BUS_TYPE_ISP_WRITEBACK;
+	else
+		pd->fimc_bus_type = pd->sensor_bus_type;
+
+	if (WARN_ON(index >= ARRAY_SIZE(fmd->sensor)))
+		return -EINVAL;
+
+	fmd->sensor[index].asd.match_type = V4L2_ASYNC_MATCH_OF;
+	fmd->sensor[index].asd.match.of.node = rem;
+	fmd->async_subdevs[index] = &fmd->sensor[index].asd;
+
+	fmd->num_sensors++;
+
+	of_node_put(rem);
+	return 0;
+}
+
+/* Register all SoC external sub-devices */
+static int fimc_md_of_sensors_register(struct fimc_md *fmd,
+				       struct device_node *np)
+{
+	struct device_node *parent = fmd->pdev->dev.of_node;
+	struct device_node *node, *ports;
+	int index = 0;
+	int ret;
+
+	/* Attach sensors linked to MIPI CSI-2 receivers */
+	for_each_available_child_of_node(parent, node) {
+		struct device_node *port;
+
+		if (of_node_cmp(node->name, "csis"))
+			continue;
+		/* The csis node can have only port subnode. */
+		port = of_get_next_child(node, NULL);
+		if (!port)
+			continue;
+
+		ret = fimc_md_parse_port_node(fmd, port, index);
+		if (ret < 0)
+			return ret;
+		index++;
+	}
+
+	/* Attach sensors listed in the parallel-ports node */
+	ports = of_get_child_by_name(parent, "parallel-ports");
+	if (!ports)
+		return 0;
+
+	for_each_child_of_node(ports, node) {
+		ret = fimc_md_parse_port_node(fmd, node, index);
+		if (ret < 0)
+			break;
+		index++;
+	}
+
+	return 0;
+}
+
+static int __of_get_csis_id(struct device_node *np)
+{
+	u32 reg = 0;
+
+	np = of_get_child_by_name(np, "port");
+	if (!np)
+		return -EINVAL;
+	of_property_read_u32(np, "reg", &reg);
+	return reg - FIMC_INPUT_MIPI_CSI2_0;
+}
+#else
+#define fimc_md_of_sensors_register(fmd, np) (-ENOSYS)
+#define __of_get_csis_id(np) (-ENOSYS)
+#endif
+
+static int fimc_md_register_sensor_entities(struct fimc_md *fmd)
+{
+	struct device_node *of_node = fmd->pdev->dev.of_node;
+	int ret;
+
+	/*
+	 * Runtime resume one of the FIMC entities to make sure
+	 * the sclk_cam clocks are not globally disabled.
+	 */
+	if (!fmd->pmf)
+		return -ENXIO;
+
+	ret = pm_runtime_get_sync(fmd->pmf);
+	if (ret < 0)
+		return ret;
+
+	fmd->num_sensors = 0;
+	ret = fimc_md_of_sensors_register(fmd, of_node);
+
+	pm_runtime_put(fmd->pmf);
+	return ret;
+}
+
+/*
+ * MIPI-CSIS, FIMC-IS and FIMC-LITE platform devices registration.
+ */
+
+static int register_fimc_lite_entity(struct fimc_md *fmd,
+				     struct fimc_lite *fimc_lite)
+{
+	struct v4l2_subdev *sd;
+	struct exynos_media_pipeline *ep;
+	int ret;
+
+	if (WARN_ON(fimc_lite->index >= FIMC_LITE_MAX_DEVS ||
+		    fmd->fimc_lite[fimc_lite->index]))
+		return -EBUSY;
+
+	sd = &fimc_lite->subdev;
+	sd->grp_id = GRP_ID_FLITE;
+
+	ep = fimc_md_pipeline_create(fmd);
+	if (!ep)
+		return -ENOMEM;
+
+	v4l2_set_subdev_hostdata(sd, ep);
+
+	ret = v4l2_device_register_subdev(&fmd->v4l2_dev, sd);
+	if (!ret) {
+		fmd->fimc_lite[fimc_lite->index] = fimc_lite;
+		if (!fmd->pmf && fimc_lite->pdev)
+			fmd->pmf = &fimc_lite->pdev->dev;
+	} else {
+		v4l2_err(&fmd->v4l2_dev, "Failed to register FIMC.LITE%d\n",
+			 fimc_lite->index);
+	}
+	return ret;
+}
+
+static int register_csis_entity(struct fimc_md *fmd,
+				struct platform_device *pdev,
+				struct v4l2_subdev *sd)
+{
+	struct device_node *node = pdev->dev.of_node;
+	int id, ret;
+
+	id = node ? __of_get_csis_id(node) : max(0, pdev->id);
+
+	if (WARN_ON(id < 0 || id >= CSIS_MAX_ENTITIES))
+		return -ENOENT;
+
+	if (WARN_ON(fmd->csis[id].sd))
+		return -EBUSY;
+
+	sd->grp_id = GRP_ID_CSIS;
+	ret = v4l2_device_register_subdev(&fmd->v4l2_dev, sd);
+	if (!ret)
+		fmd->csis[id].sd = sd;
+	else
+		v4l2_err(&fmd->v4l2_dev,
+			 "Failed to register MIPI-CSIS.%d (%d)\n", id, ret);
+	return ret;
+}
+
+static int register_fimc_is_entity(struct fimc_md *fmd,
+				     struct fimc_is *is)
+{
+	struct v4l2_subdev *isp, *scc, *scp;
+	struct exynos_media_pipeline *ep;
+	struct fimc_pipeline_isp *p;
+	struct video_device *vdev;
+	int ret, i;
+
+	for (i = 0; i < is->num_instance; i++) {
+		isp = fimc_is_isp_get_sd(is, i);
+		scc = fimc_is_scc_get_sd(is, i);
+		scp = fimc_is_scp_get_sd(is, i);
+		isp->grp_id = GRP_ID_FIMC_IS;
+		scc->grp_id = GRP_ID_FIMC_IS;
+		scp->grp_id = GRP_ID_FIMC_IS;
+
+		ep = fimc_md_isp_pipeline_create(fmd);
+		if (!ep)
+			return -ENOMEM;
+
+		v4l2_set_subdev_hostdata(isp, ep);
+		v4l2_set_subdev_hostdata(scc, ep);
+		v4l2_set_subdev_hostdata(scp, ep);
+
+		ret = v4l2_device_register_subdev(&fmd->v4l2_dev, isp);
+		if (ret)
+			v4l2_err(&fmd->v4l2_dev,
+					"Failed to register ISP subdev\n");
+
+		ret = v4l2_device_register_subdev(&fmd->v4l2_dev, scc);
+		if (ret)
+			v4l2_err(&fmd->v4l2_dev,
+					"Failed to register SCC subdev\n");
+
+		ret = v4l2_device_register_subdev(&fmd->v4l2_dev, scp);
+		if (ret)
+			v4l2_err(&fmd->v4l2_dev,
+					"Failed to register SCP subdev\n");
+
+		p = to_fimc_isp_pipeline(ep);
+		p->subdevs[IDX_ISP] = isp;
+		p->subdevs[IDX_SCC] = scc;
+		p->subdevs[IDX_SCP] = scp;
+
+		/* Create default links */
+		/* vdev -> ISP */
+		vdev = fimc_is_isp_get_vfd(is, i);
+		ret = media_entity_create_link(&isp->entity,
+					ISP_SD_PAD_SINK_DMA,
+					&vdev->entity, 0,
+					MEDIA_LNK_FL_IMMUTABLE |
+					MEDIA_LNK_FL_ENABLED);
+		if (ret)
+			return ret;
+
+		/* ISP -> SCC */
+		ret = media_entity_create_link(&isp->entity,
+					ISP_SD_PAD_SRC,
+					&scc->entity, SCALER_SD_PAD_SINK,
+					MEDIA_LNK_FL_IMMUTABLE |
+					MEDIA_LNK_FL_ENABLED);
+		if (ret)
+			return ret;
+
+		/* SCC -> SCP */
+		ret = media_entity_create_link(&scc->entity,
+					SCALER_SD_PAD_SRC_FIFO,
+					&scp->entity, SCALER_SD_PAD_SINK,
+					MEDIA_LNK_FL_IMMUTABLE |
+					MEDIA_LNK_FL_ENABLED);
+		if (ret)
+			return ret;
+
+		/* SCC -> vdev */
+		vdev = fimc_is_scc_get_vfd(is, i);
+		ret = media_entity_create_link(&scc->entity,
+					SCALER_SD_PAD_SRC_DMA,
+					&vdev->entity, 0,
+					MEDIA_LNK_FL_IMMUTABLE |
+					MEDIA_LNK_FL_ENABLED);
+		if (ret)
+			return ret;
+
+		/* SCP -> vdev */
+		vdev = fimc_is_scp_get_vfd(is, i);
+		ret = media_entity_create_link(&scp->entity,
+					SCALER_SD_PAD_SRC_DMA,
+					&vdev->entity, 0,
+					MEDIA_LNK_FL_IMMUTABLE |
+					MEDIA_LNK_FL_ENABLED);
+		if (ret)
+			return ret;
+	}
+	fmd->is = is;
+
+	return ret;
+}
+
+static int fimc_md_register_platform_entity(struct fimc_md *fmd,
+					    struct platform_device *pdev,
+					    int plat_entity)
+{
+	struct device *dev = &pdev->dev;
+	int ret = -EPROBE_DEFER;
+	void *drvdata;
+
+	/* Lock to ensure dev->driver won't change. */
+	device_lock(dev);
+
+	if (!dev->driver || !try_module_get(dev->driver->owner))
+		goto dev_unlock;
+
+	drvdata = dev_get_drvdata(dev);
+	/* Some subdev didn't probe succesfully id drvdata is NULL */
+	if (drvdata) {
+		switch (plat_entity) {
+		case IDX_FLITE:
+			ret = register_fimc_lite_entity(fmd, drvdata);
+			break;
+		case IDX_CSIS:
+			ret = register_csis_entity(fmd, pdev, drvdata);
+			break;
+		case IDX_FIMC_IS:
+			ret = register_fimc_is_entity(fmd, drvdata);
+			break;
+		default:
+			ret = -ENODEV;
+		}
+	}
+
+	module_put(dev->driver->owner);
+dev_unlock:
+	device_unlock(dev);
+	if (ret == -EPROBE_DEFER)
+		dev_info(&fmd->pdev->dev, "deferring %s device registration\n",
+			dev_name(dev));
+	else if (ret < 0)
+		dev_err(&fmd->pdev->dev, "%s device registration failed (%d)\n",
+			dev_name(dev), ret);
+	return ret;
+}
+
+/* Register FIMC, FIMC-LITE and CSIS media entities */
+static int fimc_md_register_of_platform_entities(struct fimc_md *fmd,
+						 struct device_node *parent)
+{
+	struct device_node *node;
+	int ret = 0;
+
+	for_each_available_child_of_node(parent, node) {
+		struct platform_device *pdev;
+		int plat_entity = -1;
+
+		pdev = of_find_device_by_node(node);
+		if (!pdev)
+			continue;
+
+		/* If driver of any entity isn't ready try all again later. */
+		if (!strcmp(node->name, CSIS_OF_NODE_NAME))
+			plat_entity = IDX_CSIS;
+		else if (!strcmp(node->name, FIMC_LITE_OF_NODE_NAME))
+			plat_entity = IDX_FLITE;
+		else if (!strcmp(node->name, FIMC_IS_OF_NODE_NAME))
+			plat_entity = IDX_FIMC_IS;
+
+		if (plat_entity >= 0)
+			ret = fimc_md_register_platform_entity(fmd, pdev,
+							plat_entity);
+		put_device(&pdev->dev);
+		if (ret < 0)
+			break;
+	}
+
+	return ret;
+}
+
+static void fimc_md_unregister_entities(struct fimc_md *fmd)
+{
+	int i;
+	struct fimc_is *is;
+
+	for (i = 0; i < FIMC_LITE_MAX_DEVS; i++) {
+		if (fmd->fimc_lite[i] == NULL)
+			continue;
+		v4l2_device_unregister_subdev(&fmd->fimc_lite[i]->subdev);
+		fmd->fimc_lite[i] = NULL;
+	}
+	for (i = 0; i < CSIS_MAX_ENTITIES; i++) {
+		if (fmd->csis[i].sd == NULL)
+			continue;
+		v4l2_device_unregister_subdev(fmd->csis[i].sd);
+		module_put(fmd->csis[i].sd->owner);
+		fmd->csis[i].sd = NULL;
+	}
+	for (i = 0; i < fmd->num_sensors; i++) {
+		if (fmd->sensor[i].subdev == NULL)
+			continue;
+		fimc_md_unregister_sensor(fmd->sensor[i].subdev);
+		fmd->sensor[i].subdev = NULL;
+	}
+
+	if (!fmd->is)
+		return;
+	/* Unregistering FIMC-IS entities */
+	is = fmd->is;
+	for (i = 0; i < is->num_instance; i++) {
+		struct v4l2_subdev *isp, *scc, *scp;
+
+		isp = fimc_is_isp_get_sd(is, i);
+		scc = fimc_is_scc_get_sd(is, i);
+		scp = fimc_is_scp_get_sd(is, i);
+		v4l2_device_unregister_subdev(isp);
+		v4l2_device_unregister_subdev(scc);
+		v4l2_device_unregister_subdev(scp);
+	}
+
+	v4l2_info(&fmd->v4l2_dev, "Unregistered all entities\n");
+}
+
+/**
+ * __fimc_md_create_fimc_links - create links to all FIMC entities
+ * @fmd: fimc media device
+ * @source: the source entity to create links to all fimc entities from
+ * @sensor: sensor subdev linked to FIMC[fimc_id] entity, may be null
+ * @pad: the source entity pad index
+ * @link_mask: bitmask of the fimc devices for which link should be enabled
+ */
+static int __fimc_md_create_fimc_sink_links(struct fimc_md *fmd,
+					    struct media_entity *source,
+					    struct v4l2_subdev *sensor,
+					    int pad, int link_mask)
+{
+	struct fimc_source_info *si = NULL;
+	struct media_entity *sink;
+	unsigned int flags = 0;
+	int i, ret = 0;
+
+	if (sensor) {
+		si = v4l2_get_subdev_hostdata(sensor);
+		/* Skip direct FIMC links in the logical FIMC-IS sensor path */
+		if (si && si->fimc_bus_type == FIMC_BUS_TYPE_ISP_WRITEBACK)
+			ret = 1;
+	}
+
+	for (i = 0; i < FIMC_LITE_MAX_DEVS; i++) {
+		if (!fmd->fimc_lite[i])
+			continue;
+
+		flags = ((1 << i) & link_mask) ? MEDIA_LNK_FL_ENABLED : 0;
+
+		sink = &fmd->fimc_lite[i]->subdev.entity;
+		ret = media_entity_create_link(source, pad, sink,
+					       FLITE_SD_PAD_SINK, flags);
+		if (ret)
+			return ret;
+
+		/* Notify FIMC-LITE subdev entity */
+		ret = media_entity_call(sink, link_setup, &sink->pads[0],
+					&source->pads[pad], flags);
+		if (ret)
+			break;
+
+		v4l2_info(&fmd->v4l2_dev, "created link [%s] -> [%s]\n",
+			  source->name, sink->name);
+	}
+	return 0;
+}
+
+/* Create links from FIMC-LITE source pads to other entities */
+static int __fimc_md_create_flite_source_links(struct fimc_md *fmd)
+{
+	struct media_entity *source, *sink;
+	int i, ret = 0;
+
+	for (i = 0; i < FIMC_LITE_MAX_DEVS; i++) {
+		struct fimc_lite *fimc = fmd->fimc_lite[i];
+
+		if (fimc == NULL)
+			continue;
+
+		source = &fimc->subdev.entity;
+		sink = &fimc->ve.vdev.entity;
+		/* FIMC-LITE's subdev and video node */
+		ret = media_entity_create_link(source, FLITE_SD_PAD_SOURCE_DMA,
+					       sink, 0,
+					       MEDIA_LNK_FL_IMMUTABLE |
+					       MEDIA_LNK_FL_ENABLED);
+		if (ret)
+			break;
+	}
+
+	return ret;
+}
+
+/**
+ * fimc_md_create_links - create default links between registered entities
+ *
+ * Parallel interface sensor entities are connected directly to FIMC capture
+ * entities. The sensors using MIPI CSIS bus are connected through immutable
+ * link with CSI receiver entity specified by mux_id. Any registered CSIS
+ * entity has a link to each registered FIMC capture entity. Enabled links
+ * are created by default between each subsequent registered sensor and
+ * subsequent FIMC capture entity. The number of default active links is
+ * determined by the number of available sensors or FIMC entities,
+ * whichever is less.
+ */
+static int fimc_md_create_links(struct fimc_md *fmd)
+{
+	struct v4l2_subdev *csi_sensors[CSIS_MAX_ENTITIES] = { NULL };
+	struct v4l2_subdev *sensor, *csis;
+	struct fimc_source_info *pdata;
+	struct media_entity *source;
+	int i, pad, fimc_id = 0, ret = 0;
+	u32 flags, link_mask = 0;
+
+	for (i = 0; i < fmd->num_sensors; i++) {
+		if (fmd->sensor[i].subdev == NULL)
+			continue;
+
+		sensor = fmd->sensor[i].subdev;
+		pdata = v4l2_get_subdev_hostdata(sensor);
+		if (!pdata)
+			continue;
+
+		source = NULL;
+
+		switch (pdata->sensor_bus_type) {
+		case FIMC_BUS_TYPE_MIPI_CSI2:
+			if (WARN(pdata->mux_id >= CSIS_MAX_ENTITIES,
+				"Wrong CSI channel id: %d\n", pdata->mux_id))
+				return -EINVAL;
+
+			csis = fmd->csis[pdata->mux_id].sd;
+			if (WARN(csis == NULL,
+				 "MIPI-CSI interface specified "
+				 "but s5p-csis module is not loaded!\n"))
+				return -EINVAL;
+
+			pad = sensor->entity.num_pads - 1;
+			ret = media_entity_create_link(&sensor->entity, pad,
+					      &csis->entity, CSIS_PAD_SINK,
+					      MEDIA_LNK_FL_IMMUTABLE |
+					      MEDIA_LNK_FL_ENABLED);
+			if (ret)
+				return ret;
+
+			v4l2_info(&fmd->v4l2_dev, "created link [%s] => [%s]\n",
+				  sensor->entity.name, csis->entity.name);
+
+			source = NULL;
+			csi_sensors[pdata->mux_id] = sensor;
+			break;
+
+		case FIMC_BUS_TYPE_ITU_601...FIMC_BUS_TYPE_ITU_656:
+			source = &sensor->entity;
+			pad = 0;
+			break;
+
+		default:
+			v4l2_err(&fmd->v4l2_dev, "Wrong bus_type: %x\n",
+				 pdata->sensor_bus_type);
+			return -EINVAL;
+		}
+		if (source == NULL)
+			continue;
+
+		link_mask = 1 << fimc_id++;
+		ret = __fimc_md_create_fimc_sink_links(fmd, source, sensor,
+						       pad, link_mask);
+	}
+
+	for (i = 0; i < CSIS_MAX_ENTITIES; i++) {
+		if (fmd->csis[i].sd == NULL)
+			continue;
+
+		source = &fmd->csis[i].sd->entity;
+		pad = CSIS_PAD_SOURCE;
+		sensor = csi_sensors[i];
+
+		link_mask = 1 << fimc_id++;
+		ret = __fimc_md_create_fimc_sink_links(fmd, source, sensor,
+						       pad, link_mask);
+	}
+
+	/* Create immutable links between each FIMC's subdev and video node */
+	flags = MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED;
+
+	ret = __fimc_md_create_flite_source_links(fmd);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+/*
+ * The peripheral sensor clock management.
+ */
+static void fimc_md_put_clocks(struct fimc_md *fmd)
+{
+	int i = FIMC_MAX_CAMCLKS;
+
+	while (--i >= 0) {
+		if (IS_ERR(fmd->camclk[i].clock))
+			continue;
+		clk_put(fmd->camclk[i].clock);
+		fmd->camclk[i].clock = ERR_PTR(-EINVAL);
+	}
+}
+
+static int fimc_md_get_clocks(struct fimc_md *fmd)
+{
+	struct device *dev = NULL;
+	char clk_name[32];
+	struct clk *clock;
+	int i, ret = 0;
+
+	for (i = 0; i < FIMC_MAX_CAMCLKS; i++)
+		fmd->camclk[i].clock = ERR_PTR(-EINVAL);
+
+	if (fmd->pdev->dev.of_node)
+		dev = &fmd->pdev->dev;
+
+	for (i = 0; i < SCLK_BAYER; i++) {
+		snprintf(clk_name, sizeof(clk_name), "sclk_cam%u", i);
+		clock = clk_get(dev, clk_name);
+
+		if (IS_ERR(clock)) {
+			dev_err(&fmd->pdev->dev, "Failed to get clock: %s\n",
+								clk_name);
+			ret = PTR_ERR(clock);
+			break;
+		}
+		fmd->camclk[i].clock = clock;
+	}
+	if (ret)
+		fimc_md_put_clocks(fmd);
+
+	/* Prepare bayer clk */
+	clock = clk_get(dev, "sclk_bayer");
+
+	if (IS_ERR(clock)) {
+		dev_err(&fmd->pdev->dev, "Failed to get clock: %s\n",
+							clk_name);
+		ret = PTR_ERR(clock);
+		goto err_exit;
+	}
+	ret = clk_prepare(clock);
+	if (ret < 0) {
+		clk_put(clock);
+		fmd->camclk[SCLK_BAYER].clock = ERR_PTR(-EINVAL);
+		goto err_exit;
+	}
+	fmd->camclk[SCLK_BAYER].clock = clock;
+
+	return 0;
+err_exit:
+	fimc_md_put_clocks(fmd);
+	return ret;
+}
+
+static int __fimc_md_set_camclk(struct fimc_md *fmd,
+				struct fimc_source_info *si,
+				bool on)
+{
+	struct fimc_camclk_info *camclk;
+	int ret = 0;
+
+	if (WARN_ON(si->clk_id >= FIMC_MAX_CAMCLKS) || fmd == NULL)
+		return -EINVAL;
+
+	camclk = &fmd->camclk[si->clk_id];
+
+	dbg("camclk %d, f: %lu, use_count: %d, on: %d",
+	    si->clk_id, si->clk_frequency, camclk->use_count, on);
+
+	if (on) {
+		if (camclk->use_count > 0 &&
+		    camclk->frequency != si->clk_frequency)
+			return -EINVAL;
+
+		if (camclk->use_count++ == 0) {
+			clk_set_rate(camclk->clock, si->clk_frequency);
+			camclk->frequency = si->clk_frequency;
+			ret = pm_runtime_get_sync(fmd->pmf);
+			if (ret < 0)
+				return ret;
+			ret = clk_prepare_enable(camclk->clock);
+			dbg("Enabled camclk %d: f: %lu", si->clk_id,
+			    clk_get_rate(camclk->clock));
+		}
+		ret = clk_prepare_enable(fmd->camclk[SCLK_BAYER].clock);
+		return ret;
+	}
+
+	if (WARN_ON(camclk->use_count == 0))
+		return 0;
+
+	if (--camclk->use_count == 0) {
+		clk_disable_unprepare(camclk->clock);
+		pm_runtime_put(fmd->pmf);
+		dbg("Disabled camclk %d", si->clk_id);
+	}
+	clk_disable_unprepare(fmd->camclk[SCLK_BAYER].clock);
+	return ret;
+}
+
+static int __fimc_md_modify_pipeline(struct media_entity *entity, bool enable)
+{
+	struct exynos_video_entity *ve;
+	struct fimc_pipeline *p;
+	struct video_device *vdev;
+	int ret;
+
+	vdev = media_entity_to_video_device(entity);
+	if (vdev->entity.use_count == 0)
+		return 0;
+
+	ve = vdev_to_exynos_video_entity(vdev);
+	p = to_fimc_pipeline(ve->pipe);
+	/*
+	 * Nothing to do if we are disabling the pipeline, some link
+	 * has been disconnected and p->subdevs array is cleared now.
+	 */
+	if (!enable && p->subdevs[IDX_SENSOR] == NULL)
+		return 0;
+
+	if (enable)
+		ret = __fimc_pipeline_open(ve->pipe, entity, true);
+	else
+		ret = __fimc_pipeline_close(ve->pipe);
+
+	if (ret == 0 && !enable)
+		memset(p->subdevs, 0, sizeof(p->subdevs));
+
+	return ret;
+}
+
+/* Locking: called with entity->parent->graph_mutex mutex held. */
+static int __fimc_md_modify_pipelines(struct media_entity *entity, bool enable)
+{
+	struct media_entity *entity_err = entity;
+	struct media_entity_graph graph;
+	int ret;
+
+	/*
+	 * Walk current graph and call the pipeline open/close routine for each
+	 * opened video node that belongs to the graph of entities connected
+	 * through active links. This is needed as we cannot power on/off the
+	 * subdevs in random order.
+	 */
+	media_entity_graph_walk_start(&graph, entity);
+
+	while ((entity = media_entity_graph_walk_next(&graph))) {
+		if (media_entity_type(entity) != MEDIA_ENT_T_DEVNODE)
+			continue;
+
+		ret  = __fimc_md_modify_pipeline(entity, enable);
+
+		if (ret < 0)
+			goto err;
+	}
+
+	return 0;
+ err:
+	media_entity_graph_walk_start(&graph, entity_err);
+
+	while ((entity_err = media_entity_graph_walk_next(&graph))) {
+		if (media_entity_type(entity_err) != MEDIA_ENT_T_DEVNODE)
+			continue;
+
+		__fimc_md_modify_pipeline(entity_err, !enable);
+
+		if (entity_err == entity)
+			break;
+	}
+
+	return ret;
+}
+
+static int fimc_md_link_notify(struct media_link *link, unsigned int flags,
+				unsigned int notification)
+{
+	struct media_entity *sink = link->sink->entity;
+	int ret = 0;
+
+	/* Before link disconnection */
+	if (notification == MEDIA_DEV_NOTIFY_PRE_LINK_CH) {
+		if (!(flags & MEDIA_LNK_FL_ENABLED))
+			ret = __fimc_md_modify_pipelines(sink, false);
+		else
+			; /* TODO: Link state change validation */
+	/* After link activation */
+	} else if (notification == MEDIA_DEV_NOTIFY_POST_LINK_CH &&
+		   (link->flags & MEDIA_LNK_FL_ENABLED)) {
+		ret = __fimc_md_modify_pipelines(sink, true);
+	}
+
+	return ret ? -EPIPE : 0;
+}
+
+#ifdef CONFIG_OF
+struct cam_clk {
+	struct clk_hw hw;
+	struct fimc_md *fmd;
+};
+#define to_cam_clk(_hw) container_of(_hw, struct cam_clk, hw)
+
+static int cam_clk_prepare(struct clk_hw *hw)
+{
+	struct cam_clk *camclk = to_cam_clk(hw);
+	int ret = pm_runtime_get_sync(camclk->fmd->pmf);
+
+	return ret < 0 ? ret : 0;
+}
+
+static void cam_clk_unprepare(struct clk_hw *hw)
+{
+	struct cam_clk *camclk = to_cam_clk(hw);
+	pm_runtime_put_sync(camclk->fmd->pmf);
+}
+
+static const struct clk_ops cam_clk_ops = {
+	.prepare = cam_clk_prepare,
+	.unprepare = cam_clk_unprepare,
+};
+
+static const char *cam_clk_p_names[] = { "sclk_cam0", "sclk_cam1" };
+
+static int fimc_md_register_clk_provider(struct fimc_md *fmd)
+{
+	struct cam_clk_provider *clk_provider = &fmd->clk_provider;
+	struct device *dev = &fmd->pdev->dev;
+	struct device_node *node;
+	unsigned int nclocks;
+
+	node = of_get_child_by_name(dev->of_node, "clock-controller");
+	if (!node) {
+		dev_warn(dev, "clock-controller node at %s not found\n",
+					dev->of_node->full_name);
+		return 0;
+	}
+	/* Instantiate the clocks */
+	for (nclocks = 0; nclocks < SCLK_BAYER; nclocks++) {
+		struct clk_init_data init;
+		char clk_name[16];
+		struct clk *clk;
+		struct cam_clk *camclk;
+
+		camclk = devm_kzalloc(dev, sizeof(*camclk), GFP_KERNEL);
+		if (!camclk)
+			return -ENOMEM;
+
+		snprintf(clk_name, sizeof(clk_name), "cam_clkout%d", nclocks);
+
+		init.name = clk_name;
+		init.ops = &cam_clk_ops;
+		init.flags = CLK_SET_RATE_PARENT;
+		init.parent_names = &cam_clk_p_names[nclocks];
+		init.num_parents = 1;
+		camclk->hw.init = &init;
+		camclk->fmd = fmd;
+
+		clk = devm_clk_register(dev, &camclk->hw);
+		if (IS_ERR(clk)) {
+			kfree(camclk);
+			return PTR_ERR(clk);
+		}
+		clk_provider->clks[nclocks] = clk;
+	}
+
+	clk_provider->clk_data.clks = clk_provider->clks;
+	clk_provider->clk_data.clk_num = nclocks;
+
+	return of_clk_add_provider(node, of_clk_src_onecell_get,
+					&clk_provider->clk_data);
+}
+#else
+#define fimc_md_register_clk_provider(fmd) (0)
+#endif
+
+static int subdev_notifier_bound(struct v4l2_async_notifier *notifier,
+				 struct v4l2_subdev *subdev,
+				 struct v4l2_async_subdev *asd)
+{
+	struct fimc_md *fmd = notifier_to_fimc_md(notifier);
+	struct fimc_sensor_info *si = NULL;
+	int i;
+
+	/* Find platform data for this sensor subdev */
+	for (i = 0; i < ARRAY_SIZE(fmd->sensor); i++) {
+		if (fmd->sensor[i].asd.match.of.node == subdev->dev->of_node)
+			si = &fmd->sensor[i];
+	}
+
+	if (si == NULL)
+		return -EINVAL;
+
+	v4l2_set_subdev_hostdata(subdev, &si->pdata);
+
+	if (si->pdata.fimc_bus_type == FIMC_BUS_TYPE_ISP_WRITEBACK)
+		subdev->grp_id = GRP_ID_FIMC_IS_SENSOR;
+	else
+		subdev->grp_id = GRP_ID_SENSOR;
+
+	si->subdev = subdev;
+
+	v4l2_info(&fmd->v4l2_dev, "Registered sensor subdevice: %s (%d)\n",
+		  subdev->name, fmd->num_sensors);
+
+	fmd->num_sensors++;
+
+	return 0;
+}
+
+static int subdev_notifier_complete(struct v4l2_async_notifier *notifier)
+{
+	struct fimc_md *fmd = notifier_to_fimc_md(notifier);
+	int ret;
+
+	mutex_lock(&fmd->media_dev.graph_mutex);
+
+	ret = fimc_md_create_links(fmd);
+	if (ret < 0)
+		goto unlock;
+
+	ret = v4l2_device_register_subdev_nodes(&fmd->v4l2_dev);
+unlock:
+	mutex_unlock(&fmd->media_dev.graph_mutex);
+	return ret;
+}
+
+static int fimc_md_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct v4l2_device *v4l2_dev;
+	struct fimc_md *fmd;
+	int ret;
+
+	fmd = devm_kzalloc(dev, sizeof(*fmd), GFP_KERNEL);
+	if (!fmd)
+		return -ENOMEM;
+
+	spin_lock_init(&fmd->slock);
+	fmd->pdev = pdev;
+	INIT_LIST_HEAD(&fmd->pipelines);
+	INIT_LIST_HEAD(&fmd->isp_pipelines);
+
+	strlcpy(fmd->media_dev.model, "SAMSUNG EXYNOS5 IS",
+		sizeof(fmd->media_dev.model));
+	fmd->media_dev.link_notify = fimc_md_link_notify;
+	fmd->media_dev.dev = dev;
+
+	v4l2_dev = &fmd->v4l2_dev;
+	v4l2_dev->mdev = &fmd->media_dev;
+	strlcpy(v4l2_dev->name, "exynos5-fimc-md", sizeof(v4l2_dev->name));
+
+	ret = fimc_md_register_clk_provider(fmd);
+	if (ret < 0) {
+		v4l2_err(v4l2_dev, "clock provider registration failed\n");
+		return ret;
+	}
+
+	ret = v4l2_device_register(dev, &fmd->v4l2_dev);
+	if (ret < 0) {
+		v4l2_err(v4l2_dev, "Failed to register v4l2_device: %d\n", ret);
+		return ret;
+	}
+
+	ret = media_device_register(&fmd->media_dev);
+	if (ret < 0) {
+		v4l2_err(v4l2_dev, "Failed to register media dev: %d\n", ret);
+		goto err_md;
+	}
+
+	ret = fimc_md_get_clocks(fmd);
+	if (ret)
+		goto err_clk;
+
+	fmd->user_subdev_api = (dev->of_node != NULL);
+
+	platform_set_drvdata(pdev, fmd);
+
+	/* Protect the media graph while we're registering entities */
+	mutex_lock(&fmd->media_dev.graph_mutex);
+
+	ret = fimc_md_register_of_platform_entities(fmd, dev->of_node);
+	if (ret)
+		goto err_unlock;
+
+	ret = fimc_md_register_sensor_entities(fmd);
+	if (ret)
+		goto err_unlock;
+
+	mutex_unlock(&fmd->media_dev.graph_mutex);
+
+	fmd->subdev_notifier.subdevs = fmd->async_subdevs;
+	fmd->subdev_notifier.num_subdevs = fmd->num_sensors;
+	fmd->subdev_notifier.bound = subdev_notifier_bound;
+	fmd->subdev_notifier.complete = subdev_notifier_complete;
+	fmd->num_sensors = 0;
+
+	ret = v4l2_async_notifier_register(&fmd->v4l2_dev,
+					   &fmd->subdev_notifier);
+	if (ret)
+		goto err_clk;
+
+	return 0;
+
+err_unlock:
+	mutex_unlock(&fmd->media_dev.graph_mutex);
+err_clk:
+	fimc_md_put_clocks(fmd);
+	fimc_md_unregister_entities(fmd);
+	media_device_unregister(&fmd->media_dev);
+err_md:
+	v4l2_device_unregister(&fmd->v4l2_dev);
+	fimc_md_unregister_clk_provider(fmd);
+	return ret;
+}
+
+static int fimc_md_remove(struct platform_device *pdev)
+{
+	struct fimc_md *fmd = platform_get_drvdata(pdev);
+
+	v4l2_async_notifier_unregister(&fmd->subdev_notifier);
+
+	fimc_md_unregister_entities(fmd);
+	fimc_md_pipelines_free(fmd);
+	media_device_unregister(&fmd->media_dev);
+	fimc_md_put_clocks(fmd);
+
+	return 0;
+}
+
+static struct platform_device_id fimc_driver_ids[] __always_unused = {
+	{ .name = "exynos5-fimc-md" },
+	{ },
+};
+MODULE_DEVICE_TABLE(platform, fimc_driver_ids);
+
+static const struct of_device_id fimc_md_of_match[] = {
+	{ .compatible = "samsung,exynos5-fimc" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, fimc_md_of_match);
+
+static struct platform_driver fimc_md_driver = {
+	.probe		= fimc_md_probe,
+	.remove		= fimc_md_remove,
+	.driver = {
+		.of_match_table = fimc_md_of_match,
+		.name		= "exynos5-fimc-md",
+		.owner		= THIS_MODULE,
+	}
+};
+
+static int __init fimc_md_init(void)
+{
+	request_module("s5p-csis");
+	return platform_driver_register(&fimc_md_driver);
+}
+
+static void __exit fimc_md_exit(void)
+{
+	platform_driver_unregister(&fimc_md_driver);
+}
+
+module_init(fimc_md_init);
+module_exit(fimc_md_exit);
+
+MODULE_AUTHOR("Shaik Ameer Basha <shaik.ameer@samsung.com>");
+MODULE_DESCRIPTION("EXYNOS5 FIMC media device driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/platform/exynos5-is/exynos5-mdev.h b/drivers/media/platform/exynos5-is/exynos5-mdev.h
new file mode 100644
index 0000000..7fada6c
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/exynos5-mdev.h
@@ -0,0 +1,199 @@
+/*
+ * Copyright (C) 2011 - 2012 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef EXYNOS5_MDEVICE_H_
+#define EXYNOS5_MDEVICE_H_
+
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/mutex.h>
+#include <media/media-device.h>
+#include <media/media-entity.h>
+#include <media/s5p_fimc.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-subdev.h>
+
+#include "fimc-lite.h"
+#include "mipi-csis.h"
+
+#define FIMC_OF_NODE_NAME	"fimc"
+#define FIMC_LITE_OF_NODE_NAME	"fimc-lite"
+#define CSIS_OF_NODE_NAME	"csis"
+#define FIMC_IS_OF_NODE_NAME	"fimc-is"
+
+#define FIMC_MAX_SENSORS	8
+
+enum fimc_subdev_index {
+	IDX_SENSOR,
+	IDX_CSIS,
+	IDX_FLITE,
+	IDX_FIMC_IS,
+	IDX_MAX,
+};
+
+enum fimc_isp_subdev_index {
+	IDX_ISP,
+	IDX_SCC,
+	IDX_SCP,
+	IDX_IS_MAX,
+};
+
+enum fimc_sensor_clks {
+	SCLK_CAM0,
+	SCLK_CAM1,
+	SCLK_BAYER,
+	FIMC_MAX_CAMCLKS,
+};
+
+struct fimc_pipeline {
+	struct exynos_media_pipeline ep;
+	struct list_head list;
+	struct media_entity *vdev_entity;
+	struct v4l2_subdev *subdevs[IDX_MAX];
+	struct list_head *isp_pipelines;
+};
+
+struct fimc_pipeline_isp {
+	struct exynos_media_pipeline ep;
+	struct list_head list;
+	struct v4l2_subdev *subdevs[IDX_IS_MAX];
+	bool in_use;
+};
+
+struct fimc_csis_info {
+	struct v4l2_subdev *sd;
+	int id;
+};
+
+struct fimc_camclk_info {
+	struct clk *clock;
+	int use_count;
+	unsigned long frequency;
+};
+
+/**
+ * struct fimc_sensor_info - image data source subdev information
+ * @pdata: sensor's atrributes passed as media device's platform data
+ * @asd: asynchronous subdev registration data structure
+ * @subdev: image sensor v4l2 subdev
+ * @host: fimc device the sensor is currently linked to
+ *
+ * This data structure applies to image sensor and the writeback subdevs.
+ */
+struct fimc_sensor_info {
+	struct fimc_source_info pdata;
+	struct v4l2_async_subdev asd;
+	struct v4l2_subdev *subdev;
+	struct fimc_dev *host;
+};
+
+/**
+ * struct fimc_md - fimc media device information
+ * @csis: MIPI CSIS subdevs data
+ * @sensor: array of registered sensor subdevs
+ * @num_sensors: actual number of registered sensors
+ * @camclk: external sensor clock information
+ * @fimc: array of registered fimc devices
+ * @is: fimc-is data structure
+ * @pmf: handle to the CAMCLK clock control FIMC helper device
+ * @media_dev: top level media device
+ * @v4l2_dev: top level v4l2_device holding up the subdevs
+ * @pdev: platform device this media device is hooked up into
+ * @user_subdev_api: true if subdevs are not configured by the host driver
+ * @slock: spinlock protecting @sensor array
+ */
+struct fimc_md {
+	struct fimc_csis_info csis[CSIS_MAX_ENTITIES];
+	struct fimc_sensor_info sensor[FIMC_MAX_SENSORS];
+	int num_sensors;
+	struct fimc_camclk_info camclk[FIMC_MAX_CAMCLKS];
+	struct fimc_lite *fimc_lite[FIMC_LITE_MAX_DEVS];
+	struct fimc_is *is;
+	struct device *pmf;
+	struct media_device media_dev;
+	struct v4l2_device v4l2_dev;
+	struct platform_device *pdev;
+	struct cam_clk_provider {
+		struct clk *clks[FIMC_MAX_CAMCLKS];
+		struct clk_onecell_data clk_data;
+		struct device_node *of_node;
+	} clk_provider;
+
+	struct v4l2_async_notifier subdev_notifier;
+	struct v4l2_async_subdev *async_subdevs[FIMC_MAX_SENSORS];
+
+	bool user_subdev_api;
+	spinlock_t slock;
+	struct list_head pipelines;
+	struct list_head isp_pipelines;
+};
+
+#define is_subdev_pad(pad) (pad == NULL || \
+	media_entity_type(pad->entity) == MEDIA_ENT_T_V4L2_SUBDEV)
+
+#define me_subtype(me) \
+	((me->type) & (MEDIA_ENT_TYPE_MASK | MEDIA_ENT_SUBTYPE_MASK))
+
+#define subdev_has_devnode(__sd) (__sd->flags & V4L2_SUBDEV_FL_HAS_DEVNODE)
+
+#define to_fimc_pipeline(_ep) container_of(_ep, struct fimc_pipeline, ep)
+#define to_fimc_isp_pipeline(_ep) \
+	container_of(_ep, struct fimc_pipeline_isp, ep)
+
+static inline struct fimc_md *entity_to_fimc_mdev(struct media_entity *me)
+{
+	return me->parent == NULL ? NULL :
+		container_of(me->parent, struct fimc_md, media_dev);
+}
+
+static inline struct fimc_md *notifier_to_fimc_md(struct v4l2_async_notifier *n)
+{
+	return container_of(n, struct fimc_md, subdev_notifier);
+}
+
+static inline void fimc_md_graph_lock(struct exynos_video_entity *ve)
+{
+	mutex_lock(&ve->vdev.entity.parent->graph_mutex);
+}
+
+static inline void fimc_md_graph_unlock(struct exynos_video_entity *ve)
+{
+	mutex_unlock(&ve->vdev.entity.parent->graph_mutex);
+}
+
+#ifdef CONFIG_OF
+static inline bool fimc_md_is_isp_available(struct device_node *node)
+{
+	node = of_get_child_by_name(node, FIMC_IS_OF_NODE_NAME);
+	return node ? of_device_is_available(node) : false;
+}
+
+static inline void fimc_md_unregister_clk_provider(struct fimc_md *fmd)
+{
+	if (fmd->clk_provider.of_node)
+		of_clk_del_provider(fmd->clk_provider.of_node);
+}
+#else
+
+#define fimc_md_is_isp_available(node) (false)
+#define fimc_md_unregister_clk_provider(fmd) (0)
+#endif /* CONFIG_OF */
+
+static inline struct v4l2_subdev *__fimc_md_get_subdev(
+				struct exynos_media_pipeline *ep,
+				unsigned int index)
+{
+	struct fimc_pipeline *p = to_fimc_pipeline(ep);
+
+	if (!p || index >= IDX_MAX)
+		return NULL;
+	else
+		return p->subdevs[index];
+}
+
+#endif
-- 
1.7.9.5

[RFC v3 02/13] [media] exynos5-fimc-is: Add Exynos5 FIMC-IS device tree bindings documentation

[Arun Kumar K]

The patch adds the DT binding documentation for Samsung
Exynos5 SoC series imaging subsystem (FIMC-IS).

Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
---
 .../devicetree/bindings/media/exynos5-fimc-is.txt  |   52 ++++++++++++++++++++
 1 file changed, 52 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/exynos5-fimc-is.txt

diff --git a/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt b/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
new file mode 100644
index 0000000..49a373a
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
@@ -0,0 +1,52 @@
+Samsung EXYNOS5 SoC series Imaging Subsystem (FIMC-IS)
+------------------------------------------------------
+
+The camera subsystem on Samsung Exynos5 SoC has some changes relative
+to previous SoC versions. Exynos5 has almost similar MIPI-CSIS and
+FIMC-LITE IPs but has a much improved version of FIMC-IS which can
+handle sensor controls and camera post-processing operations. The
+Exynos5 FIMC-IS has a dedicated ARM Cortex A5 processor, many
+post-processing blocks (ISP, DRC, FD, ODC, DIS, 3DNR) and two
+dedicated scalers (SCC and SCP).
+
+fimc-is node
+------------
+
+Required properties:
+
+- compatible        : must be "samsung,exynos5250-fimc-is"
+- reg               : physical base address and size of the memory mapped
+                      registers
+- interrupt-parent  : Parent interrupt controller
+- interrupts        : fimc-is interrupt to the parent combiner
+- clocks            : list of clock specifiers, corresponding to entries in
+                      clock-names property;
+- clock-names       : must contain "isp", "mcu_isp", "isp_div0", "isp_div1",
+                      "isp_divmpwm", "mcu_isp_div0", "mcu_isp_div1" entries,
+                      matching entries in the clocks property.
+
+pmu subnode
+-----------
+
+Required properties:
+ - reg : should contain PMU physical base address and size of the memory
+         mapped registers.
+
+i2c-isp (ISP I2C bus controller) nodes
+------------------------------------------
+
+Required properties:
+
+- compatible	: should be "samsung,exynos4212-i2c-isp" for Exynos4212,
+		  Exynos4412 and Exynos5250 SoCs;
+- reg		: physical base address and length of the registers set;
+- clocks	: must contain gate clock specifier for this controller;
+- clock-names	: must contain "i2c_isp" entry.
+
+For the above nodes it is required to specify a pinctrl state named "default",
+according to the pinctrl bindings defined in ../pinctrl/pinctrl-bindings.txt.
+
+Device tree nodes of the image sensors' controlled directly by the FIMC-IS
+firmware must be child nodes of their corresponding ISP I2C bus controller node.
+The data link of these image sensors must be specified using the common video
+interfaces bindings, defined in video-interfaces.txt.
-- 
1.7.9.5

[RFC v3 03/13] [media] exynos5-fimc-is: Add driver core files

[Arun Kumar K]

This driver is for the FIMC-IS IP available in Samsung Exynos5
SoC onwards. This patch adds the core files for the new driver.

Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Kilyeon Im <kilyeon.im@samsung.com>
---
 drivers/media/platform/exynos5-is/fimc-is-core.c |  394 ++++++++++++++++++++++
 drivers/media/platform/exynos5-is/fimc-is-core.h |  122 +++++++
 2 files changed, 516 insertions(+)
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.c
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.h

diff --git a/drivers/media/platform/exynos5-is/fimc-is-core.c b/drivers/media/platform/exynos5-is/fimc-is-core.c
new file mode 100644
index 0000000..7b7762b
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-core.c
@@ -0,0 +1,394 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+*
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K <arun.kk@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/bug.h>
+#include <linux/ctype.h>
+#include <linux/device.h>
+#include <linux/debugfs.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/firmware.h>
+#include <linux/fs.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/slab.h>
+#include <linux/videodev2.h>
+#include <linux/of.h>
+#include <linux/of_gpio.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/of_irq.h>
+#include <linux/pinctrl/consumer.h>
+
+#include <media/v4l2-device.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-mem2mem.h>
+#include <media/v4l2-of.h>
+#include <media/videobuf2-core.h>
+#include <media/videobuf2-dma-contig.h>
+
+#include "fimc-is.h"
+#include "fimc-is-i2c.h"
+
+#define CLK_MCU_ISP_DIV0_FREQ	(200 * 1000000)
+#define CLK_MCU_ISP_DIV1_FREQ	(100 * 1000000)
+#define CLK_ISP_DIV0_FREQ	(134 * 1000000)
+#define CLK_ISP_DIV1_FREQ	(68 * 1000000)
+#define CLK_ISP_DIVMPWM_FREQ	(34 * 1000000)
+
+static char *fimc_is_clock_name[] = {
+	[IS_CLK_ISP]		= "isp",
+	[IS_CLK_MCU_ISP]	= "mcu_isp",
+	[IS_CLK_ISP_DIV0]	= "isp_div0",
+	[IS_CLK_ISP_DIV1]	= "isp_div1",
+	[IS_CLK_ISP_DIVMPWM]	= "isp_divmpwm",
+	[IS_CLK_MCU_ISP_DIV0]	= "mcu_isp_div0",
+	[IS_CLK_MCU_ISP_DIV1]	= "mcu_isp_div1",
+};
+
+static void fimc_is_put_clocks(struct fimc_is *is)
+{
+	int i;
+
+	for (i = 0; i < IS_CLK_MAX_NUM; i++) {
+		if (IS_ERR(is->clock[i]))
+			continue;
+		clk_unprepare(is->clock[i]);
+		clk_put(is->clock[i]);
+		is->clock[i] = NULL;
+	}
+}
+
+static int fimc_is_get_clocks(struct fimc_is *is)
+{
+	struct device *dev = &is->pdev->dev;
+	int i, ret;
+
+	for (i = 0; i < IS_CLK_MAX_NUM; i++) {
+		is->clock[i] = clk_get(dev, fimc_is_clock_name[i]);
+		if (IS_ERR(is->clock[i]))
+			goto err;
+		ret = clk_prepare(is->clock[i]);
+		if (ret < 0) {
+			clk_put(is->clock[i]);
+			is->clock[i] = ERR_PTR(-EINVAL);
+			goto err;
+		}
+	}
+	return 0;
+err:
+	fimc_is_put_clocks(is);
+	pr_err("Failed to get clock: %s\n", fimc_is_clock_name[i]);
+	return -ENXIO;
+}
+
+static int fimc_is_configure_clocks(struct fimc_is *is)
+{
+	int i, ret;
+
+	for (i = 0; i < IS_CLK_MAX_NUM; i++)
+		is->clock[i] = ERR_PTR(-EINVAL);
+
+	ret = fimc_is_get_clocks(is);
+	if (ret)
+		return ret;
+
+	/* Set rates */
+	ret = clk_set_rate(is->clock[IS_CLK_MCU_ISP_DIV0],
+			CLK_MCU_ISP_DIV0_FREQ);
+	if (ret)
+		return ret;
+	ret = clk_set_rate(is->clock[IS_CLK_MCU_ISP_DIV1],
+			CLK_MCU_ISP_DIV1_FREQ);
+	if (ret)
+		return ret;
+	ret = clk_set_rate(is->clock[IS_CLK_ISP_DIV0], CLK_ISP_DIV0_FREQ);
+	if (ret)
+		return ret;
+	ret = clk_set_rate(is->clock[IS_CLK_ISP_DIV1], CLK_ISP_DIV1_FREQ);
+	if (ret)
+		return ret;
+	ret = clk_set_rate(is->clock[IS_CLK_ISP_DIVMPWM],
+			CLK_ISP_DIVMPWM_FREQ);
+	return ret;
+}
+
+static void fimc_is_pipelines_destroy(struct fimc_is *is)
+{
+	int i;
+
+	for (i = 0; i < is->num_instance; i++)
+		fimc_is_pipeline_destroy(&is->pipeline[i]);
+}
+
+static int fimc_is_parse_sensor_config(struct fimc_is *is, unsigned int index,
+						struct device_node *node)
+{
+	struct fimc_is_sensor *sensor = &is->sensor[index];
+	u32 tmp = 0;
+	int ret;
+
+	sensor->drvdata = exynos5_is_sensor_get_drvdata(node);
+	if (!sensor->drvdata) {
+		dev_err(&is->pdev->dev, "no driver data found for: %s\n",
+							 node->full_name);
+		return -EINVAL;
+	}
+
+	node = v4l2_of_get_next_endpoint(node, NULL);
+	if (!node)
+		return -ENXIO;
+
+	node = v4l2_of_get_remote_port(node);
+	if (!node)
+		return -ENXIO;
+
+	/* Use MIPI-CSIS channel id to determine the ISP I2C bus index. */
+	ret = of_property_read_u32(node, "reg", &tmp);
+	if (ret < 0) {
+		dev_err(&is->pdev->dev, "reg property not found at: %s\n",
+							 node->full_name);
+		return ret;
+	}
+
+	sensor->i2c_bus = tmp - FIMC_INPUT_MIPI_CSI2_0;
+	return 0;
+}
+
+static int fimc_is_parse_sensor(struct fimc_is *is)
+{
+	struct device_node *i2c_bus, *child;
+	int ret, index = 0;
+
+	for_each_compatible_node(i2c_bus, NULL, FIMC_IS_I2C_COMPATIBLE) {
+		for_each_available_child_of_node(i2c_bus, child) {
+			ret = fimc_is_parse_sensor_config(is, index, child);
+
+			if (ret < 0 || index >= FIMC_IS_NUM_SENSORS) {
+				of_node_put(child);
+				return ret;
+			}
+			index++;
+		}
+	}
+	return 0;
+}
+
+static int fimc_is_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct resource *res;
+	struct fimc_is *is;
+	void __iomem *regs;
+	struct device_node *node;
+	int irq, ret;
+	int i;
+
+	pr_debug("FIMC-IS Probe Enter\n");
+
+	if (!pdev->dev.of_node)
+		return -ENODEV;
+
+	is = devm_kzalloc(&pdev->dev, sizeof(*is), GFP_KERNEL);
+	if (!is)
+		return -ENOMEM;
+
+	is->pdev = pdev;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	regs = devm_ioremap_resource(dev, res);
+	if (IS_ERR(regs))
+		return PTR_ERR(regs);
+
+	/* Get the PMU base */
+	node = of_get_child_by_name(dev->of_node, "pmu");
+	if (!node)
+		return -ENODEV;
+	is->pmu_regs = of_iomap(node, 0);
+	if (!is->pmu_regs)
+		return -ENOMEM;
+
+	irq = irq_of_parse_and_map(dev->of_node, 0);
+	if (irq < 0) {
+		dev_err(dev, "Failed to get IRQ\n");
+		return irq;
+	}
+
+	ret = of_property_read_u32(pdev->dev.of_node, "num-instance",
+			&is->num_instance);
+	if (ret && !is->num_instance) {
+		dev_err(dev, "Error num instances\n");
+		return -EINVAL;
+	}
+
+	ret = fimc_is_configure_clocks(is);
+	if (ret < 0) {
+		dev_err(dev, "Clock config failed\n");
+		goto err_clk;
+	}
+
+	platform_set_drvdata(pdev, is);
+	pm_runtime_enable(dev);
+
+	ret = pm_runtime_get_sync(dev);
+	if (ret < 0)
+		goto err_pm;
+
+	is->alloc_ctx = vb2_dma_contig_init_ctx(dev);
+	if (IS_ERR(is->alloc_ctx)) {
+		ret = PTR_ERR(is->alloc_ctx);
+		goto err_vb;
+	}
+
+	/* Get IS-sensor contexts */
+	ret = fimc_is_parse_sensor(is);
+	if (ret < 0)
+		goto err_vb;
+
+	/* Initialize FIMC Pipeline */
+	for (i = 0; i < is->num_instance; i++) {
+		ret = fimc_is_pipeline_init(&is->pipeline[i], i, is);
+		if (ret < 0)
+			goto err_sd;
+	}
+
+	/* Initialize FIMC Interface */
+	ret = fimc_is_interface_init(&is->interface, regs, irq);
+	if (ret < 0)
+		goto err_sd;
+
+	pm_runtime_put(dev);
+
+	dev_dbg(dev, "FIMC-IS registered successfully\n");
+
+	return 0;
+
+err_sd:
+	fimc_is_pipelines_destroy(is);
+err_vb:
+	vb2_dma_contig_cleanup_ctx(is->alloc_ctx);
+err_pm:
+	pm_runtime_put(dev);
+err_clk:
+	fimc_is_put_clocks(is);
+
+	return ret;
+}
+
+int fimc_is_clk_enable(struct fimc_is *is)
+{
+	int ret;
+
+	ret = clk_enable(is->clock[IS_CLK_ISP]);
+	if (ret)
+		return ret;
+	ret = clk_enable(is->clock[IS_CLK_MCU_ISP]);
+	return ret;
+}
+
+void fimc_is_clk_disable(struct fimc_is *is)
+{
+	clk_disable(is->clock[IS_CLK_ISP]);
+	clk_disable(is->clock[IS_CLK_MCU_ISP]);
+}
+
+static int fimc_is_pm_resume(struct device *dev)
+{
+	struct fimc_is *is = dev_get_drvdata(dev);
+	int ret;
+
+	ret = fimc_is_clk_enable(is);
+	if (ret < 0) {
+		dev_err(dev, "Could not enable clocks\n");
+		return ret;
+	}
+	return 0;
+}
+
+static int fimc_is_pm_suspend(struct device *dev)
+{
+	struct fimc_is *is = dev_get_drvdata(dev);
+
+	fimc_is_clk_disable(is);
+	return 0;
+}
+
+static int fimc_is_runtime_resume(struct device *dev)
+{
+	return fimc_is_pm_resume(dev);
+}
+
+static int fimc_is_runtime_suspend(struct device *dev)
+{
+	return fimc_is_pm_suspend(dev);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int fimc_is_resume(struct device *dev)
+{
+	return fimc_is_pm_resume(dev);
+}
+
+static int fimc_is_suspend(struct device *dev)
+{
+	return fimc_is_pm_suspend(dev);
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static int fimc_is_remove(struct platform_device *pdev)
+{
+	struct fimc_is *is = platform_get_drvdata(pdev);
+	struct device *dev = &pdev->dev;
+
+	pm_runtime_disable(dev);
+	pm_runtime_set_suspended(dev);
+	fimc_is_pipelines_destroy(is);
+	vb2_dma_contig_cleanup_ctx(is->alloc_ctx);
+	fimc_is_put_clocks(is);
+	return 0;
+}
+
+static const struct dev_pm_ops fimc_is_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(fimc_is_suspend, fimc_is_resume)
+	SET_RUNTIME_PM_OPS(fimc_is_runtime_suspend, fimc_is_runtime_resume,
+			   NULL)
+};
+
+static const struct of_device_id exynos5_fimc_is_match[] = {
+	{
+		.compatible = "samsung,exynos5250-fimc-is",
+	},
+	{},
+};
+MODULE_DEVICE_TABLE(of, exynos5_fimc_is_match);
+
+static struct platform_driver fimc_is_driver = {
+	.probe		= fimc_is_probe,
+	.remove		= fimc_is_remove,
+	.driver = {
+		.name	= FIMC_IS_DRV_NAME,
+		.owner	= THIS_MODULE,
+		.pm	= &fimc_is_pm_ops,
+		.of_match_table = exynos5_fimc_is_match,
+	}
+};
+module_platform_driver(fimc_is_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Arun Kumar K <arun.kk@samsung.com>");
+MODULE_DESCRIPTION("Samsung Exynos5 (FIMC-IS) Imaging Subsystem driver");
diff --git a/drivers/media/platform/exynos5-is/fimc-is-core.h b/drivers/media/platform/exynos5-is/fimc-is-core.h
new file mode 100644
index 0000000..45b56cc
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-core.h
@@ -0,0 +1,122 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ *  Arun Kumar K <arun.kk@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef FIMC_IS_CORE_H_
+#define FIMC_IS_CORE_H_
+
+#include <linux/bug.h>
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/firmware.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/slab.h>
+#include <linux/videodev2.h>
+
+#include <asm/barrier.h>
+#include <linux/sizes.h>
+#include <linux/io.h>
+#include <linux/irqreturn.h>
+#include <linux/platform_device.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+
+#include <media/media-entity.h>
+#include <media/videobuf2-core.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-mem2mem.h>
+#include <media/v4l2-mediabus.h>
+#include <media/s5p_fimc.h>
+
+#define FIMC_IS_DRV_NAME		"exynos5-fimc-is"
+
+#define FIMC_IS_COMMAND_TIMEOUT		(3 * HZ)
+#define FIMC_IS_STARTUP_TIMEOUT		(3 * HZ)
+#define FIMC_IS_SHUTDOWN_TIMEOUT	(10 * HZ)
+
+#define FW_SHARED_OFFSET		(0x8c0000)
+#define DEBUG_CNT			(500*1024)
+#define DEBUG_OFFSET			(0x840000)
+#define DEBUGCTL_OFFSET			(0x8bd000)
+#define DEBUG_FCOUNT			(0x8c64c0)
+
+#define FIMC_IS_MAX_INSTANCES		1
+
+#define FIMC_IS_NUM_SENSORS		2
+#define FIMC_IS_NUM_PIPELINES		1
+
+#define FIMC_IS_MAX_PLANES		3
+#define FIMC_IS_NUM_SCALERS		2
+
+enum fimc_is_clks {
+	IS_CLK_ISP,
+	IS_CLK_MCU_ISP,
+	IS_CLK_ISP_DIV0,
+	IS_CLK_ISP_DIV1,
+	IS_CLK_ISP_DIVMPWM,
+	IS_CLK_MCU_ISP_DIV0,
+	IS_CLK_MCU_ISP_DIV1,
+	IS_CLK_MAX_NUM
+};
+
+/* Video capture states */
+enum fimc_is_video_state {
+	STATE_INIT,
+	STATE_BUFS_ALLOCATED,
+	STATE_RUNNING,
+};
+
+enum fimc_is_scaler_id {
+	SCALER_SCC,
+	SCALER_SCP
+};
+
+enum fimc_is_sensor_pos {
+	SENSOR_CAM0,
+	SENSOR_CAM1
+};
+
+struct fimc_is_buf {
+	struct list_head list;
+	struct vb2_buffer *vb;
+	unsigned int paddr[FIMC_IS_MAX_PLANES];
+};
+
+struct fimc_is_meminfo {
+	unsigned int fw_paddr;
+	unsigned int fw_vaddr;
+	unsigned int region_paddr;
+	unsigned int region_vaddr;
+	unsigned int shared_paddr;
+	unsigned int shared_vaddr;
+};
+
+/**
+ * struct fimc_is_fmt - the driver's internal color format data
+ * @name: format description
+ * @fourcc: the fourcc code for this format
+ * @depth: number of bytes per pixel
+ * @num_planes: number of planes for this color format
+ */
+struct fimc_is_fmt {
+	char		*name;
+	unsigned int	fourcc;
+	unsigned int	depth[FIMC_IS_MAX_PLANES];
+	unsigned int	num_planes;
+};
+
+#endif
-- 
1.7.9.5

[RFC v3 04/13] [media] exynos5-fimc-is: Add common driver header files

[Arun Kumar K]

This patch adds all the common header files used by the fimc-is
driver. It includes the commands for interfacing with the firmware
and error codes from IS firmware, metadata and command parameter
definitions.

Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Kilyeon Im <kilyeon.im@samsung.com>
---
 drivers/media/platform/exynos5-is/fimc-is-cmd.h    |  187 +++
 drivers/media/platform/exynos5-is/fimc-is-err.h    |  257 +++++
 .../media/platform/exynos5-is/fimc-is-metadata.h   |  767 +++++++++++++
 drivers/media/platform/exynos5-is/fimc-is-param.h  | 1212 ++++++++++++++++++++
 4 files changed, 2423 insertions(+)
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-cmd.h
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-err.h
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-metadata.h
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-param.h

diff --git a/drivers/media/platform/exynos5-is/fimc-is-cmd.h b/drivers/media/platform/exynos5-is/fimc-is-cmd.h
new file mode 100644
index 0000000..6250280
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-cmd.h
@@ -0,0 +1,187 @@
+/*
+ * Samsung Exynos5 SoC series FIMC-IS driver
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd
+ * Kil-yeon Lim <kilyeon.im@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef FIMC_IS_CMD_H
+#define FIMC_IS_CMD_H
+
+#define IS_COMMAND_VER 122 /* IS COMMAND VERSION 1.22 */
+
+enum is_cmd {
+	/* HOST -> IS */
+	HIC_PREVIEW_STILL = 0x1,
+	HIC_PREVIEW_VIDEO,
+	HIC_CAPTURE_STILL,
+	HIC_CAPTURE_VIDEO,
+	HIC_PROCESS_START,
+	HIC_PROCESS_STOP,
+	HIC_STREAM_ON,
+	HIC_STREAM_OFF,
+	HIC_SHOT,
+	HIC_GET_STATIC_METADATA,
+	HIC_SET_CAM_CONTROL,
+	HIC_GET_CAM_CONTROL,
+	HIC_SET_PARAMETER,
+	HIC_GET_PARAMETER,
+	HIC_SET_A5_MEM_ACCESS,
+	RESERVED2,
+	HIC_GET_STATUS,
+	/* SENSOR PART*/
+	HIC_OPEN_SENSOR,
+	HIC_CLOSE_SENSOR,
+	HIC_SIMMIAN_INIT,
+	HIC_SIMMIAN_WRITE,
+	HIC_SIMMIAN_READ,
+	HIC_POWER_DOWN,
+	HIC_GET_SET_FILE_ADDR,
+	HIC_LOAD_SET_FILE,
+	HIC_MSG_CONFIG,
+	HIC_MSG_TEST,
+	/* IS -> HOST */
+	IHC_GET_SENSOR_NUMBER = 0x1000,
+	/* Parameter1 : Address of space to copy a setfile */
+	/* Parameter2 : Space szie */
+	IHC_SET_SHOT_MARK,
+	/* PARAM1 : a frame number */
+	/* PARAM2 : confidence level(smile 0~100) */
+	/* PARMA3 : confidence level(blink 0~100) */
+	IHC_SET_FACE_MARK,
+	/* PARAM1 : coordinate count */
+	/* PARAM2 : coordinate buffer address */
+	IHC_FRAME_DONE,
+	/* PARAM1 : frame start number */
+	/* PARAM2 : frame count */
+	IHC_AA_DONE,
+	IHC_NOT_READY,
+	IHC_FLASH_READY
+};
+
+enum is_reply {
+	ISR_DONE	= 0x2000,
+	ISR_NDONE
+};
+
+enum is_scenario_id {
+	ISS_PREVIEW_STILL,
+	ISS_PREVIEW_VIDEO,
+	ISS_CAPTURE_STILL,
+	ISS_CAPTURE_VIDEO,
+	ISS_END
+};
+
+enum is_subscenario_id {
+	ISS_SUB_SCENARIO_STILL,
+	ISS_SUB_SCENARIO_VIDEO,
+	ISS_SUB_SCENARIO_SCENE1,
+	ISS_SUB_SCENARIO_SCENE2,
+	ISS_SUB_SCENARIO_SCENE3,
+	ISS_SUB_END
+};
+
+struct is_setfile_header_element {
+	u32 binary_addr;
+	u32 binary_size;
+};
+
+struct is_setfile_header {
+	struct is_setfile_header_element isp[ISS_END];
+	struct is_setfile_header_element drc[ISS_END];
+	struct is_setfile_header_element fd[ISS_END];
+};
+
+struct is_common_reg {
+	u32 hicmd;
+	u32 hic_sensorid;
+	u32 hic_param[4];
+
+	u32 reserved1[3];
+
+	u32 ihcmd_iflag;
+	u32 ihcmd;
+	u32 ihc_sensorid;
+	u32 ihc_param[4];
+
+	u32 reserved2[3];
+
+	u32 isp_bayer_iflag;
+	u32 isp_bayer_sensor_id;
+	u32 isp_bayer_param[2];
+
+	u32 reserved3[4];
+
+	u32 scc_iflag;
+	u32 scc_sensor_id;
+	u32 scc_param[3];
+
+	u32 reserved4[3];
+
+	u32 dnr_iflag;
+	u32 dnr_sensor_id;
+	u32 dnr_param[2];
+
+	u32 reserved5[4];
+
+	u32 scp_iflag;
+	u32 scp_sensor_id;
+	u32 scp_param[3];
+
+	u32 reserved6[1];
+
+	u32 isp_yuv_iflag;
+	u32 isp_yuv_sensor_id;
+	u32 isp_yuv_param[2];
+
+	u32 reserved7[1];
+
+	u32 shot_iflag;
+	u32 shot_sensor_id;
+	u32 shot_param[2];
+
+	u32 reserved8[1];
+
+	u32 meta_iflag;
+	u32 meta_sensor_id;
+	u32 meta_param1;
+
+	u32 reserved9[1];
+
+	u32 fcount;
+};
+
+struct is_mcuctl_reg {
+	u32 mcuctl;
+	u32 bboar;
+
+	u32 intgr0;
+	u32 intcr0;
+	u32 intmr0;
+	u32 intsr0;
+	u32 intmsr0;
+
+	u32 intgr1;
+	u32 intcr1;
+	u32 intmr1;
+	u32 intsr1;
+	u32 intmsr1;
+
+	u32 intcr2;
+	u32 intmr2;
+	u32 intsr2;
+	u32 intmsr2;
+
+	u32 gpoctrl;
+	u32 cpoenctlr;
+	u32 gpictlr;
+
+	u32 pad[0xD];
+
+	struct is_common_reg common_reg;
+};
+#endif
diff --git a/drivers/media/platform/exynos5-is/fimc-is-err.h b/drivers/media/platform/exynos5-is/fimc-is-err.h
new file mode 100644
index 0000000..e19eced
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-err.h
@@ -0,0 +1,257 @@
+/*
+ * Samsung Exynos5 SoC series FIMC-IS driver
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd
+ * Arun Kumar K <arun.kk@samsung.com>
+ * Kil-yeon Lim <kilyeon.im@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef FIMC_IS_ERR_H
+#define FIMC_IS_ERR_H
+
+#define IS_ERROR_VER 012 /* IS ERROR VERSION 0.07 */
+
+/* IS error enum */
+enum is_error {
+
+	IS_ERROR_SUCCESS = 0,
+
+	/* General 1 ~ 100 */
+	IS_ERROR_INVALID_COMMAND = 1,
+	IS_ERROR_REQUEST_FAIL,
+	IS_ERROR_INVALID_SCENARIO,
+	IS_ERROR_INVALID_SENSORID,
+	IS_ERROR_INVALID_MODE_CHANGE,
+	IS_ERROR_INVALID_MAGIC_NUMBER,
+	IS_ERROR_INVALID_SETFILE_HDR,
+	IS_ERROR_ISP_SETFILE_VERSION_MISMATCH,
+	IS_ERROR_ISP_SETFILE_REVISION_MISMATCH,
+	IS_ERROR_BUSY,
+	IS_ERROR_SET_PARAMETER,
+	IS_ERROR_INVALID_PATH,
+	IS_ERROR_OPEN_SENSOR_FAIL,
+	IS_ERROR_ENTRY_MSG_THREAD_DOWN,
+	IS_ERROR_ISP_FRAME_END_NOT_DONE,
+	IS_ERROR_DRC_FRAME_END_NOT_DONE,
+	IS_ERROR_SCALERC_FRAME_END_NOT_DONE,
+	IS_ERROR_ODC_FRAME_END_NOT_DONE,
+	IS_ERROR_DIS_FRAME_END_NOT_DONE,
+	IS_ERROR_TDNR_FRAME_END_NOT_DONE,
+	IS_ERROR_SCALERP_FRAME_END_NOT_DONE,
+	IS_ERROR_WAIT_STREAM_OFF_NOT_DONE,
+	IS_ERROR_NO_MSG_IS_RECEIVED,
+	IS_ERROR_SENSOR_MSG_FAIL,
+	IS_ERROR_ISP_MSG_FAIL,
+	IS_ERROR_DRC_MSG_FAIL,
+	IS_ERROR_SCALERC_MSG_FAIL,
+	IS_ERROR_ODC_MSG_FAIL,
+	IS_ERROR_DIS_MSG_FAIL,
+	IS_ERROR_TDNR_MSG_FAIL,
+	IS_ERROR_SCALERP_MSG_FAIL,
+	IS_ERROR_LHFD_MSG_FAIL,
+	IS_ERROR_INTERNAL_STOP,
+	IS_ERROR_UNKNOWN,
+	IS_ERROR_TIME_OUT_FLAG,
+
+	/* Sensor 100 ~ 200 */
+	IS_ERROR_SENSOR_PWRDN_FAIL = 100,
+	IS_ERROR_SENSOR_STREAM_ON_FAIL,
+	IS_ERROR_SENSOR_STREAM_OFF_FAIL,
+
+	/* ISP 200 ~ 300 */
+	IS_ERROR_ISP_PWRDN_FAIL = 200,
+	IS_ERROR_ISP_MULTIPLE_INPUT,
+	IS_ERROR_ISP_ABSENT_INPUT,
+	IS_ERROR_ISP_ABSENT_OUTPUT,
+	IS_ERROR_ISP_NONADJACENT_OUTPUT,
+	IS_ERROR_ISP_FORMAT_MISMATCH,
+	IS_ERROR_ISP_WIDTH_MISMATCH,
+	IS_ERROR_ISP_HEIGHT_MISMATCH,
+	IS_ERROR_ISP_BITWIDTH_MISMATCH,
+	IS_ERROR_ISP_FRAME_END_TIME_OUT,
+
+	/* DRC 300 ~ 400 */
+	IS_ERROR_DRC_PWRDN_FAIL = 300,
+	IS_ERROR_DRC_MULTIPLE_INPUT,
+	IS_ERROR_DRC_ABSENT_INPUT,
+	IS_ERROR_DRC_NONADJACENT_INTPUT,
+	IS_ERROR_DRC_ABSENT_OUTPUT,
+	IS_ERROR_DRC_NONADJACENT_OUTPUT,
+	IS_ERROR_DRC_FORMAT_MISMATCH,
+	IS_ERROR_DRC_WIDTH_MISMATCH,
+	IS_ERROR_DRC_HEIGHT_MISMATCH,
+	IS_ERROR_DRC_BITWIDTH_MISMATCH,
+	IS_ERROR_DRC_FRAME_END_TIME_OUT,
+
+	/*SCALERC(400~500)*/
+	IS_ERROR_SCALERC_PWRDN_FAIL = 400,
+
+	/*ODC(500~600)*/
+	IS_ERROR_ODC_PWRDN_FAIL = 500,
+
+	/*DIS(600~700)*/
+	IS_ERROR_DIS_PWRDN_FAIL = 600,
+
+	/*TDNR(700~800)*/
+	IS_ERROR_TDNR_PWRDN_FAIL = 700,
+
+	/*SCALERP(800~900)*/
+	IS_ERROR_SCALERP_PWRDN_FAIL = 800,
+
+	/*FD(900~1000)*/
+	IS_ERROR_FD_PWRDN_FAIL = 900,
+	IS_ERROR_FD_MULTIPLE_INPUT,
+	IS_ERROR_FD_ABSENT_INPUT,
+	IS_ERROR_FD_NONADJACENT_INPUT,
+	IS_ERROR_LHFD_FRAME_END_TIME_OUT,
+};
+
+/* Set parameter error enum */
+enum error {
+	/* Common error (0~99) */
+	ERROR_COMMON_NONE		= 0,
+	ERROR_COMMON_CMD		= 1,	/* Invalid command*/
+	ERROR_COMMON_PARAMETER		= 2,	/* Invalid parameter*/
+	/* setfile is not loaded before adjusting */
+	ERROR_COMMON_SETFILE_LOAD	= 3,
+	/* setfile is not Adjusted before runnng. */
+	ERROR_COMMON_SETFILE_ADJUST	= 4,
+	/* index of setfile is not valid. */
+	ERROR_COMMON_SETFILE_INDEX = 5,
+	/* Input path can be changed in ready state(stop) */
+	ERROR_COMMON_INPUT_PATH		= 6,
+	/* IP can not start if input path is not set */
+	ERROR_COMMON_INPUT_INIT		= 7,
+	/* Output path can be changed in ready state(stop) */
+	ERROR_COMMON_OUTPUT_PATH	= 8,
+	/* IP can not start if output path is not set */
+	ERROR_COMMON_OUTPUT_INIT	= 9,
+
+	ERROR_CONTROL_NONE		= ERROR_COMMON_NONE,
+	ERROR_CONTROL_BYPASS		= 11,	/* Enable or Disable */
+	ERROR_CONTROL_BUF		= 12,	/* invalid buffer info */
+
+	ERROR_OTF_INPUT_NONE		= ERROR_COMMON_NONE,
+	/* invalid command */
+	ERROR_OTF_INPUT_CMD		= 21,
+	/* invalid format  (DRC: YUV444, FD: YUV444, 422, 420) */
+	ERROR_OTF_INPUT_FORMAT		= 22,
+	/* invalid width (DRC: 128~8192, FD: 32~8190) */
+	ERROR_OTF_INPUT_WIDTH		= 23,
+	/* invalid height (DRC: 64~8192, FD: 16~8190) */
+	ERROR_OTF_INPUT_HEIGHT		= 24,
+	/* invalid bit-width (DRC: 8~12bits, FD: 8bit) */
+	ERROR_OTF_INPUT_BIT_WIDTH	= 25,
+	/* invalid frame time for ISP */
+	ERROR_OTF_INPUT_USER_FRAMETILE = 26,
+
+	ERROR_DMA_INPUT_NONE		= ERROR_COMMON_NONE,
+	/* invalid width (DRC: 128~8192, FD: 32~8190) */
+	ERROR_DMA_INPUT_WIDTH		= 31,
+	/* invalid height (DRC: 64~8192, FD: 16~8190) */
+	ERROR_DMA_INPUT_HEIGHT		= 32,
+	/* invalid format (DRC: YUV444 or YUV422, FD: YUV444, 422, 420) */
+	ERROR_DMA_INPUT_FORMAT		= 33,
+	/* invalid bit-width (DRC: 8~12bit, FD: 8bit) */
+	ERROR_DMA_INPUT_BIT_WIDTH	= 34,
+	/* invalid order(DRC: YYCbCrorYCbYCr, FD:NO,YYCbCr,YCbYCr,CbCr,CrCb) */
+	ERROR_DMA_INPUT_ORDER		= 35,
+	/* invalid palne (DRC: 3, FD: 1, 2, 3) */
+	ERROR_DMA_INPUT_PLANE		= 36,
+
+	ERROR_OTF_OUTPUT_NONE		= ERROR_COMMON_NONE,
+	/* invalid width (DRC: 128~8192) */
+	ERROR_OTF_OUTPUT_WIDTH		= 41,
+	/* invalid height (DRC: 64~8192) */
+	ERROR_OTF_OUTPUT_HEIGHT		= 42,
+	/* invalid format (DRC: YUV444) */
+	ERROR_OTF_OUTPUT_FORMAT		= 43,
+	/* invalid bit-width (DRC: 8~12bits) */
+	ERROR_OTF_OUTPUT_BIT_WIDTH	= 44,
+	/* invalid crop size (ODC: left>2, right>10) */
+	ERROR_OTF_OUTPUT_CROP		= 45,
+
+	ERROR_DMA_OUTPUT_NONE		= ERROR_COMMON_NONE,
+	ERROR_DMA_OUTPUT_WIDTH		= 51,	/* invalid width */
+	ERROR_DMA_OUTPUT_HEIGHT		= 52,	/* invalid height */
+	ERROR_DMA_OUTPUT_FORMAT		= 53,	/* invalid format */
+	ERROR_DMA_OUTPUT_BIT_WIDTH	= 54,	/* invalid bit-width */
+	ERROR_DMA_OUTPUT_PLANE		= 55,	/* invalid plane */
+	ERROR_DMA_OUTPUT_ORDER		= 56,	/* invalid order */
+	ERROR_DMA_OUTPUT_BUF		= 57,	/* invalid buffer info */
+
+	ERROR_GLOBAL_SHOTMODE_NONE	= ERROR_COMMON_NONE,
+
+	/* SENSOR Error(100~199) */
+	ERROR_SENSOR_NONE		= ERROR_COMMON_NONE,
+	ERROR_SENSOR_I2C_FAIL		= 101,
+	ERROR_SENSOR_INVALID_FRAMERATE,
+	ERROR_SENSOR_INVALID_EXPOSURETIME,
+	ERROR_SENSOR_INVALID_SIZE,
+	ERROR_SENSOR_ACTURATOR_INIT_FAIL,
+	ERROR_SENSOR_INVALID_AF_POS,
+	ERROR_SENSOR_UNSUPPORT_FUNC,
+	ERROR_SENSOR_UNSUPPORT_PERI,
+	ERROR_SENSOR_UNSUPPORT_AF,
+	ERROR_SENSOR_FLASH_FAIL,
+	ERROR_SENSOR_START_FAIL,
+	ERROR_SENSOR_STOP_FAIL,
+
+	/* ISP Error (200~299) */
+	ERROR_ISP_AF_NONE		= ERROR_COMMON_NONE,
+	ERROR_ISP_AF_BUSY		= 201,
+	ERROR_ISP_AF_INVALID_COMMAND	= 202,
+	ERROR_ISP_AF_INVALID_MODE	= 203,
+	ERROR_ISP_FLASH_NONE		= ERROR_COMMON_NONE,
+	ERROR_ISP_AWB_NONE		= ERROR_COMMON_NONE,
+	ERROR_ISP_IMAGE_EFFECT_NONE	= ERROR_COMMON_NONE,
+	ERROR_ISP_IMAGE_EFFECT_INVALID	= 231,
+	ERROR_ISP_ISO_NONE		= ERROR_COMMON_NONE,
+	ERROR_ISP_ADJUST_NONE		= ERROR_COMMON_NONE,
+	ERROR_ISP_METERING_NONE		= ERROR_COMMON_NONE,
+	ERROR_ISP_AFC_NONE		= ERROR_COMMON_NONE,
+
+	/* DRC Error (300~399) */
+
+	/* FD Error  (400~499) */
+	ERROR_FD_NONE					= ERROR_COMMON_NONE,
+	/* Invalid max number (1~16) */
+	ERROR_FD_CONFIG_MAX_NUMBER_STATE		= 401,
+	ERROR_FD_CONFIG_MAX_NUMBER_INVALID		= 402,
+	ERROR_FD_CONFIG_YAW_ANGLE_STATE			= 403,
+	ERROR_FD_CONFIG_YAW_ANGLE_INVALID		= 404,
+	ERROR_FD_CONFIG_ROLL_ANGLE_STATE		= 405,
+	ERROR_FD_CONFIG_ROLL_ANGLE_INVALID		= 406,
+	ERROR_FD_CONFIG_SMILE_MODE_INVALID		= 407,
+	ERROR_FD_CONFIG_BLINK_MODE_INVALID		= 408,
+	ERROR_FD_CONFIG_EYES_DETECT_INVALID		= 409,
+	ERROR_FD_CONFIG_MOUTH_DETECT_INVALID		= 410,
+	ERROR_FD_CONFIG_ORIENTATION_STATE		= 411,
+	ERROR_FD_CONFIG_ORIENTATION_INVALID		= 412,
+	ERROR_FD_CONFIG_ORIENTATION_VALUE_INVALID	= 413,
+	/* PARAM_FdResultStr can be only applied
+	 * in ready-state or stream off */
+	ERROR_FD_RESULT				= 414,
+	/* PARAM_FdModeStr can be only applied
+	 * in ready-state or stream off */
+	ERROR_FD_MODE					= 415,
+
+	/*SCALER ERR(500~599)*/
+	ERROR_SCALER_NONE			= ERROR_COMMON_NONE,
+	ERROR_SCALER_DMA_OUTSEL			= 501,
+	ERROR_SCALER_H_RATIO			= 502,
+	ERROR_SCALER_V_RATIO			= 503,
+	ERROR_SCALER_FRAME_BUFFER_SEQ		= 504,
+
+	ERROR_SCALER_IMAGE_EFFECT		= 510,
+
+	ERROR_SCALER_ROTATE			= 520,
+	ERROR_SCALER_FLIP			= 521,
+
+};
+
+#endif
diff --git a/drivers/media/platform/exynos5-is/fimc-is-metadata.h b/drivers/media/platform/exynos5-is/fimc-is-metadata.h
new file mode 100644
index 0000000..2f6339d
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-metadata.h
@@ -0,0 +1,767 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Kil-yeon Lim <kilyeon.im@samsung.com>
+ * Arun Kumar K <arun.kk@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef FIMC_IS_METADATA_H_
+#define FIMC_IS_METADATA_H_
+
+struct rational {
+	uint32_t num;
+	uint32_t den;
+};
+
+#define CAMERA2_MAX_AVAILABLE_MODE	21
+#define CAMERA2_MAX_FACES		16
+
+/*
+ * Controls/dynamic metadata
+ */
+
+enum metadata_mode {
+	METADATA_MODE_NONE,
+	METADATA_MODE_FULL
+};
+
+struct camera2_request_ctl {
+	uint32_t		id;
+	enum metadata_mode	metadatamode;
+	uint8_t			outputstreams[16];
+	uint32_t		framecount;
+};
+
+struct camera2_request_dm {
+	uint32_t		id;
+	enum metadata_mode	metadatamode;
+	uint32_t		framecount;
+};
+
+
+
+enum optical_stabilization_mode {
+	OPTICAL_STABILIZATION_MODE_OFF,
+	OPTICAL_STABILIZATION_MODE_ON
+};
+
+enum lens_facing {
+	LENS_FACING_BACK,
+	LENS_FACING_FRONT
+};
+
+struct camera2_lens_ctl {
+	uint32_t				focus_distance;
+	float					aperture;
+	float					focal_length;
+	float					filter_density;
+	enum optical_stabilization_mode		optical_stabilization_mode;
+};
+
+struct camera2_lens_dm {
+	uint32_t				focus_distance;
+	float					aperture;
+	float					focal_length;
+	float					filter_density;
+	enum optical_stabilization_mode		optical_stabilization_mode;
+	float					focus_range[2];
+};
+
+struct camera2_lens_sm {
+	float				minimum_focus_distance;
+	float				hyper_focal_distance;
+	float				available_focal_length[2];
+	float				available_apertures;
+	/* assuming 1 aperture */
+	float				available_filter_densities;
+	/* assuming 1 ND filter value */
+	enum optical_stabilization_mode	available_optical_stabilization;
+	/* assuming 1 */
+	uint32_t			shading_map_size;
+	float				shading_map[3][40][30];
+	uint32_t			geometric_correction_map_size;
+	float				geometric_correction_map[2][3][40][30];
+	enum lens_facing		facing;
+	float				position[2];
+};
+
+enum sensor_colorfilter_arrangement {
+	SENSOR_COLORFILTER_ARRANGEMENT_RGGB,
+	SENSOR_COLORFILTER_ARRANGEMENT_GRBG,
+	SENSOR_COLORFILTER_ARRANGEMENT_GBRG,
+	SENSOR_COLORFILTER_ARRANGEMENT_BGGR,
+	SENSOR_COLORFILTER_ARRANGEMENT_RGB
+};
+
+enum sensor_ref_illuminant {
+	SENSOR_ILLUMINANT_DAYLIGHT = 1,
+	SENSOR_ILLUMINANT_FLUORESCENT = 2,
+	SENSOR_ILLUMINANT_TUNGSTEN = 3,
+	SENSOR_ILLUMINANT_FLASH = 4,
+	SENSOR_ILLUMINANT_FINE_WEATHER = 9,
+	SENSOR_ILLUMINANT_CLOUDY_WEATHER = 10,
+	SENSOR_ILLUMINANT_SHADE = 11,
+	SENSOR_ILLUMINANT_DAYLIGHT_FLUORESCENT = 12,
+	SENSOR_ILLUMINANT_DAY_WHITE_FLUORESCENT = 13,
+	SENSOR_ILLUMINANT_COOL_WHITE_FLUORESCENT = 14,
+	SENSOR_ILLUMINANT_WHITE_FLUORESCENT = 15,
+	SENSOR_ILLUMINANT_STANDARD_A = 17,
+	SENSOR_ILLUMINANT_STANDARD_B = 18,
+	SENSOR_ILLUMINANT_STANDARD_C = 19,
+	SENSOR_ILLUMINANT_D55 = 20,
+	SENSOR_ILLUMINANT_D65 = 21,
+	SENSOR_ILLUMINANT_D75 = 22,
+	SENSOR_ILLUMINANT_D50 = 23,
+	SENSOR_ILLUMINANT_ISO_STUDIO_TUNGSTEN = 24
+};
+
+struct camera2_sensor_ctl {
+	/* unit : nano */
+	uint64_t	exposure_time;
+	/* unit : nano(It's min frame duration */
+	uint64_t	frame_duration;
+	/* unit : percent(need to change ISO value?) */
+	uint32_t	sensitivity;
+};
+
+struct camera2_sensor_dm {
+	uint64_t	exposure_time;
+	uint64_t	frame_duration;
+	uint32_t	sensitivity;
+	uint64_t	timestamp;
+};
+
+struct camera2_sensor_sm {
+	uint32_t	exposure_time_range[2];
+	uint32_t	max_frame_duration;
+	/* list of available sensitivities. */
+	uint32_t	available_sensitivities[10];
+	enum sensor_colorfilter_arrangement colorfilter_arrangement;
+	float		physical_size[2];
+	uint32_t	pixel_array_size[2];
+	uint32_t	active_array_size[4];
+	uint32_t	white_level;
+	uint32_t	black_level_pattern[4];
+	struct rational	color_transform1[9];
+	struct rational	color_transform2[9];
+	enum sensor_ref_illuminant	reference_illuminant1;
+	enum sensor_ref_illuminant	reference_illuminant2;
+	struct rational	forward_matrix1[9];
+	struct rational	forward_matrix2[9];
+	struct rational	calibration_transform1[9];
+	struct rational	calibration_transform2[9];
+	struct rational	base_gain_factor;
+	uint32_t	max_analog_sensitivity;
+	float		noise_model_coefficients[2];
+	uint32_t	orientation;
+};
+
+
+
+enum flash_mode {
+	CAM2_FLASH_MODE_OFF = 1,
+	CAM2_FLASH_MODE_SINGLE,
+	CAM2_FLASH_MODE_TORCH,
+	CAM2_FLASH_MODE_BEST
+};
+
+struct camera2_flash_ctl {
+	enum flash_mode		flash_mode;
+	uint32_t		firing_power;
+	uint64_t		firing_time;
+};
+
+struct camera2_flash_dm {
+	enum flash_mode		flash_mode;
+	/* 10 is max power */
+	uint32_t		firing_power;
+	/* unit : microseconds */
+	uint64_t		firing_time;
+	/* 1 : stable, 0 : unstable */
+	uint32_t		firing_stable;
+	/* 1 : success, 0 : fail */
+	uint32_t		decision;
+};
+
+struct camera2_flash_sm {
+	uint32_t	available;
+	uint64_t	charge_duration;
+};
+
+enum processing_mode {
+	PROCESSING_MODE_OFF = 1,
+	PROCESSING_MODE_FAST,
+	PROCESSING_MODE_HIGH_QUALITY
+};
+
+
+struct camera2_hotpixel_ctl {
+	enum processing_mode	mode;
+};
+
+struct camera2_hotpixel_dm {
+	enum processing_mode	mode;
+};
+
+struct camera2_demosaic_ctl {
+	enum processing_mode	mode;
+};
+
+struct camera2_demosaic_dm {
+	enum processing_mode	mode;
+};
+
+struct camera2_noise_reduction_ctl {
+	enum processing_mode	mode;
+	uint32_t		strength;
+};
+
+struct camera2_noise_reduction_dm {
+	enum processing_mode	mode;
+	uint32_t		strength;
+};
+
+struct camera2_shading_ctl {
+	enum processing_mode	mode;
+};
+
+struct camera2_shading_dm {
+	enum processing_mode	mode;
+};
+
+struct camera2_geometric_ctl {
+	enum processing_mode	mode;
+};
+
+struct camera2_geometric_dm {
+	enum processing_mode	mode;
+};
+
+enum color_correction_mode {
+	COLOR_CORRECTION_MODE_FAST = 1,
+	COLOR_CORRECTION_MODE_HIGH_QUALITY,
+	COLOR_CORRECTION_MODE_TRANSFORM_MATRIX,
+	COLOR_CORRECTION_MODE_EFFECT_MONO,
+	COLOR_CORRECTION_MODE_EFFECT_NEGATIVE,
+	COLOR_CORRECTION_MODE_EFFECT_SOLARIZE,
+	COLOR_CORRECTION_MODE_EFFECT_SEPIA,
+	COLOR_CORRECTION_MODE_EFFECT_POSTERIZE,
+	COLOR_CORRECTION_MODE_EFFECT_WHITEBOARD,
+	COLOR_CORRECTION_MODE_EFFECT_BLACKBOARD,
+	COLOR_CORRECTION_MODE_EFFECT_AQUA
+};
+
+
+struct camera2_color_correction_ctl {
+	enum color_correction_mode	mode;
+	float				transform[9];
+	uint32_t			hue;
+	uint32_t			saturation;
+	uint32_t			brightness;
+};
+
+struct camera2_color_correction_dm {
+	enum color_correction_mode	mode;
+	float				transform[9];
+	uint32_t			hue;
+	uint32_t			saturation;
+	uint32_t			brightness;
+};
+
+struct camera2_color_correction_sm {
+	/* assuming 10 supported modes */
+	uint8_t			available_modes[CAMERA2_MAX_AVAILABLE_MODE];
+	uint32_t		hue_range[2];
+	uint32_t		saturation_range[2];
+	uint32_t		brightness_range[2];
+};
+
+enum tonemap_mode {
+	TONEMAP_MODE_FAST = 1,
+	TONEMAP_MODE_HIGH_QUALITY,
+	TONEMAP_MODE_CONTRAST_CURVE
+};
+
+struct camera2_tonemap_ctl {
+	enum tonemap_mode		mode;
+	/* assuming maxCurvePoints = 64 */
+	float				curve_red[64];
+	float				curve_green[64];
+	float				curve_blue[64];
+};
+
+struct camera2_tonemap_dm {
+	enum tonemap_mode		mode;
+	/* assuming maxCurvePoints = 64 */
+	float				curve_red[64];
+	float				curve_green[64];
+	float				curve_blue[64];
+};
+
+struct camera2_tonemap_sm {
+	uint32_t	max_curve_points;
+};
+
+struct camera2_edge_ctl {
+	enum processing_mode	mode;
+	uint32_t		strength;
+};
+
+struct camera2_edge_dm {
+	enum processing_mode	mode;
+	uint32_t		strength;
+};
+
+enum scaler_formats {
+	SCALER_FORMAT_BAYER_RAW,
+	SCALER_FORMAT_YV12,
+	SCALER_FORMAT_NV21,
+	SCALER_FORMAT_JPEG,
+	SCALER_FORMAT_UNKNOWN
+};
+
+struct camera2_scaler_ctl {
+	uint32_t	crop_region[3];
+};
+
+struct camera2_scaler_dm {
+	uint32_t	crop_region[3];
+};
+
+struct camera2_scaler_sm {
+	enum scaler_formats available_formats[4];
+	/* assuming # of availableFormats = 4 */
+	uint32_t	available_raw_sizes;
+	uint64_t	available_raw_min_durations;
+	/* needs check */
+	uint32_t	available_processed_sizes[8];
+	uint64_t	available_processed_min_durations[8];
+	uint32_t	available_jpeg_sizes[8][2];
+	uint64_t	available_jpeg_min_durations[8];
+	uint32_t	available_max_digital_zoom[8];
+};
+
+struct camera2_jpeg_ctl {
+	uint32_t	quality;
+	uint32_t	thumbnail_size[2];
+	uint32_t	thumbnail_quality;
+	double		gps_coordinates[3];
+	uint32_t	gps_processing_method;
+	uint64_t	gps_timestamp;
+	uint32_t	orientation;
+};
+
+struct camera2_jpeg_dm {
+	uint32_t	quality;
+	uint32_t	thumbnail_size[2];
+	uint32_t	thumbnail_quality;
+	double		gps_coordinates[3];
+	uint32_t	gps_processing_method;
+	uint64_t	gps_timestamp;
+	uint32_t	orientation;
+};
+
+struct camera2_jpeg_sm {
+	uint32_t	available_thumbnail_sizes[8][2];
+	uint32_t	maxsize;
+	/* assuming supported size=8 */
+};
+
+enum face_detect_mode {
+	FACEDETECT_MODE_OFF = 1,
+	FACEDETECT_MODE_SIMPLE,
+	FACEDETECT_MODE_FULL
+};
+
+enum stats_mode {
+	STATS_MODE_OFF = 1,
+	STATS_MODE_ON
+};
+
+struct camera2_stats_ctl {
+	enum face_detect_mode	face_detect_mode;
+	enum stats_mode		histogram_mode;
+	enum stats_mode		sharpness_map_mode;
+};
+
+
+struct camera2_stats_dm {
+	enum face_detect_mode	face_detect_mode;
+	uint32_t		face_rectangles[CAMERA2_MAX_FACES][4];
+	uint8_t			face_scores[CAMERA2_MAX_FACES];
+	uint32_t		face_landmarks[CAMERA2_MAX_FACES][6];
+	uint32_t		face_ids[CAMERA2_MAX_FACES];
+	enum stats_mode		histogram_mode;
+	uint32_t		histogram[3 * 256];
+	enum stats_mode		sharpness_map_mode;
+};
+
+
+struct camera2_stats_sm {
+	uint8_t		available_face_detect_modes[CAMERA2_MAX_AVAILABLE_MODE];
+	/* assuming supported modes = 3 */
+	uint32_t	max_face_count;
+	uint32_t	histogram_bucket_count;
+	uint32_t	max_histogram_count;
+	uint32_t	sharpness_map_size[2];
+	uint32_t	max_sharpness_map_value;
+};
+
+enum aa_capture_intent {
+	AA_CAPTURE_INTENT_CUSTOM = 0,
+	AA_CAPTURE_INTENT_PREVIEW,
+	AA_CAPTURE_INTENT_STILL_CAPTURE,
+	AA_CAPTURE_INTENT_VIDEO_RECORD,
+	AA_CAPTURE_INTENT_VIDEO_SNAPSHOT,
+	AA_CAPTURE_INTENT_ZERO_SHUTTER_LAG
+};
+
+enum aa_mode {
+	AA_CONTROL_OFF = 1,
+	AA_CONTROL_AUTO,
+	AA_CONTROL_USE_SCENE_MODE
+};
+
+enum aa_scene_mode {
+	AA_SCENE_MODE_UNSUPPORTED = 1,
+	AA_SCENE_MODE_FACE_PRIORITY,
+	AA_SCENE_MODE_ACTION,
+	AA_SCENE_MODE_PORTRAIT,
+	AA_SCENE_MODE_LANDSCAPE,
+	AA_SCENE_MODE_NIGHT,
+	AA_SCENE_MODE_NIGHT_PORTRAIT,
+	AA_SCENE_MODE_THEATRE,
+	AA_SCENE_MODE_BEACH,
+	AA_SCENE_MODE_SNOW,
+	AA_SCENE_MODE_SUNSET,
+	AA_SCENE_MODE_STEADYPHOTO,
+	AA_SCENE_MODE_FIREWORKS,
+	AA_SCENE_MODE_SPORTS,
+	AA_SCENE_MODE_PARTY,
+	AA_SCENE_MODE_CANDLELIGHT,
+	AA_SCENE_MODE_BARCODE,
+	AA_SCENE_MODE_NIGHT_CAPTURE
+};
+
+enum aa_effect_mode {
+	AA_EFFECT_OFF = 1,
+	AA_EFFECT_MONO,
+	AA_EFFECT_NEGATIVE,
+	AA_EFFECT_SOLARIZE,
+	AA_EFFECT_SEPIA,
+	AA_EFFECT_POSTERIZE,
+	AA_EFFECT_WHITEBOARD,
+	AA_EFFECT_BLACKBOARD,
+	AA_EFFECT_AQUA
+};
+
+enum aa_aemode {
+	AA_AEMODE_OFF = 1,
+	AA_AEMODE_LOCKED,
+	AA_AEMODE_ON,
+	AA_AEMODE_ON_AUTO_FLASH,
+	AA_AEMODE_ON_ALWAYS_FLASH,
+	AA_AEMODE_ON_AUTO_FLASH_REDEYE
+};
+
+enum aa_ae_flashmode {
+	/* all flash control stop */
+	AA_FLASHMODE_OFF = 1,
+	/* internal 3A can control flash */
+	AA_FLASHMODE_ON,
+	/* internal 3A can do auto flash algorithm */
+	AA_FLASHMODE_AUTO,
+	/* internal 3A can fire flash by auto result */
+	AA_FLASHMODE_CAPTURE,
+	/* internal 3A can control flash forced */
+	AA_FLASHMODE_ON_ALWAYS
+
+};
+
+enum aa_ae_antibanding_mode {
+	AA_AE_ANTIBANDING_OFF = 1,
+	AA_AE_ANTIBANDING_50HZ,
+	AA_AE_ANTIBANDING_60HZ,
+	AA_AE_ANTIBANDING_AUTO
+};
+
+enum aa_awbmode {
+	AA_AWBMODE_OFF = 1,
+	AA_AWBMODE_LOCKED,
+	AA_AWBMODE_WB_AUTO,
+	AA_AWBMODE_WB_INCANDESCENT,
+	AA_AWBMODE_WB_FLUORESCENT,
+	AA_AWBMODE_WB_WARM_FLUORESCENT,
+	AA_AWBMODE_WB_DAYLIGHT,
+	AA_AWBMODE_WB_CLOUDY_DAYLIGHT,
+	AA_AWBMODE_WB_TWILIGHT,
+	AA_AWBMODE_WB_SHADE
+};
+
+enum aa_afmode {
+	AA_AFMODE_OFF = 1,
+	AA_AFMODE_AUTO,
+	AA_AFMODE_MACRO,
+	AA_AFMODE_CONTINUOUS_VIDEO,
+	AA_AFMODE_CONTINUOUS_PICTURE,
+	AA_AFMODE_EDOF
+};
+
+enum aa_afstate {
+	AA_AFSTATE_INACTIVE = 1,
+	AA_AFSTATE_PASSIVE_SCAN,
+	AA_AFSTATE_ACTIVE_SCAN,
+	AA_AFSTATE_AF_ACQUIRED_FOCUS,
+	AA_AFSTATE_AF_FAILED_FOCUS
+};
+
+enum ae_state {
+	AE_STATE_INACTIVE = 1,
+	AE_STATE_SEARCHING,
+	AE_STATE_CONVERGED,
+	AE_STATE_LOCKED,
+	AE_STATE_FLASH_REQUIRED,
+	AE_STATE_PRECAPTURE
+};
+
+enum awb_state {
+	AWB_STATE_INACTIVE = 1,
+	AWB_STATE_SEARCHING,
+	AWB_STATE_CONVERGED,
+	AWB_STATE_LOCKED
+};
+
+enum aa_isomode {
+	AA_ISOMODE_AUTO = 1,
+	AA_ISOMODE_MANUAL,
+};
+
+struct camera2_aa_ctl {
+	enum aa_capture_intent		capture_intent;
+	enum aa_mode			mode;
+	enum aa_scene_mode		scene_mode;
+	uint32_t			video_stabilization_mode;
+	enum aa_aemode			ae_mode;
+	uint32_t			ae_regions[5];
+	/* 5 per region(x1,y1,x2,y2,weight). Currently assuming 1 region. */
+	int32_t				ae_exp_compensation;
+	uint32_t			ae_target_fps_range[2];
+	enum aa_ae_antibanding_mode	ae_anti_banding_mode;
+	enum aa_ae_flashmode		ae_flash_mode;
+	enum aa_awbmode			awb_mode;
+	uint32_t			awb_regions[5];
+	/* 5 per region(x1,y1,x2,y2,weight). Currently assuming 1 region. */
+	enum aa_afmode			af_mode;
+	uint32_t			af_regions[5];
+	/* 5 per region(x1,y1,x2,y2,weight). Currently assuming 1 region. */
+	uint32_t			af_trigger;
+	enum aa_isomode			iso_mode;
+	uint32_t			iso_value;
+
+};
+
+struct camera2_aa_dm {
+	enum aa_mode				mode;
+	enum aa_effect_mode			effect_mode;
+	enum aa_scene_mode			scene_mode;
+	uint32_t				video_stabilization_mode;
+	enum aa_aemode				ae_mode;
+	uint32_t				ae_regions[5];
+	/* 5 per region(x1,y1,x2,y2,weight). Currently assuming 1 region. */
+	enum ae_state				ae_state;
+	enum aa_ae_flashmode			ae_flash_mode;
+	enum aa_awbmode				awb_mode;
+	uint32_t				awb_regions[5];
+	enum awb_state				awb_state;
+	/* 5 per region(x1,y1,x2,y2,weight). Currently assuming 1 region. */
+	enum aa_afmode				af_mode;
+	uint32_t				af_regions[5];
+	/* 5 per region(x1,y1,x2,y2,weight). Currently assuming 1 region */
+	enum aa_afstate				af_state;
+	enum aa_isomode				iso_mode;
+	uint32_t				iso_value;
+};
+
+struct camera2_aa_sm {
+	uint8_t	available_scene_modes[CAMERA2_MAX_AVAILABLE_MODE];
+	uint8_t	available_effects[CAMERA2_MAX_AVAILABLE_MODE];
+	/* Assuming # of available scene modes = 10 */
+	uint32_t max_regions;
+	uint8_t ae_available_modes[CAMERA2_MAX_AVAILABLE_MODE];
+	/* Assuming # of available ae modes = 8 */
+	struct rational	ae_compensation_step;
+	int32_t	ae_compensation_range[2];
+	uint32_t ae_available_target_fps_ranges[CAMERA2_MAX_AVAILABLE_MODE][2];
+	uint8_t	 ae_available_antibanding_modes[CAMERA2_MAX_AVAILABLE_MODE];
+	uint8_t	awb_available_modes[CAMERA2_MAX_AVAILABLE_MODE];
+	/* Assuming # of awbAvailableModes = 10 */
+	uint8_t	af_available_modes[CAMERA2_MAX_AVAILABLE_MODE];
+	/* Assuming # of afAvailableModes = 4 */
+	uint8_t	available_video_stabilization_modes[4];
+	/* Assuming # of availableVideoStabilizationModes = 4 */
+	uint32_t iso_range[2];
+};
+
+struct camera2_lens_usm {
+	/* Frame delay between sending command and applying frame data */
+	uint32_t	focus_distance_frame_delay;
+};
+
+struct camera2_sensor_usm {
+	/* Frame delay between sending command and applying frame data */
+	uint32_t	exposure_time_frame_delay;
+	uint32_t	frame_duration_frame_delay;
+	uint32_t	sensitivity_frame_delay;
+};
+
+struct camera2_flash_usm {
+	/* Frame delay between sending command and applying frame data */
+	uint32_t	flash_mode_frame_delay;
+	uint32_t	firing_power_frame_delay;
+	uint64_t	firing_time_frame_delay;
+};
+
+struct camera2_ctl {
+	struct camera2_request_ctl		request;
+	struct camera2_lens_ctl			lens;
+	struct camera2_sensor_ctl		sensor;
+	struct camera2_flash_ctl		flash;
+	struct camera2_hotpixel_ctl		hotpixel;
+	struct camera2_demosaic_ctl		demosaic;
+	struct camera2_noise_reduction_ctl	noise;
+	struct camera2_shading_ctl		shading;
+	struct camera2_geometric_ctl		geometric;
+	struct camera2_color_correction_ctl	color;
+	struct camera2_tonemap_ctl		tonemap;
+	struct camera2_edge_ctl			edge;
+	struct camera2_scaler_ctl		scaler;
+	struct camera2_jpeg_ctl			jpeg;
+	struct camera2_stats_ctl		stats;
+	struct camera2_aa_ctl			aa;
+};
+
+struct camera2_dm {
+	struct camera2_request_dm		request;
+	struct camera2_lens_dm			lens;
+	struct camera2_sensor_dm		sensor;
+	struct camera2_flash_dm			flash;
+	struct camera2_hotpixel_dm		hotpixel;
+	struct camera2_demosaic_dm		demosaic;
+	struct camera2_noise_reduction_dm	noise;
+	struct camera2_shading_dm		shading;
+	struct camera2_geometric_dm		geometric;
+	struct camera2_color_correction_dm	color;
+	struct camera2_tonemap_dm		tonemap;
+	struct camera2_edge_dm			edge;
+	struct camera2_scaler_dm		scaler;
+	struct camera2_jpeg_dm			jpeg;
+	struct camera2_stats_dm			stats;
+	struct camera2_aa_dm			aa;
+};
+
+struct camera2_sm {
+	struct camera2_lens_sm			lens;
+	struct camera2_sensor_sm		sensor;
+	struct camera2_flash_sm			flash;
+	struct camera2_color_correction_sm	color;
+	struct camera2_tonemap_sm		tonemap;
+	struct camera2_scaler_sm		scaler;
+	struct camera2_jpeg_sm			jpeg;
+	struct camera2_stats_sm			stats;
+	struct camera2_aa_sm			aa;
+
+	/* User-defined(ispfw specific) static metadata. */
+	struct camera2_lens_usm			lensud;
+	struct camera2_sensor_usm		sensor_ud;
+	struct camera2_flash_usm		flash_ud;
+};
+
+/*
+ * User-defined control for lens.
+ */
+struct camera2_lens_uctl {
+	struct camera2_lens_ctl ctl;
+
+	/* It depends by af algorithm(normally 255 or 1023) */
+	uint32_t        max_pos;
+	/* Some actuator support slew rate control. */
+	uint32_t        slew_rate;
+};
+
+/*
+ * User-defined metadata for lens.
+ */
+struct camera2_lens_udm {
+	/* It depends by af algorithm(normally 255 or 1023) */
+	uint32_t        max_pos;
+	/* Some actuator support slew rate control. */
+	uint32_t        slew_rate;
+};
+
+/*
+ * User-defined control for sensor.
+ */
+struct camera2_sensor_uctl {
+	struct camera2_sensor_ctl ctl;
+	/* Dynamic frame duration.
+	 * This feature is decided to max. value between
+	 * 'sensor.exposureTime'+alpha and 'sensor.frameDuration'.
+	 */
+	uint64_t        dynamic_frame_duration;
+};
+
+struct camera2_scaler_uctl {
+	/* Target address for next frame.
+	 * [0] invalid address, stop
+	 * [others] valid address
+	 */
+	uint32_t scc_target_address[4];
+	uint32_t scp_target_address[4];
+};
+
+struct camera2_flash_uctl {
+	struct camera2_flash_ctl ctl;
+};
+
+struct camera2_uctl {
+	/* Set sensor, lens, flash control for next frame.
+	 * This flag can be combined.
+	 * [0 bit] lens
+	 * [1 bit] sensor
+	 * [2 bit] flash
+	 */
+	uint32_t u_update_bitmap;
+
+	/* For debugging */
+	uint32_t u_frame_number;
+
+	/* isp fw specific control(user-defined) of lens. */
+	struct camera2_lens_uctl	lens_ud;
+	/* isp fw specific control(user-defined) of sensor. */
+	struct camera2_sensor_uctl	sensor_ud;
+	/* isp fw specific control(user-defined) of flash. */
+	struct camera2_flash_uctl	flash_ud;
+
+	struct camera2_scaler_uctl	scaler_ud;
+};
+
+struct camera2_udm {
+	struct camera2_lens_udm		lens;
+};
+
+struct camera2_shot {
+	/* standard area */
+	struct camera2_ctl	ctl;
+	struct camera2_dm	dm;
+	/* user defined area */
+	struct camera2_uctl	uctl;
+	struct camera2_udm	udm;
+	/* magic : 23456789 */
+	uint32_t		magicnumber;
+};
+#endif
diff --git a/drivers/media/platform/exynos5-is/fimc-is-param.h b/drivers/media/platform/exynos5-is/fimc-is-param.h
new file mode 100644
index 0000000..0beb43e
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-param.h
@@ -0,0 +1,1212 @@
+/*
+ * Samsung Exynos5 SoC series FIMC-IS driver
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd
+ * Kil-yeon Lim <kilyeon.im@samsung.com>
+ * Arun Kumar K <arun.kk@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef FIMC_IS_PARAM_H
+#define FIMC_IS_PARAM_H
+
+#define MAGIC_NUMBER 0x01020304
+
+#define PARAMETER_MAX_SIZE    128  /* in byte */
+#define PARAMETER_MAX_MEMBER  (PARAMETER_MAX_SIZE/4)
+
+enum is_param_set_bit {
+	PARAM_GLOBAL_SHOTMODE = 0,
+	PARAM_SENSOR_CONTROL,
+	PARAM_SENSOR_OTF_INPUT,
+	PARAM_SENSOR_OTF_OUTPUT,
+	PARAM_SENSOR_FRAME_RATE,
+	PARAM_SENSOR_DMA_OUTPUT,
+	PARAM_BUFFER_CONTROL,
+	PARAM_BUFFER_OTF_INPUT,
+	PARAM_BUFFER_OTF_OUTPUT,
+	PARAM_ISP_CONTROL,
+	PARAM_ISP_OTF_INPUT = 10,
+	PARAM_ISP_DMA1_INPUT,
+	PARAM_ISP_DMA2_INPUT,
+	PARAM_ISP_AA,
+	PARAM_ISP_FLASH,
+	PARAM_ISP_AWB,
+	PARAM_ISP_IMAGE_EFFECT,
+	PARAM_ISP_ISO,
+	PARAM_ISP_ADJUST,
+	PARAM_ISP_METERING,
+	PARAM_ISP_AFC = 20,
+	PARAM_ISP_OTF_OUTPUT,
+	PARAM_ISP_DMA1_OUTPUT,
+	PARAM_ISP_DMA2_OUTPUT,
+	PARAM_DRC_CONTROL,
+	PARAM_DRC_OTF_INPUT,
+	PARAM_DRC_DMA_INPUT,
+	PARAM_DRC_OTF_OUTPUT,
+	PARAM_SCALERC_CONTROL,
+	PARAM_SCALERC_OTF_INPUT,
+	PARAM_SCALERC_IMAGE_EFFECT = 30,
+	PARAM_SCALERC_INPUT_CROP,
+	PARAM_SCALERC_OUTPUT_CROP,
+	PARAM_SCALERC_OTF_OUTPUT,
+	PARAM_SCALERC_DMA_OUTPUT = 34,
+	PARAM_ODC_CONTROL,
+	PARAM_ODC_OTF_INPUT,
+	PARAM_ODC_OTF_OUTPUT,
+	PARAM_DIS_CONTROL,
+	PARAM_DIS_OTF_INPUT,
+	PARAM_DIS_OTF_OUTPUT = 40,
+	PARAM_TDNR_CONTROL,
+	PARAM_TDNR_OTF_INPUT,
+	PARAM_TDNR_1ST_FRAME,
+	PARAM_TDNR_OTF_OUTPUT,
+	PARAM_TDNR_DMA_OUTPUT,
+	PARAM_SCALERP_CONTROL,
+	PARAM_SCALERP_OTF_INPUT,
+	PARAM_SCALERP_IMAGE_EFFECT,
+	PARAM_SCALERP_INPUT_CROP,
+	PARAM_SCALERP_OUTPUT_CROP = 50,
+	PARAM_SCALERP_ROTATION,
+	PARAM_SCALERP_FLIP,
+	PARAM_SCALERP_OTF_OUTPUT,
+	PARAM_SCALERP_DMA_OUTPUT,
+	PARAM_FD_CONTROL,
+	PARAM_FD_OTF_INPUT,
+	PARAM_FD_DMA_INPUT,
+	PARAM_FD_CONFIG = 58,
+	PARAM_END,
+};
+
+/* ----------------------  Input  ----------------------------------- */
+enum control_command {
+	CONTROL_COMMAND_STOP	= 0,
+	CONTROL_COMMAND_START	= 1,
+	CONTROL_COMMAND_TEST	= 2
+};
+
+enum bypass_command {
+	CONTROL_BYPASS_DISABLE		= 0,
+	CONTROL_BYPASS_ENABLE		= 1
+};
+
+enum control_error {
+	CONTROL_ERROR_NONE		= 0
+};
+
+enum otf_input_command {
+	OTF_INPUT_COMMAND_DISABLE	= 0,
+	OTF_INPUT_COMMAND_ENABLE	= 1
+};
+
+enum otf_input_format {
+	OTF_INPUT_FORMAT_BAYER		= 0, /* 1 Channel */
+	OTF_INPUT_FORMAT_YUV444		= 1, /* 3 Channel */
+	OTF_INPUT_FORMAT_YUV422		= 2, /* 3 Channel */
+	OTF_INPUT_FORMAT_YUV420		= 3, /* 3 Channel */
+	OTF_INPUT_FORMAT_STRGEN_COLORBAR_BAYER = 10,
+	OTF_INPUT_FORMAT_BAYER_DMA	= 11,
+};
+
+enum otf_input_bitwidth {
+	OTF_INPUT_BIT_WIDTH_14BIT	= 14,
+	OTF_INPUT_BIT_WIDTH_12BIT	= 12,
+	OTF_INPUT_BIT_WIDTH_11BIT	= 11,
+	OTF_INPUT_BIT_WIDTH_10BIT	= 10,
+	OTF_INPUT_BIT_WIDTH_9BIT	= 9,
+	OTF_INPUT_BIT_WIDTH_8BIT	= 8
+};
+
+enum otf_input_order {
+	OTF_INPUT_ORDER_BAYER_GR_BG	= 0,
+	OTF_INPUT_ORDER_BAYER_RG_GB	= 1,
+	OTF_INPUT_ORDER_BAYER_BG_GR	= 2,
+	OTF_INPUT_ORDER_BAYER_GB_RG	= 3
+};
+
+enum otf_intput_error {
+	OTF_INPUT_ERROR_NONE		= 0 /* Input setting is done */
+};
+
+enum dma_input_command {
+	DMA_INPUT_COMMAND_DISABLE	= 0,
+	DMA_INPUT_COMMAND_ENABLE	= 1,
+	DMA_INPUT_COMMAND_BUF_MNGR	= 2,
+	DMA_INPUT_COMMAND_RUN_SINGLE	= 3,
+};
+
+enum dma_inut_format {
+	DMA_INPUT_FORMAT_BAYER		= 0,
+	DMA_INPUT_FORMAT_YUV444		= 1,
+	DMA_INPUT_FORMAT_YUV422		= 2,
+	DMA_INPUT_FORMAT_YUV420		= 3,
+};
+
+enum dma_input_bitwidth {
+	DMA_INPUT_BIT_WIDTH_14BIT	= 14,
+	DMA_INPUT_BIT_WIDTH_12BIT	= 12,
+	DMA_INPUT_BIT_WIDTH_11BIT	= 11,
+	DMA_INPUT_BIT_WIDTH_10BIT	= 10,
+	DMA_INPUT_BIT_WIDTH_9BIT	= 9,
+	DMA_INPUT_BIT_WIDTH_8BIT	= 8
+};
+
+enum dma_input_plane {
+	DMA_INPUT_PLANE_3	= 3,
+	DMA_INPUT_PLANE_2	= 2,
+	DMA_INPUT_PLANE_1	= 1
+};
+
+enum dma_input_order {
+	/* (for DMA_INPUT_PLANE_3) */
+	DMA_INPUT_ORDER_NONE	= 0,
+	/* (only valid at DMA_INPUT_PLANE_2) */
+	DMA_INPUT_ORDER_CBCR	= 1,
+	/* (only valid at DMA_INPUT_PLANE_2) */
+	DMA_INPUT_ORDER_CRCB	= 2,
+	/* (only valid at DMA_INPUT_PLANE_1 & DMA_INPUT_FORMAT_YUV444) */
+	DMA_INPUT_ORDER_YCBCR	= 3,
+	/* (only valid at DMA_INPUT_FORMAT_YUV422 & DMA_INPUT_PLANE_1) */
+	DMA_INPUT_ORDER_YYCBCR	= 4,
+	/* (only valid at DMA_INPUT_FORMAT_YUV422 & DMA_INPUT_PLANE_1) */
+	DMA_INPUT_ORDER_YCBYCR	= 5,
+	/* (only valid at DMA_INPUT_FORMAT_YUV422 & DMA_INPUT_PLANE_1) */
+	DMA_INPUT_ORDER_YCRYCB	= 6,
+	/* (only valid at DMA_INPUT_FORMAT_YUV422 & DMA_INPUT_PLANE_1) */
+	DMA_INPUT_ORDER_CBYCRY	= 7,
+	/* (only valid at DMA_INPUT_FORMAT_YUV422 & DMA_INPUT_PLANE_1) */
+	DMA_INPUT_ORDER_CRYCBY	= 8,
+	/* (only valid at DMA_INPUT_FORMAT_BAYER) */
+	DMA_INPUT_ORDER_GR_BG	= 9
+};
+
+enum dma_input_error {
+	DMA_INPUT_ERROR_NONE	= 0 /*  DMA input setting is done */
+};
+
+/* ----------------------  Output  ----------------------------------- */
+enum otf_output_crop {
+	OTF_OUTPUT_CROP_DISABLE		= 0,
+	OTF_OUTPUT_CROP_ENABLE		= 1
+};
+
+enum otf_output_command {
+	OTF_OUTPUT_COMMAND_DISABLE	= 0,
+	OTF_OUTPUT_COMMAND_ENABLE	= 1
+};
+
+enum orf_output_format {
+	OTF_OUTPUT_FORMAT_YUV444	= 1,
+	OTF_OUTPUT_FORMAT_YUV422	= 2,
+	OTF_OUTPUT_FORMAT_YUV420	= 3,
+	OTF_OUTPUT_FORMAT_RGB		= 4
+};
+
+enum otf_output_bitwidth {
+	OTF_OUTPUT_BIT_WIDTH_14BIT	= 14,
+	OTF_OUTPUT_BIT_WIDTH_12BIT	= 12,
+	OTF_OUTPUT_BIT_WIDTH_11BIT	= 11,
+	OTF_OUTPUT_BIT_WIDTH_10BIT	= 10,
+	OTF_OUTPUT_BIT_WIDTH_9BIT	= 9,
+	OTF_OUTPUT_BIT_WIDTH_8BIT	= 8
+};
+
+enum otf_output_order {
+	OTF_OUTPUT_ORDER_BAYER_GR_BG	= 0,
+};
+
+enum otf_output_error {
+	OTF_OUTPUT_ERROR_NONE = 0 /* Output Setting is done */
+};
+
+enum dma_output_command {
+	DMA_OUTPUT_COMMAND_DISABLE	= 0,
+	DMA_OUTPUT_COMMAND_ENABLE	= 1,
+	DMA_OUTPUT_COMMAND_BUF_MNGR	= 2,
+	DMA_OUTPUT_UPDATE_MASK_BITS	= 3
+};
+
+enum dma_output_format {
+	DMA_OUTPUT_FORMAT_BAYER		= 0,
+	DMA_OUTPUT_FORMAT_YUV444	= 1,
+	DMA_OUTPUT_FORMAT_YUV422	= 2,
+	DMA_OUTPUT_FORMAT_YUV420	= 3,
+	DMA_OUTPUT_FORMAT_RGB		= 4
+};
+
+enum dma_output_bitwidth {
+	DMA_OUTPUT_BIT_WIDTH_14BIT	= 14,
+	DMA_OUTPUT_BIT_WIDTH_12BIT	= 12,
+	DMA_OUTPUT_BIT_WIDTH_11BIT	= 11,
+	DMA_OUTPUT_BIT_WIDTH_10BIT	= 10,
+	DMA_OUTPUT_BIT_WIDTH_9BIT	= 9,
+	DMA_OUTPUT_BIT_WIDTH_8BIT	= 8
+};
+
+enum dma_output_plane {
+	DMA_OUTPUT_PLANE_3		= 3,
+	DMA_OUTPUT_PLANE_2		= 2,
+	DMA_OUTPUT_PLANE_1		= 1
+};
+
+enum dma_output_order {
+	DMA_OUTPUT_ORDER_NONE		= 0,
+	/* (for DMA_OUTPUT_PLANE_3) */
+	DMA_OUTPUT_ORDER_CBCR		= 1,
+	/* (only valid at DMA_INPUT_PLANE_2) */
+	DMA_OUTPUT_ORDER_CRCB		= 2,
+	/* (only valid at DMA_OUTPUT_PLANE_2) */
+	DMA_OUTPUT_ORDER_YYCBCR		= 3,
+	/* (only valid at DMA_OUTPUT_FORMAT_YUV422 & DMA_OUTPUT_PLANE_1) */
+	DMA_OUTPUT_ORDER_YCBYCR		= 4,
+	/* (only valid at DMA_OUTPUT_FORMAT_YUV422 & DMA_OUTPUT_PLANE_1) */
+	DMA_OUTPUT_ORDER_YCRYCB		= 5,
+	/* (only valid at DMA_OUTPUT_FORMAT_YUV422 & DMA_OUTPUT_PLANE_1) */
+	DMA_OUTPUT_ORDER_CBYCRY		= 6,
+	/* (only valid at DMA_OUTPUT_FORMAT_YUV422 & DMA_OUTPUT_PLANE_1) */
+	DMA_OUTPUT_ORDER_CRYCBY		= 7,
+	/* (only valid at DMA_OUTPUT_FORMAT_YUV422 & DMA_OUTPUT_PLANE_1) */
+	DMA_OUTPUT_ORDER_YCBCR		= 8,
+	/* (only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1) */
+	DMA_OUTPUT_ORDER_CRYCB		= 9,
+	/* (only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1) */
+	DMA_OUTPUT_ORDER_CRCBY		= 10,
+	/* (only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1) */
+	DMA_OUTPUT_ORDER_CBYCR		= 11,
+	/* (only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1) */
+	DMA_OUTPUT_ORDER_YCRCB		= 12,
+	/* (only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1) */
+	DMA_OUTPUT_ORDER_CBCRY		= 13,
+	/* (only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1) */
+	DMA_OUTPUT_ORDER_BGR		= 14,
+	/* (only valid at DMA_OUTPUT_FORMAT_RGB) */
+	DMA_OUTPUT_ORDER_GB_BG		= 15
+	/* (only valid at DMA_OUTPUT_FORMAT_BAYER) */
+};
+
+enum dma_output_notify_dma_done {
+	DMA_OUTPUT_NOTIFY_DMA_DONE_DISABLE	= 0,
+	DMA_OUTPUT_NOTIFY_DMA_DONE_ENBABLE	= 1,
+};
+
+enum dma_output_error {
+	DMA_OUTPUT_ERROR_NONE		= 0 /* DMA output setting is done */
+};
+
+/* ----------------------  Global  ----------------------------------- */
+enum global_shotmode_error {
+	GLOBAL_SHOTMODE_ERROR_NONE	= 0 /* shot-mode setting is done */
+};
+
+/* -------------------------  AA  ------------------------------------ */
+enum isp_lock_command {
+	ISP_AA_COMMAND_START	= 0,
+	ISP_AA_COMMAND_STOP	= 1
+};
+
+enum isp_lock_target {
+	ISP_AA_TARGET_AF	= 1,
+	ISP_AA_TARGET_AE	= 2,
+	ISP_AA_TARGET_AWB	= 4
+};
+
+enum isp_af_mode {
+	ISP_AF_MANUAL = 0,
+	ISP_AF_SINGLE,
+	ISP_AF_CONTINUOUS,
+	ISP_AF_REGION,
+	ISP_AF_SLEEP,
+	ISP_AF_INIT,
+	ISP_AF_SET_CENTER_WINDOW,
+	ISP_AF_SET_TOUCH_WINDOW,
+	ISP_AF_SET_FACE_WINDOW
+};
+
+enum isp_af_scene {
+	ISP_AF_SCENE_NORMAL		= 0,
+	ISP_AF_SCENE_MACRO		= 1
+};
+
+enum isp_af_touch {
+	ISP_AF_TOUCH_DISABLE = 0,
+	ISP_AF_TOUCH_ENABLE
+};
+
+enum isp_af_face {
+	ISP_AF_FACE_DISABLE = 0,
+	ISP_AF_FACE_ENABLE
+};
+
+enum isp_af_reponse {
+	ISP_AF_RESPONSE_PREVIEW = 0,
+	ISP_AF_RESPONSE_MOVIE
+};
+
+enum isp_af_sleep {
+	ISP_AF_SLEEP_OFF		= 0,
+	ISP_AF_SLEEP_ON			= 1
+};
+
+enum isp_af_continuous {
+	ISP_AF_CONTINUOUS_DISABLE	= 0,
+	ISP_AF_CONTINUOUS_ENABLE	= 1
+};
+
+enum isp_af_error {
+	ISP_AF_ERROR_NONE		= 0, /* AF mode change is done */
+	ISP_AF_EROOR_NO_LOCK_DONE	= 1  /* AF lock is done */
+};
+
+/* -------------------------  Flash  ------------------------------------- */
+enum isp_flash_command {
+	ISP_FLASH_COMMAND_DISABLE	= 0,
+	ISP_FLASH_COMMAND_MANUALON	= 1, /* (forced flash) */
+	ISP_FLASH_COMMAND_AUTO		= 2,
+	ISP_FLASH_COMMAND_TORCH		= 3,   /* 3 sec */
+	ISP_FLASH_COMMAND_FLASH_ON	= 4,
+	ISP_FLASH_COMMAND_CAPTURE	= 5,
+	ISP_FLASH_COMMAND_TRIGGER	= 6,
+	ISP_FLASH_COMMAND_CALIBRATION	= 7
+};
+
+enum isp_flash_redeye {
+	ISP_FLASH_REDEYE_DISABLE	= 0,
+	ISP_FLASH_REDEYE_ENABLE		= 1
+};
+
+enum isp_flash_error {
+	ISP_FLASH_ERROR_NONE		= 0 /* Flash setting is done */
+};
+
+/* --------------------------  AWB  ------------------------------------ */
+enum isp_awb_command {
+	ISP_AWB_COMMAND_AUTO		= 0,
+	ISP_AWB_COMMAND_ILLUMINATION	= 1,
+	ISP_AWB_COMMAND_MANUAL	= 2
+};
+
+enum isp_awb_illumination {
+	ISP_AWB_ILLUMINATION_DAYLIGHT		= 0,
+	ISP_AWB_ILLUMINATION_CLOUDY		= 1,
+	ISP_AWB_ILLUMINATION_TUNGSTEN		= 2,
+	ISP_AWB_ILLUMINATION_FLUORESCENT	= 3
+};
+
+enum isp_awb_error {
+	ISP_AWB_ERROR_NONE		= 0 /* AWB setting is done */
+};
+
+/* --------------------------  Effect  ----------------------------------- */
+enum isp_imageeffect_command {
+	ISP_IMAGE_EFFECT_DISABLE		= 0,
+	ISP_IMAGE_EFFECT_MONOCHROME		= 1,
+	ISP_IMAGE_EFFECT_NEGATIVE_MONO		= 2,
+	ISP_IMAGE_EFFECT_NEGATIVE_COLOR		= 3,
+	ISP_IMAGE_EFFECT_SEPIA			= 4,
+	ISP_IMAGE_EFFECT_AQUA			= 5,
+	ISP_IMAGE_EFFECT_EMBOSS			= 6,
+	ISP_IMAGE_EFFECT_EMBOSS_MONO		= 7,
+	ISP_IMAGE_EFFECT_SKETCH			= 8,
+	ISP_IMAGE_EFFECT_RED_YELLOW_POINT	= 9,
+	ISP_IMAGE_EFFECT_GREEN_POINT		= 10,
+	ISP_IMAGE_EFFECT_BLUE_POINT		= 11,
+	ISP_IMAGE_EFFECT_MAGENTA_POINT		= 12,
+	ISP_IMAGE_EFFECT_WARM_VINTAGE		= 13,
+	ISP_IMAGE_EFFECT_COLD_VINTAGE		= 14,
+	ISP_IMAGE_EFFECT_POSTERIZE		= 15,
+	ISP_IMAGE_EFFECT_SOLARIZE		= 16,
+	ISP_IMAGE_EFFECT_WASHED			= 17,
+	ISP_IMAGE_EFFECT_CCM			= 18,
+};
+
+enum isp_imageeffect_error {
+	ISP_IMAGE_EFFECT_ERROR_NONE	= 0 /* Image effect setting is done */
+};
+
+/* ---------------------------  ISO  ------------------------------------ */
+enum isp_iso_command {
+	ISP_ISO_COMMAND_AUTO		= 0,
+	ISP_ISO_COMMAND_MANUAL		= 1
+};
+
+enum iso_error {
+	ISP_ISO_ERROR_NONE		= 0 /* ISO setting is done */
+};
+
+/* --------------------------  Adjust  ----------------------------------- */
+enum iso_adjust_command {
+	ISP_ADJUST_COMMAND_AUTO			= 0,
+	ISP_ADJUST_COMMAND_MANUAL_CONTRAST	= (1 << 0),
+	ISP_ADJUST_COMMAND_MANUAL_SATURATION	= (1 << 1),
+	ISP_ADJUST_COMMAND_MANUAL_SHARPNESS	= (1 << 2),
+	ISP_ADJUST_COMMAND_MANUAL_EXPOSURE	= (1 << 3),
+	ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS	= (1 << 4),
+	ISP_ADJUST_COMMAND_MANUAL_HUE		= (1 << 5),
+	ISP_ADJUST_COMMAND_MANUAL_HOTPIXEL	= (1 << 6),
+	ISP_ADJUST_COMMAND_MANUAL_NOISEREDUCTION = (1 << 7),
+	ISP_ADJUST_COMMAND_MANUAL_SHADING	= (1 << 8),
+	ISP_ADJUST_COMMAND_MANUAL_GAMMA		= (1 << 9),
+	ISP_ADJUST_COMMAND_MANUAL_EDGEENHANCEMENT = (1 << 10),
+	ISP_ADJUST_COMMAND_MANUAL_SCENE		= (1 << 11),
+	ISP_ADJUST_COMMAND_MANUAL_FRAMETIME	= (1 << 12),
+	ISP_ADJUST_COMMAND_MANUAL_ALL		= 0x1FFF
+};
+
+enum isp_adjust_scene_index {
+	ISP_ADJUST_SCENE_NORMAL			= 0,
+	ISP_ADJUST_SCENE_NIGHT_PREVIEW		= 1,
+	ISP_ADJUST_SCENE_NIGHT_CAPTURE		= 2
+};
+
+
+enum isp_adjust_error {
+	ISP_ADJUST_ERROR_NONE		= 0 /* Adjust setting is done */
+};
+
+/* -------------------------  Metering  ---------------------------------- */
+enum isp_metering_command {
+	ISP_METERING_COMMAND_AVERAGE		= 0,
+	ISP_METERING_COMMAND_SPOT		= 1,
+	ISP_METERING_COMMAND_MATRIX		= 2,
+	ISP_METERING_COMMAND_CENTER		= 3,
+	ISP_METERING_COMMAND_EXPOSURE_MODE	= (1 << 8)
+};
+
+enum isp_exposure_mode {
+	ISP_EXPOSUREMODE_OFF		= 1,
+	ISP_EXPOSUREMODE_AUTO		= 2
+};
+
+enum isp_metering_error {
+	ISP_METERING_ERROR_NONE	= 0 /* Metering setting is done */
+};
+
+/* --------------------------  AFC  ----------------------------------- */
+enum isp_afc_command {
+	ISP_AFC_COMMAND_DISABLE		= 0,
+	ISP_AFC_COMMAND_AUTO		= 1,
+	ISP_AFC_COMMAND_MANUAL		= 2
+};
+
+enum isp_afc_manual {
+	ISP_AFC_MANUAL_50HZ		= 50,
+	ISP_AFC_MANUAL_60HZ		= 60
+};
+
+enum isp_afc_error {
+	ISP_AFC_ERROR_NONE	= 0 /* AFC setting is done */
+};
+
+enum isp_scene_command {
+	ISP_SCENE_NONE		= 0,
+	ISP_SCENE_PORTRAIT	= 1,
+	ISP_SCENE_LANDSCAPE     = 2,
+	ISP_SCENE_SPORTS        = 3,
+	ISP_SCENE_PARTYINDOOR	= 4,
+	ISP_SCENE_BEACHSNOW	= 5,
+	ISP_SCENE_SUNSET	= 6,
+	ISP_SCENE_DAWN		= 7,
+	ISP_SCENE_FALL		= 8,
+	ISP_SCENE_NIGHT		= 9,
+	ISP_SCENE_AGAINSTLIGHTWLIGHT	= 10,
+	ISP_SCENE_AGAINSTLIGHTWOLIGHT	= 11,
+	ISP_SCENE_FIRE			= 12,
+	ISP_SCENE_TEXT			= 13,
+	ISP_SCENE_CANDLE		= 14
+};
+
+/* --------------------------  Scaler  --------------------------------- */
+enum scaler_imageeffect_command {
+	SCALER_IMAGE_EFFECT_COMMNAD_DISABLE	= 0,
+	SCALER_IMAGE_EFFECT_COMMNAD_SEPIA_CB	= 1,
+	SCALER_IMAGE_EFFECT_COMMAND_SEPIA_CR	= 2,
+	SCALER_IMAGE_EFFECT_COMMAND_NEGATIVE	= 3,
+	SCALER_IMAGE_EFFECT_COMMAND_ARTFREEZE	= 4,
+	SCALER_IMAGE_EFFECT_COMMAND_EMBOSSING	= 5,
+	SCALER_IMAGE_EFFECT_COMMAND_SILHOUETTE	= 6
+};
+
+enum scaler_imageeffect_error {
+	SCALER_IMAGE_EFFECT_ERROR_NONE		= 0
+};
+
+enum scaler_crop_command {
+	SCALER_CROP_COMMAND_DISABLE		= 0,
+	SCALER_CROP_COMMAND_ENABLE		= 1
+};
+
+enum scaler_crop_error {
+	SCALER_CROP_ERROR_NONE			= 0 /* crop setting is done */
+};
+
+enum scaler_scaling_command {
+	SCALER_SCALING_COMMNAD_DISABLE		= 0,
+	SCALER_SCALING_COMMAND_UP		= 1,
+	SCALER_SCALING_COMMAND_DOWN		= 2
+};
+
+enum scaler_scaling_error {
+	SCALER_SCALING_ERROR_NONE		= 0
+};
+
+enum scaler_rotation_command {
+	SCALER_ROTATION_COMMAND_DISABLE		= 0,
+	SCALER_ROTATION_COMMAND_CLOCKWISE90	= 1
+};
+
+enum scaler_rotation_error {
+	SCALER_ROTATION_ERROR_NONE		= 0
+};
+
+enum scaler_flip_command {
+	SCALER_FLIP_COMMAND_NORMAL		= 0,
+	SCALER_FLIP_COMMAND_X_MIRROR		= 1,
+	SCALER_FLIP_COMMAND_Y_MIRROR		= 2,
+	SCALER_FLIP_COMMAND_XY_MIRROR		= 3 /* (180 rotation) */
+};
+
+enum scaler_flip_error {
+	SCALER_FLIP_ERROR_NONE			= 0 /* flip setting is done */
+};
+
+/* --------------------------  3DNR  ----------------------------------- */
+enum tdnr_1st_frame_command {
+	TDNR_1ST_FRAME_COMMAND_NOPROCESSING	= 0,
+	TDNR_1ST_FRAME_COMMAND_2DNR		= 1
+};
+
+enum tdnr_1st_frame_error {
+	TDNR_1ST_FRAME_ERROR_NONE		= 0
+		/*1st frame setting is done*/
+};
+
+/* ----------------------------  FD  ------------------------------------- */
+enum fd_config_command {
+	FD_CONFIG_COMMAND_MAXIMUM_NUMBER	= 0x1,
+	FD_CONFIG_COMMAND_ROLL_ANGLE		= 0x2,
+	FD_CONFIG_COMMAND_YAW_ANGLE		= 0x4,
+	FD_CONFIG_COMMAND_SMILE_MODE		= 0x8,
+	FD_CONFIG_COMMAND_BLINK_MODE		= 0x10,
+	FD_CONFIG_COMMAND_EYES_DETECT		= 0x20,
+	FD_CONFIG_COMMAND_MOUTH_DETECT		= 0x40,
+	FD_CONFIG_COMMAND_ORIENTATION		= 0x80,
+	FD_CONFIG_COMMAND_ORIENTATION_VALUE	= 0x100
+};
+
+enum fd_config_roll_angle {
+	FD_CONFIG_ROLL_ANGLE_BASIC		= 0,
+	FD_CONFIG_ROLL_ANGLE_PRECISE_BASIC	= 1,
+	FD_CONFIG_ROLL_ANGLE_SIDES		= 2,
+	FD_CONFIG_ROLL_ANGLE_PRECISE_SIDES	= 3,
+	FD_CONFIG_ROLL_ANGLE_FULL		= 4,
+	FD_CONFIG_ROLL_ANGLE_PRECISE_FULL	= 5,
+};
+
+enum fd_config_yaw_angle {
+	FD_CONFIG_YAW_ANGLE_0			= 0,
+	FD_CONFIG_YAW_ANGLE_45			= 1,
+	FD_CONFIG_YAW_ANGLE_90			= 2,
+	FD_CONFIG_YAW_ANGLE_45_90		= 3,
+};
+
+enum fd_config_smile_mode {
+	FD_CONFIG_SMILE_MODE_DISABLE		= 0,
+	FD_CONFIG_SMILE_MODE_ENABLE		= 1
+};
+
+enum fd_config_blink_mode {
+	FD_CONFIG_BLINK_MODE_DISABLE		= 0,
+	FD_CONFIG_BLINK_MODE_ENABLE		= 1
+};
+
+enum fd_config_eye_result {
+	FD_CONFIG_EYES_DETECT_DISABLE		= 0,
+	FD_CONFIG_EYES_DETECT_ENABLE		= 1
+};
+
+enum fd_config_mouth_result {
+	FD_CONFIG_MOUTH_DETECT_DISABLE		= 0,
+	FD_CONFIG_MOUTH_DETECT_ENABLE		= 1
+};
+
+enum fd_config_orientation {
+	FD_CONFIG_ORIENTATION_DISABLE		= 0,
+	FD_CONFIG_ORIENTATION_ENABLE		= 1
+};
+
+struct param_control {
+	u32	cmd;
+	u32	bypass;
+	u32	buffer_address;
+	u32	buffer_number;
+	/* 0: continuous, 1: single */
+	u32	run_mode;
+	u32	reserved[PARAMETER_MAX_MEMBER-6];
+	u32	err;
+};
+
+struct param_otf_input {
+	u32	cmd;
+	u32	width;
+	u32	height;
+	u32	format;
+	u32	bitwidth;
+	u32	order;
+	u32	crop_offset_x;
+	u32	crop_offset_y;
+	u32	crop_width;
+	u32	crop_height;
+	u32	frametime_min;
+	u32	frametime_max;
+	u32	reserved[PARAMETER_MAX_MEMBER-13];
+	u32	err;
+};
+
+struct param_dma_input {
+	u32	cmd;
+	u32	width;
+	u32	height;
+	u32	format;
+	u32	bitwidth;
+	u32	plane;
+	u32	order;
+	u32	buffer_number;
+	u32	buffer_address;
+	u32	bayer_crop_offset_x;
+	u32	bayer_crop_offset_y;
+	u32	bayer_crop_width;
+	u32	bayer_crop_height;
+	u32	dma_crop_offset_x;
+	u32	dma_crop_offset_y;
+	u32	dma_crop_width;
+	u32	dma_crop_height;
+	u32	user_min_frametime;
+	u32	user_max_frametime;
+	u32	wide_frame_gap;
+	u32	frame_gap;
+	u32	line_gap;
+	u32	reserved[PARAMETER_MAX_MEMBER-23];
+	u32	err;
+};
+
+struct param_otf_output {
+	u32	cmd;
+	u32	width;
+	u32	height;
+	u32	format;
+	u32	bitwidth;
+	u32	order;
+	u32	crop_offset_x;
+	u32	crop_offset_y;
+	u32	reserved[PARAMETER_MAX_MEMBER-9];
+	u32	err;
+};
+
+struct param_dma_output {
+	u32	cmd;
+	u32	width;
+	u32	height;
+	u32	format;
+	u32	bitwidth;
+	u32	plane;
+	u32	order;
+	u32	buffer_number;
+	u32	buffer_address;
+	u32	notify_dma_done;
+	u32	dma_out_mask;
+	u32	reserved[PARAMETER_MAX_MEMBER-12];
+	u32	err;
+};
+
+struct param_global_shotmode {
+	u32	cmd;
+	u32	skip_frames;
+	u32	reserved[PARAMETER_MAX_MEMBER-3];
+	u32	err;
+};
+
+struct param_sensor_framerate {
+	u32	frame_rate;
+	u32	reserved[PARAMETER_MAX_MEMBER-2];
+	u32	err;
+};
+
+struct param_isp_aa {
+	u32	cmd;
+	u32	target;
+	u32	mode;
+	u32	scene;
+	u32	af_touch;
+	u32	af_face;
+	u32	af_response;
+	u32	sleep;
+	u32	touch_x;
+	u32	touch_y;
+	u32	manual_af_setting;
+	/*0: Legacy, 1: Camera 2.0*/
+	u32	cam_api2p0;
+	/* For android.control.afRegions in Camera 2.0,
+	Resolution based on YUV output size*/
+	u32	af_region_left;
+	/* For android.control.afRegions in Camera 2.0,
+	Resolution based on YUV output size*/
+	u32	af_region_top;
+	/* For android.control.afRegions in Camera 2.0,
+	Resolution based on YUV output size*/
+	u32	af_region_right;
+	/* For android.control.afRegions in Camera 2.0,
+	Resolution based on YUV output size*/
+	u32	af_region_bottom;
+	u32	reserved[PARAMETER_MAX_MEMBER-17];
+	u32	err;
+};
+
+struct param_isp_flash {
+	u32	cmd;
+	u32	redeye;
+	u32	flash_intensity;
+	u32	reserved[PARAMETER_MAX_MEMBER-4];
+	u32	err;
+};
+
+struct param_isp_awb {
+	u32	cmd;
+	u32	illumination;
+	u32	reserved[PARAMETER_MAX_MEMBER-3];
+	u32	err;
+};
+
+struct param_isp_imageeffect {
+	u32	cmd;
+	u32	reserved[PARAMETER_MAX_MEMBER-2];
+	u32	err;
+};
+
+struct param_isp_iso {
+	u32	cmd;
+	u32	value;
+	u32	reserved[PARAMETER_MAX_MEMBER-3];
+	u32	err;
+};
+
+struct param_isp_adjust {
+	u32	cmd;
+	s32	contrast;
+	s32	saturation;
+	s32	sharpness;
+	s32	exposure;
+	s32	brightness;
+	s32	hue;
+	/* 0 or 1 */
+	u32	hotpixel_enable;
+	/* -127 ~ 127 */
+	s32	noise_reduction_strength;
+	/* 0 or 1 */
+	u32	shading_correction_enable;
+	/* 0 or 1 */
+	u32	user_gamma_enable;
+	/* -127 ~ 127 */
+	s32	edge_enhancement_strength;
+	/* ISP_AdjustSceneIndexEnum */
+	u32	user_scene_mode;
+	u32	min_frametime;
+	u32	max_frametime;
+	u32	reserved[PARAMETER_MAX_MEMBER-16];
+	u32	err;
+};
+
+struct param_isp_metering {
+	u32	cmd;
+	u32	win_pos_x;
+	u32	win_pos_y;
+	u32	win_width;
+	u32	win_height;
+	u32	exposure_mode;
+	/* 0: Legacy, 1: Camera 2.0 */
+	u32	cam_api2p0;
+	u32	reserved[PARAMETER_MAX_MEMBER-8];
+	u32	err;
+};
+
+struct param_isp_afc {
+	u32	cmd;
+	u32	manual;
+	u32	reserved[PARAMETER_MAX_MEMBER-3];
+	u32	err;
+};
+
+struct param_scaler_imageeffect {
+	u32	cmd;
+	u32	reserved[PARAMETER_MAX_MEMBER-2];
+	u32	err;
+};
+
+struct param_scaler_input_crop {
+	u32  cmd;
+	u32  pos_x;
+	u32  pos_y;
+	u32  crop_width;
+	u32  crop_height;
+	u32  in_width;
+	u32  in_height;
+	u32  out_width;
+	u32  out_height;
+	u32  reserved[PARAMETER_MAX_MEMBER-10];
+	u32  err;
+};
+
+struct param_scaler_output_crop {
+	u32  cmd;
+	u32  pos_x;
+	u32  pos_y;
+	u32  crop_width;
+	u32  crop_height;
+	u32  format;
+	u32  reserved[PARAMETER_MAX_MEMBER-7];
+	u32  err;
+};
+
+struct param_scaler_rotation {
+	u32	cmd;
+	u32	reserved[PARAMETER_MAX_MEMBER-2];
+	u32	err;
+};
+
+struct param_scaler_flip {
+	u32	cmd;
+	u32	reserved[PARAMETER_MAX_MEMBER-2];
+	u32	err;
+};
+
+struct param_3dnr_1stframe {
+	u32	cmd;
+	u32	reserved[PARAMETER_MAX_MEMBER-2];
+	u32	err;
+};
+
+struct param_fd_config {
+	u32	cmd;
+	u32	max_number;
+	u32	roll_angle;
+	u32	yaw_angle;
+	s32	smile_mode;
+	s32	blink_mode;
+	u32	eye_detect;
+	u32	mouth_detect;
+	u32	orientation;
+	u32	orientation_value;
+	u32	reserved[PARAMETER_MAX_MEMBER-11];
+	u32	err;
+};
+
+struct global_param {
+	struct param_global_shotmode	shotmode; /* 0 */
+};
+
+/* To be added */
+struct sensor_param {
+	struct param_control		control;
+	struct param_otf_input		otf_input;
+	struct param_otf_output		otf_output;
+	struct param_sensor_framerate	frame_rate;
+	struct param_dma_output		dma_output;
+};
+
+struct buffer_param {
+	struct param_control	control;
+	struct param_otf_input	otf_input;
+	struct param_otf_output	otf_output;
+};
+
+struct isp_param {
+	struct param_control		control;
+	struct param_otf_input		otf_input;
+	struct param_dma_input		dma1_input;
+	struct param_dma_input		dma2_input;
+	struct param_isp_aa		aa;
+	struct param_isp_flash		flash;
+	struct param_isp_awb		awb;
+	struct param_isp_imageeffect	effect;
+	struct param_isp_iso		iso;
+	struct param_isp_adjust		adjust;
+	struct param_isp_metering	metering;
+	struct param_isp_afc		afc;
+	struct param_otf_output		otf_output;
+	struct param_dma_output		dma1_output;
+	struct param_dma_output		dma2_output;
+};
+
+struct drc_param {
+	struct param_control		control;
+	struct param_otf_input		otf_input;
+	struct param_dma_input		dma_input;
+	struct param_otf_output		otf_output;
+};
+
+struct scalerc_param {
+	struct param_control		control;
+	struct param_otf_input		otf_input;
+	struct param_scaler_imageeffect	effect;
+	struct param_scaler_input_crop	input_crop;
+	struct param_scaler_output_crop	 output_crop;
+	struct param_otf_output		otf_output;
+	struct param_dma_output		dma_output;
+};
+
+struct odc_param {
+	struct param_control		control;
+	struct param_otf_input		otf_input;
+	struct param_otf_output		otf_output;
+};
+
+struct dis_param {
+	struct param_control		control;
+	struct param_otf_input		otf_input;
+	struct param_otf_output		otf_output;
+};
+
+struct tdnr_param {
+	struct param_control		control;
+	struct param_otf_input		otf_input;
+	struct param_3dnr_1stframe	frame;
+	struct param_otf_output		otf_output;
+	struct param_dma_output		dma_output;
+};
+
+struct scalerp_param {
+	struct param_control			control;
+	struct param_otf_input			otf_input;
+	struct param_scaler_imageeffect		effect;
+	struct param_scaler_input_crop		input_crop;
+	struct param_scaler_output_crop		output_crop;
+	struct param_scaler_rotation		rotation;
+	struct param_scaler_flip		flip;
+	struct param_otf_output			otf_output;
+	struct param_dma_output			dma_output;
+};
+
+struct fd_param {
+	struct param_control			control;
+	struct param_otf_input			otf_input;
+	struct param_dma_input			dma_input;
+	struct param_fd_config			config;
+};
+
+struct is_param_region {
+	struct global_param	global;
+	struct sensor_param	sensor;
+	struct buffer_param	buf;
+	struct isp_param	isp;
+	struct drc_param	drc;
+	struct scalerc_param	scalerc;
+	struct odc_param	odc;
+	struct dis_param	dis;
+	struct tdnr_param	tdnr;
+	struct scalerp_param	scalerp;
+	struct fd_param		fd;
+};
+
+#define	NUMBER_OF_GAMMA_CURVE_POINTS	32
+
+struct is_sensor_tune {
+	u32 exposure;
+	u32 analog_gain;
+	u32 frame_rate;
+	u32 actuator_pos;
+};
+
+struct is_tune_gammacurve {
+	u32 num_pts_x[NUMBER_OF_GAMMA_CURVE_POINTS];
+	u32 num_pts_y_r[NUMBER_OF_GAMMA_CURVE_POINTS];
+	u32 num_pts_y_g[NUMBER_OF_GAMMA_CURVE_POINTS];
+	u32 num_pts_y_b[NUMBER_OF_GAMMA_CURVE_POINTS];
+};
+
+struct is_isp_tune {
+	/* Brightness level : range 0~100, default : 7 */
+	u32 brightness_level;
+	/* Contrast level : range -127~127, default : 0 */
+	s32 contrast_level;
+	/* Saturation level : range -127~127, default : 0 */
+	s32 saturation_level;
+	s32 gamma_level;
+	struct is_tune_gammacurve gamma_curve[4];
+	/* Hue : range -127~127, default : 0 */
+	s32 hue;
+	/* Sharpness blur : range -127~127, default : 0 */
+	s32 sharpness_blur;
+	/* Despeckle : range -127~127, default : 0 */
+	s32 despeckle;
+	/* Edge color supression : range -127~127, default : 0 */
+	s32 edge_color_supression;
+	/* Noise reduction : range -127~127, default : 0 */
+	s32 noise_reduction;
+	/* (32*4 + 9)*4 = 548 bytes */
+};
+
+struct is_tune_region {
+	struct is_sensor_tune sensor_tune;
+	struct is_isp_tune isp_tune;
+};
+
+struct rational_t {
+	u32 num;
+	u32 den;
+};
+
+struct srational_t {
+	s32 num;
+	s32 den;
+};
+
+#define FLASH_FIRED_SHIFT	0
+#define FLASH_NOT_FIRED		0
+#define FLASH_FIRED		1
+
+#define FLASH_STROBE_SHIFT				1
+#define FLASH_STROBE_NO_DETECTION			0
+#define FLASH_STROBE_RESERVED				1
+#define FLASH_STROBE_RETURN_LIGHT_NOT_DETECTED		2
+#define FLASH_STROBE_RETURN_LIGHT_DETECTED		3
+
+#define FLASH_MODE_SHIFT			3
+#define FLASH_MODE_UNKNOWN			0
+#define FLASH_MODE_COMPULSORY_FLASH_FIRING	1
+#define FLASH_MODE_COMPULSORY_FLASH_SUPPRESSION	2
+#define FLASH_MODE_AUTO_MODE			3
+
+#define FLASH_FUNCTION_SHIFT		5
+#define FLASH_FUNCTION_PRESENT		0
+#define FLASH_FUNCTION_NONE		1
+
+#define FLASH_RED_EYE_SHIFT		6
+#define FLASH_RED_EYE_DISABLED		0
+#define FLASH_RED_EYE_SUPPORTED		1
+
+struct exif_attribute {
+	struct rational_t exposure_time;
+	struct srational_t shutter_speed;
+	u32 iso_speed_rating;
+	u32 flash;
+	struct srational_t brightness;
+};
+
+struct is_frame_header {
+	u32 valid;
+	u32 bad_mark;
+	u32 captured;
+	u32 frame_number;
+	struct exif_attribute	exif;
+};
+
+struct is_fd_rect {
+	u32 offset_x;
+	u32 offset_y;
+	u32 width;
+	u32 height;
+};
+
+struct is_face_marker {
+	u32	frame_number;
+	struct is_fd_rect face;
+	struct is_fd_rect left_eye;
+	struct is_fd_rect right_eye;
+	struct is_fd_rect mouth;
+	u32	roll_angle;
+	u32	yaw_angle;
+	u32	confidence;
+	u32	stracked;
+	u32	tracked_faceid;
+	u32	smile_level;
+	u32	blink_level;
+};
+
+#define MAX_FRAME_COUNT		8
+#define MAX_FRAME_COUNT_PREVIEW	4
+#define MAX_FRAME_COUNT_CAPTURE	1
+#define MAX_FACE_COUNT		16
+
+#define MAX_SHARED_COUNT	500
+
+struct is_region {
+	struct is_param_region	parameter;
+	struct is_tune_region	tune;
+	struct is_frame_header	header[MAX_FRAME_COUNT];
+	struct is_face_marker	face[MAX_FACE_COUNT];
+	u32			shared[MAX_SHARED_COUNT];
+};
+
+struct is_time_measure_us {
+	u32  min_time_us;
+	u32  max_time_us;
+	u32  avrg_time_us;
+	u32  current_time_us;
+};
+
+struct is_debug_frame_descriptor {
+	u32	sensor_frame_time;
+	u32	sensor_exposure_time;
+	u32	sensor_analog_gain;
+	u32	req_lei;
+};
+
+#define MAX_FRAMEDESCRIPTOR_CONTEXT_NUM	(30 * 20)	/* 600 frame */
+#define MAX_VERSION_DISPLAY_BUF		(32)
+
+struct is_share_region {
+	u32	frame_time;
+	u32	exposure_time;
+	u32	analog_gain;
+
+	u32	r_gain;
+	u32	g_gain;
+	u32	b_gain;
+
+	u32	af_position;
+	u32	af_status;
+	u32	af_scene_type;
+
+	u32	frame_descp_onoff_control;
+	u32	frame_descp_update_done;
+	u32	frame_descp_idx;
+	u32	frame_descp_max_idx;
+
+	struct is_debug_frame_descriptor
+		dbg_frame_descp_ctx[MAX_FRAMEDESCRIPTOR_CONTEXT_NUM];
+
+	u32	chip_id;
+	u32	chip_rev_no;
+	u8	ispfw_version_no[MAX_VERSION_DISPLAY_BUF];
+	u8	ispfw_version_date[MAX_VERSION_DISPLAY_BUF];
+	u8	sirc_sdk_version_no[MAX_VERSION_DISPLAY_BUF];
+	u8	sirc_sdk_revsion_no[MAX_VERSION_DISPLAY_BUF];
+	u8	sirc_sdk_version_date[MAX_VERSION_DISPLAY_BUF];
+
+	/*measure timing*/
+	struct is_time_measure_us	isp_sdk_time;
+};
+
+struct is_debug_control {
+	u32 write_point;	/* 0~500KB boundary*/
+	u32 assert_flag;	/* 0:Not Invoked, 1:Invoked*/
+	u32 pabort_flag;	/* 0:Not Invoked, 1:Invoked*/
+	u32 dabort_flag;	/* 0:Not Invoked, 1:Invoked*/
+	u32 pd_ready_flag;	/* 0:Normal, 1:EnterIdle(Ready to power down)*/
+	u32 isp_frame_err;	/* Frame Error Counters */
+	u32 drc_frame_err;
+	u32 scc_frame_err;
+	u32 odc_frame_err;
+	u32 dis_frame_err;
+	u32 tdnr_frame_err;
+	u32 scp_frame_err;
+	u32 fd_frame_err;
+	u32 isp_frame_drop;	/* Frame Drop Counters*/
+	u32 drc_frame_drop;
+	u32 dis_frame_drop;
+	u32 uifdframedrop;
+};
+
+#endif
-- 
1.7.9.5

[RFC v3 05/13] [media] exynos5-fimc-is: Add register definition and context header

[Arun Kumar K]

This patch adds the register definition file for the fimc-is driver
and also the header file containing the main context for the driver.

Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Kilyeon Im <kilyeon.im@samsung.com>
---
 drivers/media/platform/exynos5-is/fimc-is-regs.h |  105 +++++++++++++++
 drivers/media/platform/exynos5-is/fimc-is.h      |  153 ++++++++++++++++++++++
 2 files changed, 258 insertions(+)
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-regs.h
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is.h

diff --git a/drivers/media/platform/exynos5-is/fimc-is-regs.h b/drivers/media/platform/exynos5-is/fimc-is-regs.h
new file mode 100644
index 0000000..06aa466
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-regs.h
@@ -0,0 +1,105 @@
+/*
+ * Samsung Exynos5 SoC series FIMC-IS driver
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd
+ * Arun Kumar K <arun.kk@samsung.com>
+ * Kil-yeon Lim <kilyeon.im@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef FIMC_IS_REGS_H
+#define FIMC_IS_REGS_H
+
+/* WDT_ISP register */
+#define WDT			0x00170000
+/* MCUCTL register */
+#define MCUCTL			0x00180000
+/* MCU Controller Register */
+#define MCUCTLR				(MCUCTL+0x00)
+#define MCUCTLR_AXI_ISPX_AWCACHE(x)	((x) << 16)
+#define MCUCTLR_AXI_ISPX_ARCACHE(x)	((x) << 12)
+#define MCUCTLR_MSWRST			(1 << 0)
+/* Boot Base OFfset Address Register */
+#define BBOAR				(MCUCTL+0x04)
+#define BBOAR_BBOA(x)			((x) << 0)
+
+/* Interrupt Generation Register 0 from Host CPU to VIC */
+#define INTGR0				(MCUCTL+0x08)
+#define INTGR0_INTGC(n)			(1 << ((n) + 16))
+#define INTGR0_INTGD(n)			(1 << (n))
+
+/* Interrupt Clear Register 0 from Host CPU to VIC */
+#define INTCR0				(MCUCTL+0x0c)
+#define INTCR0_INTCC(n)			(1 << ((n) + 16))
+#define INTCR0_INTCD(n)			(1 << (n))
+
+/* Interrupt Mask Register 0 from Host CPU to VIC */
+#define INTMR0				(MCUCTL+0x10)
+#define INTMR0_INTMC(n)			(1 << ((n) + 16))
+#define INTMR0_INTMD(n)			(1 << (n))
+
+/* Interrupt Status Register 0 from Host CPU to VIC */
+#define INTSR0				(MCUCTL+0x14)
+#define INTSR0_GET_INTSD(n, x)		(((x) >> (n)) & 0x1)
+#define INTSR0_GET_INTSC(n, x)		(((x) >> ((n) + 16)) & 0x1)
+
+/* Interrupt Mask Status Register 0 from Host CPU to VIC */
+#define INTMSR0				(MCUCTL+0x18)
+#define INTMSR0_GET_INTMSD(n, x)	(((x) >> (n)) & 0x1)
+#define INTMSR0_GET_INTMSC(n, x)	(((x) >> ((n) + 16)) & 0x1)
+
+/* Interrupt Generation Register 1 from ISP CPU to Host IC */
+#define INTGR1				(MCUCTL+0x1c)
+#define INTGR1_INTGC(n)			(1 << (n))
+
+/* Interrupt Clear Register 1 from ISP CPU to Host IC */
+#define INTCR1				(MCUCTL+0x20)
+#define INTCR1_INTCC(n)			(1 << (n))
+
+/* Interrupt Mask Register 1 from ISP CPU to Host IC */
+#define INTMR1				(MCUCTL+0x24)
+#define INTMR1_INTMC(n)			(1 << (n))
+
+/* Interrupt Status Register 1 from ISP CPU to Host IC */
+#define INTSR1				(MCUCTL+0x28)
+/* Interrupt Mask Status Register 1 from ISP CPU to Host IC */
+#define INTMSR1				(MCUCTL+0x2c)
+/* Interrupt Clear Register 2 from ISP BLK's interrupts to Host IC */
+#define INTCR2				(MCUCTL+0x30)
+#define INTCR2_INTCC(n)			(1 << (n))
+
+/* Interrupt Mask Register 2 from ISP BLK's interrupts to Host IC */
+#define INTMR2				(MCUCTL+0x34)
+#define INTMR2_INTMCIS(n)		(1 << (n))
+
+/* Interrupt Status Register 2 from ISP BLK's interrupts to Host IC */
+#define INTSR2				(MCUCTL+0x38)
+/* Interrupt Mask Status Register 2 from ISP BLK's interrupts to Host IC */
+#define INTMSR2				(MCUCTL+0x3c)
+/* General Purpose Output Control Register (0~17) */
+#define GPOCTLR				(MCUCTL+0x40)
+#define GPOCTLR_GPOG(n, x)		((x) << (n))
+
+/* General Purpose Pad Output Enable Register (0~17) */
+#define GPOENCTLR			(MCUCTL+0x44)
+#define GPOENCTLR_GPOEN0(n, x)		((x) << (n))
+
+/* General Purpose Input Control Register (0~17) */
+#define GPICTLR				(MCUCTL+0x48)
+
+/* IS Shared Registers between ISP CPU and HOST CPU */
+#define ISSR(n)			(MCUCTL + 0x80 + (n))
+
+/* PMU for FIMC-IS*/
+#define PMUREG_CMU_RESET_ISP_SYS_PWR_REG	0x1584
+#define PMUREG_ISP_ARM_CONFIGURATION		0x2280
+#define PMUREG_ISP_ARM_STATUS			0x2284
+#define PMUREG_ISP_ARM_OPTION			0x2288
+#define PMUREG_ISP_LOW_POWER_OFF		0x0004
+#define PMUREG_ISP_CONFIGURATION		0x4020
+#define PMUREG_ISP_STATUS			0x4024
+
+#endif
diff --git a/drivers/media/platform/exynos5-is/fimc-is.h b/drivers/media/platform/exynos5-is/fimc-is.h
new file mode 100644
index 0000000..a7379dc
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is.h
@@ -0,0 +1,153 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ *  Arun Kumar K <arun.kk@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef FIMC_IS_H_
+#define FIMC_IS_H_
+
+#include "fimc-is-err.h"
+#include "fimc-is-core.h"
+#include "fimc-is-param.h"
+#include "fimc-is-pipeline.h"
+#include "fimc-is-interface.h"
+
+#define fimc_interface_to_is(p) container_of(p, struct fimc_is, interface)
+#define fimc_sensor_to_is(p) container_of(p, struct fimc_is, sensor)
+
+/* Macros used by media dev to get the subdev and vfd */
+/* is --> driver data from pdev
+ * pid --> pipeline index */
+#define fimc_is_isp_get_sd(is, pid) (&is->pipeline[pid].isp.subdev)
+#define fimc_is_isp_get_vfd(is, pid) (&is->pipeline[pid].isp.vfd)
+#define fimc_is_scc_get_sd(is, pid) \
+	(&is->pipeline[pid].scaler[SCALER_SCC].subdev)
+#define fimc_is_scc_get_vfd(is, pid) \
+	(&is->pipeline[pid].scaler[SCALER_SCC].vfd)
+#define fimc_is_scp_get_sd(is, pid) \
+	(&is->pipeline[pid].scaler[SCALER_SCP].subdev)
+#define fimc_is_scp_get_vfd(is, pid) \
+	(&is->pipeline[pid].scaler[SCALER_SCP].vfd)
+/* is --> driver data from pdev
+ * sid --> sensor index */
+#define fimc_is_sensor_get_sd(is, sid) (&is->sensor[sid].subdev)
+
+
+/**
+ * struct fimc_is - fimc lite structure
+ * @pdev: pointer to FIMC-IS platform device
+ * @pdata: platform data for FIMC-IS
+ * @alloc_ctx: videobuf2 memory allocator context
+ * @clk: FIMC-IS clocks
+ * @pmu_regs: PMU reg base address
+ * @minfo: internal memory organization info
+ * @sensor: FIMC-IS sensor context
+ * @pipeline: hardware pipeline context
+ * @interface: hardware interface context
+ */
+struct fimc_is {
+	struct platform_device		*pdev;
+
+	struct vb2_alloc_ctx		*alloc_ctx;
+	struct clk			*clock[IS_CLK_MAX_NUM];
+	void __iomem			*pmu_regs;
+
+	struct fimc_is_meminfo		minfo;
+
+	int				num_instance;
+	struct fimc_is_sensor		sensor[FIMC_IS_NUM_SENSORS];
+	struct fimc_is_pipeline		pipeline[FIMC_IS_NUM_PIPELINES];
+	struct fimc_is_interface	interface;
+};
+
+/* Queue operations for ISP */
+static inline void fimc_is_isp_wait_queue_add(struct fimc_is_isp *isp,
+		struct fimc_is_buf *buf)
+{
+	list_add_tail(&buf->list, &isp->wait_queue);
+	isp->wait_queue_cnt++;
+}
+
+static inline struct fimc_is_buf *fimc_is_isp_wait_queue_get(
+		struct fimc_is_isp *isp)
+{
+	struct fimc_is_buf *buf;
+	buf = list_entry(isp->wait_queue.next,
+			struct fimc_is_buf, list);
+	list_del(&buf->list);
+	isp->wait_queue_cnt--;
+	return buf;
+}
+
+static inline void fimc_is_isp_run_queue_add(struct fimc_is_isp *isp,
+		struct fimc_is_buf *buf)
+{
+	list_add_tail(&buf->list, &isp->run_queue);
+	isp->run_queue_cnt++;
+}
+
+static inline struct fimc_is_buf *fimc_is_isp_run_queue_get(
+		struct fimc_is_isp *isp)
+{
+	struct fimc_is_buf *buf;
+	buf = list_entry(isp->run_queue.next,
+			struct fimc_is_buf, list);
+	list_del(&buf->list);
+	isp->run_queue_cnt--;
+	return buf;
+}
+
+/* Queue operations for SCALER */
+static inline void fimc_is_scaler_wait_queue_add(struct fimc_is_scaler *scp,
+		struct fimc_is_buf *buf)
+{
+	list_add_tail(&buf->list, &scp->wait_queue);
+	scp->wait_queue_cnt++;
+}
+
+static inline struct fimc_is_buf *fimc_is_scaler_wait_queue_get(
+		struct fimc_is_scaler *scp)
+{
+	struct fimc_is_buf *buf;
+	buf = list_entry(scp->wait_queue.next,
+			struct fimc_is_buf, list);
+	list_del(&buf->list);
+	scp->wait_queue_cnt--;
+	return buf;
+}
+
+static inline void fimc_is_scaler_run_queue_add(struct fimc_is_scaler *scp,
+		struct fimc_is_buf *buf)
+{
+	list_add_tail(&buf->list, &scp->run_queue);
+	scp->run_queue_cnt++;
+}
+
+static inline struct fimc_is_buf *fimc_is_scaler_run_queue_get(
+		struct fimc_is_scaler *scp)
+{
+	struct fimc_is_buf *buf;
+	buf = list_entry(scp->run_queue.next,
+			struct fimc_is_buf, list);
+	list_del(&buf->list);
+	scp->run_queue_cnt--;
+	return buf;
+}
+
+static inline void pmu_is_write(u32 v, struct fimc_is *is, unsigned int offset)
+{
+	writel(v, is->pmu_regs + offset);
+}
+
+static inline u32 pmu_is_read(struct fimc_is *is, unsigned int offset)
+{
+	return readl(is->pmu_regs + offset);
+}
+
+#endif
-- 
1.7.9.5

[RFC v3 06/13] [media] exynos5-fimc-is: Add isp subdev

[Arun Kumar K]

fimc-is driver takes video data input from the ISP video node
which is added in this patch. This node accepts Bayer input
buffers which is given from the IS sensors.

Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Kilyeon Im <kilyeon.im@samsung.com>
---
 drivers/media/platform/exynos5-is/fimc-is-isp.c |  509 +++++++++++++++++++++++
 drivers/media/platform/exynos5-is/fimc-is-isp.h |   93 +++++
 2 files changed, 602 insertions(+)
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-isp.c
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-isp.h

diff --git a/drivers/media/platform/exynos5-is/fimc-is-isp.c b/drivers/media/platform/exynos5-is/fimc-is-isp.c
new file mode 100644
index 0000000..e97e473
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-isp.c
@@ -0,0 +1,509 @@
+/*
+ * Samsung EXYNOS5250 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ *  Arun Kumar K <arun.kk@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <media/v4l2-ioctl.h>
+#include <media/videobuf2-dma-contig.h>
+
+#include "fimc-is.h"
+
+#define ISP_DRV_NAME "fimc-is-isp"
+
+static const struct fimc_is_fmt formats[] = {
+	{
+		.name           = "Bayer GR-BG 8bits",
+		.fourcc         = V4L2_PIX_FMT_SGRBG8,
+		.depth		= { 8 },
+		.num_planes     = 1,
+	},
+	{
+		.name           = "Bayer GR-BG 10bits",
+		.fourcc         = V4L2_PIX_FMT_SGRBG10,
+		.depth		= { 16 },
+		.num_planes     = 1,
+	},
+	{
+		.name           = "Bayer GR-BG 12bits",
+		.fourcc         = V4L2_PIX_FMT_SGRBG12,
+		.depth		= { 16 },
+		.num_planes     = 1,
+	},
+};
+#define NUM_FORMATS ARRAY_SIZE(formats)
+
+static const struct fimc_is_fmt *find_format(struct v4l2_format *f)
+{
+	unsigned int i;
+
+	for (i = 0; i < NUM_FORMATS; i++) {
+		if (formats[i].fourcc == f->fmt.pix_mp.pixelformat)
+			return &formats[i];
+	}
+	return NULL;
+}
+
+static int isp_video_output_start_streaming(struct vb2_queue *vq,
+					unsigned int count)
+{
+	struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+
+	set_bit(STATE_RUNNING, &isp->output_state);
+	return 0;
+}
+
+static int isp_video_output_stop_streaming(struct vb2_queue *vq)
+{
+	struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+
+	clear_bit(STATE_RUNNING, &isp->output_state);
+	return 0;
+}
+
+static int isp_video_output_queue_setup(struct vb2_queue *vq,
+			const struct v4l2_format *pfmt,
+			unsigned int *num_buffers, unsigned int *num_planes,
+			unsigned int sizes[], void *allocators[])
+{
+	struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+	const struct fimc_is_fmt *fmt = isp->fmt;
+	unsigned int wh, i;
+
+	if (!fmt)
+		return -EINVAL;
+
+	*num_planes = fmt->num_planes;
+	wh = isp->width * isp->height;
+
+	for (i = 0; i < *num_planes; i++) {
+		allocators[i] = isp->alloc_ctx;
+		sizes[i] = (wh * fmt->depth[i]) / 8;
+	}
+	return 0;
+}
+
+static int isp_video_output_buffer_init(struct vb2_buffer *vb)
+{
+	struct vb2_queue *vq = vb->vb2_queue;
+	struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+	struct fimc_is_buf *buf;
+
+	buf = &isp->output_bufs[vb->v4l2_buf.index];
+	/* Initialize buffer */
+	buf->vb = vb;
+	buf->paddr[0] = vb2_dma_contig_plane_dma_addr(vb, 0);
+	isp->out_buf_cnt++;
+	return 0;
+}
+
+static void isp_video_output_buffer_queue(struct vb2_buffer *vb)
+{
+	struct vb2_queue *vq = vb->vb2_queue;
+	struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+	struct fimc_is_buf *buf;
+
+	buf = &isp->output_bufs[vb->v4l2_buf.index];
+
+	fimc_is_pipeline_buf_lock(isp->pipeline);
+	fimc_is_isp_wait_queue_add(isp, buf);
+	fimc_is_pipeline_buf_unlock(isp->pipeline);
+
+	/* Call shot command */
+	fimc_is_pipeline_shot(isp->pipeline);
+}
+
+static const struct vb2_ops isp_video_output_qops = {
+	.queue_setup	 = isp_video_output_queue_setup,
+	.buf_init	 = isp_video_output_buffer_init,
+	.buf_queue	 = isp_video_output_buffer_queue,
+	.wait_prepare	 = vb2_ops_wait_prepare,
+	.wait_finish	 = vb2_ops_wait_finish,
+	.start_streaming = isp_video_output_start_streaming,
+	.stop_streaming	 = isp_video_output_stop_streaming,
+};
+
+static const struct v4l2_file_operations isp_video_output_fops = {
+	.owner		= THIS_MODULE,
+	.open		= v4l2_fh_open,
+	.release	= vb2_fop_release,
+	.poll		= vb2_fop_poll,
+	.unlocked_ioctl	= video_ioctl2,
+	.mmap		= vb2_fop_mmap,
+};
+
+/*
+ * Video node ioctl operations
+ */
+static int isp_querycap_output(struct file *file, void *priv,
+					struct v4l2_capability *cap)
+{
+	strncpy(cap->driver, ISP_DRV_NAME, sizeof(cap->driver) - 1);
+	strncpy(cap->card, ISP_DRV_NAME, sizeof(cap->card) - 1);
+	snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
+			ISP_DRV_NAME);
+	cap->device_caps = V4L2_CAP_STREAMING;
+	cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
+	return 0;
+}
+
+static int isp_enum_fmt_mplane(struct file *file, void *priv,
+				     struct v4l2_fmtdesc *f)
+{
+	const struct fimc_is_fmt *fmt;
+
+	if (f->index >= NUM_FORMATS)
+		return -EINVAL;
+
+	fmt = &formats[f->index];
+	strlcpy(f->description, fmt->name, sizeof(f->description));
+	f->pixelformat = fmt->fourcc;
+
+	return 0;
+}
+
+static int isp_g_fmt_mplane(struct file *file, void *fh,
+				  struct v4l2_format *f)
+{
+	struct fimc_is_isp *isp = video_drvdata(file);
+	struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
+	struct v4l2_plane_pix_format *plane_fmt = &pixm->plane_fmt[0];
+	const struct fimc_is_fmt *fmt = isp->fmt;
+
+	plane_fmt->bytesperline = (isp->width * fmt->depth[0]) / 8;
+	plane_fmt->sizeimage = plane_fmt->bytesperline * isp->height;
+	memset(plane_fmt->reserved, 0, sizeof(plane_fmt->reserved));
+
+	pixm->num_planes = fmt->num_planes;
+	pixm->pixelformat = fmt->fourcc;
+	pixm->width = isp->width;
+	pixm->height = isp->height;
+	pixm->field = V4L2_FIELD_NONE;
+	pixm->colorspace = V4L2_COLORSPACE_JPEG;
+	memset(pixm->reserved, 0, sizeof(pixm->reserved));
+
+	return 0;
+}
+
+static int isp_try_fmt_mplane(struct file *file, void *fh,
+		struct v4l2_format *f)
+{
+	const struct fimc_is_fmt *fmt;
+	struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
+	struct v4l2_plane_pix_format *plane_fmt = &pixm->plane_fmt[0];
+
+	fmt = find_format(f);
+	if (!fmt)
+		fmt = (struct fimc_is_fmt *) &formats[0];
+
+	v4l_bound_align_image(&pixm->width,
+			ISP_MIN_WIDTH + SENSOR_WIDTH_PADDING,
+			ISP_MAX_WIDTH + SENSOR_WIDTH_PADDING, 0,
+			&pixm->height,
+			ISP_MIN_HEIGHT + SENSOR_HEIGHT_PADDING,
+			ISP_MAX_HEIGHT + SENSOR_HEIGHT_PADDING, 0,
+			0);
+
+	plane_fmt->bytesperline = (pixm->width * fmt->depth[0]) / 8;
+	plane_fmt->sizeimage = (pixm->width * pixm->height *
+				fmt->depth[0]) / 8;
+	memset(plane_fmt->reserved, 0, sizeof(plane_fmt->reserved));
+
+	pixm->num_planes = fmt->num_planes;
+	pixm->pixelformat = fmt->fourcc;
+	pixm->colorspace = V4L2_COLORSPACE_JPEG;
+	pixm->field = V4L2_FIELD_NONE;
+	memset(pixm->reserved, 0, sizeof(pixm->reserved));
+
+	return 0;
+}
+
+static int isp_s_fmt_mplane(struct file *file, void *priv,
+		struct v4l2_format *f)
+{
+	struct fimc_is_isp *isp = video_drvdata(file);
+	const struct fimc_is_fmt *fmt;
+	int ret;
+
+	ret = isp_try_fmt_mplane(file, priv, f);
+	if (ret)
+		return ret;
+
+	/* Get format type */
+	fmt = find_format(f);
+	if (!fmt) {
+		fmt = (struct fimc_is_fmt *) &formats[0];
+		f->fmt.pix_mp.pixelformat = fmt->fourcc;
+		f->fmt.pix_mp.num_planes = fmt->num_planes;
+	}
+
+	isp->fmt = fmt;
+	isp->width = f->fmt.pix_mp.width;
+	isp->height = f->fmt.pix_mp.height;
+	isp->size_image = f->fmt.pix_mp.plane_fmt[0].sizeimage;
+	set_bit(STATE_INIT, &isp->output_state);
+	return 0;
+}
+
+static int isp_reqbufs(struct file *file, void *priv,
+		struct v4l2_requestbuffers *reqbufs)
+{
+	struct fimc_is_isp *isp = video_drvdata(file);
+	int ret;
+
+	reqbufs->count = max_t(u32, FIMC_IS_ISP_REQ_BUFS_MIN, reqbufs->count);
+	ret = vb2_reqbufs(&isp->vbq, reqbufs);
+	if (ret) {
+		pr_err("vb2 req buffers failed\n");
+		return ret;
+	}
+
+	isp->out_buf_cnt = 0;
+	set_bit(STATE_BUFS_ALLOCATED, &isp->output_state);
+	return 0;
+}
+
+static const struct v4l2_ioctl_ops isp_video_output_ioctl_ops = {
+	.vidioc_querycap		= isp_querycap_output,
+	.vidioc_enum_fmt_vid_out_mplane	= isp_enum_fmt_mplane,
+	.vidioc_try_fmt_vid_out_mplane	= isp_try_fmt_mplane,
+	.vidioc_s_fmt_vid_out_mplane	= isp_s_fmt_mplane,
+	.vidioc_g_fmt_vid_out_mplane	= isp_g_fmt_mplane,
+	.vidioc_reqbufs			= isp_reqbufs,
+	.vidioc_querybuf		= vb2_ioctl_querybuf,
+	.vidioc_qbuf			= vb2_ioctl_qbuf,
+	.vidioc_dqbuf			= vb2_ioctl_dqbuf,
+	.vidioc_streamon		= vb2_ioctl_streamon,
+	.vidioc_streamoff		= vb2_ioctl_streamoff,
+};
+
+static int isp_subdev_registered(struct v4l2_subdev *sd)
+{
+	struct fimc_is_isp *isp = v4l2_get_subdevdata(sd);
+	struct vb2_queue *q = &isp->vbq;
+	struct video_device *vfd = &isp->vfd;
+	int ret;
+
+	mutex_init(&isp->video_lock);
+
+	memset(vfd, 0, sizeof(*vfd));
+	snprintf(vfd->name, sizeof(vfd->name), "fimc-is-isp.output");
+
+	vfd->fops = &isp_video_output_fops;
+	vfd->ioctl_ops = &isp_video_output_ioctl_ops;
+	vfd->v4l2_dev = sd->v4l2_dev;
+	vfd->release = video_device_release_empty;
+	vfd->lock = &isp->video_lock;
+	vfd->queue = q;
+	vfd->vfl_dir = VFL_DIR_TX;
+	set_bit(V4L2_FL_USE_FH_PRIO, &vfd->flags);
+
+	memset(q, 0, sizeof(*q));
+	q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
+	q->io_modes = VB2_MMAP | VB2_DMABUF;
+	q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
+	q->ops = &isp_video_output_qops;
+	q->mem_ops = &vb2_dma_contig_memops;
+	q->drv_priv = isp;
+
+	ret = vb2_queue_init(q);
+	if (ret < 0)
+		return ret;
+
+	isp->vd_pad.flags = MEDIA_PAD_FL_SINK;
+	ret = media_entity_init(&vfd->entity, 1, &isp->vd_pad, 0);
+	if (ret < 0)
+		return ret;
+
+	video_set_drvdata(vfd, isp);
+
+	ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
+	if (ret < 0) {
+		media_entity_cleanup(&vfd->entity);
+		return ret;
+	}
+
+	v4l2_info(sd->v4l2_dev, "Registered %s as /dev/%s\n",
+		  vfd->name, video_device_node_name(vfd));
+	return 0;
+}
+
+static void isp_subdev_unregistered(struct v4l2_subdev *sd)
+{
+	struct fimc_is_isp *isp = v4l2_get_subdevdata(sd);
+
+	if (isp && video_is_registered(&isp->vfd))
+		video_unregister_device(&isp->vfd);
+}
+
+static const struct v4l2_subdev_internal_ops isp_subdev_internal_ops = {
+	.registered = isp_subdev_registered,
+	.unregistered = isp_subdev_unregistered,
+};
+
+static struct fimc_is_sensor *fimc_is_get_sensor(struct fimc_is *is,
+		int sensor_id)
+{
+	int i;
+
+	for (i = 0; i < FIMC_IS_NUM_SENSORS; i++) {
+		if (is->sensor[i].drvdata->id == sensor_id)
+			return &is->sensor[i];
+	}
+	return NULL;
+}
+
+static int isp_s_power(struct v4l2_subdev *sd, int on)
+{
+	struct fimc_is_isp *isp = v4l2_get_subdevdata(sd);
+	struct fimc_is *is = isp->pipeline->is;
+	struct v4l2_subdev *sensor_sd = isp->sensor_sd;
+	struct fimc_is_sensor *sensor;
+	const struct sensor_drv_data *sdata;
+	struct media_pad *pad;
+	struct v4l2_subdev_format fmt;
+	int ret;
+
+	if (!sensor_sd)
+		return -EINVAL;
+
+	if (on) {
+		ret = pm_runtime_get_sync(&is->pdev->dev);
+		if (ret < 0)
+			return ret;
+
+		sdata = exynos5_is_sensor_get_drvdata(sensor_sd->dev->of_node);
+		sensor = fimc_is_get_sensor(is, sdata->id);
+		/* Retrieve the sensor format */
+		pad = &sensor_sd->entity.pads[0];
+		fmt.pad = 0;
+		fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
+		ret = v4l2_subdev_call(sensor_sd, pad, get_fmt, NULL, &fmt);
+		if (ret)
+			return ret;
+
+		sensor->width = fmt.format.width - SENSOR_WIDTH_PADDING;
+		sensor->height = fmt.format.height - SENSOR_HEIGHT_PADDING;
+		sensor->pixel_width = fmt.format.width;
+		sensor->pixel_height = fmt.format.height;
+
+		ret = fimc_is_pipeline_open(isp->pipeline, sensor);
+		if (ret)
+			pr_err("Pipeline open failed\n");
+	} else {
+		ret = fimc_is_pipeline_close(isp->pipeline);
+		if (ret)
+			pr_err("Pipeline close failed\n");
+		pm_runtime_put_sync(&is->pdev->dev);
+	}
+
+	return ret;
+}
+
+static struct v4l2_subdev_core_ops isp_core_ops = {
+	.s_power = isp_s_power,
+};
+
+static int isp_s_stream(struct v4l2_subdev *sd, int enable)
+{
+	struct fimc_is_isp *isp = v4l2_get_subdevdata(sd);
+	struct fimc_is *is = isp->pipeline->is;
+	struct v4l2_subdev *sensor_sd = isp->sensor_sd;
+	const struct sensor_drv_data *sdata;
+	struct fimc_is_sensor *sensor;
+	int ret;
+
+	if (!sensor_sd)
+		return -EINVAL;
+
+	if (enable) {
+		sdata = exynos5_is_sensor_get_drvdata(sensor_sd->dev->of_node);
+		sensor = fimc_is_get_sensor(is, sdata->id);
+		/* Check sensor resolution match */
+		if ((sensor->pixel_width != isp->width) ||
+			(sensor->pixel_height != isp->height)) {
+			pr_err("Resolution mismatch\n");
+			return -EPIPE;
+		}
+		ret = fimc_is_pipeline_start(isp->pipeline);
+		if (ret)
+			pr_err("Pipeline start failed.\n");
+	} else {
+		ret = fimc_is_pipeline_stop(isp->pipeline);
+		if (ret)
+			pr_err("Pipeline stop failed.\n");
+	}
+
+	return ret;
+}
+
+static const struct v4l2_subdev_video_ops isp_video_ops = {
+	.s_stream       = isp_s_stream,
+};
+
+static struct v4l2_subdev_ops isp_subdev_ops = {
+	.core = &isp_core_ops,
+	.video = &isp_video_ops,
+};
+
+int fimc_is_isp_subdev_create(struct fimc_is_isp *isp,
+		struct vb2_alloc_ctx *alloc_ctx,
+		struct fimc_is_pipeline *pipeline)
+{
+	struct v4l2_ctrl_handler *handler = &isp->ctrl_handler;
+	struct v4l2_subdev *sd = &isp->subdev;
+	int ret;
+
+	/* Init context vars */
+	isp->alloc_ctx = alloc_ctx;
+	isp->pipeline = pipeline;
+	isp->fmt = &formats[1];
+	INIT_LIST_HEAD(&isp->wait_queue);
+	INIT_LIST_HEAD(&isp->run_queue);
+	isp->width = ISP_DEF_WIDTH;
+	isp->height = ISP_DEF_HEIGHT;
+
+	v4l2_subdev_init(sd, &isp_subdev_ops);
+	sd->owner = THIS_MODULE;
+	sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
+	snprintf(sd->name, sizeof(sd->name), ISP_DRV_NAME);
+
+	isp->subdev_pads[ISP_SD_PAD_SINK_DMA].flags = MEDIA_PAD_FL_SINK;
+	isp->subdev_pads[ISP_SD_PAD_SINK_OTF].flags = MEDIA_PAD_FL_SINK;
+	isp->subdev_pads[ISP_SD_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE;
+	ret = media_entity_init(&sd->entity, ISP_SD_PADS_NUM,
+			isp->subdev_pads, 0);
+	if (ret < 0)
+		return ret;
+
+	ret = v4l2_ctrl_handler_init(handler, 1);
+	if (handler->error)
+		goto err_ctrl;
+
+	sd->ctrl_handler = handler;
+	sd->internal_ops = &isp_subdev_internal_ops;
+	v4l2_set_subdevdata(sd, isp);
+
+	return 0;
+
+err_ctrl:
+	media_entity_cleanup(&sd->entity);
+	v4l2_ctrl_handler_free(handler);
+	return ret;
+}
+
+void fimc_is_isp_subdev_destroy(struct fimc_is_isp *isp)
+{
+	struct v4l2_subdev *sd = &isp->subdev;
+
+	v4l2_device_unregister_subdev(sd);
+	media_entity_cleanup(&sd->entity);
+	v4l2_ctrl_handler_free(&isp->ctrl_handler);
+	v4l2_set_subdevdata(sd, NULL);
+}
+
diff --git a/drivers/media/platform/exynos5-is/fimc-is-isp.h b/drivers/media/platform/exynos5-is/fimc-is-isp.h
new file mode 100644
index 0000000..2d5069d
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-isp.h
@@ -0,0 +1,93 @@
+/*
+ * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2012 Samsung Electronics Co., Ltd.
+ *  Arun Kumar K <arun.kk@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef FIMC_IS_ISP_H_
+#define FIMC_IS_ISP_H_
+
+#include "fimc-is-core.h"
+#include "fimc-is-pipeline.h"
+
+#define FIMC_IS_ISP_REQ_BUFS_MIN	2
+
+#define ISP_SD_PAD_SINK_DMA	0
+#define ISP_SD_PAD_SINK_OTF	1
+#define ISP_SD_PAD_SRC		2
+#define ISP_SD_PADS_NUM		3
+
+#define ISP_DEF_WIDTH		1296
+#define ISP_DEF_HEIGHT		732
+
+#define ISP_MAX_WIDTH		4808
+#define ISP_MAX_HEIGHT		3356
+#define ISP_MIN_WIDTH		32
+#define ISP_MIN_HEIGHT		32
+
+#define ISP_MAX_BUFS		2
+
+/**
+ * struct fimc_is_isp - ISP context
+ * @vfd: video device node
+ * @fh: v4l2 file handle
+ * @alloc_ctx: videobuf2 memory allocator context
+ * @subdev: fimc-is-isp subdev
+ * @vd_pad: media pad for the output video node
+ * @subdev_pads: the subdev media pads
+ * @ctrl_handler: v4l2 control handler
+ * @video_lock: video lock mutex
+ * @sensor_sd: sensor subdev used with this isp instance
+ * @pipeline: pipeline instance for this isp context
+ * @vbq: vb2 buffers queue for ISP output video node
+ * @wait_queue: list holding buffers waiting to be queued to HW
+ * @wait_queue_cnt: wait queue number of buffers
+ * @run_queue: list holding buffers queued to HW
+ * @run_queue_cnt: run queue number of buffers
+ * @output_bufs: isp output buffers array
+ * @out_buf_cnt: number of output buffers in use
+ * @fmt: output plane format for isp
+ * @width: user configured input width
+ * @height: user configured input height
+ * @size_image: image size in bytes
+ * @output_state: state of the output video node operations
+ */
+struct fimc_is_isp {
+	struct video_device		vfd;
+	struct v4l2_fh			fh;
+	struct vb2_alloc_ctx		*alloc_ctx;
+	struct v4l2_subdev		subdev;
+	struct media_pad		vd_pad;
+	struct media_pad		subdev_pads[ISP_SD_PADS_NUM];
+	struct v4l2_ctrl_handler	ctrl_handler;
+	struct mutex			video_lock;
+
+	struct v4l2_subdev		*sensor_sd;
+	struct fimc_is_pipeline		*pipeline;
+
+	struct vb2_queue		vbq;
+	struct list_head		wait_queue;
+	unsigned int			wait_queue_cnt;
+	struct list_head		run_queue;
+	unsigned int			run_queue_cnt;
+
+	struct fimc_is_buf		output_bufs[ISP_MAX_BUFS];
+	unsigned int			out_buf_cnt;
+
+	const struct fimc_is_fmt	*fmt;
+	unsigned int			width;
+	unsigned int			height;
+	unsigned int			size_image;
+	unsigned long			output_state;
+};
+
+int fimc_is_isp_subdev_create(struct fimc_is_isp *isp,
+		struct vb2_alloc_ctx *alloc_ctx,
+		struct fimc_is_pipeline *pipeline);
+void fimc_is_isp_subdev_destroy(struct fimc_is_isp *isp);
+
+#endif /* FIMC_IS_ISP_H_ */
-- 
1.7.9.5

[RFC v3 07/13] [media] exynos5-fimc-is: Add scaler subdev

[Arun Kumar K]

FIMC-IS has two hardware scalers named as scaler-codec and
scaler-preview. This patch adds the common code handling the
video nodes and subdevs of both the scalers.

Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Kilyeon Im <kilyeon.im@samsung.com>
---
 drivers/media/platform/exynos5-is/fimc-is-scaler.c |  458 ++++++++++++++++++++
 drivers/media/platform/exynos5-is/fimc-is-scaler.h |  112 +++++
 2 files changed, 570 insertions(+)
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-scaler.c
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-scaler.h

diff --git a/drivers/media/platform/exynos5-is/fimc-is-scaler.c b/drivers/media/platform/exynos5-is/fimc-is-scaler.c
new file mode 100644
index 0000000..7cff186
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-scaler.c
@@ -0,0 +1,458 @@
+/*
+ * Samsung EXYNOS5250 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ *  Arun Kumar K <arun.kk@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <media/v4l2-ioctl.h>
+#include <media/videobuf2-dma-contig.h>
+
+#include "fimc-is.h"
+
+#define IS_SCALER_DRV_NAME "fimc-is-scaler"
+
+static const struct fimc_is_fmt formats[] = {
+	{
+		.name           = "YUV 4:2:0 3p MultiPlanar",
+		.fourcc         = V4L2_PIX_FMT_YUV420M,
+		.depth		= {8, 2, 2},
+		.num_planes     = 3,
+	},
+	{
+		.name           = "YUV 4:2:0 2p MultiPlanar",
+		.fourcc         = V4L2_PIX_FMT_NV12M,
+		.depth		= {8, 4},
+		.num_planes     = 2,
+	},
+	{
+		.name           = "YUV 4:2:2 1p MultiPlanar",
+		.fourcc         = V4L2_PIX_FMT_NV16,
+		.depth		= {16},
+		.num_planes     = 1,
+	},
+};
+#define NUM_FORMATS ARRAY_SIZE(formats)
+
+static const struct fimc_is_fmt *find_format(struct v4l2_format *f)
+{
+	unsigned int i;
+
+	for (i = 0; i < NUM_FORMATS; i++) {
+		if (formats[i].fourcc == f->fmt.pix_mp.pixelformat)
+			return &formats[i];
+	}
+	return NULL;
+}
+
+static int scaler_video_capture_start_streaming(struct vb2_queue *vq,
+					unsigned int count)
+{
+	struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+	int ret;
+
+	/* Scaler start */
+	ret = fimc_is_pipeline_scaler_start(ctx->pipeline,
+			ctx->scaler_id,
+			(unsigned int **)ctx->buf_paddr,
+			vq->num_buffers,
+			ctx->fmt->num_planes);
+	if (ret) {
+		pr_err("Scaler start failed.\n");
+		return -EINVAL;
+	}
+
+	set_bit(STATE_RUNNING, &ctx->capture_state);
+	return 0;
+}
+
+static int scaler_video_capture_stop_streaming(struct vb2_queue *vq)
+{
+	struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+	int ret;
+
+	/* Scaler stop */
+	ret = fimc_is_pipeline_scaler_stop(ctx->pipeline, ctx->scaler_id);
+	if (ret)
+		pr_debug("Scaler already stopped.\n");
+
+	clear_bit(STATE_RUNNING, &ctx->capture_state);
+	return 0;
+}
+
+static int scaler_video_capture_queue_setup(struct vb2_queue *vq,
+			const struct v4l2_format *pfmt,
+			unsigned int *num_buffers, unsigned int *num_planes,
+			unsigned int sizes[], void *allocators[])
+{
+	struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+	const struct fimc_is_fmt *fmt = ctx->fmt;
+	unsigned int wh;
+	int i;
+
+	if (!fmt)
+		return -EINVAL;
+
+	*num_planes = fmt->num_planes;
+	wh = ctx->width * ctx->height;
+
+	for (i = 0; i < *num_planes; i++) {
+		allocators[i] = ctx->alloc_ctx;
+		sizes[i] = (wh * fmt->depth[i]) / 8;
+	}
+	return 0;
+}
+
+static int scaler_video_capture_buffer_init(struct vb2_buffer *vb)
+{
+	struct vb2_queue *vq = vb->vb2_queue;
+	struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+	struct fimc_is_buf *buf;
+	const struct fimc_is_fmt *fmt;
+	int i;
+
+	buf = &ctx->capture_bufs[vb->v4l2_buf.index];
+	/* Initialize buffer */
+	buf->vb = vb;
+	fmt = ctx->fmt;
+	for (i = 0; i < fmt->num_planes; i++)
+		buf->paddr[i] = vb2_dma_contig_plane_dma_addr(vb, i);
+
+	ctx->cap_buf_cnt++;
+	return 0;
+}
+
+static void scaler_video_capture_buffer_queue(struct vb2_buffer *vb)
+{
+	struct vb2_queue *vq = vb->vb2_queue;
+	struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+	struct fimc_is_buf *buf;
+
+	buf = &ctx->capture_bufs[vb->v4l2_buf.index];
+
+	/* Add buffer to the wait queue */
+	pr_debug("Add buffer %d in Scaler %d\n",
+			vb->v4l2_buf.index, ctx->scaler_id);
+	fimc_is_pipeline_buf_lock(ctx->pipeline);
+	fimc_is_scaler_wait_queue_add(ctx, buf);
+	fimc_is_pipeline_buf_unlock(ctx->pipeline);
+}
+
+static void scaler_lock(struct vb2_queue *vq)
+{
+	struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+	mutex_lock(&ctx->video_lock);
+}
+
+static void scaler_unlock(struct vb2_queue *vq)
+{
+	struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+	mutex_unlock(&ctx->video_lock);
+}
+
+static const struct vb2_ops scaler_video_capture_qops = {
+	.queue_setup		= scaler_video_capture_queue_setup,
+	.buf_init		= scaler_video_capture_buffer_init,
+	.buf_queue		= scaler_video_capture_buffer_queue,
+	.wait_prepare		= scaler_unlock,
+	.wait_finish		= scaler_lock,
+	.start_streaming	= scaler_video_capture_start_streaming,
+	.stop_streaming		= scaler_video_capture_stop_streaming,
+};
+
+static const struct v4l2_file_operations scaler_video_capture_fops = {
+	.owner		= THIS_MODULE,
+	.open		= v4l2_fh_open,
+	.release	= vb2_fop_release,
+	.poll		= vb2_fop_poll,
+	.unlocked_ioctl	= video_ioctl2,
+	.mmap		= vb2_fop_mmap,
+};
+
+/*
+ * Video node ioctl operations
+ */
+static int scaler_querycap_capture(struct file *file, void *priv,
+					struct v4l2_capability *cap)
+{
+	strncpy(cap->driver, IS_SCALER_DRV_NAME, sizeof(cap->driver) - 1);
+	strncpy(cap->card, IS_SCALER_DRV_NAME, sizeof(cap->card) - 1);
+	snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
+			IS_SCALER_DRV_NAME);
+	cap->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_CAPTURE_MPLANE;
+	cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
+	return 0;
+}
+
+static int scaler_enum_fmt_mplane(struct file *file, void *priv,
+				     struct v4l2_fmtdesc *f)
+{
+	const struct fimc_is_fmt *fmt;
+
+	if (f->index >= NUM_FORMATS)
+		return -EINVAL;
+
+	fmt = &formats[f->index];
+	strlcpy(f->description, fmt->name, sizeof(f->description));
+	f->pixelformat = fmt->fourcc;
+	return 0;
+}
+
+static int scaler_g_fmt_mplane(struct file *file, void *priv,
+				  struct v4l2_format *f)
+{
+	struct fimc_is_scaler *ctx = video_drvdata(file);
+	struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
+	const struct fimc_is_fmt *fmt = ctx->fmt;
+	int i;
+
+	for (i = 0; i < fmt->num_planes; i++) {
+		struct v4l2_plane_pix_format *plane_fmt = &pixm->plane_fmt[i];
+		plane_fmt->bytesperline = (ctx->width * fmt->depth[i]) / 8;
+		plane_fmt->sizeimage = plane_fmt->bytesperline * ctx->height;
+		memset(plane_fmt->reserved, 0, sizeof(plane_fmt->reserved));
+	}
+
+	pixm->num_planes = fmt->num_planes;
+	pixm->pixelformat = fmt->fourcc;
+	pixm->width = ctx->width;
+	pixm->height = ctx->height;
+	pixm->field = V4L2_FIELD_NONE;
+	pixm->colorspace = V4L2_COLORSPACE_JPEG;
+	memset(pixm->reserved, 0, sizeof(pixm->reserved));
+
+	return 0;
+}
+
+static int scaler_try_fmt_mplane(struct file *file, void *priv,
+				  struct v4l2_format *f)
+{
+	const struct fimc_is_fmt *fmt;
+	struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
+	u32 i;
+
+	fmt = find_format(f);
+	if (!fmt)
+		fmt = &formats[0];
+
+	v4l_bound_align_image(&pixm->width, SCALER_MIN_WIDTH,
+			SCALER_MAX_WIDTH, 0,
+			&pixm->height, SCALER_MIN_HEIGHT,
+			SCALER_MAX_HEIGHT, 0, 0);
+
+	for (i = 0; i < fmt->num_planes; i++) {
+		struct v4l2_plane_pix_format *plane_fmt = &pixm->plane_fmt[i];
+
+		plane_fmt->bytesperline = (pixm->width * fmt->depth[i]) / 8;
+		plane_fmt->sizeimage = (pixm->width * pixm->height *
+					fmt->depth[i]) / 8;
+		memset(plane_fmt->reserved, 0, sizeof(plane_fmt->reserved));
+	}
+	pixm->num_planes = fmt->num_planes;
+	pixm->pixelformat = fmt->fourcc;
+	pixm->colorspace = V4L2_COLORSPACE_JPEG;
+	pixm->field = V4L2_FIELD_NONE;
+	memset(pixm->reserved, 0, sizeof(pixm->reserved));
+
+	return 0;
+}
+
+static int scaler_s_fmt_mplane(struct file *file, void *priv,
+				struct v4l2_format *f)
+{
+	struct fimc_is_scaler *ctx = video_drvdata(file);
+	const struct fimc_is_fmt *fmt;
+	int ret;
+
+	ret = scaler_try_fmt_mplane(file, priv, f);
+	if (ret)
+		return ret;
+
+	/* Get format type */
+	fmt = find_format(f);
+	if (!fmt) {
+		fmt = &formats[0];
+		f->fmt.pix_mp.pixelformat = fmt->fourcc;
+		f->fmt.pix_mp.num_planes = fmt->num_planes;
+	}
+
+	/* Save values to context */
+	ctx->fmt = fmt;
+	ctx->width = f->fmt.pix_mp.width;
+	ctx->height = f->fmt.pix_mp.height;
+	ctx->pipeline->scaler_width[ctx->scaler_id] = ctx->width;
+	ctx->pipeline->scaler_height[ctx->scaler_id] = ctx->height;
+	set_bit(STATE_INIT, &ctx->capture_state);
+	return 0;
+}
+
+static int scaler_reqbufs(struct file *file, void *priv,
+		struct v4l2_requestbuffers *reqbufs)
+{
+	struct fimc_is_scaler *ctx = video_drvdata(file);
+	int ret;
+
+	reqbufs->count = max_t(u32, FIMC_IS_SCALER_REQ_BUFS_MIN,
+			reqbufs->count);
+	ret = vb2_reqbufs(&ctx->vbq, reqbufs);
+	if (ret) {
+		pr_err("vb2 req buffers failed\n");
+		return ret;
+	}
+
+	ctx->cap_buf_cnt = 0;
+	set_bit(STATE_BUFS_ALLOCATED, &ctx->capture_state);
+	return 0;
+}
+
+static const struct v4l2_ioctl_ops scaler_video_capture_ioctl_ops = {
+	.vidioc_querycap		= scaler_querycap_capture,
+	.vidioc_enum_fmt_vid_cap_mplane	= scaler_enum_fmt_mplane,
+	.vidioc_try_fmt_vid_cap_mplane	= scaler_try_fmt_mplane,
+	.vidioc_s_fmt_vid_cap_mplane	= scaler_s_fmt_mplane,
+	.vidioc_g_fmt_vid_cap_mplane	= scaler_g_fmt_mplane,
+	.vidioc_reqbufs			= scaler_reqbufs,
+	.vidioc_querybuf		= vb2_ioctl_querybuf,
+	.vidioc_qbuf			= vb2_ioctl_qbuf,
+	.vidioc_dqbuf			= vb2_ioctl_dqbuf,
+	.vidioc_expbuf			= vb2_ioctl_expbuf,
+	.vidioc_streamon		= vb2_ioctl_streamon,
+	.vidioc_streamoff		= vb2_ioctl_streamoff,
+};
+
+static int scaler_subdev_registered(struct v4l2_subdev *sd)
+{
+	struct fimc_is_scaler *ctx = v4l2_get_subdevdata(sd);
+	struct vb2_queue *q = &ctx->vbq;
+	struct video_device *vfd = &ctx->vfd;
+	int ret;
+
+	mutex_init(&ctx->video_lock);
+
+	memset(vfd, 0, sizeof(*vfd));
+	if (ctx->scaler_id == SCALER_SCC)
+		snprintf(vfd->name, sizeof(vfd->name), "fimc-is-scaler.codec");
+	else
+		snprintf(vfd->name, sizeof(vfd->name),
+				"fimc-is-scaler.preview");
+
+	vfd->fops = &scaler_video_capture_fops;
+	vfd->ioctl_ops = &scaler_video_capture_ioctl_ops;
+	vfd->v4l2_dev = sd->v4l2_dev;
+	vfd->release = video_device_release_empty;
+	vfd->lock = &ctx->video_lock;
+	vfd->queue = q;
+	vfd->vfl_dir = VFL_DIR_RX;
+	set_bit(V4L2_FL_USE_FH_PRIO, &vfd->flags);
+
+	memset(q, 0, sizeof(*q));
+	q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
+	q->io_modes = VB2_MMAP | VB2_DMABUF;
+	q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
+	q->ops = &scaler_video_capture_qops;
+	q->mem_ops = &vb2_dma_contig_memops;
+	q->drv_priv = ctx;
+
+	ret = vb2_queue_init(q);
+	if (ret < 0)
+		return ret;
+
+	ctx->vd_pad.flags = MEDIA_PAD_FL_SINK;
+	ret = media_entity_init(&vfd->entity, 1, &ctx->vd_pad, 0);
+	if (ret < 0)
+		return ret;
+
+	video_set_drvdata(vfd, ctx);
+
+	ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
+	if (ret < 0) {
+		media_entity_cleanup(&vfd->entity);
+		return ret;
+	}
+
+	v4l2_info(sd->v4l2_dev, "Registered %s as /dev/%s\n",
+		  vfd->name, video_device_node_name(vfd));
+	return 0;
+}
+
+static void scaler_subdev_unregistered(struct v4l2_subdev *sd)
+{
+	struct fimc_is_scaler *ctx = v4l2_get_subdevdata(sd);
+
+	if (ctx && video_is_registered(&ctx->vfd))
+		video_unregister_device(&ctx->vfd);
+}
+
+static const struct v4l2_subdev_internal_ops scaler_subdev_internal_ops = {
+	.registered = scaler_subdev_registered,
+	.unregistered = scaler_subdev_unregistered,
+};
+
+static struct v4l2_subdev_ops scaler_subdev_ops;
+
+int fimc_is_scaler_subdev_create(struct fimc_is_scaler *ctx,
+		enum fimc_is_scaler_id scaler_id,
+		struct vb2_alloc_ctx *alloc_ctx,
+		struct fimc_is_pipeline *pipeline)
+{
+	struct v4l2_ctrl_handler *handler = &ctx->ctrl_handler;
+	struct v4l2_subdev *sd = &ctx->subdev;
+	int ret;
+
+	/* Set context data */
+	ctx->scaler_id = scaler_id;
+	ctx->alloc_ctx = alloc_ctx;
+	ctx->pipeline = pipeline;
+	ctx->fmt = &formats[0];
+	ctx->width = SCALER_DEF_WIDTH;
+	ctx->height = SCALER_DEF_HEIGHT;
+	init_waitqueue_head(&ctx->event_q);
+	INIT_LIST_HEAD(&ctx->wait_queue);
+	INIT_LIST_HEAD(&ctx->run_queue);
+
+	/* Initialize scaler subdev */
+	v4l2_subdev_init(sd, &scaler_subdev_ops);
+	sd->owner = THIS_MODULE;
+	sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
+	if (scaler_id == SCALER_SCC)
+		snprintf(sd->name, sizeof(sd->name), "fimc-is-scc");
+	else
+		snprintf(sd->name, sizeof(sd->name), "fimc-is-scp");
+
+	ctx->subdev_pads[SCALER_SD_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
+	ctx->subdev_pads[SCALER_SD_PAD_SRC_FIFO].flags = MEDIA_PAD_FL_SOURCE;
+	ctx->subdev_pads[SCALER_SD_PAD_SRC_DMA].flags = MEDIA_PAD_FL_SOURCE;
+	ret = media_entity_init(&sd->entity, ISP_SD_PADS_NUM,
+			ctx->subdev_pads, 0);
+	if (ret < 0)
+		return ret;
+
+	ret = v4l2_ctrl_handler_init(handler, 1);
+	if (handler->error)
+		goto err_ctrl;
+
+	sd->ctrl_handler = handler;
+	sd->internal_ops = &scaler_subdev_internal_ops;
+	v4l2_set_subdevdata(sd, ctx);
+
+	return 0;
+err_ctrl:
+	media_entity_cleanup(&sd->entity);
+	v4l2_ctrl_handler_free(handler);
+	return ret;
+}
+
+void fimc_is_scaler_subdev_destroy(struct fimc_is_scaler *ctx)
+{
+	struct v4l2_subdev *sd = &ctx->subdev;
+
+	v4l2_device_unregister_subdev(sd);
+	media_entity_cleanup(&sd->entity);
+	v4l2_ctrl_handler_free(&ctx->ctrl_handler);
+	v4l2_set_subdevdata(sd, NULL);
+}
+
diff --git a/drivers/media/platform/exynos5-is/fimc-is-scaler.h b/drivers/media/platform/exynos5-is/fimc-is-scaler.h
new file mode 100644
index 0000000..6d3d831
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-scaler.h
@@ -0,0 +1,112 @@
+/*
+ * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ *  Arun Kumar K <arun.kk@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef FIMC_IS_SCALER_H_
+#define FIMC_IS_SCALER_H_
+
+#include <linux/sizes.h>
+#include <linux/io.h>
+#include <linux/irqreturn.h>
+#include <linux/platform_device.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+#include <linux/videodev2.h>
+
+#include <media/media-entity.h>
+#include <media/videobuf2-core.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-mediabus.h>
+#include <media/s5p_fimc.h>
+
+#include "fimc-is-core.h"
+
+#define SCALER_SD_PAD_SINK	0
+#define SCALER_SD_PAD_SRC_FIFO	1
+#define SCALER_SD_PAD_SRC_DMA	2
+#define SCALER_SD_PADS_NUM	3
+
+#define SCALER_MAX_BUFS		32
+#define SCALER_MAX_PLANES	3
+
+#define FIMC_IS_SCALER_REQ_BUFS_MIN	2
+
+#define SCALER_DEF_WIDTH	1280
+#define SCALER_DEF_HEIGHT	720
+#define SCALER_MAX_WIDTH	4808
+#define SCALER_MAX_HEIGHT	3356
+#define SCALER_MIN_WIDTH	32
+#define SCALER_MIN_HEIGHT	32
+
+/**
+ * struct fimc_is_scaler - fimc-is scaler structure
+ * @vfd: video device node
+ * @fh: v4l2 file handle
+ * @alloc_ctx: videobuf2 memory allocator context
+ * @subdev: fimc-is-scaler subdev
+ * @vd_pad: media pad for the output video node
+ * @subdev_pads: the subdev media pads
+ * @ctrl_handler: v4l2 control handler
+ * @video_lock: video lock mutex
+ * @event_q: notifies scaler events
+ * @pipeline: pipeline instance for this scaler context
+ * @scaler_id: distinguishes scaler preview or scaler codec
+ * @vbq: vb2 buffers queue for ISP output video node
+ * @wait_queue: list holding buffers waiting to be queued to HW
+ * @wait_queue_cnt: wait queue number of buffers
+ * @run_queue: list holding buffers queued to HW
+ * @run_queue_cnt: run queue number of buffers
+ * @capture_bufs: scaler capture buffers array
+ * @cap_buf_cnt: number of capture buffers in use
+ * @fmt: capture plane format for scaler
+ * @width: user configured output width
+ * @height: user configured output height
+ * @capture_state: state of the capture video node operations
+ * @buf_paddr: holds the physical address of capture buffers
+ */
+struct fimc_is_scaler {
+	struct video_device		vfd;
+	struct v4l2_fh			fh;
+	struct vb2_alloc_ctx		*alloc_ctx;
+	struct v4l2_subdev		subdev;
+	struct media_pad		vd_pad;
+	struct media_pad		subdev_pads[SCALER_SD_PADS_NUM];
+	struct v4l2_mbus_framefmt	subdev_fmt;
+	struct v4l2_ctrl_handler	ctrl_handler;
+
+	struct mutex		video_lock;
+	wait_queue_head_t	event_q;
+
+	struct fimc_is_pipeline	*pipeline;
+	enum fimc_is_scaler_id	scaler_id;
+
+	struct vb2_queue	vbq;
+	struct list_head	wait_queue;
+	unsigned int		wait_queue_cnt;
+	struct list_head	run_queue;
+	unsigned int		run_queue_cnt;
+
+	struct fimc_is_buf	capture_bufs[SCALER_MAX_BUFS];
+	unsigned int		cap_buf_cnt;
+
+	const struct fimc_is_fmt *fmt;
+	unsigned int		width;
+	unsigned int		height;
+	unsigned long		capture_state;
+	unsigned int		buf_paddr[SCALER_MAX_BUFS][SCALER_MAX_PLANES];
+};
+
+int fimc_is_scaler_subdev_create(struct fimc_is_scaler *ctx,
+		enum fimc_is_scaler_id scaler_id,
+		struct vb2_alloc_ctx *alloc_ctx,
+		struct fimc_is_pipeline *pipeline);
+void fimc_is_scaler_subdev_destroy(struct fimc_is_scaler *scaler);
+
+#endif /* FIMC_IS_SCALER_H_ */
-- 
1.7.9.5

[RFC v3 08/13] [media] exynos5-fimc-is: Add sensor interface

[Arun Kumar K]

Some sensors to be used with fimc-is are exclusively controlled
by the fimc-is firmware. This minimal sensor driver provides
the required info for the firmware to configure the sensors
sitting on I2C bus.

Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
---
 drivers/media/platform/exynos5-is/fimc-is-sensor.c |   46 +++++++++++++
 drivers/media/platform/exynos5-is/fimc-is-sensor.h |   69 ++++++++++++++++++++
 2 files changed, 115 insertions(+)
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-sensor.c
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-sensor.h

diff --git a/drivers/media/platform/exynos5-is/fimc-is-sensor.c b/drivers/media/platform/exynos5-is/fimc-is-sensor.c
new file mode 100644
index 0000000..3e4aae9
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-sensor.c
@@ -0,0 +1,46 @@
+/*
+ * Samsung EXYNOS5250 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Authors:  Sylwester Nawrocki <s.nawrocki@samsung.com>
+ *           Arun Kumar K <arun.kk@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "fimc-is-sensor.h"
+
+static const struct sensor_drv_data s5k6a3_drvdata = {
+	.id		= FIMC_IS_SENSOR_ID_S5K6A3,
+	.open_timeout	= S5K6A3_OPEN_TIMEOUT,
+	.setfile_name	= "setfile_6a3.bin",
+};
+
+static const struct sensor_drv_data s5k4e5_drvdata = {
+	.id		= FIMC_IS_SENSOR_ID_S5K4E5,
+	.open_timeout	= S5K4E5_OPEN_TIMEOUT,
+	.setfile_name	= "setfile_4e5.bin",
+};
+
+static const struct of_device_id fimc_is_sensor_of_ids[] = {
+	{
+		.compatible	= "samsung,s5k6a3",
+		.data		= &s5k6a3_drvdata,
+	},
+	{
+		.compatible	= "samsung,s5k4e5",
+		.data		= &s5k4e5_drvdata,
+	},
+	{  }
+};
+
+const struct sensor_drv_data *exynos5_is_sensor_get_drvdata(
+			struct device_node *node)
+{
+	const struct of_device_id *of_id;
+
+	of_id = of_match_node(fimc_is_sensor_of_ids, node);
+	return of_id ? of_id->data : NULL;
+}
diff --git a/drivers/media/platform/exynos5-is/fimc-is-sensor.h b/drivers/media/platform/exynos5-is/fimc-is-sensor.h
new file mode 100644
index 0000000..51e18ea
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-sensor.h
@@ -0,0 +1,69 @@
+/*
+ * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ *
+ * Authors:  Sylwester Nawrocki <s.nawrocki@samsung.com>
+ *	     Younghwan Joo <yhwan.joo@samsung.com>
+ *	     Arun Kumar K <arun.kk@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef FIMC_IS_SENSOR_H_
+#define FIMC_IS_SENSOR_H_
+
+#include <linux/of.h>
+#include <linux/types.h>
+
+#define S5K6A3_OPEN_TIMEOUT		2000 /* ms */
+#define S5K6A3_SENSOR_WIDTH		1392
+#define S5K6A3_SENSOR_HEIGHT		1392
+
+#define S5K4E5_OPEN_TIMEOUT		2000 /* ms */
+#define S5K4E5_SENSOR_WIDTH		2560
+#define S5K4E5_SENSOR_HEIGHT		1920
+
+#define SENSOR_WIDTH_PADDING		16
+#define SENSOR_HEIGHT_PADDING		10
+
+enum fimc_is_sensor_id {
+	FIMC_IS_SENSOR_ID_S5K3H2 = 1,
+	FIMC_IS_SENSOR_ID_S5K6A3,
+	FIMC_IS_SENSOR_ID_S5K4E5,
+	FIMC_IS_SENSOR_ID_S5K3H7,
+	FIMC_IS_SENSOR_ID_CUSTOM,
+	FIMC_IS_SENSOR_ID_END
+};
+
+#define IS_SENSOR_CTRL_BUS_I2C0		0
+#define IS_SENSOR_CTRL_BUS_I2C1		1
+
+struct sensor_drv_data {
+	enum fimc_is_sensor_id id;
+	/* sensor open timeout in ms */
+	unsigned short open_timeout;
+	char *setfile_name;
+};
+
+/**
+ * struct fimc_is_sensor - fimc-is sensor data structure
+ * @drvdata: a pointer to the sensor's parameters data structure
+ * @i2c_bus: ISP I2C bus index (0...1)
+ * @test_pattern: true to enable video test pattern
+ */
+struct fimc_is_sensor {
+	const struct sensor_drv_data *drvdata;
+	unsigned int i2c_bus;
+	unsigned int width;
+	unsigned int height;
+	unsigned int pixel_width;
+	unsigned int pixel_height;
+	u8 test_pattern;
+};
+
+const struct sensor_drv_data *exynos5_is_sensor_get_drvdata(
+			struct device_node *node);
+
+#endif /* FIMC_IS_SENSOR_H_ */
-- 
1.7.9.5

[RFC v3 09/13] [media] exynos5-fimc-is: Add the hardware pipeline control

[Arun Kumar K]

This patch adds the crucial hardware pipeline control for the
fimc-is driver. All the subdev nodes will call this pipeline
interfaces to reach the hardware. Responsibilities of this module
involves configuring and maintaining the hardware pipeline involving
multiple sub-ips like ISP, DRC, Scalers, ODC, 3DNR, FD etc.

Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Kilyeon Im <kilyeon.im@samsung.com>
---
 .../media/platform/exynos5-is/fimc-is-pipeline.c   | 1961 ++++++++++++++++++++
 .../media/platform/exynos5-is/fimc-is-pipeline.h   |  129 ++
 2 files changed, 2090 insertions(+)
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-pipeline.c
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-pipeline.h

diff --git a/drivers/media/platform/exynos5-is/fimc-is-pipeline.c b/drivers/media/platform/exynos5-is/fimc-is-pipeline.c
new file mode 100644
index 0000000..070f1dc
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-pipeline.c
@@ -0,0 +1,1961 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+*
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K <arun.kk@samsung.com>
+ * Kil-yeon Lim <kilyeon.im@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "fimc-is.h"
+#include "fimc-is-pipeline.h"
+#include "fimc-is-metadata.h"
+#include "fimc-is-regs.h"
+#include "fimc-is-cmd.h"
+#include <media/videobuf2-dma-contig.h>
+#include <linux/delay.h>
+
+/* Default setting values */
+#define DEFAULT_PREVIEW_STILL_WIDTH		(1280) /* sensor margin : 16 */
+#define DEFAULT_PREVIEW_STILL_HEIGHT		(720) /* sensor margin : 12 */
+#define DEFAULT_CAPTURE_VIDEO_WIDTH		(1920)
+#define DEFAULT_CAPTURE_VIDEO_HEIGHT		(1080)
+#define DEFAULT_CAPTURE_STILL_WIDTH		(2560)
+#define DEFAULT_CAPTURE_STILL_HEIGHT		(1920)
+#define DEFAULT_CAPTURE_STILL_CROP_WIDTH	(2560)
+#define DEFAULT_CAPTURE_STILL_CROP_HEIGHT	(1440)
+#define DEFAULT_PREVIEW_VIDEO_WIDTH		(640)
+#define DEFAULT_PREVIEW_VIDEO_HEIGHT		(480)
+
+static void *fw_cookie;
+static void *shot_cookie;
+
+/* Init params for pipeline devices */
+static const struct sensor_param init_sensor_param = {
+	.frame_rate = {
+		.frame_rate = 30,
+	},
+};
+
+static const struct isp_param init_isp_param = {
+	.control = {
+		.cmd = CONTROL_COMMAND_START,
+		.bypass = CONTROL_BYPASS_DISABLE,
+		.err = CONTROL_ERROR_NONE,
+	},
+	.otf_input = {
+		.cmd = OTF_INPUT_COMMAND_DISABLE,
+		.width = DEFAULT_CAPTURE_STILL_WIDTH,
+		.height = DEFAULT_CAPTURE_STILL_HEIGHT,
+		.format = OTF_INPUT_FORMAT_BAYER,
+		.bitwidth = OTF_INPUT_BIT_WIDTH_10BIT,
+		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
+		.crop_offset_x = 0,
+		.crop_offset_y = 0,
+		.crop_width = 0,
+		.crop_height = 0,
+		.frametime_min = 0,
+		.frametime_max = 33333,
+		.err = OTF_INPUT_ERROR_NONE,
+	},
+	.dma1_input = {
+		.cmd = DMA_INPUT_COMMAND_DISABLE,
+		.width = 0,
+		.height = 0,
+		.format = 0,
+		.bitwidth = 0,
+		.plane = 0,
+		.order = 0,
+		.buffer_number = 0,
+		.buffer_address = 0,
+		.err = 0,
+	},
+	.dma2_input = {
+		.cmd = DMA_INPUT_COMMAND_DISABLE,
+		.width = 0, .height = 0,
+		.format = 0, .bitwidth = 0, .plane = 0,
+		.order = 0, .buffer_number = 0, .buffer_address = 0,
+		.err = 0,
+	},
+	.aa = {
+		.cmd = ISP_AA_COMMAND_START,
+		.target = ISP_AA_TARGET_AF | ISP_AA_TARGET_AE |
+						ISP_AA_TARGET_AWB,
+		.mode = ISP_AF_CONTINUOUS,
+		.scene = 0,
+		.sleep = 0,
+		.af_face = 0,
+		.touch_x = 0, .touch_y = 0,
+		.manual_af_setting = 0,
+		.err = ISP_AF_ERROR_NONE,
+	},
+	.flash = {
+		.cmd = ISP_FLASH_COMMAND_DISABLE,
+		.redeye = ISP_FLASH_REDEYE_DISABLE,
+		.err = ISP_FLASH_ERROR_NONE,
+	},
+	.awb = {
+		.cmd = ISP_AWB_COMMAND_AUTO,
+		.illumination = 0,
+		.err = ISP_AWB_ERROR_NONE,
+	},
+	.effect = {
+		.cmd = ISP_IMAGE_EFFECT_DISABLE,
+		.err = ISP_IMAGE_EFFECT_ERROR_NONE,
+	},
+	.iso = {
+		.cmd = ISP_ISO_COMMAND_AUTO,
+		.value = 0,
+		.err = ISP_ISO_ERROR_NONE,
+	},
+	.adjust = {
+		.cmd = ISP_ADJUST_COMMAND_AUTO,
+		.contrast = 0,
+		.saturation = 0,
+		.sharpness = 0,
+		.exposure = 0,
+		.brightness = 0,
+		.hue = 0,
+		.err = ISP_ADJUST_ERROR_NONE,
+	},
+	.metering = {
+		.cmd = ISP_METERING_COMMAND_CENTER,
+		.win_pos_x = 0, .win_pos_y = 0,
+		.win_width = DEFAULT_CAPTURE_STILL_WIDTH,
+		.win_height = DEFAULT_CAPTURE_STILL_HEIGHT,
+		.err = ISP_METERING_ERROR_NONE,
+	},
+	.afc = {
+		.cmd = ISP_AFC_COMMAND_AUTO,
+		.manual = 0, .err = ISP_AFC_ERROR_NONE,
+	},
+	.otf_output = {
+		.cmd = OTF_OUTPUT_COMMAND_ENABLE,
+		.width = DEFAULT_CAPTURE_STILL_WIDTH,
+		.height = DEFAULT_CAPTURE_STILL_HEIGHT,
+		.format = OTF_OUTPUT_FORMAT_YUV444,
+		.bitwidth = OTF_OUTPUT_BIT_WIDTH_12BIT,
+		.order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
+		.crop_offset_x = 0,
+		.crop_offset_y = 0,
+		.err = OTF_OUTPUT_ERROR_NONE,
+	},
+	.dma1_output = {
+		.cmd = DMA_OUTPUT_COMMAND_DISABLE,
+		.dma_out_mask = 0,
+		.width = DEFAULT_CAPTURE_STILL_WIDTH,
+		.height = DEFAULT_CAPTURE_STILL_HEIGHT,
+		.format = DMA_INPUT_FORMAT_YUV444,
+		.bitwidth = DMA_INPUT_BIT_WIDTH_8BIT,
+		.plane = DMA_INPUT_PLANE_1,
+		.order = DMA_INPUT_ORDER_YCBCR,
+		.buffer_number = 0,
+		.buffer_address = 0,
+		.err = DMA_OUTPUT_ERROR_NONE,
+	},
+	.dma2_output = {
+		.cmd = DMA_OUTPUT_COMMAND_DISABLE,
+		.width = DEFAULT_CAPTURE_STILL_WIDTH,
+		.height = DEFAULT_CAPTURE_STILL_HEIGHT,
+		.format = DMA_OUTPUT_FORMAT_BAYER,
+		.bitwidth = DMA_OUTPUT_BIT_WIDTH_12BIT,
+		.plane = DMA_OUTPUT_PLANE_1,
+		.order = DMA_OUTPUT_ORDER_GB_BG,
+		.buffer_number = 0,
+		.buffer_address = 0,
+		.dma_out_mask = 0xFFFFFFFF,
+		.err = DMA_OUTPUT_ERROR_NONE,
+	},
+};
+
+static const struct drc_param init_drc_param = {
+	.control = {
+		.cmd = CONTROL_COMMAND_START,
+		.bypass = CONTROL_BYPASS_ENABLE,
+		.err = CONTROL_ERROR_NONE,
+	},
+	.otf_input = {
+		.cmd = OTF_INPUT_COMMAND_ENABLE,
+		.width = DEFAULT_CAPTURE_STILL_WIDTH,
+		.height = DEFAULT_CAPTURE_STILL_HEIGHT,
+		.format = OTF_INPUT_FORMAT_YUV444,
+		.bitwidth = OTF_INPUT_BIT_WIDTH_12BIT,
+		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
+		.err = OTF_INPUT_ERROR_NONE,
+	},
+	.dma_input = {
+		.cmd = DMA_INPUT_COMMAND_DISABLE,
+		.width = DEFAULT_CAPTURE_STILL_WIDTH,
+		.height = DEFAULT_CAPTURE_STILL_HEIGHT,
+		.format = DMA_INPUT_FORMAT_YUV444,
+		.bitwidth = DMA_INPUT_BIT_WIDTH_8BIT,
+		.plane = DMA_INPUT_PLANE_1,
+		.order = DMA_INPUT_ORDER_YCBCR,
+		.buffer_number = 0,
+		.buffer_address = 0,
+		.err = 0,
+	},
+	.otf_output = {
+		.cmd = OTF_OUTPUT_COMMAND_ENABLE,
+		.width = DEFAULT_CAPTURE_STILL_WIDTH,
+		.height = DEFAULT_CAPTURE_STILL_HEIGHT,
+		.format = OTF_OUTPUT_FORMAT_YUV444,
+		.bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
+		.order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
+		.crop_offset_x = 0,
+		.crop_offset_y = 0,
+		.err = OTF_OUTPUT_ERROR_NONE,
+	},
+};
+
+static const struct scalerc_param init_scalerc_param = {
+	.control = {
+		.cmd = CONTROL_COMMAND_START,
+		.bypass = CONTROL_BYPASS_ENABLE,
+		.err = CONTROL_ERROR_NONE,
+	},
+	.otf_input = {
+		.cmd = OTF_INPUT_COMMAND_ENABLE,
+		.width = DEFAULT_CAPTURE_STILL_WIDTH,
+		.height = DEFAULT_CAPTURE_STILL_HEIGHT,
+		.format = OTF_INPUT_FORMAT_YUV444,
+		.bitwidth = OTF_INPUT_BIT_WIDTH_12BIT,
+		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
+		.crop_offset_x = 0,
+		.crop_offset_y = 0,
+		.crop_width = 0,
+		.crop_height = 0,
+		.err = OTF_INPUT_ERROR_NONE,
+	},
+	.effect = {
+		.cmd = 0,
+		.err = 0,
+	},
+	.input_crop = {
+		.cmd = OTF_INPUT_COMMAND_ENABLE,
+		.pos_x = 0,
+		.pos_y = 0,
+		.crop_width = DEFAULT_CAPTURE_STILL_CROP_WIDTH,
+		.crop_height = DEFAULT_CAPTURE_STILL_CROP_HEIGHT,
+		.in_width = DEFAULT_CAPTURE_STILL_WIDTH,
+		.in_height = DEFAULT_CAPTURE_STILL_HEIGHT,
+		.out_width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+		.out_height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+		.err = 0,
+	},
+	.output_crop = {
+		.cmd = SCALER_CROP_COMMAND_DISABLE,
+		.pos_x = 0,
+		.pos_y = 0,
+		.crop_width = DEFAULT_CAPTURE_STILL_WIDTH,
+		.crop_height = DEFAULT_CAPTURE_STILL_HEIGHT,
+		.format = DMA_OUTPUT_FORMAT_YUV420,
+		.err = 0,
+	},
+	.otf_output = {
+		.cmd = OTF_OUTPUT_COMMAND_ENABLE,
+		.width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+		.height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+		.format = OTF_OUTPUT_FORMAT_YUV444,
+		.bitwidth = OTF_OUTPUT_BIT_WIDTH_8BIT,
+		.order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
+		.crop_offset_x = 0,
+		.crop_offset_y = 0,
+		.err = OTF_OUTPUT_ERROR_NONE,
+	},
+	.dma_output = {
+		.cmd = DMA_OUTPUT_COMMAND_DISABLE,
+		.width = DEFAULT_CAPTURE_STILL_WIDTH,
+		.height = DEFAULT_CAPTURE_STILL_HEIGHT,
+		.format = DMA_OUTPUT_FORMAT_YUV420,
+		.bitwidth = DMA_OUTPUT_BIT_WIDTH_8BIT,
+		.plane = DMA_OUTPUT_PLANE_3,
+		.order = DMA_OUTPUT_ORDER_NONE,
+		.buffer_number = 0,
+		.buffer_address = 0,
+		.dma_out_mask = 0xffff,
+		.err = DMA_OUTPUT_ERROR_NONE,
+	},
+};
+
+static const struct odc_param init_odc_param = {
+	.control = {
+		.cmd = CONTROL_COMMAND_START,
+		.bypass = CONTROL_BYPASS_ENABLE,
+		.err = CONTROL_ERROR_NONE,
+	},
+	.otf_input = {
+		.cmd = OTF_INPUT_COMMAND_ENABLE,
+		.width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+		.height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+		.format = OTF_INPUT_FORMAT_YUV444,
+		.bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
+		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
+		.crop_offset_x = 0,
+		.crop_offset_y = 0,
+		.crop_width = 0,
+		.crop_height = 0,
+		.err = OTF_INPUT_ERROR_NONE,
+	},
+	.otf_output = {
+		.cmd = OTF_OUTPUT_COMMAND_ENABLE,
+		.width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+		.height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+		.format = OTF_OUTPUT_FORMAT_YUV422,
+		.bitwidth = OTF_OUTPUT_BIT_WIDTH_8BIT,
+		.order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
+		.crop_offset_x = 0,
+		.crop_offset_y = 0,
+		.err = OTF_OUTPUT_ERROR_NONE,
+	},
+};
+
+static const struct dis_param init_dis_param = {
+	.control = {
+		.cmd = CONTROL_COMMAND_START,
+		.bypass = CONTROL_BYPASS_ENABLE,
+		.err = CONTROL_ERROR_NONE,
+	},
+	.otf_input = {
+		.cmd = OTF_INPUT_COMMAND_ENABLE,
+		.width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+		.height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+		.format = OTF_INPUT_FORMAT_YUV422,
+		.bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
+		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
+		.crop_offset_x = 0,
+		.crop_offset_y = 0,
+		.crop_width = 0,
+		.crop_height = 0,
+		.err = OTF_INPUT_ERROR_NONE,
+	},
+	.otf_output = {
+		.cmd = OTF_OUTPUT_COMMAND_ENABLE,
+		.width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+		.height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+		.format = OTF_OUTPUT_FORMAT_YUV422,
+		.bitwidth = OTF_OUTPUT_BIT_WIDTH_8BIT,
+		.order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
+		.crop_offset_x = 0,
+		.crop_offset_y = 0,
+		.err = OTF_OUTPUT_ERROR_NONE,
+	},
+};
+static const struct tdnr_param init_tdnr_param = {
+	.control = {
+		.cmd = CONTROL_COMMAND_START,
+		.bypass = CONTROL_BYPASS_ENABLE,
+		.err = CONTROL_ERROR_NONE,
+	},
+	.otf_input = {
+		.cmd = OTF_INPUT_COMMAND_ENABLE,
+		.width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+		.height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+		.format = OTF_INPUT_FORMAT_YUV422,
+		.bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
+		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
+		.err = OTF_INPUT_ERROR_NONE,
+	},
+	.frame = {
+		.cmd = 0,
+		.err = 0,
+	},
+	.otf_output = {
+		.cmd = OTF_OUTPUT_COMMAND_ENABLE,
+		.width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+		.height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+		.format = OTF_OUTPUT_FORMAT_YUV444,
+		.bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
+		.order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
+		.crop_offset_x = 0,
+		.crop_offset_y = 0,
+		.err = OTF_OUTPUT_ERROR_NONE,
+	},
+	.dma_output = {
+		.cmd = DMA_OUTPUT_COMMAND_DISABLE,
+		.width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+		.height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+		.format = DMA_OUTPUT_FORMAT_YUV420,
+		.bitwidth = DMA_OUTPUT_BIT_WIDTH_8BIT,
+		.plane = DMA_OUTPUT_PLANE_2,
+		.order = DMA_OUTPUT_ORDER_CBCR,
+		.buffer_number = 0,
+		.buffer_address = 0,
+		.dma_out_mask = 0xffff,
+		.err = DMA_OUTPUT_ERROR_NONE,
+	},
+};
+
+static const struct scalerp_param init_scalerp_param = {
+	.control = {
+		.cmd = CONTROL_COMMAND_START,
+		.bypass = CONTROL_BYPASS_ENABLE,
+		.err = CONTROL_ERROR_NONE,
+	},
+	.otf_input = {
+		.cmd = OTF_INPUT_COMMAND_ENABLE,
+		.width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+		.height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+		.format = OTF_INPUT_FORMAT_YUV444,
+		.bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
+		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
+		.crop_offset_x = 0,
+		.crop_offset_y = 0,
+		.crop_width = 0,
+		.crop_height = 0,
+		.err = OTF_INPUT_ERROR_NONE,
+	},
+	.effect = {
+		.cmd = 0,
+		.err = 0,
+	},
+	.input_crop = {
+		.cmd = OTF_INPUT_COMMAND_ENABLE,
+		.pos_x = 0,
+		.pos_y = 0,
+		.crop_width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+		.crop_height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+		.in_width = DEFAULT_CAPTURE_VIDEO_WIDTH,
+		.in_height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
+		.out_width = DEFAULT_PREVIEW_STILL_WIDTH,
+		.out_height = DEFAULT_PREVIEW_STILL_HEIGHT,
+		.err = 0,
+	},
+	.output_crop = {
+		.cmd = SCALER_CROP_COMMAND_DISABLE,
+		.pos_x = 0,
+		.pos_y = 0,
+		.crop_width = DEFAULT_PREVIEW_STILL_WIDTH,
+		.crop_height = DEFAULT_PREVIEW_STILL_HEIGHT,
+		.format = OTF_OUTPUT_FORMAT_YUV420,
+		.err = 0,
+	},
+	.rotation = {
+		.cmd = 0,
+		.err = 0,
+	},
+	.flip = {
+		.cmd = 0,
+		.err = 0,
+	},
+	.otf_output = {
+		.cmd = OTF_OUTPUT_COMMAND_ENABLE,
+		.width = DEFAULT_PREVIEW_STILL_WIDTH,
+		.height = DEFAULT_PREVIEW_STILL_HEIGHT,
+		.format = OTF_INPUT_FORMAT_YUV444,
+		.bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
+		.order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
+		.crop_offset_x = 0,
+		.crop_offset_y = 0,
+		.err = OTF_OUTPUT_ERROR_NONE,
+	},
+	.dma_output = {
+		.cmd = DMA_OUTPUT_COMMAND_DISABLE,
+		.width = DEFAULT_PREVIEW_STILL_WIDTH,
+		.height = DEFAULT_PREVIEW_STILL_HEIGHT,
+		.format = OTF_OUTPUT_FORMAT_YUV420,
+		.bitwidth = DMA_OUTPUT_BIT_WIDTH_8BIT,
+		.plane = DMA_OUTPUT_PLANE_3,
+		.order = DMA_OUTPUT_ORDER_NONE,
+		.buffer_number = 0,
+		.buffer_address = 0,
+		.dma_out_mask = 0xffff,
+		.err = DMA_OUTPUT_ERROR_NONE,
+	},
+};
+
+static const struct fd_param init_fd_param = {
+	.control = {
+		.cmd = CONTROL_COMMAND_STOP,
+		.bypass = CONTROL_BYPASS_DISABLE,
+		.err = CONTROL_ERROR_NONE,
+	},
+	.otf_input = {
+		.cmd = OTF_INPUT_COMMAND_ENABLE,
+		.width = DEFAULT_PREVIEW_STILL_WIDTH,
+		.height = DEFAULT_PREVIEW_STILL_HEIGHT,
+		.format = OTF_INPUT_FORMAT_YUV444,
+		.bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
+		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
+		.err = OTF_INPUT_ERROR_NONE,
+	},
+	.dma_input = {
+		.cmd = DMA_INPUT_COMMAND_DISABLE,
+		.width = 0, .height = 0,
+		.format = 0, .bitwidth = 0, .plane = 0,
+		.order = 0, .buffer_number = 0, .buffer_address = 0,
+		.err = 0,
+	},
+	.config = {
+		.cmd = FD_CONFIG_COMMAND_MAXIMUM_NUMBER |
+			FD_CONFIG_COMMAND_ROLL_ANGLE |
+			FD_CONFIG_COMMAND_YAW_ANGLE |
+			FD_CONFIG_COMMAND_SMILE_MODE |
+			FD_CONFIG_COMMAND_BLINK_MODE |
+			FD_CONFIG_COMMAND_EYES_DETECT |
+			FD_CONFIG_COMMAND_MOUTH_DETECT |
+			FD_CONFIG_COMMAND_ORIENTATION |
+			FD_CONFIG_COMMAND_ORIENTATION_VALUE,
+		.max_number = CAMERA2_MAX_FACES,
+		.roll_angle = FD_CONFIG_ROLL_ANGLE_FULL,
+		.yaw_angle = FD_CONFIG_YAW_ANGLE_45_90,
+		.smile_mode = FD_CONFIG_SMILE_MODE_DISABLE,
+		.blink_mode = FD_CONFIG_BLINK_MODE_DISABLE,
+		.eye_detect = FD_CONFIG_EYES_DETECT_ENABLE,
+		.mouth_detect = FD_CONFIG_MOUTH_DETECT_DISABLE,
+		.orientation = FD_CONFIG_ORIENTATION_DISABLE,
+		.orientation_value = 0,
+		.err = ERROR_FD_NONE,
+	},
+};
+
+static int fimc_is_pipeline_create_subdevs(struct fimc_is_pipeline *pipeline)
+{
+	struct fimc_is *is = pipeline->is;
+	int ret;
+
+	/* ISP */
+	ret = fimc_is_isp_subdev_create(&pipeline->isp,
+			is->alloc_ctx, pipeline);
+	if (ret < 0)
+		return ret;
+
+	/* SCC scaler */
+	ret = fimc_is_scaler_subdev_create(&pipeline->scaler[SCALER_SCC],
+			SCALER_SCC, is->alloc_ctx, pipeline);
+	if (ret < 0)
+		return ret;
+
+	/* SCP scaler */
+	ret = fimc_is_scaler_subdev_create(&pipeline->scaler[SCALER_SCP],
+			SCALER_SCP, is->alloc_ctx, pipeline);
+	if (ret < 0)
+		return ret;
+
+	return ret;
+}
+
+static int fimc_is_pipeline_unregister_subdevs(struct fimc_is_pipeline *p)
+{
+	fimc_is_isp_subdev_destroy(&p->isp);
+	fimc_is_scaler_subdev_destroy(&p->scaler[SCALER_SCC]);
+	fimc_is_scaler_subdev_destroy(&p->scaler[SCALER_SCP]);
+
+	return 0;
+}
+
+int fimc_is_pipeline_init(struct fimc_is_pipeline *pipeline,
+			unsigned int instance, void *is_ctx)
+{
+	struct fimc_is *is = is_ctx;
+	unsigned int i;
+	int ret;
+
+	if (test_bit(PIPELINE_INIT, &pipeline->state)) {
+		pr_debug("Pipeline init already done.\n");
+		return -EINVAL;
+	}
+
+	/* Initialize context variables */
+	pipeline->instance = instance;
+	pipeline->is = is;
+	pipeline->minfo = &is->minfo;
+	pipeline->state = 0;
+	pipeline->force_down = false;
+	for (i = 0; i < FIMC_IS_NUM_COMPS; i++)
+		pipeline->comp_state[i] = 0;
+
+	spin_lock_init(&pipeline->slock_buf);
+	init_waitqueue_head(&pipeline->wait_q);
+	mutex_init(&pipeline->pipe_lock);
+	mutex_init(&pipeline->pipe_scl_lock);
+
+	ret = fimc_is_pipeline_create_subdevs(pipeline);
+	if (ret) {
+		pr_err("Subdev creation failed\n");
+		return -EINVAL;
+	}
+
+	/* Setting default width & height for scc & scp */
+	pipeline->scaler_width[SCALER_SCC] = DEFAULT_CAPTURE_VIDEO_WIDTH;
+	pipeline->scaler_height[SCALER_SCC] = DEFAULT_CAPTURE_VIDEO_HEIGHT;
+	pipeline->scaler_width[SCALER_SCP] = DEFAULT_PREVIEW_VIDEO_WIDTH;
+	pipeline->scaler_height[SCALER_SCP] = DEFAULT_PREVIEW_VIDEO_HEIGHT;
+
+	set_bit(PIPELINE_INIT, &pipeline->state);
+	return 0;
+}
+
+int fimc_is_pipeline_destroy(struct fimc_is_pipeline *pipeline)
+{
+	if (!pipeline)
+		return -EINVAL;
+
+	if (!test_bit(PIPELINE_INIT, &pipeline->state)) {
+		pr_debug("Pipeline not inited.\n");
+		return -EINVAL;
+	}
+	return fimc_is_pipeline_unregister_subdevs(pipeline);
+}
+
+static int fimc_is_pipeline_initmem(struct fimc_is_pipeline *pipeline,
+		struct vb2_alloc_ctx *alloc_ctx)
+{
+	struct fimc_is_meminfo *minfo = pipeline->minfo;
+	dma_addr_t *fw_phy_addr;
+	unsigned int offset;
+
+	/* Allocate memory */
+	pr_debug("Allocating memory : %d\n",
+			FIMC_IS_A5_MEM_SIZE + FIMC_IS_A5_SEN_SIZE);
+	fw_cookie = vb2_dma_contig_memops.alloc(alloc_ctx,
+			FIMC_IS_A5_MEM_SIZE + FIMC_IS_A5_SEN_SIZE,
+			GFP_KERNEL);
+
+	if (IS_ERR(fw_cookie)) {
+		pr_err("Error in allocating FW memory.\n");
+		return -ENOMEM;
+	}
+
+	fw_phy_addr = vb2_dma_contig_memops.cookie(fw_cookie);
+	/* FW memory should be 64MB aligned */
+	if (*fw_phy_addr & FIMC_IS_FW_BASE_MASK) {
+		pr_err("FW memory not 64MB aligned.\n");
+		vb2_dma_contig_memops.put(fw_cookie);
+		return -EIO;
+	}
+	minfo->fw_paddr = *fw_phy_addr;
+
+	minfo->fw_vaddr =
+		(unsigned int) vb2_dma_contig_memops.vaddr(fw_cookie);
+
+	pr_debug("FW |Phy Addr : 0x%08x, Virt Addr : 0x%08x\n",
+			minfo->fw_paddr, minfo->fw_vaddr);
+
+	/* Assigning memory regions */
+	offset = FIMC_IS_A5_MEM_SIZE - FIMC_IS_REGION_SIZE;
+	minfo->region_paddr = minfo->fw_paddr + offset;
+	minfo->region_vaddr = minfo->fw_vaddr + offset;
+	pipeline->is_region = (struct is_region *)minfo->region_vaddr;
+
+	minfo->shared_paddr = minfo->fw_paddr +
+		((unsigned int)&pipeline->is_region->shared[0] -
+		 minfo->fw_vaddr);
+	minfo->shared_vaddr = minfo->fw_vaddr +
+		((unsigned int)&pipeline->is_region->shared[0] -
+		 minfo->fw_vaddr);
+
+	/* Allocate shot buffer */
+	shot_cookie = vb2_dma_contig_memops.alloc(alloc_ctx,
+			sizeof(struct camera2_shot), GFP_KERNEL);
+	if (IS_ERR(shot_cookie)) {
+		pr_err("Error in allocating temp memory.\n");
+		return -ENOMEM;
+	}
+	fw_phy_addr = vb2_dma_contig_memops.cookie(shot_cookie);
+	pipeline->shot_paddr = *fw_phy_addr;
+	pipeline->shot_vaddr =
+		(unsigned int) vb2_dma_contig_memops.vaddr(shot_cookie);
+
+	return 0;
+}
+
+static void fimc_is_pipeline_freemem(struct fimc_is_pipeline *pipeline)
+{
+	if (fw_cookie)
+		vb2_dma_contig_memops.put(fw_cookie);
+	if (shot_cookie)
+		vb2_dma_contig_memops.put(shot_cookie);
+}
+
+static int fimc_is_pipeline_load_firmware(struct fimc_is_pipeline *pipeline)
+{
+	struct firmware *fw_blob;
+	struct fimc_is *is = pipeline->is;
+	int ret;
+
+	ret = request_firmware((const struct firmware **)&fw_blob,
+			"fimc-is-fw.bin", &is->pdev->dev);
+	if (ret != 0) {
+		pr_err("Firmware file not found\n");
+		return -EINVAL;
+	}
+	pr_debug("Firmware size : %d\n", fw_blob->size);
+	if (fw_blob->size > FIMC_IS_A5_MEM_SIZE + FIMC_IS_A5_SEN_SIZE) {
+		pr_err("Firmware file too big.\n");
+		release_firmware(fw_blob);
+		return -ENOMEM;
+	}
+
+	memcpy((void *)pipeline->minfo->fw_vaddr, fw_blob->data, fw_blob->size);
+	wmb();
+	release_firmware(fw_blob);
+
+	return 0;
+}
+
+static void fimc_is_pipeline_forcedown(struct fimc_is_pipeline *pipeline,
+		bool on)
+{
+	struct fimc_is *is = pipeline->is;
+	if (on) {
+		pr_debug("Set low poweroff mode\n");
+		pmu_is_write(0x0, is, PMUREG_ISP_ARM_OPTION);
+		pmu_is_write(0x1CF82000, is, PMUREG_ISP_LOW_POWER_OFF);
+		pipeline->force_down = true;
+	} else {
+		pr_debug("Clear low poweroff mode\n");
+		pmu_is_write(0xFFFFFFFF, is, PMUREG_ISP_ARM_OPTION);
+		pmu_is_write(0x8, is, PMUREG_ISP_LOW_POWER_OFF);
+		pipeline->force_down = false;
+	}
+}
+
+static int fimc_is_pipeline_power(struct fimc_is_pipeline *pipeline, int on)
+{
+	int ret = 0;
+	u32 timeout;
+	struct fimc_is *is = pipeline->is;
+	struct device *dev = &is->pdev->dev;
+
+	if (on) {
+		/* force poweroff setting */
+		if (pipeline->force_down)
+			fimc_is_pipeline_forcedown(pipeline, false);
+
+		/* FIMC-IS local power enable */
+		ret = pm_runtime_get_sync(dev);
+
+		/* A5 start address setting */
+		writel(pipeline->minfo->fw_paddr, is->interface.regs + BBOAR);
+
+		/* A5 power on*/
+		pmu_is_write(0x1, is, PMUREG_ISP_ARM_CONFIGURATION);
+
+		/* enable A5 */
+		pmu_is_write(0x00018000, is, PMUREG_ISP_ARM_OPTION);
+		timeout = 1000;
+		while ((pmu_is_read(is, PMUREG_ISP_ARM_STATUS) & 0x1) != 0x1) {
+			if (timeout == 0)
+				pr_err("A5 power on failed\n");
+			timeout--;
+			udelay(1);
+		}
+	} else {
+		/* disable A5 */
+		pmu_is_write(0x10000, is, PMUREG_ISP_ARM_OPTION);
+		/* A5 power off*/
+		pmu_is_write(0x0, is, PMUREG_ISP_ARM_CONFIGURATION);
+
+		/* Check A5 power off status register */
+		timeout = 1000;
+		while (pmu_is_read(is, PMUREG_ISP_ARM_STATUS) & 0x1) {
+			if (timeout == 0) {
+				pr_err("A5 power off failed\n");
+				fimc_is_pipeline_forcedown(pipeline, true);
+			}
+			timeout--;
+			udelay(1);
+		}
+
+		pmu_is_write(0x0, is, PMUREG_CMU_RESET_ISP_SYS_PWR_REG);
+
+		/* FIMC-IS local power down */
+		pm_runtime_put_sync(dev);
+	}
+
+	return ret;
+}
+
+static int fimc_is_pipeline_load_setfile(struct fimc_is_pipeline *pipeline,
+		unsigned int setfile_addr,
+		unsigned char *setfile_name)
+{
+	struct fimc_is *is = pipeline->is;
+	struct firmware *fw_blob;
+	int ret;
+
+	ret = request_firmware((const struct firmware **)&fw_blob,
+			setfile_name, &is->pdev->dev);
+	if (ret != 0) {
+		pr_err("Setfile %s not found\n", setfile_name);
+		return -EINVAL;
+	}
+
+	memcpy((void *)pipeline->minfo->fw_vaddr + setfile_addr,
+			fw_blob->data, fw_blob->size);
+	wmb();
+	release_firmware(fw_blob);
+
+	return 0;
+}
+
+static int fimc_is_pipeline_setfile(struct fimc_is_pipeline *pipeline)
+{
+	struct fimc_is *is = pipeline->is;
+	struct fimc_is_sensor *sensor = pipeline->sensor;
+	int ret;
+	unsigned int setfile_addr;
+
+	/* Get setfile addr from HW */
+	ret = fimc_is_itf_get_setfile_addr(&is->interface,
+			pipeline->instance, &setfile_addr);
+	if (ret < 0) {
+		pr_err("Get setfile addr failed.\n");
+		return ret;
+	}
+
+	if (!sensor->drvdata->setfile_name)
+		return -EINVAL;
+
+	/* Load setfile */
+	ret = fimc_is_pipeline_load_setfile(pipeline, setfile_addr,
+			sensor->drvdata->setfile_name);
+	if (ret < 0) {
+		pr_err("Load setfile failed.\n");
+		return ret;
+	}
+
+	/* Send HW command */
+	ret = fimc_is_itf_load_setfile(&is->interface, pipeline->instance);
+	if (ret < 0) {
+		pr_err("HW Load setfile failed.\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int fimc_is_pipeline_isp_setparams(struct fimc_is_pipeline *pipeline,
+		unsigned int enable)
+{
+	struct isp_param *isp_param = &pipeline->is_region->parameter.isp;
+	struct fimc_is *is = pipeline->is;
+	unsigned int indexes, lindex, hindex;
+	unsigned int sensor_width, sensor_height, scc_width, scc_height;
+	unsigned int crop_x, crop_y, isp_width, isp_height;
+	unsigned int sensor_ratio, output_ratio;
+	int ret;
+
+	/* Crop calculation */
+	sensor_width = pipeline->sensor_width;
+	sensor_height = pipeline->sensor_height;
+	scc_width = pipeline->scaler_width[SCALER_SCC];
+	scc_height = pipeline->scaler_height[SCALER_SCC];
+	isp_width = sensor_width;
+	isp_height = sensor_height;
+	crop_x = crop_y = 0;
+
+	sensor_ratio = sensor_width * 1000 / sensor_height;
+	output_ratio = scc_width * 1000 / scc_height;
+
+	if (sensor_ratio == output_ratio) {
+		isp_width = sensor_width;
+		isp_height = sensor_height;
+	} else if (sensor_ratio < output_ratio) {
+		isp_height = (sensor_width * scc_height) / scc_width;
+		isp_height = ALIGN(isp_height, 2);
+		crop_y = ((sensor_height - isp_height) >> 1) & 0xFFFFFFFE;
+	} else {
+		isp_width = (sensor_height * scc_width) / scc_height;
+		isp_width = ALIGN(isp_width, 4);
+		crop_x =  ((sensor_width - isp_width) >> 1) & 0xFFFFFFFE;
+	}
+	pipeline->isp_width = isp_width;
+	pipeline->isp_height = isp_height;
+
+	indexes = hindex = lindex = 0;
+
+	isp_param->otf_output.cmd = OTF_OUTPUT_COMMAND_ENABLE;
+	isp_param->otf_output.width = pipeline->sensor_width;
+	isp_param->otf_output.height = pipeline->sensor_height;
+	isp_param->otf_output.format = OTF_OUTPUT_FORMAT_YUV444;
+	isp_param->otf_output.bitwidth = OTF_OUTPUT_BIT_WIDTH_12BIT;
+	isp_param->otf_output.order = OTF_INPUT_ORDER_BAYER_GR_BG;
+	lindex |= LOWBIT_OF(PARAM_ISP_OTF_OUTPUT);
+	hindex |= HIGHBIT_OF(PARAM_ISP_OTF_OUTPUT);
+	indexes++;
+
+	isp_param->dma1_output.cmd = DMA_OUTPUT_COMMAND_DISABLE;
+	lindex |= LOWBIT_OF(PARAM_ISP_DMA1_OUTPUT);
+	hindex |= HIGHBIT_OF(PARAM_ISP_DMA1_OUTPUT);
+	indexes++;
+
+	isp_param->dma2_output.cmd = DMA_OUTPUT_COMMAND_DISABLE;
+	lindex |= LOWBIT_OF(PARAM_ISP_DMA2_OUTPUT);
+	hindex |= HIGHBIT_OF(PARAM_ISP_DMA2_OUTPUT);
+	indexes++;
+
+	if (enable)
+		isp_param->control.bypass = CONTROL_BYPASS_DISABLE;
+	else
+		isp_param->control.bypass = CONTROL_BYPASS_ENABLE;
+	isp_param->control.cmd = CONTROL_COMMAND_START;
+	isp_param->control.run_mode = 1;
+	lindex |= LOWBIT_OF(PARAM_ISP_CONTROL);
+	hindex |= HIGHBIT_OF(PARAM_ISP_CONTROL);
+	indexes++;
+
+	isp_param->dma1_input.cmd = DMA_INPUT_COMMAND_BUF_MNGR;
+	isp_param->dma1_input.width = sensor_width;
+	isp_param->dma1_input.height = sensor_height;
+	isp_param->dma1_input.dma_crop_offset_x = crop_x;
+	isp_param->dma1_input.dma_crop_offset_y = crop_y;
+	isp_param->dma1_input.dma_crop_width = isp_width;
+	isp_param->dma1_input.dma_crop_height = isp_height;
+	isp_param->dma1_input.bayer_crop_offset_x = 0;
+	isp_param->dma1_input.bayer_crop_offset_y = 0;
+	isp_param->dma1_input.bayer_crop_width = 0;
+	isp_param->dma1_input.bayer_crop_height = 0;
+	isp_param->dma1_input.user_min_frametime = 0;
+	isp_param->dma1_input.user_max_frametime = 66666;
+	isp_param->dma1_input.wide_frame_gap = 1;
+	isp_param->dma1_input.frame_gap = 4096;
+	isp_param->dma1_input.line_gap = 45;
+	isp_param->dma1_input.order = DMA_INPUT_ORDER_GR_BG;
+	isp_param->dma1_input.plane = 1;
+	isp_param->dma1_input.buffer_number = 1;
+	isp_param->dma1_input.buffer_address = 0;
+	isp_param->dma1_input.reserved[1] = 0;
+	isp_param->dma1_input.reserved[2] = 0;
+	if (pipeline->isp.fmt->fourcc == V4L2_PIX_FMT_SGRBG8)
+		isp_param->dma1_input.bitwidth = DMA_INPUT_BIT_WIDTH_8BIT;
+	else if (pipeline->isp.fmt->fourcc == V4L2_PIX_FMT_SGRBG10)
+		isp_param->dma1_input.bitwidth = DMA_INPUT_BIT_WIDTH_10BIT;
+	else
+		isp_param->dma1_input.bitwidth = DMA_INPUT_BIT_WIDTH_12BIT;
+	lindex |= LOWBIT_OF(PARAM_ISP_DMA1_INPUT);
+	hindex |= HIGHBIT_OF(PARAM_ISP_DMA1_INPUT);
+	indexes++;
+
+	lindex = 0xFFFFFFFF;
+	hindex = 0xFFFFFFFF;
+
+	wmb();
+	ret = fimc_is_itf_set_param(&is->interface, pipeline->instance,
+			indexes, lindex, hindex);
+	if (ret) {
+		pr_err("fimc_is_itf_set_param failed\n");
+		return -EINVAL;
+	}
+
+	set_bit(COMP_ENABLE, &pipeline->comp_state[IS_ISP]);
+
+	return 0;
+}
+
+static int fimc_is_pipeline_drc_setparams(struct fimc_is_pipeline *pipeline,
+		unsigned int enable)
+{
+	struct drc_param *drc_param = &pipeline->is_region->parameter.drc;
+	struct fimc_is *is = pipeline->is;
+	int ret;
+	unsigned int indexes, lindex, hindex;
+
+	indexes = hindex = lindex = 0;
+	if (enable)
+		drc_param->control.bypass = CONTROL_BYPASS_DISABLE;
+	else
+		drc_param->control.bypass = CONTROL_BYPASS_ENABLE;
+	lindex |= LOWBIT_OF(PARAM_DRC_CONTROL);
+	hindex |= HIGHBIT_OF(PARAM_DRC_CONTROL);
+	indexes++;
+
+	drc_param->otf_input.cmd = OTF_INPUT_COMMAND_ENABLE;
+	drc_param->otf_input.width = pipeline->isp_width;
+	drc_param->otf_input.height = pipeline->isp_height;
+	lindex |= LOWBIT_OF(PARAM_DRC_OTF_INPUT);
+	hindex |= HIGHBIT_OF(PARAM_DRC_OTF_INPUT);
+	indexes++;
+
+	drc_param->otf_output.cmd = OTF_OUTPUT_COMMAND_ENABLE;
+	drc_param->otf_output.width = pipeline->isp_width;
+	drc_param->otf_output.height = pipeline->isp_height;
+	lindex |= LOWBIT_OF(PARAM_DRC_OTF_OUTPUT);
+	hindex |= HIGHBIT_OF(PARAM_DRC_OTF_OUTPUT);
+	indexes++;
+
+	wmb();
+	ret = fimc_is_itf_set_param(&is->interface, pipeline->instance,
+			indexes, lindex, hindex);
+	if (ret) {
+		pr_err("fimc_is_itf_set_param failed\n");
+		return -EINVAL;
+	}
+	if (enable)
+		set_bit(COMP_ENABLE, &pipeline->comp_state[IS_DRC]);
+	else
+		clear_bit(COMP_ENABLE, &pipeline->comp_state[IS_DRC]);
+
+	return 0;
+}
+
+static int fimc_is_pipeline_scc_setparams(struct fimc_is_pipeline *pipeline,
+		unsigned int enable)
+{
+	struct scalerc_param *scc_param =
+		&pipeline->is_region->parameter.scalerc;
+	struct fimc_is *is = pipeline->is;
+	int ret;
+	unsigned int indexes, lindex, hindex;
+	unsigned int scc_width, scc_height;
+
+	scc_width = pipeline->scaler_width[SCALER_SCC];
+	scc_height = pipeline->scaler_height[SCALER_SCC];
+
+	indexes = hindex = lindex = 0;
+	if (enable)
+		scc_param->control.bypass = CONTROL_BYPASS_DISABLE;
+	else
+		scc_param->control.bypass = CONTROL_BYPASS_ENABLE;
+	lindex |= LOWBIT_OF(PARAM_SCALERC_CONTROL);
+	hindex |= HIGHBIT_OF(PARAM_SCALERC_CONTROL);
+	indexes++;
+
+	scc_param->otf_input.cmd = OTF_INPUT_COMMAND_ENABLE;
+	scc_param->otf_input.width = pipeline->isp_width;
+	scc_param->otf_input.height = pipeline->isp_height;
+	lindex |= LOWBIT_OF(PARAM_SCALERC_OTF_INPUT);
+	hindex |= HIGHBIT_OF(PARAM_SCALERC_OTF_INPUT);
+	indexes++;
+
+	/* SCC OUTPUT */
+	scc_param->input_crop.cmd = SCALER_CROP_COMMAND_ENABLE;
+	scc_param->input_crop.pos_x = 0;
+	scc_param->input_crop.pos_y = 0;
+	scc_param->input_crop.crop_width = pipeline->isp_width;
+	scc_param->input_crop.crop_height = pipeline->isp_height;
+	scc_param->input_crop.in_width = pipeline->isp_width;
+	scc_param->input_crop.in_height = pipeline->isp_height;
+	scc_param->input_crop.out_width = scc_width;
+	scc_param->input_crop.out_height = scc_height;
+	lindex |= LOWBIT_OF(PARAM_SCALERC_INPUT_CROP);
+	hindex |= HIGHBIT_OF(PARAM_SCALERC_INPUT_CROP);
+	indexes++;
+
+	scc_param->output_crop.cmd = SCALER_CROP_COMMAND_DISABLE;
+	scc_param->output_crop.pos_x = 0;
+	scc_param->output_crop.pos_y = 0;
+	scc_param->output_crop.crop_width = scc_width;
+	scc_param->output_crop.crop_height = scc_height;
+	lindex |= LOWBIT_OF(PARAM_SCALERC_OUTPUT_CROP);
+	hindex |= HIGHBIT_OF(PARAM_SCALERC_OUTPUT_CROP);
+	indexes++;
+
+	scc_param->otf_output.cmd = OTF_OUTPUT_COMMAND_ENABLE;
+	scc_param->otf_output.width = scc_width;
+	scc_param->otf_output.height = scc_height;
+	lindex |= LOWBIT_OF(PARAM_SCALERC_OTF_OUTPUT);
+	hindex |= HIGHBIT_OF(PARAM_SCALERC_OTF_OUTPUT);
+	indexes++;
+
+	scc_param->dma_output.width = scc_width;
+	scc_param->dma_output.height = scc_height;
+	lindex |= LOWBIT_OF(PARAM_SCALERC_DMA_OUTPUT);
+	hindex |= HIGHBIT_OF(PARAM_SCALERC_DMA_OUTPUT);
+	indexes++;
+
+	wmb();
+	ret = fimc_is_itf_set_param(&is->interface, pipeline->instance,
+			indexes, lindex, hindex);
+	if (ret) {
+		pr_err("fimc_is_itf_set_param failed\n");
+		return -EINVAL;
+	}
+	set_bit(COMP_ENABLE, &pipeline->comp_state[IS_SCC]);
+	return 0;
+}
+
+static int fimc_is_pipeline_odc_setparams(struct fimc_is_pipeline *pipeline,
+		unsigned int enable)
+{
+	struct odc_param *odc_param = &pipeline->is_region->parameter.odc;
+	struct fimc_is *is = pipeline->is;
+	int ret;
+	unsigned int indexes, lindex, hindex;
+	unsigned int scc_width, scc_height;
+
+	scc_width = pipeline->scaler_width[SCALER_SCC];
+	scc_height = pipeline->scaler_height[SCALER_SCC];
+
+	indexes = hindex = lindex = 0;
+	if (enable)
+		odc_param->control.bypass = CONTROL_BYPASS_DISABLE;
+	else
+		odc_param->control.bypass = CONTROL_BYPASS_ENABLE;
+	lindex |= LOWBIT_OF(PARAM_ODC_CONTROL);
+	hindex |= HIGHBIT_OF(PARAM_ODC_CONTROL);
+	indexes++;
+
+	odc_param->otf_input.width = scc_width;
+	odc_param->otf_input.height = scc_height;
+	lindex |= LOWBIT_OF(PARAM_ODC_OTF_INPUT);
+	hindex |= HIGHBIT_OF(PARAM_ODC_OTF_INPUT);
+	indexes++;
+
+	odc_param->otf_output.width = scc_width;
+	odc_param->otf_output.height = scc_height;
+	lindex |= LOWBIT_OF(PARAM_ODC_OTF_OUTPUT);
+	hindex |= HIGHBIT_OF(PARAM_ODC_OTF_OUTPUT);
+	indexes++;
+
+	wmb();
+	ret = fimc_is_itf_set_param(&is->interface, pipeline->instance,
+			indexes, lindex, hindex);
+	if (ret) {
+		pr_err("fimc_is_itf_set_param failed\n");
+		return -EINVAL;
+	}
+	if (enable)
+		set_bit(COMP_ENABLE, &pipeline->comp_state[IS_ODC]);
+	else
+		clear_bit(COMP_ENABLE, &pipeline->comp_state[IS_ODC]);
+
+	return 0;
+}
+
+static int fimc_is_pipeline_dis_setparams(struct fimc_is_pipeline *pipeline,
+		unsigned int enable)
+{
+	struct dis_param *dis_param = &pipeline->is_region->parameter.dis;
+	struct fimc_is *is = pipeline->is;
+	int ret;
+	unsigned int indexes, lindex, hindex;
+	unsigned int scc_width, scc_height;
+
+	scc_width = pipeline->scaler_width[SCALER_SCC];
+	scc_height = pipeline->scaler_height[SCALER_SCC];
+
+	indexes = hindex = lindex = 0;
+	if (enable)
+		dis_param->control.bypass = CONTROL_BYPASS_DISABLE;
+	else
+		dis_param->control.bypass = CONTROL_BYPASS_ENABLE;
+	lindex |= LOWBIT_OF(PARAM_DIS_CONTROL);
+	hindex |= HIGHBIT_OF(PARAM_DIS_CONTROL);
+	indexes++;
+
+	/* DIS INPUT */
+	dis_param->otf_input.width = scc_width;
+	dis_param->otf_input.height = scc_height;
+	lindex |= LOWBIT_OF(PARAM_DIS_OTF_INPUT);
+	hindex |= HIGHBIT_OF(PARAM_DIS_OTF_INPUT);
+	indexes++;
+
+	/* DIS OUTPUT */
+	dis_param->otf_output.width = scc_width;
+	dis_param->otf_output.height = scc_height;
+	lindex |= LOWBIT_OF(PARAM_DIS_OTF_OUTPUT);
+	hindex |= HIGHBIT_OF(PARAM_DIS_OTF_OUTPUT);
+	indexes++;
+
+	wmb();
+	ret = fimc_is_itf_set_param(&is->interface, pipeline->instance,
+			indexes, lindex, hindex);
+	if (ret) {
+		pr_err("fimc_is_itf_set_param failed\n");
+		return -EINVAL;
+	}
+	if (enable)
+		set_bit(COMP_ENABLE, &pipeline->comp_state[IS_DIS]);
+	else
+		clear_bit(COMP_ENABLE, &pipeline->comp_state[IS_DIS]);
+
+	return 0;
+}
+
+static int fimc_is_pipeline_3dnr_setparams(struct fimc_is_pipeline *pipeline,
+		unsigned int enable)
+{
+	struct tdnr_param *tdnr_param = &pipeline->is_region->parameter.tdnr;
+	struct fimc_is *is = pipeline->is;
+	int ret;
+	unsigned int indexes, lindex, hindex;
+	unsigned int scc_width, scc_height;
+
+	scc_width = pipeline->scaler_width[SCALER_SCC];
+	scc_height = pipeline->scaler_height[SCALER_SCC];
+
+	indexes = hindex = lindex = 0;
+	if (enable)
+		tdnr_param->control.bypass = CONTROL_BYPASS_DISABLE;
+	else
+		tdnr_param->control.bypass = CONTROL_BYPASS_ENABLE;
+	lindex |= LOWBIT_OF(PARAM_TDNR_CONTROL);
+	hindex |= HIGHBIT_OF(PARAM_TDNR_CONTROL);
+	indexes++;
+
+	tdnr_param->otf_input.width = scc_width;
+	tdnr_param->otf_input.height = scc_height;
+	lindex |= LOWBIT_OF(PARAM_TDNR_OTF_INPUT);
+	hindex |= HIGHBIT_OF(PARAM_TDNR_OTF_INPUT);
+	indexes++;
+
+	tdnr_param->dma_output.width = scc_width;
+	tdnr_param->dma_output.height = scc_height;
+	lindex |= LOWBIT_OF(PARAM_TDNR_DMA_OUTPUT);
+	hindex |= HIGHBIT_OF(PARAM_TDNR_DMA_OUTPUT);
+	indexes++;
+
+	tdnr_param->otf_output.width = scc_width;
+	tdnr_param->otf_output.height = scc_height;
+	lindex |= LOWBIT_OF(PARAM_TDNR_OTF_OUTPUT);
+	hindex |= HIGHBIT_OF(PARAM_TDNR_OTF_OUTPUT);
+	indexes++;
+
+	wmb();
+	ret = fimc_is_itf_set_param(&is->interface, pipeline->instance,
+			indexes, lindex, hindex);
+	if (ret) {
+		pr_err("fimc_is_itf_set_param failed\n");
+		return -EINVAL;
+	}
+	if (enable)
+		set_bit(COMP_ENABLE, &pipeline->comp_state[IS_TDNR]);
+	else
+		clear_bit(COMP_ENABLE, &pipeline->comp_state[IS_TDNR]);
+
+	return 0;
+}
+
+static int fimc_is_pipeline_scp_setparams(struct fimc_is_pipeline *pipeline,
+		unsigned int enable)
+{
+	struct scalerp_param *scp_param =
+		&pipeline->is_region->parameter.scalerp;
+	struct fimc_is *is = pipeline->is;
+	int ret;
+	unsigned int indexes, lindex, hindex;
+	unsigned int scc_width, scc_height;
+	unsigned int scp_width, scp_height;
+
+	scc_width = pipeline->scaler_width[SCALER_SCC];
+	scc_height = pipeline->scaler_height[SCALER_SCC];
+	scp_width = pipeline->scaler_width[SCALER_SCP];
+	scp_height = pipeline->scaler_height[SCALER_SCP];
+
+	indexes = hindex = lindex = 0;
+	if (enable)
+		scp_param->control.bypass = CONTROL_BYPASS_DISABLE;
+	else
+		scp_param->control.bypass = CONTROL_BYPASS_ENABLE;
+	lindex |= LOWBIT_OF(PARAM_SCALERP_CONTROL);
+	hindex |= HIGHBIT_OF(PARAM_SCALERP_CONTROL);
+	indexes++;
+
+	/* SCP Input */
+	scp_param->otf_input.width = scc_width;
+	scp_param->otf_input.height = scc_height;
+	lindex |= LOWBIT_OF(PARAM_SCALERP_OTF_INPUT);
+	hindex |= HIGHBIT_OF(PARAM_SCALERP_OTF_INPUT);
+	indexes++;
+
+	/* SCP Output */
+	scp_param->input_crop.cmd = SCALER_CROP_COMMAND_ENABLE;
+	scp_param->input_crop.pos_x = 0;
+	scp_param->input_crop.pos_y = 0;
+	scp_param->input_crop.crop_width = scc_width;
+	scp_param->input_crop.crop_height = scc_height;
+	scp_param->input_crop.in_width = scc_width;
+	scp_param->input_crop.in_height = scc_height;
+	scp_param->input_crop.out_width = scp_width;
+	scp_param->input_crop.out_height = scp_height;
+	lindex |= LOWBIT_OF(PARAM_SCALERP_INPUT_CROP);
+	hindex |= HIGHBIT_OF(PARAM_SCALERP_INPUT_CROP);
+	indexes++;
+
+	scp_param->output_crop.cmd = SCALER_CROP_COMMAND_DISABLE;
+	lindex |= LOWBIT_OF(PARAM_SCALERP_OUTPUT_CROP);
+	hindex |= HIGHBIT_OF(PARAM_SCALERP_OUTPUT_CROP);
+	indexes++;
+
+	scp_param->otf_output.width = scp_width;
+	scp_param->otf_output.height = scp_height;
+	lindex |= LOWBIT_OF(PARAM_SCALERP_OTF_OUTPUT);
+	hindex |= HIGHBIT_OF(PARAM_SCALERP_OTF_OUTPUT);
+	indexes++;
+
+	scp_param->dma_output.width = scp_width;
+	scp_param->dma_output.height = scp_height;
+	lindex |= LOWBIT_OF(PARAM_SCALERP_DMA_OUTPUT);
+	hindex |= HIGHBIT_OF(PARAM_SCALERP_DMA_OUTPUT);
+	indexes++;
+
+	wmb();
+	ret = fimc_is_itf_set_param(&is->interface, pipeline->instance,
+			indexes, lindex, hindex);
+	if (ret) {
+		pr_err("fimc_is_itf_set_param failed\n");
+		return -EINVAL;
+	}
+	set_bit(COMP_ENABLE, &pipeline->comp_state[IS_SCP]);
+
+	return 0;
+}
+
+static int fimc_is_pipeline_fd_setparams(struct fimc_is_pipeline *pipeline,
+		unsigned int enable)
+{
+	struct fd_param *fd_param = &pipeline->is_region->parameter.fd;
+	struct fimc_is *is = pipeline->is;
+	int ret;
+	unsigned int indexes, lindex, hindex;
+
+	indexes = hindex = lindex = 0;
+	if (enable)
+		fd_param->control.bypass = CONTROL_BYPASS_DISABLE;
+	else
+		fd_param->control.bypass = CONTROL_BYPASS_ENABLE;
+	lindex |= LOWBIT_OF(PARAM_FD_CONTROL);
+	hindex |= HIGHBIT_OF(PARAM_FD_CONTROL);
+	indexes++;
+
+	fd_param->otf_input.width = pipeline->scaler_width[SCALER_SCP];
+	fd_param->otf_input.height = pipeline->scaler_height[SCALER_SCP];
+	lindex |= LOWBIT_OF(PARAM_FD_OTF_INPUT);
+	hindex |= HIGHBIT_OF(PARAM_FD_OTF_INPUT);
+	indexes++;
+
+	wmb();
+	ret = fimc_is_itf_set_param(&is->interface, pipeline->instance,
+			indexes, lindex, hindex);
+	if (ret) {
+		pr_err("fimc_is_itf_set_param failed\n");
+		return -EINVAL;
+	}
+	if (enable)
+		set_bit(COMP_ENABLE, &pipeline->comp_state[IS_FD]);
+	else
+		clear_bit(COMP_ENABLE, &pipeline->comp_state[IS_FD]);
+
+	return 0;
+}
+
+void fimc_is_pipeline_buf_lock(struct fimc_is_pipeline *pipeline)
+{
+	spin_lock_irqsave(&pipeline->slock_buf, pipeline->slock_flags);
+}
+
+void fimc_is_pipeline_buf_unlock(struct fimc_is_pipeline *pipeline)
+{
+	spin_unlock_irqrestore(&pipeline->slock_buf, pipeline->slock_flags);
+}
+
+int fimc_is_pipeline_setparams(struct fimc_is_pipeline *pipeline)
+{
+	int ret;
+
+	/* Enabling basic components in pipeline */
+	ret = fimc_is_pipeline_isp_setparams(pipeline, true);
+	ret |= fimc_is_pipeline_drc_setparams(pipeline, false);
+	ret |= fimc_is_pipeline_scc_setparams(pipeline, true);
+	ret |= fimc_is_pipeline_odc_setparams(pipeline, false);
+	ret |= fimc_is_pipeline_dis_setparams(pipeline, false);
+	ret |= fimc_is_pipeline_3dnr_setparams(pipeline, false);
+	ret |= fimc_is_pipeline_scp_setparams(pipeline, true);
+	ret |= fimc_is_pipeline_fd_setparams(pipeline, false);
+	if (ret < 0)
+		pr_err("Pipeline setparam failed.\n");
+
+	return ret;
+}
+
+int fimc_is_pipeline_scaler_start(struct fimc_is_pipeline *pipeline,
+		enum fimc_is_scaler_id scaler_id,
+		unsigned int **buf_paddr,
+		unsigned int num_bufs,
+		unsigned int num_planes)
+{
+	struct fimc_is *is = pipeline->is;
+	struct scalerp_param *scp_param =
+		&pipeline->is_region->parameter.scalerp;
+	struct scalerc_param *scc_param =
+		&pipeline->is_region->parameter.scalerc;
+	struct param_dma_output *dma_output;
+	const struct fimc_is_fmt *fmt;
+	unsigned int region_index;
+	unsigned long *comp_state;
+	int ret;
+	unsigned int pipe_start_flag = 0;
+	unsigned int i, j, buf_index, buf_mask = 0;
+	unsigned int indexes, lindex, hindex;
+
+	if (!test_bit(PIPELINE_OPEN, &pipeline->state)) {
+		pr_err("Pipeline not opened.\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&pipeline->pipe_scl_lock);
+
+	if (test_bit(PIPELINE_START, &pipeline->state)) {
+		/* Pipeline is started.
+		 * Stop it now to set params and start again */
+		ret = fimc_is_pipeline_stop(pipeline);
+		if (ret) {
+			pr_err("Not able to stop pipeline\n");
+			goto exit;
+		}
+		pipe_start_flag = 1;
+	}
+
+	indexes = lindex = hindex = 0;
+
+	if (scaler_id == SCALER_SCC) {
+		dma_output = &scc_param->dma_output;
+		region_index = FIMC_IS_SCC_REGION_INDEX;
+		comp_state = &pipeline->comp_state[IS_SCC];
+		fmt = pipeline->scaler[SCALER_SCC].fmt;
+		lindex |= LOWBIT_OF(PARAM_SCALERC_DMA_OUTPUT);
+		hindex |= HIGHBIT_OF(PARAM_SCALERC_DMA_OUTPUT);
+	} else {
+		dma_output = &scp_param->dma_output;
+		comp_state = &pipeline->comp_state[IS_SCP];
+		fmt = pipeline->scaler[SCALER_SCC].fmt;
+		region_index = FIMC_IS_SCP_REGION_INDEX;
+		lindex |= LOWBIT_OF(PARAM_SCALERP_DMA_OUTPUT);
+		hindex |= HIGHBIT_OF(PARAM_SCALERP_DMA_OUTPUT);
+	}
+	indexes++;
+
+	for (i = 0; i < num_bufs; i++) {
+		for (j = 0; j < num_planes; j++) {
+			buf_index = i * num_planes + j;
+			pipeline->is_region->shared[region_index + buf_index] =
+				(unsigned int) &buf_paddr[i][j];
+		}
+		buf_mask |= (1 << i);
+	}
+
+	dma_output->cmd = DMA_OUTPUT_COMMAND_ENABLE;
+	dma_output->dma_out_mask = buf_mask;
+	dma_output->buffer_number = num_bufs;
+	dma_output->plane = num_planes;
+	if ((fmt->fourcc == V4L2_PIX_FMT_YUV420M) ||
+			(fmt->fourcc == V4L2_PIX_FMT_NV12M))
+		dma_output->format = DMA_OUTPUT_FORMAT_YUV420;
+	else if (fmt->fourcc == V4L2_PIX_FMT_NV16)
+		dma_output->format = DMA_OUTPUT_FORMAT_YUV422;
+
+	dma_output->buffer_address = pipeline->minfo->shared_paddr +
+				region_index * sizeof(unsigned int);
+
+	ret = fimc_is_itf_set_param(&is->interface, pipeline->instance,
+			indexes, lindex, hindex);
+	if (ret)
+		pr_err("fimc_is_itf_set_param is fail\n");
+	else
+		set_bit(COMP_START, comp_state);
+
+	if (pipe_start_flag) {
+		ret = fimc_is_pipeline_start(pipeline);
+		if (ret) {
+			pr_err("Not able to start pipeline back\n");
+			goto exit;
+		}
+	}
+
+exit:
+	mutex_unlock(&pipeline->pipe_scl_lock);
+	return ret;
+}
+
+int fimc_is_pipeline_scaler_stop(struct fimc_is_pipeline *pipeline,
+		enum fimc_is_scaler_id scaler_id)
+{
+	struct fimc_is *is = pipeline->is;
+	struct scalerp_param *scp_param =
+		&pipeline->is_region->parameter.scalerp;
+	struct scalerc_param *scc_param =
+		&pipeline->is_region->parameter.scalerc;
+	struct param_dma_output *dma_output;
+	unsigned int pipe_start_flag = 0;
+	unsigned int indexes, lindex, hindex;
+	unsigned long *comp_state;
+	int ret;
+
+	if (!test_bit(PIPELINE_OPEN, &pipeline->state))
+		return -EINVAL;
+
+	mutex_lock(&pipeline->pipe_scl_lock);
+
+	if (test_bit(PIPELINE_START, &pipeline->state)) {
+		/* Pipeline is started.
+		 * Stop it now to set params and start again */
+		ret = fimc_is_pipeline_stop(pipeline);
+		if (ret) {
+			pr_err("Not able to stop pipeline\n");
+			goto exit;
+		}
+		pipe_start_flag = 1;
+	}
+
+	comp_state = (scaler_id == SCALER_SCC) ?
+		&pipeline->comp_state[IS_SCC] : &pipeline->comp_state[IS_SCP];
+
+	if (!test_bit(COMP_START, comp_state)) {
+		pr_debug("Scaler not started\n");
+		ret = 0;
+		goto exit;
+	}
+
+	indexes = lindex = hindex = 0;
+
+	if (scaler_id == SCALER_SCC) {
+		dma_output = &scc_param->dma_output;
+		lindex |= LOWBIT_OF(PARAM_SCALERC_DMA_OUTPUT);
+		hindex |= HIGHBIT_OF(PARAM_SCALERC_DMA_OUTPUT);
+	} else {
+		dma_output = &scp_param->dma_output;
+		lindex |= LOWBIT_OF(PARAM_SCALERP_DMA_OUTPUT);
+		hindex |= HIGHBIT_OF(PARAM_SCALERP_DMA_OUTPUT);
+	}
+	indexes++;
+	dma_output->cmd = DMA_OUTPUT_COMMAND_DISABLE;
+
+	ret = fimc_is_itf_set_param(&is->interface, pipeline->instance,
+			indexes, lindex, hindex);
+	if (ret < 0)
+		pr_err("fimc_is_itf_set_param is fail\n");
+	else
+		clear_bit(COMP_START, comp_state);
+
+	if (pipe_start_flag) {
+		ret = fimc_is_pipeline_start(pipeline);
+		if (ret) {
+			pr_err("Not able to start pipeline back\n");
+			return -EINVAL;
+		}
+	}
+
+exit:
+	mutex_unlock(&pipeline->pipe_scl_lock);
+	return ret;
+}
+
+void fimc_is_pipeline_config_shot(struct fimc_is_pipeline *pipeline)
+{
+	struct camera2_shot *shot =
+		(struct camera2_shot *)pipeline->shot_vaddr;
+
+	shot->magicnumber = 0x23456789;
+
+	shot->ctl.aa.mode = AA_CONTROL_AUTO;
+	shot->ctl.aa.ae_mode = AA_AEMODE_ON;
+}
+
+int fimc_is_pipeline_shot(struct fimc_is_pipeline *pipeline)
+{
+	struct fimc_is *is = pipeline->is;
+	int ret;
+	unsigned int rcount;
+	struct camera2_shot *shot =
+		(struct camera2_shot *)pipeline->shot_vaddr;
+	struct fimc_is_buf *scc_buf, *scp_buf, *bayer_buf;
+
+	if (!test_bit(PIPELINE_START, &pipeline->state)) {
+		/* Pipeline not started yet */
+		return -EINVAL;
+	}
+
+	if (test_bit(PIPELINE_RUN, &pipeline->state)) {
+		/* Pipeline busy. Caller need to wait */
+		return -EBUSY;
+	}
+
+	fimc_is_pipeline_buf_lock(pipeline);
+
+	if (list_empty(&pipeline->isp.wait_queue)) {
+		/* No more bayer buffers */
+		wake_up(&pipeline->wait_q);
+		fimc_is_pipeline_buf_unlock(pipeline);
+		return 0;
+	}
+
+	/* Set the state as RUN */
+	set_bit(PIPELINE_RUN, &pipeline->state);
+
+	/* Get bayer input buffer */
+	bayer_buf = fimc_is_isp_wait_queue_get(&pipeline->isp);
+	if (!bayer_buf) {
+		fimc_is_pipeline_buf_unlock(pipeline);
+		goto err_exit;
+	}
+	fimc_is_isp_run_queue_add(&pipeline->isp, bayer_buf);
+
+	/* Get SCC buffer */
+	if (test_bit(COMP_START, &pipeline->comp_state[IS_SCC]) &&
+		!list_empty(&pipeline->scaler[SCALER_SCC].wait_queue)) {
+		scc_buf = fimc_is_scaler_wait_queue_get(
+				&pipeline->scaler[SCALER_SCC]);
+		if (scc_buf) {
+			fimc_is_scaler_run_queue_add(
+					&pipeline->scaler[SCALER_SCC],
+					scc_buf);
+			shot->uctl.scaler_ud.scc_target_address[0] =
+							scc_buf->paddr[0];
+			shot->uctl.scaler_ud.scc_target_address[1] =
+							scc_buf->paddr[1];
+			shot->uctl.scaler_ud.scc_target_address[2] =
+							scc_buf->paddr[2];
+			set_bit(COMP_RUN, &pipeline->comp_state[IS_SCC]);
+		}
+	} else {
+		pr_debug("No SCC buffer available\n");
+		shot->uctl.scaler_ud.scc_target_address[0] = 0;
+		shot->uctl.scaler_ud.scc_target_address[1] = 0;
+		shot->uctl.scaler_ud.scc_target_address[2] = 0;
+	}
+
+	/* Get SCP buffer */
+	if (test_bit(COMP_START, &pipeline->comp_state[IS_SCP]) &&
+		!list_empty(&pipeline->scaler[SCALER_SCP].wait_queue)) {
+		scp_buf = fimc_is_scaler_wait_queue_get(
+				&pipeline->scaler[SCALER_SCP]);
+		if (scp_buf) {
+			fimc_is_scaler_run_queue_add(
+					&pipeline->scaler[SCALER_SCP],
+					scp_buf);
+			shot->uctl.scaler_ud.scp_target_address[0] =
+							scp_buf->paddr[0];
+			shot->uctl.scaler_ud.scp_target_address[1] =
+							scp_buf->paddr[1];
+			shot->uctl.scaler_ud.scp_target_address[2] =
+							scp_buf->paddr[2];
+			set_bit(COMP_RUN, &pipeline->comp_state[IS_SCP]);
+		}
+	} else {
+		pr_debug("No SCP buffer available\n");
+		shot->uctl.scaler_ud.scp_target_address[0] = 0;
+		shot->uctl.scaler_ud.scp_target_address[1] = 0;
+		shot->uctl.scaler_ud.scp_target_address[2] = 0;
+	}
+	fimc_is_pipeline_buf_unlock(pipeline);
+
+	/* Send shot command */
+	pipeline->fcount++;
+	rcount = pipeline->fcount;
+	shot->ctl.request.framecount = pipeline->fcount;
+	pr_debug("Shot command fcount : %d, Bayer addr : 0x%08x\n",
+			pipeline->fcount, bayer_buf->paddr[0]);
+	ret = fimc_is_itf_shot_nblk(&is->interface, pipeline->instance,
+			bayer_buf->paddr[0],
+			pipeline->shot_paddr,
+			pipeline->fcount,
+			rcount);
+	if (ret < 0) {
+		pr_err("Shot command failed.\n");
+		goto err_exit;
+	}
+	return 0;
+
+err_exit:
+	clear_bit(PIPELINE_RUN, &pipeline->state);
+	clear_bit(COMP_RUN, &pipeline->comp_state[IS_SCC]);
+	clear_bit(COMP_RUN, &pipeline->comp_state[IS_SCP]);
+	return -EINVAL;
+}
+
+int fimc_is_pipeline_start(struct fimc_is_pipeline *pipeline)
+{
+	int ret;
+	struct fimc_is *is = pipeline->is;
+
+	/* Check if open or not */
+	if (!test_bit(PIPELINE_OPEN, &pipeline->state)) {
+		pr_err("Pipeline not open.\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&pipeline->pipe_lock);
+
+	/* Check if already started */
+	if (test_bit(PIPELINE_START, &pipeline->state)) {
+		pr_debug("Pipeline already started.\n");
+		mutex_unlock(&pipeline->pipe_lock);
+		return 0;
+	}
+
+	/* Set pipeline component params */
+	ret = fimc_is_pipeline_setparams(pipeline);
+	if (ret < 0) {
+		pr_err("Set params failed\n");
+		goto err_exit;
+	}
+
+	/* Send preview still command */
+	ret = fimc_is_itf_preview_still(&is->interface, pipeline->instance);
+	if (ret) {
+		pr_err("Preview still command failed\n");
+		goto err_exit;
+	}
+
+	/* Confiture shot memory to A5 */
+	ret = fimc_is_itf_cfg_mem(&is->interface, pipeline->instance,
+			pipeline->shot_paddr, sizeof(struct camera2_shot));
+	if (ret < 0) {
+		pr_err("Config A5 mem failed.\n");
+		goto err_exit;
+	}
+
+	/* Set shot params */
+	fimc_is_pipeline_config_shot(pipeline);
+
+	/* Process ON command */
+	ret = fimc_is_itf_process_on(&is->interface, pipeline->instance);
+	if (ret) {
+		pr_err("Process on failed\n");
+		goto err_exit;
+	}
+
+	/* Stream ON */
+	ret = fimc_is_itf_stream_on(&is->interface, pipeline->instance);
+	if (ret < 0) {
+		pr_err("Stream On failed.\n");
+		goto err_exit;
+	}
+
+	/* Set state to START */
+	set_bit(PIPELINE_START, &pipeline->state);
+
+	mutex_unlock(&pipeline->pipe_lock);
+	return 0;
+
+err_exit:
+	mutex_unlock(&pipeline->pipe_lock);
+	return ret;
+}
+
+int fimc_is_pipeline_stop(struct fimc_is_pipeline *pipeline)
+{
+	int ret;
+	struct fimc_is *is = pipeline->is;
+
+	mutex_lock(&pipeline->pipe_lock);
+
+	/* Check if started */
+	if (!test_bit(PIPELINE_OPEN, &pipeline->state) ||
+		!test_bit(PIPELINE_START, &pipeline->state)) {
+		pr_debug("Pipeline not open/started.\n");
+		ret = -EINVAL;
+		goto err_exit;
+	}
+
+	/* Wait if any operation is in progress */
+	ret = wait_event_timeout(pipeline->wait_q,
+			!test_bit(PIPELINE_RUN, &pipeline->state),
+			FIMC_IS_COMMAND_TIMEOUT);
+	if (!ret) {
+		pr_err("Pipeline timeout");
+		ret = -EBUSY;
+		goto err_exit;
+	}
+
+	/* Wait for scaler operations if any to complete */
+	ret = wait_event_timeout(pipeline->scaler[SCALER_SCC].event_q,
+			!test_bit(COMP_RUN, &pipeline->comp_state[IS_SCC]),
+			FIMC_IS_COMMAND_TIMEOUT);
+	if (!ret) {
+		pr_err("SCC timeout");
+		ret = -EBUSY;
+		goto err_exit;
+	}
+	ret = wait_event_timeout(pipeline->scaler[SCALER_SCP].event_q,
+			!test_bit(COMP_RUN, &pipeline->comp_state[IS_SCP]),
+			FIMC_IS_COMMAND_TIMEOUT);
+	if (!ret) {
+		pr_err("SCP timeout");
+		ret = -EBUSY;
+		goto err_exit;
+	}
+
+
+	/* Process OFF */
+	ret = fimc_is_itf_process_off(&is->interface, pipeline->instance);
+	if (ret) {
+		pr_err("Process off failed\n");
+		ret = -EINVAL;
+		goto err_exit;
+	}
+
+	/* Stream OFF */
+	ret = fimc_is_itf_stream_off(&is->interface, pipeline->instance);
+	if (ret < 0) {
+		pr_err("Stream Off failed.\n");
+		ret = -EINVAL;
+		goto err_exit;
+	}
+
+	/* Clear state */
+	clear_bit(PIPELINE_START, &pipeline->state);
+
+	mutex_unlock(&pipeline->pipe_lock);
+	return 0;
+
+err_exit:
+	mutex_unlock(&pipeline->pipe_lock);
+	return ret;
+}
+
+int fimc_is_pipeline_open(struct fimc_is_pipeline *pipeline,
+			struct fimc_is_sensor *sensor)
+{
+	struct fimc_is *is = pipeline->is;
+	struct is_region *region;
+	int ret;
+
+	pr_debug("Pipeline open, instance : %d\n", pipeline->instance);
+
+	if (!sensor)
+		return -EINVAL;
+
+	mutex_lock(&pipeline->pipe_lock);
+
+	/* Check if already open */
+	if (test_bit(PIPELINE_OPEN, &pipeline->state)) {
+		pr_err("Pipeline already open.\n");
+		ret = -EINVAL;
+		goto err_exit;
+	}
+
+	/* Init pipeline params */
+	pipeline->fcount = 0;
+	pipeline->sensor = sensor;
+	pipeline->sensor_width = sensor->width;
+	pipeline->sensor_height = sensor->height;
+
+	/* Init memory */
+	ret = fimc_is_pipeline_initmem(pipeline, is->alloc_ctx);
+	if (ret < 0) {
+		pr_err("Pipeline memory init failed.\n");
+		goto err_exit;
+	}
+
+	/* Load firmware */
+	ret = fimc_is_pipeline_load_firmware(pipeline);
+	if (ret < 0) {
+		pr_err("Firmware load failed.\n");
+		goto err_fw;
+	}
+
+	/* Power ON */
+	ret = fimc_is_pipeline_power(pipeline, 1);
+	if (ret < 0) {
+		pr_err("A5 power on failed.\n");
+		goto err_fw;
+	}
+
+	/* Wait for FW Init to complete */
+	ret = fimc_is_itf_wait_init_state(&is->interface);
+	if (ret < 0) {
+		pr_err("FW init failed.\n");
+		goto err_fw;
+	}
+
+	/* Open Sensor */
+	region = pipeline->is_region;
+	ret = fimc_is_itf_open_sensor(&is->interface,
+			pipeline->instance,
+			sensor->drvdata->id,
+			sensor->i2c_bus,
+			pipeline->minfo->shared_paddr);
+	if (ret < 0) {
+		pr_err("Open sensor failed\n");
+		goto err_exit;
+	}
+
+	pr_debug("Magic Number : %x\n",
+			pipeline->is_region->shared[MAX_SHARED_COUNT-1]);
+
+	/* Copy init params to FW region */
+	memset(&region->parameter, 0x0, sizeof(struct is_param_region));
+
+	memcpy(&region->parameter.sensor, &init_sensor_param,
+			sizeof(struct sensor_param));
+	memcpy(&region->parameter.isp, &init_isp_param,
+			sizeof(struct isp_param));
+	memcpy(&region->parameter.drc, &init_drc_param,
+			sizeof(struct drc_param));
+	memcpy(&region->parameter.scalerc, &init_scalerc_param,
+			sizeof(struct scalerc_param));
+	memcpy(&region->parameter.odc, &init_odc_param,
+			sizeof(struct odc_param));
+	memcpy(&region->parameter.dis, &init_dis_param,
+			sizeof(struct dis_param));
+	memcpy(&region->parameter.tdnr, &init_tdnr_param,
+			sizeof(struct tdnr_param));
+	memcpy(&region->parameter.scalerp, &init_scalerp_param,
+			sizeof(struct scalerp_param));
+	memcpy(&region->parameter.fd, &init_fd_param,
+			sizeof(struct fd_param));
+
+	/* Load setfile */
+	ret = fimc_is_pipeline_setfile(pipeline);
+	if (ret < 0)
+		goto err_exit;
+
+	/* Stream off */
+	ret = fimc_is_itf_stream_off(&is->interface, pipeline->instance);
+	if (ret < 0)
+		goto err_exit;
+
+	/* Process off */
+	ret = fimc_is_itf_process_off(&is->interface, pipeline->instance);
+	if (ret < 0)
+		goto err_exit;
+
+	/* Set state to OPEN */
+	set_bit(PIPELINE_OPEN, &pipeline->state);
+
+	mutex_unlock(&pipeline->pipe_lock);
+	return 0;
+
+err_fw:
+	fimc_is_pipeline_freemem(pipeline);
+err_exit:
+	mutex_unlock(&pipeline->pipe_lock);
+	return ret;
+}
+
+int fimc_is_pipeline_close(struct fimc_is_pipeline *pipeline)
+{
+	int ret;
+	struct fimc_is *is = pipeline->is;
+
+	mutex_lock(&pipeline->pipe_lock);
+
+	/* Check if opened */
+	if (!test_bit(PIPELINE_OPEN, &pipeline->state)) {
+		pr_err("Pipeline not opened\n");
+		ret = -EINVAL;
+		goto err_exit;
+	}
+
+	/* Stop pipeline */
+	if (test_bit(PIPELINE_START, &pipeline->state)) {
+		pr_err("Cannot close pipeline when its started\n");
+		ret = -EINVAL;
+		goto err_exit;
+	}
+
+	/* FW power off command */
+	ret = fimc_is_itf_power_down(&is->interface, pipeline->instance);
+	if (ret)
+		pr_err("FW power down error\n");
+
+	/* Pipeline power off*/
+	fimc_is_pipeline_power(pipeline, 0);
+
+	/* Free memory */
+	fimc_is_pipeline_freemem(pipeline);
+
+	clear_bit(PIPELINE_OPEN, &pipeline->state);
+	mutex_unlock(&pipeline->pipe_lock);
+	return 0;
+
+err_exit:
+	mutex_unlock(&pipeline->pipe_lock);
+	return ret;
+}
diff --git a/drivers/media/platform/exynos5-is/fimc-is-pipeline.h b/drivers/media/platform/exynos5-is/fimc-is-pipeline.h
new file mode 100644
index 0000000..2c5cff9
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-pipeline.h
@@ -0,0 +1,129 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ *  Arun Kumar K <arun.kk@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef FIMC_IS_PIPELINE_H_
+#define FIMC_IS_PIPELINE_H_
+
+#include "fimc-is-core.h"
+#include "fimc-is-sensor.h"
+#include "fimc-is-isp.h"
+#include "fimc-is-scaler.h"
+
+#define FIMC_IS_A5_MEM_SIZE		(0x00A00000)
+#define FIMC_IS_A5_SEN_SIZE		(0x00100000)
+#define FIMC_IS_REGION_SIZE		(0x5000)
+#define FIMC_IS_SETFILE_SIZE		(0xc0d8)
+#define FIMC_IS_TDNR_MEM_SIZE		(1920*1080*4)
+#define FIMC_IS_DEBUG_REGION_ADDR	(0x00840000)
+#define FIMC_IS_SHARED_REGION_ADDR	(0x008C0000)
+
+#define FIMC_IS_SCP_REGION_INDEX	400
+#define FIMC_IS_SCC_REGION_INDEX	447
+
+#define MAX_ODC_INTERNAL_BUF_WIDTH	(2560)  /* 4808 in HW */
+#define MAX_ODC_INTERNAL_BUF_HEIGHT	(1920)  /* 3356 in HW */
+#define SIZE_ODC_INTERNAL_BUF \
+	(MAX_ODC_INTERNAL_BUF_WIDTH * MAX_ODC_INTERNAL_BUF_HEIGHT * 3)
+
+#define MAX_DIS_INTERNAL_BUF_WIDTH	(2400)
+#define MAX_DIS_INTERNAL_BUF_HEIGHT	(1360)
+#define SIZE_DIS_INTERNAL_BUF \
+	(MAX_DIS_INTERNAL_BUF_WIDTH * MAX_DIS_INTERNAL_BUF_HEIGHT * 2)
+
+#define MAX_3DNR_INTERNAL_BUF_WIDTH	(1920)
+#define MAX_3DNR_INTERNAL_BUF_HEIGHT	(1088)
+#define SIZE_DNR_INTERNAL_BUF \
+	(MAX_3DNR_INTERNAL_BUF_WIDTH * MAX_3DNR_INTERNAL_BUF_HEIGHT * 2)
+
+#define NUM_ODC_INTERNAL_BUF		(2)
+#define NUM_DIS_INTERNAL_BUF		(5)
+#define NUM_DNR_INTERNAL_BUF		(2)
+
+#define FIMC_IS_FW_BASE_MASK		((1 << 26) - 1)
+
+#define FIMC_IS_NUM_COMPS		8
+
+enum pipeline_state {
+	PIPELINE_INIT,
+	PIPELINE_OPEN,
+	PIPELINE_START,
+	PIPELINE_RUN,
+};
+
+enum is_components {
+	IS_ISP,
+	IS_DRC,
+	IS_SCC,
+	IS_ODC,
+	IS_DIS,
+	IS_TDNR,
+	IS_SCP,
+	IS_FD
+};
+
+enum component_state {
+	COMP_ENABLE,
+	COMP_START,
+	COMP_RUN
+};
+
+struct fimc_is_pipeline {
+	unsigned long		state;
+	unsigned long		comp_state[FIMC_IS_NUM_COMPS];
+	bool			force_down;
+	unsigned int		instance;
+	spinlock_t		slock_buf;
+	unsigned long		slock_flags;
+	wait_queue_head_t	wait_q;
+	struct mutex		pipe_lock;
+	struct mutex		pipe_scl_lock;
+
+	struct fimc_is_meminfo	*minfo;
+	struct is_region	*is_region;
+
+	void			*is;
+	struct fimc_is_sensor	*sensor;
+	struct fimc_is_isp	isp;
+	struct fimc_is_scaler	scaler[FIMC_IS_NUM_SCALERS];
+
+	unsigned int		fcount;
+	unsigned int		sensor_width;
+	unsigned int		sensor_height;
+	unsigned int		isp_width;
+	unsigned int		isp_height;
+	unsigned int		scaler_width[FIMC_IS_NUM_SCALERS];
+	unsigned int		scaler_height[FIMC_IS_NUM_SCALERS];
+
+	unsigned int		shot_paddr;
+	unsigned int		shot_vaddr;
+};
+
+void fimc_is_pipeline_buf_lock(struct fimc_is_pipeline *pipeline);
+void fimc_is_pipeline_buf_unlock(struct fimc_is_pipeline *pipeline);
+int fimc_is_pipeline_setparams(struct fimc_is_pipeline *pipeline);
+int fimc_is_pipeline_scaler_start(struct fimc_is_pipeline *pipeline,
+		enum fimc_is_scaler_id scaler_id,
+		unsigned int **buf_paddr,
+		unsigned int num_bufs,
+		unsigned int num_planes);
+int fimc_is_pipeline_scaler_stop(struct fimc_is_pipeline *pipeline,
+		enum fimc_is_scaler_id scaler_id);
+void fimc_is_pipeline_config_shot(struct fimc_is_pipeline *pipeline);
+int fimc_is_pipeline_shot(struct fimc_is_pipeline *pipeline);
+int fimc_is_pipeline_start(struct fimc_is_pipeline *pipeline);
+int fimc_is_pipeline_stop(struct fimc_is_pipeline *pipeline);
+int fimc_is_pipeline_init(struct fimc_is_pipeline *pipeline,
+			unsigned int instance, void *is_ctx);
+int fimc_is_pipeline_destroy(struct fimc_is_pipeline *pipeline);
+int fimc_is_pipeline_open(struct fimc_is_pipeline *pipeline,
+			struct fimc_is_sensor *sensor);
+int fimc_is_pipeline_close(struct fimc_is_pipeline *pipeline);
+
+#endif
-- 
1.7.9.5

[RFC v3 10/13] [media] exynos5-fimc-is: Add the hardware interface module

[Arun Kumar K]

The hardware interface module finally sends the commands to the
FIMC-IS firmware and runs the interrupt handler for getting the
responses.

Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Kilyeon Im <kilyeon.im@samsung.com>
---
 .../media/platform/exynos5-is/fimc-is-interface.c  |  861 ++++++++++++++++++++
 .../media/platform/exynos5-is/fimc-is-interface.h  |  128 +++
 2 files changed, 989 insertions(+)
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-interface.c
 create mode 100644 drivers/media/platform/exynos5-is/fimc-is-interface.h

diff --git a/drivers/media/platform/exynos5-is/fimc-is-interface.c b/drivers/media/platform/exynos5-is/fimc-is-interface.c
new file mode 100644
index 0000000..12073be
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-interface.c
@@ -0,0 +1,861 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+*
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Kil-yeon Lim <kilyeon.im@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include "fimc-is.h"
+#include "fimc-is-cmd.h"
+#include "fimc-is-regs.h"
+
+#define init_request_barrier(itf) mutex_init(&itf->request_barrier)
+#define enter_request_barrier(itf) mutex_lock(&itf->request_barrier)
+#define exit_request_barrier(itf) mutex_unlock(&itf->request_barrier)
+
+static inline void itf_get_cmd(struct fimc_is_interface *itf,
+	struct fimc_is_msg *msg, unsigned int index)
+{
+	struct is_common_reg __iomem *com_regs = itf->com_regs;
+
+	memset(msg, 0, sizeof(*msg));
+
+	switch (index) {
+	case INTR_GENERAL:
+		msg->command = com_regs->ihcmd;
+		msg->instance = com_regs->ihc_sensorid;
+		msg->param[0] = com_regs->ihc_param[0];
+		msg->param[1] = com_regs->ihc_param[1];
+		msg->param[2] = com_regs->ihc_param[2];
+		msg->param[3] = com_regs->ihc_param[3];
+		break;
+	case INTR_SCC_FDONE:
+		msg->command = IHC_FRAME_DONE;
+		msg->instance = com_regs->scc_sensor_id;
+		msg->param[0] = com_regs->scc_param[0];
+		msg->param[1] = com_regs->scc_param[1];
+		msg->param[2] = com_regs->scc_param[2];
+		break;
+	case INTR_SCP_FDONE:
+		msg->command = IHC_FRAME_DONE;
+		msg->instance = com_regs->scp_sensor_id;
+		msg->param[0] = com_regs->scp_param[0];
+		msg->param[1] = com_regs->scp_param[1];
+		msg->param[2] = com_regs->scp_param[2];
+		break;
+	case INTR_META_DONE:
+		msg->command = IHC_FRAME_DONE;
+		msg->instance = com_regs->meta_sensor_id;
+		msg->param[0] = com_regs->meta_param1;
+		break;
+	case INTR_SHOT_DONE:
+		msg->command = IHC_FRAME_DONE;
+		msg->instance = com_regs->shot_sensor_id;
+		msg->param[0] = com_regs->shot_param[0];
+		msg->param[1] = com_regs->shot_param[1];
+		break;
+	default:
+		pr_err("unknown command getting\n");
+		break;
+	}
+}
+
+static inline unsigned int itf_get_intr(struct fimc_is_interface *itf)
+{
+	unsigned int status;
+	struct is_common_reg __iomem *com_regs = itf->com_regs;
+
+	status = readl(itf->regs + INTMSR1) | com_regs->ihcmd_iflag |
+		com_regs->scc_iflag |
+		com_regs->scp_iflag |
+		com_regs->meta_iflag |
+		com_regs->shot_iflag;
+
+	return status;
+}
+
+static void itf_set_state(struct fimc_is_interface *itf,
+		unsigned long state)
+{
+	unsigned long flags;
+	spin_lock_irqsave(&itf->slock_state, flags);
+	__set_bit(state, &itf->state);
+	spin_unlock_irqrestore(&itf->slock_state, flags);
+}
+
+static void itf_clr_state(struct fimc_is_interface *itf,
+		unsigned long state)
+{
+	unsigned long flags;
+	spin_lock_irqsave(&itf->slock_state, flags);
+	__clear_bit(state, &itf->state);
+	spin_unlock_irqrestore(&itf->slock_state, flags);
+}
+
+static int itf_get_state(struct fimc_is_interface *itf,
+		unsigned long state)
+{
+	int ret = 0;
+	unsigned long flags;
+
+	spin_lock_irqsave(&itf->slock_state, flags);
+	ret = test_bit(state, &itf->state);
+	spin_unlock_irqrestore(&itf->slock_state, flags);
+	return ret;
+}
+
+static void itf_init_wakeup(struct fimc_is_interface *itf)
+{
+	itf_set_state(itf, IS_IF_STATE_INIT);
+	wake_up(&itf->irq_queue);
+}
+
+void itf_busy_wakeup(struct fimc_is_interface *itf)
+{
+	itf_clr_state(itf, IS_IF_STATE_BUSY);
+	wake_up(&itf->irq_queue);
+}
+
+static int itf_wait_hw_ready(struct fimc_is_interface *itf)
+{
+	int t;
+	for (t = TRY_RECV_AWARE_COUNT; t >= 0; t--) {
+		unsigned int cfg = readl(itf->regs + INTMSR0);
+		unsigned int status = INTMSR0_GET_INTMSD(0, cfg);
+		if (!status)
+			return 0;
+	}
+	pr_err("INTMSR0's 0 bit is not cleared.\n");
+	return -EINVAL;
+}
+
+static int itf_wait_idlestate(struct fimc_is_interface *itf)
+{
+	int ret;
+
+	ret = wait_event_timeout(itf->irq_queue,
+			!itf_get_state(itf, IS_IF_STATE_BUSY),
+			FIMC_IS_COMMAND_TIMEOUT);
+	if (!ret) {
+		pr_err("timeout");
+		return -ETIME;
+	}
+	return 0;
+}
+
+int fimc_is_itf_wait_init_state(struct fimc_is_interface *itf)
+{
+	int ret = 0;
+
+	ret = wait_event_timeout(itf->irq_queue,
+		itf_get_state(itf, IS_IF_STATE_INIT),
+		FIMC_IS_STARTUP_TIMEOUT);
+
+	if (!ret) {
+		pr_err("timeout\n");
+		return -ETIME;
+	}
+	return 0;
+}
+
+/* Send Host to IS command interrupt */
+static void itf_hic_interrupt(struct fimc_is_interface *itf)
+{
+	writel(INTGR0_INTGD(0), itf->regs + INTGR0);
+}
+
+static int itf_send_sensor_number(struct fimc_is_interface *itf)
+{
+	struct fimc_is_msg msg = {
+		.command = ISR_DONE,
+		.param[0] = IHC_GET_SENSOR_NUMBER,
+		.param[1] = 1
+	};
+	unsigned long flags;
+
+	spin_lock_irqsave(&itf->slock, flags);
+	itf->com_regs->hicmd = msg.command;
+	itf->com_regs->hic_sensorid = msg.instance;
+	itf->com_regs->hic_param[0] = msg.param[0];
+	itf->com_regs->hic_param[1] = msg.param[1];
+	itf->com_regs->hic_param[2] = msg.param[2];
+	itf->com_regs->hic_param[3] = msg.param[3];
+	itf_hic_interrupt(itf);
+	spin_unlock_irqrestore(&itf->slock, flags);
+
+	return 0;
+}
+
+static int fimc_is_itf_set_cmd(struct fimc_is_interface *itf,
+	struct fimc_is_msg *msg)
+{
+	int ret = 0;
+	bool block_io;
+	unsigned long flags;
+
+	enter_request_barrier(itf);
+
+	switch (msg->command) {
+	case HIC_STREAM_ON:
+		if (itf->streaming == IS_IF_STREAMING_ON)
+			goto exit;
+		else
+			block_io = true;
+		break;
+	case HIC_STREAM_OFF:
+		if (itf->streaming == IS_IF_STREAMING_OFF)
+			goto exit;
+		else
+			block_io = true;
+		break;
+	case HIC_PROCESS_START:
+		if (itf->processing == IS_IF_PROCESSING_ON)
+			goto exit;
+		else
+			block_io = true;
+		break;
+	case HIC_PROCESS_STOP:
+		if (itf->processing == IS_IF_PROCESSING_OFF)
+			goto exit;
+		else
+			block_io = true;
+		break;
+	case HIC_POWER_DOWN:
+		if (itf->pdown_ready == IS_IF_POWER_DOWN_READY)
+			goto exit;
+		else
+			block_io = true;
+		break;
+	case HIC_OPEN_SENSOR:
+	case HIC_GET_SET_FILE_ADDR:
+	case HIC_SET_PARAMETER:
+	case HIC_PREVIEW_STILL:
+	case HIC_GET_STATIC_METADATA:
+	case HIC_SET_A5_MEM_ACCESS:
+	case HIC_SET_CAM_CONTROL:
+		block_io = true;
+		break;
+	case HIC_SHOT:
+	case ISR_DONE:
+		block_io = false;
+		break;
+	default:
+		block_io = true;
+		break;
+	}
+
+	ret = itf_wait_hw_ready(itf);
+	if (ret) {
+		pr_err("waiting for ready is fail");
+		ret = -EBUSY;
+		goto exit;
+	}
+
+	spin_lock_irqsave(&itf->slock, flags);
+	itf_set_state(itf, IS_IF_STATE_BUSY);
+	itf->com_regs->hicmd = msg->command;
+	itf->com_regs->hic_sensorid = msg->instance;
+	itf->com_regs->hic_param[0] = msg->param[0];
+	itf->com_regs->hic_param[1] = msg->param[1];
+	itf->com_regs->hic_param[2] = msg->param[2];
+	itf->com_regs->hic_param[3] = msg->param[3];
+	itf_hic_interrupt(itf);
+	spin_unlock_irqrestore(&itf->slock, flags);
+
+	if (!block_io)
+		goto exit;
+
+	ret = itf_wait_idlestate(itf);
+	if (ret) {
+		pr_err("%d command is timeout\n", msg->command);
+		itf_clr_state(itf, IS_IF_STATE_BUSY);
+		ret = -ETIME;
+		goto exit;
+	}
+
+	if (itf->reply.command == ISR_DONE) {
+		switch (msg->command) {
+		case HIC_STREAM_ON:
+			itf->streaming = IS_IF_STREAMING_ON;
+			break;
+		case HIC_STREAM_OFF:
+			itf->streaming = IS_IF_STREAMING_OFF;
+			break;
+		case HIC_PROCESS_START:
+			itf->processing = IS_IF_PROCESSING_ON;
+			break;
+		case HIC_PROCESS_STOP:
+			itf->processing = IS_IF_PROCESSING_OFF;
+			break;
+		case HIC_POWER_DOWN:
+			itf->pdown_ready = IS_IF_POWER_DOWN_READY;
+			break;
+		case HIC_OPEN_SENSOR:
+			if (itf->reply.param[0] == HIC_POWER_DOWN) {
+				pr_err("firmware power down");
+				itf->pdown_ready = IS_IF_POWER_DOWN_READY;
+				ret = -ECANCELED;
+				goto exit;
+			} else
+				itf->pdown_ready = IS_IF_POWER_DOWN_NREADY;
+			break;
+		default:
+			break;
+		}
+	} else {
+		pr_err("ISR_NDONE is occured");
+		ret = -EINVAL;
+	}
+exit:
+	exit_request_barrier(itf);
+
+	if (ret)
+		pr_err("Error returned from FW. See debugfs for error log\n");
+
+
+	return ret;
+}
+
+static int fimc_is_itf_set_cmd_shot(struct fimc_is_interface *itf,
+		struct fimc_is_msg *msg)
+{
+	int ret = 0;
+	unsigned long flags;
+
+	spin_lock_irqsave(&itf->slock, flags);
+	itf->com_regs->hicmd = msg->command;
+	itf->com_regs->hic_sensorid = msg->instance;
+	itf->com_regs->hic_param[0] = msg->param[0];
+	itf->com_regs->hic_param[1] = msg->param[1];
+	itf->com_regs->hic_param[2] = msg->param[2];
+	itf->com_regs->hic_param[3] = msg->param[3];
+	itf->com_regs->fcount = msg->param[2];
+	itf_hic_interrupt(itf);
+	spin_unlock_irqrestore(&itf->slock, flags);
+
+	return ret;
+}
+
+static void itf_handle_general(struct fimc_is_interface *itf,
+		struct fimc_is_msg *msg)
+{
+	bool is_blocking = true;
+
+	switch (msg->command) {
+
+	case IHC_GET_SENSOR_NUMBER:
+		pr_debug("IS version : %d.%d\n",
+			ISDRV_VERSION, msg->param[0]);
+		/* Respond with sensor number */
+		itf_send_sensor_number(itf);
+		itf_init_wakeup(itf);
+		break;
+	case ISR_DONE:
+		switch (msg->param[0]) {
+		case HIC_OPEN_SENSOR:
+			pr_debug("open done\n");
+			break;
+		case HIC_GET_SET_FILE_ADDR:
+			pr_debug("saddr(%p) done\n",
+				(void *)msg->param[1]);
+			break;
+		case HIC_LOAD_SET_FILE:
+			pr_debug("setfile done\n");
+			break;
+		case HIC_SET_A5_MEM_ACCESS:
+			pr_debug("cfgmem done\n");
+			break;
+		case HIC_PROCESS_START:
+			pr_debug("process_on done\n");
+			break;
+		case HIC_PROCESS_STOP:
+			pr_debug("process_off done\n");
+			break;
+		case HIC_STREAM_ON:
+			pr_debug("stream_on done\n");
+			break;
+		case HIC_STREAM_OFF:
+			pr_debug("stream_off done\n");
+			break;
+		case HIC_SET_PARAMETER:
+			pr_debug("s_param done\n");
+			break;
+		case HIC_GET_STATIC_METADATA:
+			pr_debug("g_capability done\n");
+			break;
+		case HIC_PREVIEW_STILL:
+			pr_debug("a_param(%dx%d) done\n",
+				msg->param[1],
+				msg->param[2]);
+			break;
+		case HIC_POWER_DOWN:
+			pr_debug("powerdown done\n");
+			break;
+		/*non-blocking command*/
+		case HIC_SHOT:
+			is_blocking = false;
+			pr_err("shot done is not acceptable\n");
+			break;
+		case HIC_SET_CAM_CONTROL:
+			is_blocking = false;
+			pr_err("camctrl is not acceptable\n");
+			break;
+		default:
+			is_blocking = false;
+			pr_err("unknown done is invokded\n");
+			break;
+		}
+		break;
+	case ISR_NDONE:
+		switch (msg->param[0]) {
+		case HIC_SHOT:
+			is_blocking = false;
+			pr_err("shot NOT done is not acceptable\n");
+			break;
+		case HIC_SET_CAM_CONTROL:
+			is_blocking = false;
+			pr_debug("camctrl NOT done\n");
+			break;
+		case HIC_SET_PARAMETER:
+			pr_err("s_param NOT done\n");
+			pr_err("param2 : 0x%08X\n", msg->param[1]);
+			pr_err("param3 : 0x%08X\n", msg->param[2]);
+			pr_err("param4 : 0x%08X\n", msg->param[3]);
+			break;
+		default:
+			pr_err("a command(%d) not done", msg->param[0]);
+			break;
+		}
+		break;
+	case IHC_SET_FACE_MARK:
+		is_blocking = false;
+		pr_err("FACE_MARK(%d,%d,%d) is not acceptable\n",
+			msg->param[0],
+			msg->param[1],
+			msg->param[2]);
+		break;
+	case IHC_AA_DONE:
+		is_blocking = false;
+		pr_err("AA_DONE(%d,%d,%d) is not acceptable\n",
+			msg->param[0],
+			msg->param[1],
+			msg->param[2]);
+		break;
+	case IHC_FLASH_READY:
+		is_blocking = false;
+		pr_err("IHC_FLASH_READY is not acceptable");
+		break;
+	case IHC_NOT_READY:
+		is_blocking = false;
+		pr_err("IHC_NOT_READY is occured, need reset");
+		break;
+	default:
+		is_blocking = false;
+		pr_err("func_general unknown(0x%08X) end\n", msg->command);
+		break;
+	}
+
+	if (is_blocking) {
+		memcpy(&itf->reply, msg,
+			sizeof(struct fimc_is_msg));
+		itf_busy_wakeup(itf);
+	}
+}
+
+static void itf_handle_scaler_done(struct fimc_is_interface *itf,
+		struct fimc_is_msg *msg)
+{
+	struct fimc_is *is = fimc_interface_to_is(itf);
+	struct fimc_is_pipeline *pipeline = &is->pipeline[msg->instance];
+	struct fimc_is_buf *buf;
+	struct fimc_is_scaler *scl;
+	const struct fimc_is_fmt *fmt;
+	struct timeval *tv;
+	struct timespec ts;
+	unsigned int wh, i;
+	unsigned int fcount = msg->param[0];
+	unsigned long *comp_state;
+
+	if (msg->param[3] == SCALER_SCC) {
+		scl = &pipeline->scaler[SCALER_SCC];
+		comp_state = &pipeline->comp_state[IS_SCC];
+	} else {
+		scl = &pipeline->scaler[SCALER_SCP];
+		comp_state = &pipeline->comp_state[IS_SCP];
+	}
+
+	fmt = scl->fmt;
+
+	fimc_is_pipeline_buf_lock(pipeline);
+	if (!list_empty(&scl->run_queue)) {
+
+		wh = scl->width * scl->height;
+		buf = fimc_is_scaler_run_queue_get(scl);
+		for (i = 0; i < fmt->num_planes; i++) {
+			vb2_set_plane_payload(buf->vb, i,
+					(wh * fmt->depth[i]) / 8);
+		}
+
+		/* Set timestamp */
+		ktime_get_ts(&ts);
+		tv = &buf->vb->v4l2_buf.timestamp;
+		tv->tv_sec = ts.tv_sec;
+		tv->tv_usec = ts.tv_nsec / NSEC_PER_USEC;
+		buf->vb->v4l2_buf.sequence = fcount;
+
+		pr_debug("SCP buffer done %d/%d\n",
+				msg->param[0], msg->param[2]);
+		vb2_buffer_done(buf->vb, VB2_BUF_STATE_DONE);
+	}
+	fimc_is_pipeline_buf_unlock(pipeline);
+	clear_bit(COMP_RUN, comp_state);
+	wake_up(&scl->event_q);
+}
+
+static void itf_handle_shot_done(struct fimc_is_interface *itf,
+		struct fimc_is_msg *msg)
+{
+	struct fimc_is *is = fimc_interface_to_is(itf);
+	struct fimc_is_pipeline *pipeline = &is->pipeline[msg->instance];
+	unsigned int status = msg->param[1];
+	struct fimc_is_buf *bayer_buf;
+	int ret;
+
+	if (status != ISR_DONE)
+		pr_err("Shot done is invalid(0x%08X)\n", status);
+
+	/* DQ the bayer input buffer */
+	fimc_is_pipeline_buf_lock(pipeline);
+	bayer_buf = fimc_is_isp_run_queue_get(&pipeline->isp);
+	if (bayer_buf) {
+		vb2_buffer_done(bayer_buf->vb, VB2_BUF_STATE_DONE);
+		pr_debug("Bayer buffer done.\n");
+	}
+	fimc_is_pipeline_buf_unlock(pipeline);
+
+	/* Clear state & call shot again */
+	clear_bit(PIPELINE_RUN, &pipeline->state);
+
+	ret = fimc_is_pipeline_shot(pipeline);
+	if (ret)
+		pr_err("Shot failed\n");
+}
+
+/* Main FIMC-IS interrupt handler */
+static irqreturn_t itf_irq_handler(int irq, void *data)
+{
+	struct fimc_is_interface *itf;
+	struct fimc_is_msg msg;
+	unsigned int status, intr;
+	struct is_common_reg __iomem *com_regs;
+
+	itf = (struct fimc_is_interface *)data;
+	com_regs = itf->com_regs;
+	status = itf_get_intr(itf);
+
+	for (intr = INTR_GENERAL; intr < INTR_MAX_MAP; intr++) {
+
+		if (status & (1 << intr)) {
+			itf_get_cmd(itf, &msg, intr);
+
+			switch (intr) {
+			case INTR_GENERAL:
+				itf_handle_general(itf, &msg);
+				com_regs->ihcmd_iflag = 0;
+				break;
+			case INTR_SHOT_DONE:
+				itf_handle_shot_done(itf, &msg);
+				com_regs->shot_iflag = 0;
+				break;
+			case INTR_SCC_FDONE:
+				msg.param[3] = SCALER_SCC;
+				itf_handle_scaler_done(itf, &msg);
+				com_regs->scc_iflag = 0;
+				break;
+			case INTR_SCP_FDONE:
+				msg.param[3] = SCALER_SCP;
+				itf_handle_scaler_done(itf, &msg);
+				com_regs->scp_iflag = 0;
+				break;
+			case INTR_META_DONE:
+				com_regs->meta_iflag = 0;
+				break;
+			}
+			status &= ~(1 << intr);
+			writel((1 << intr), itf->regs + INTCR1);
+		}
+	}
+
+	if (status != 0)
+		pr_err("status is NOT all clear(0x%08X)", status);
+
+	return IRQ_HANDLED;
+}
+
+int fimc_is_itf_open_sensor(struct fimc_is_interface *itf,
+		unsigned int instance,
+		unsigned int sensor_id,
+		unsigned int i2c_channel,
+		unsigned int sensor_ext)
+{
+	struct fimc_is_msg msg = {0,};
+
+	msg.command = HIC_OPEN_SENSOR;
+	msg.instance = instance;
+	msg.param[0] = sensor_id;
+	msg.param[1] = i2c_channel;
+	msg.param[2] = sensor_ext;
+
+	return fimc_is_itf_set_cmd(itf, &msg);
+}
+
+int fimc_is_itf_get_setfile_addr(struct fimc_is_interface *itf,
+		unsigned int instance, unsigned int *setfile_addr)
+{
+	int ret;
+	struct fimc_is_msg msg = {0,};
+
+	msg.command = HIC_GET_SET_FILE_ADDR;
+	msg.instance = instance;
+
+	ret = fimc_is_itf_set_cmd(itf, &msg);
+	*setfile_addr = itf->reply.param[1];
+
+	return ret;
+}
+
+int fimc_is_itf_load_setfile(struct fimc_is_interface *itf,
+		unsigned int instance)
+{
+	struct fimc_is_msg msg = {0,};
+
+	msg.command = HIC_LOAD_SET_FILE;
+	msg.instance = instance;
+
+	return fimc_is_itf_set_cmd(itf, &msg);
+}
+
+int fimc_is_itf_stream_on(struct fimc_is_interface *itf,
+		unsigned int instance)
+{
+	struct fimc_is_msg msg = {0,};
+
+	msg.command = HIC_STREAM_ON;
+	msg.instance = instance;
+
+	return fimc_is_itf_set_cmd(itf, &msg);
+}
+
+int fimc_is_itf_stream_off(struct fimc_is_interface *itf,
+		unsigned int instance)
+{
+	struct fimc_is_msg msg = {0,};
+
+	msg.command = HIC_STREAM_OFF;
+	msg.instance = instance;
+
+	return fimc_is_itf_set_cmd(itf, &msg);
+}
+
+int fimc_is_itf_process_on(struct fimc_is_interface *itf,
+		unsigned int instance)
+{
+	struct fimc_is_msg msg = {0,};
+
+	msg.command = HIC_PROCESS_START;
+	msg.instance = instance;
+
+	return fimc_is_itf_set_cmd(itf, &msg);
+}
+
+int fimc_is_itf_process_off(struct fimc_is_interface *itf,
+		unsigned int instance)
+{
+	struct fimc_is_msg msg = {0,};
+
+	msg.command = HIC_PROCESS_STOP;
+	msg.instance = instance;
+
+	return fimc_is_itf_set_cmd(itf, &msg);
+}
+
+int fimc_is_itf_set_param(struct fimc_is_interface *itf,
+		unsigned int instance,
+		unsigned int indexes,
+		unsigned int lindex,
+		unsigned int hindex)
+{
+	struct fimc_is_msg msg = {0,};
+
+	msg.command = HIC_SET_PARAMETER;
+	msg.instance = instance;
+	msg.param[0] = ISS_PREVIEW_STILL;
+	msg.param[1] = indexes;
+	msg.param[2] = lindex;
+	msg.param[3] = hindex;
+
+	return fimc_is_itf_set_cmd(itf, &msg);
+}
+
+int fimc_is_itf_preview_still(struct fimc_is_interface *itf,
+		unsigned int instance)
+{
+	struct fimc_is_msg msg = {0,};
+
+	msg.command = HIC_PREVIEW_STILL;
+	msg.instance = instance;
+
+	return fimc_is_itf_set_cmd(itf, &msg);
+}
+
+int fimc_is_itf_get_capability(struct fimc_is_interface *itf,
+	unsigned int instance, unsigned int address)
+{
+	struct fimc_is_msg msg = {0,};
+
+	msg.command = HIC_GET_STATIC_METADATA;
+	msg.instance = instance;
+	msg.param[0] = address;
+
+	return fimc_is_itf_set_cmd(itf, &msg);
+}
+
+int fimc_is_itf_cfg_mem(struct fimc_is_interface *itf,
+		unsigned int instance, unsigned int address,
+		unsigned int size)
+{
+	struct fimc_is_msg msg = {0,};
+
+	msg.command = HIC_SET_A5_MEM_ACCESS;
+	msg.instance = instance;
+	msg.param[0] = address;
+	msg.param[1] = size;
+
+	return fimc_is_itf_set_cmd(itf, &msg);
+}
+
+int fimc_is_itf_shot_nblk(struct fimc_is_interface *itf,
+		unsigned int instance, unsigned int bayer,
+		unsigned int shot, unsigned int fcount, unsigned int rcount)
+{
+	struct fimc_is_msg msg = {0,};
+
+	msg.command = HIC_SHOT;
+	msg.instance = instance;
+	msg.param[0] = bayer;
+	msg.param[1] = shot;
+	msg.param[2] = fcount;
+	msg.param[3] = rcount;
+
+	return fimc_is_itf_set_cmd_shot(itf, &msg);
+}
+
+int fimc_is_itf_power_down(struct fimc_is_interface *itf,
+		unsigned int instance)
+{
+	struct fimc_is_msg msg = {0,};
+	int ret;
+
+	msg.command = HIC_POWER_DOWN;
+	msg.instance = instance;
+
+	ret = fimc_is_itf_set_cmd(itf, &msg);
+	itf_clr_state(itf, IS_IF_STATE_INIT);
+
+	return ret;
+}
+
+/* Debugfs for showing FW debug messages */
+static int fimc_is_log_show(struct seq_file *s, void *data)
+{
+	struct fimc_is_interface *itf = s->private;
+	struct fimc_is *is = fimc_interface_to_is(itf);
+
+	const u8 *buf = (u8 *) (is->minfo.fw_vaddr + DEBUG_OFFSET);
+
+	if (is->minfo.fw_vaddr == 0) {
+		pr_err("Firmware memory is not initialized\n");
+		return -EIO;
+	}
+
+	seq_printf(s, "%s\n", buf);
+	return 0;
+}
+
+static int fimc_is_debugfs_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, fimc_is_log_show, inode->i_private);
+}
+
+static const struct file_operations fimc_is_debugfs_fops = {
+	.open		= fimc_is_debugfs_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static void fimc_is_debugfs_remove(struct fimc_is_interface *itf)
+{
+	debugfs_remove(itf->debugfs_entry);
+	itf->debugfs_entry = NULL;
+}
+
+static int fimc_is_debugfs_create(struct fimc_is_interface *itf)
+{
+	struct dentry *dentry;
+
+	itf->debugfs_entry = debugfs_create_dir("fimc_is", NULL);
+
+	dentry = debugfs_create_file("fw_log", S_IRUGO, itf->debugfs_entry,
+					itf, &fimc_is_debugfs_fops);
+	if (!dentry)
+		fimc_is_debugfs_remove(itf);
+
+	return itf->debugfs_entry == NULL ? -EIO : 0;
+}
+
+int fimc_is_interface_init(struct fimc_is_interface *itf,
+		void __iomem *regs, int irq)
+{
+	struct fimc_is *is = fimc_interface_to_is(itf);
+	struct device *dev = &is->pdev->dev;
+	int ret;
+
+	if (!regs || !irq) {
+		pr_err("Invalid args\n");
+		return -EINVAL;
+	}
+
+	itf->regs = regs;
+	itf->com_regs = (struct is_common_reg *)(regs + ISSR(0));
+
+	init_waitqueue_head(&itf->irq_queue);
+	spin_lock_init(&itf->slock_state);
+	spin_lock_init(&itf->slock);
+
+	/* Register interrupt handler */
+	ret = devm_request_irq(dev, irq, itf_irq_handler,
+			       0, dev_name(dev), itf);
+	if (ret) {
+		dev_err(dev, "Failed to install irq (%d)\n", ret);
+		return -EINVAL;
+	}
+
+	/* Initialize context vars */
+	itf->streaming = IS_IF_STREAMING_INIT;
+	itf->processing = IS_IF_PROCESSING_INIT;
+	itf->pdown_ready = IS_IF_POWER_DOWN_READY;
+	itf->debug_cnt = 0;
+	init_request_barrier(itf);
+
+	/* Debugfs for FW debug log */
+	fimc_is_debugfs_create(itf);
+
+	return 0;
+}
diff --git a/drivers/media/platform/exynos5-is/fimc-is-interface.h b/drivers/media/platform/exynos5-is/fimc-is-interface.h
new file mode 100644
index 0000000..faf86d8
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-interface.h
@@ -0,0 +1,128 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ *  Arun Kumar K <arun.kk@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef FIMC_IS_INTERFACE_H_
+#define FIMC_IS_INTERFACE_H_
+
+#include "fimc-is-core.h"
+
+#define TRY_RECV_AWARE_COUNT    100
+
+#define ISDRV_VERSION		111
+
+#define LOWBIT_OF(num)  (num >= 32 ? 0 : (unsigned int)1<<num)
+#define HIGHBIT_OF(num) (num >= 32 ? (unsigned int)1<<(num-32) : 0)
+
+enum interrupt_map {
+	INTR_GENERAL            = 0,
+	INTR_ISP_FDONE          = 1,
+	INTR_SCC_FDONE          = 2,
+	INTR_DNR_FDONE          = 3,
+	INTR_SCP_FDONE          = 4,
+	INTR_ISP_YUV_DONE	= 5,
+	INTR_META_DONE          = 6,
+	INTR_SHOT_DONE          = 7,
+	INTR_MAX_MAP
+};
+
+enum fimc_is_interface_state {
+	IS_IF_STATE_INIT,
+	IS_IF_STATE_OPEN,
+	IS_IF_STATE_START,
+	IS_IF_STATE_BUSY
+};
+
+enum streaming_state {
+	IS_IF_STREAMING_INIT,
+	IS_IF_STREAMING_OFF,
+	IS_IF_STREAMING_ON
+};
+
+enum processing_state {
+	IS_IF_PROCESSING_INIT,
+	IS_IF_PROCESSING_OFF,
+	IS_IF_PROCESSING_ON
+};
+
+enum pdown_ready_state {
+	IS_IF_POWER_DOWN_READY,
+	IS_IF_POWER_DOWN_NREADY
+};
+
+struct fimc_is_msg {
+	unsigned int	id;
+	unsigned int	command;
+	unsigned int	instance;
+	unsigned int	param[4];
+};
+
+struct fimc_is_interface {
+
+	unsigned long			state;
+
+	void __iomem			*regs;
+	struct is_common_reg __iomem    *com_regs;
+	spinlock_t			slock;
+	spinlock_t			slock_state;
+	wait_queue_head_t		irq_queue;
+
+	spinlock_t			process_barrier;
+	struct mutex			request_barrier;
+
+	enum streaming_state		streaming;
+	enum processing_state		processing;
+	enum pdown_ready_state		pdown_ready;
+
+	struct fimc_is_msg		reply;
+
+	int				debug_cnt;
+	struct dentry                   *debugfs_entry;
+
+};
+
+int fimc_is_interface_init(struct fimc_is_interface *itf,
+		void __iomem *regs, int irq);
+int fimc_is_itf_wait_init_state(struct fimc_is_interface *itf);
+int fimc_is_itf_hw_dump(struct fimc_is_interface *itf);
+int fimc_is_itf_open_sensor(struct fimc_is_interface *itf,
+		unsigned int instance,
+		unsigned int sensor_id,
+		unsigned int i2c_channel,
+		unsigned int sensor_ext);
+int fimc_is_itf_get_setfile_addr(struct fimc_is_interface *this,
+		unsigned int instance, unsigned int *setfile_addr);
+int fimc_is_itf_load_setfile(struct fimc_is_interface *itf,
+		unsigned int instance);
+int fimc_is_itf_stream_on(struct fimc_is_interface *itf,
+		unsigned int instance);
+int fimc_is_itf_stream_off(struct fimc_is_interface *itf,
+		unsigned int instance);
+int fimc_is_itf_process_on(struct fimc_is_interface *itf,
+		unsigned int instance);
+int fimc_is_itf_process_off(struct fimc_is_interface *itf,
+		unsigned int instance);
+int fimc_is_itf_set_param(struct fimc_is_interface *this,
+		unsigned int instance,
+		unsigned int indexes,
+		unsigned int lindex,
+		unsigned int hindex);
+int fimc_is_itf_preview_still(struct fimc_is_interface *itf,
+		unsigned int instance);
+int fimc_is_itf_get_capability(struct fimc_is_interface *itf,
+	unsigned int instance, unsigned int address);
+int fimc_is_itf_cfg_mem(struct fimc_is_interface *itf,
+		unsigned int instance, unsigned int address,
+		unsigned int size);
+int fimc_is_itf_shot_nblk(struct fimc_is_interface *itf,
+		unsigned int instance, unsigned int bayer,
+		unsigned int shot, unsigned int fcount, unsigned int rcount);
+int fimc_is_itf_power_down(struct fimc_is_interface *itf,
+		unsigned int instance);
+#endif
-- 
1.7.9.5

[RFC v3 11/13] [media] exynos5-is: Add Kconfig and Makefile

[Arun Kumar K]

Adds Kconfig and Makefile for exynos5-is driver files.

Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Kilyeon Im <kilyeon.im@samsung.com>
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
---
 drivers/media/platform/Kconfig             |    1 +
 drivers/media/platform/Makefile            |    1 +
 drivers/media/platform/exynos5-is/Kconfig  |   19 +++++++++++++++++++
 drivers/media/platform/exynos5-is/Makefile |    7 +++++++
 4 files changed, 28 insertions(+)
 create mode 100644 drivers/media/platform/exynos5-is/Kconfig
 create mode 100644 drivers/media/platform/exynos5-is/Makefile

diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
index 08de865..4b0475e 100644
--- a/drivers/media/platform/Kconfig
+++ b/drivers/media/platform/Kconfig
@@ -123,6 +123,7 @@ config VIDEO_S3C_CAMIF
 
 source "drivers/media/platform/soc_camera/Kconfig"
 source "drivers/media/platform/exynos4-is/Kconfig"
+source "drivers/media/platform/exynos5-is/Kconfig"
 source "drivers/media/platform/s5p-tv/Kconfig"
 
 endif # V4L_PLATFORM_DRIVERS
diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile
index eee28dd..b1225e5 100644
--- a/drivers/media/platform/Makefile
+++ b/drivers/media/platform/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_VIDEO_SAMSUNG_S5P_TV)	+= s5p-tv/
 
 obj-$(CONFIG_VIDEO_SAMSUNG_S5P_G2D)	+= s5p-g2d/
 obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC)	+= exynos-gsc/
+obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS5_MDEV)	+= exynos5-is/
 
 obj-$(CONFIG_BLACKFIN)                  += blackfin/
 
diff --git a/drivers/media/platform/exynos5-is/Kconfig b/drivers/media/platform/exynos5-is/Kconfig
new file mode 100644
index 0000000..99d5edf
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/Kconfig
@@ -0,0 +1,19 @@
+config VIDEO_SAMSUNG_EXYNOS5_MDEV
+	bool "Samsung Exynos5 Media Device driver"
+	depends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API && PM_RUNTIME && VIDEO_SAMSUNG_EXYNOS4_IS
+	help
+	  This is a v4l2 based media controller driver for
+	  Exynos5 SoC.
+
+if VIDEO_SAMSUNG_EXYNOS5_MDEV
+
+config VIDEO_SAMSUNG_EXYNOS5_FIMC_IS
+	tristate "Samsung Exynos5 SoC FIMC-IS driver"
+	depends on I2C && OF
+	depends on VIDEO_EXYNOS4_FIMC_IS
+	select VIDEOBUF2_DMA_CONTIG
+	help
+	  This is a V4L2 driver for Samsung Exynos5 SoC series Imaging
+	  Subsystem known as FIMC-IS.
+
+endif #VIDEO_SAMSUNG_EXYNOS5_MDEV
diff --git a/drivers/media/platform/exynos5-is/Makefile b/drivers/media/platform/exynos5-is/Makefile
new file mode 100644
index 0000000..c4e37e0
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/Makefile
@@ -0,0 +1,7 @@
+ccflags-y += -Idrivers/media/platform/exynos4-is
+exynos5-fimc-is-objs := fimc-is-core.o fimc-is-isp.o fimc-is-scaler.o
+exynos5-fimc-is-objs += fimc-is-pipeline.o fimc-is-interface.o fimc-is-sensor.o
+exynos-mdevice-objs := exynos5-mdev.o
+
+obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS5_FIMC_IS) += exynos5-fimc-is.o
+obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS5_MDEV) += exynos-mdevice.o
-- 
1.7.9.5

[RFC v3 12/13] V4L: s5k6a3: Change sensor min/max resolutions

[Arun Kumar K]

s5k6a3 sensor has actual pixel resolution of 1408x1402 against
the active resolution 1392x1392. The real resolution is needed
when raw sensor SRGB data is dumped to memory by fimc-lite.

Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
---
 drivers/media/i2c/s5k6a3.c |   14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/media/i2c/s5k6a3.c b/drivers/media/i2c/s5k6a3.c
index ccbb4fc..d81638d 100644
--- a/drivers/media/i2c/s5k6a3.c
+++ b/drivers/media/i2c/s5k6a3.c
@@ -30,6 +30,9 @@
 #define S5K6A3_SENSOR_MIN_WIDTH		32
 #define S5K6A3_SENSOR_MIN_HEIGHT	32
 
+#define S5K6A3_WIDTH_PADDING		16
+#define S5K6A3_HEIGHT_PADDING		10
+
 #define S5K6A3_DEF_PIX_WIDTH		1296
 #define S5K6A3_DEF_PIX_HEIGHT		732
 
@@ -107,10 +110,13 @@ static void s5k6a3_try_format(struct v4l2_mbus_framefmt *mf)
 
 	fmt = find_sensor_format(mf);
 	mf->code = fmt->code;
-	v4l_bound_align_image(&mf->width, S5K6A3_SENSOR_MIN_WIDTH,
-			      S5K6A3_SENSOR_MAX_WIDTH, 0,
-			      &mf->height, S5K6A3_SENSOR_MIN_HEIGHT,
-			      S5K6A3_SENSOR_MAX_HEIGHT, 0, 0);
+	v4l_bound_align_image(&mf->width,
+			S5K6A3_SENSOR_MIN_WIDTH + S5K6A3_WIDTH_PADDING,
+			S5K6A3_SENSOR_MAX_WIDTH + S5K6A3_WIDTH_PADDING, 0,
+			&mf->height,
+			S5K6A3_SENSOR_MIN_HEIGHT + S5K6A3_HEIGHT_PADDING,
+			S5K6A3_SENSOR_MAX_HEIGHT + S5K6A3_HEIGHT_PADDING, 0,
+			0);
 }
 
 static struct v4l2_mbus_framefmt *__s5k6a3_get_format(
-- 
1.7.9.5

[RFC v3 13/13] V4L: Add driver for s5k4e5 image sensor

[Arun Kumar K]

This patch adds subdev driver for Samsung S5K4E5 raw image sensor.
Like s5k6a3, it is also another fimc-is firmware controlled
sensor. This minimal sensor driver doesn't do any I2C communications
as its done by ISP firmware. It can be updated if needed to a
regular sensor driver by adding the I2C communication.

Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
---
 drivers/media/i2c/Kconfig  |    8 +
 drivers/media/i2c/Makefile |    1 +
 drivers/media/i2c/s5k4e5.c |  362 ++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 371 insertions(+)
 create mode 100644 drivers/media/i2c/s5k4e5.c

diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
index f7e9147..271028b 100644
--- a/drivers/media/i2c/Kconfig
+++ b/drivers/media/i2c/Kconfig
@@ -572,6 +572,14 @@ config VIDEO_S5K6A3
 	  This is a V4L2 sensor-level driver for Samsung S5K6A3 raw
 	  camera sensor.
 
+config VIDEO_S5K4E5
+	tristate "Samsung S5K4E5 sensor support"
+	depends on MEDIA_CAMERA_SUPPORT
+	depends on I2C && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API && OF
+	---help---
+	  This is a V4L2 sensor-level driver for Samsung S5K4E5 raw
+	  camera sensor.
+
 config VIDEO_S5K4ECGX
         tristate "Samsung S5K4ECGX sensor support"
         depends on I2C && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API
diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
index cf3cf03..0aeed8e 100644
--- a/drivers/media/i2c/Makefile
+++ b/drivers/media/i2c/Makefile
@@ -65,6 +65,7 @@ obj-$(CONFIG_VIDEO_SR030PC30)	+= sr030pc30.o
 obj-$(CONFIG_VIDEO_NOON010PC30)	+= noon010pc30.o
 obj-$(CONFIG_VIDEO_S5K6AA)	+= s5k6aa.o
 obj-$(CONFIG_VIDEO_S5K6A3)	+= s5k6a3.o
+obj-$(CONFIG_VIDEO_S5K4E5)	+= s5k4e5.o
 obj-$(CONFIG_VIDEO_S5K4ECGX)	+= s5k4ecgx.o
 obj-$(CONFIG_VIDEO_S5C73M3)	+= s5c73m3/
 obj-$(CONFIG_VIDEO_ADP1653)	+= adp1653.o
diff --git a/drivers/media/i2c/s5k4e5.c b/drivers/media/i2c/s5k4e5.c
new file mode 100644
index 0000000..a713c6a
--- /dev/null
+++ b/drivers/media/i2c/s5k4e5.c
@@ -0,0 +1,362 @@
+/*
+ * Samsung S5K4E5 image sensor driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Author: Arun Kumar K <arun.kk@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_gpio.h>
+#include <linux/pm_runtime.h>
+#include <linux/regulator/consumer.h>
+#include <linux/slab.h>
+#include <linux/videodev2.h>
+#include <media/v4l2-async.h>
+#include <media/v4l2-subdev.h>
+
+#define S5K4E5_SENSOR_MAX_WIDTH		2560
+#define S5K4E5_SENSOR_MAX_HEIGHT	1920
+#define S5K4E5_SENSOR_MIN_WIDTH		32
+#define S5K4E5_SENSOR_MIN_HEIGHT	32
+
+#define S5K4E5_WIDTH_PADDING		16
+#define S5K4E5_HEIGHT_PADDING		10
+
+#define S5K4E5_DEF_PIX_WIDTH		1296
+#define S5K4E5_DEF_PIX_HEIGHT		732
+
+#define S5K4E5_DRV_NAME			"S5K4E5"
+#define S5K4E5_CLK_NAME			"mclk"
+
+#define S5K4E5_NUM_SUPPLIES		2
+
+/**
+ * struct s5k4e5 - fimc-is sensor data structure
+ * @dev: pointer to this I2C client device structure
+ * @subdev: the image sensor's v4l2 subdev
+ * @pad: subdev media source pad
+ * @supplies: image sensor's voltage regulator supplies
+ * @gpio_reset: GPIO connected to the sensor's reset pin
+ * @lock: mutex protecting the structure's members below
+ * @format: media bus format at the sensor's source pad
+ */
+struct s5k4e5 {
+	struct device *dev;
+	struct v4l2_subdev subdev;
+	struct media_pad pad;
+	struct regulator_bulk_data supplies[S5K4E5_NUM_SUPPLIES];
+	int gpio_reset;
+	struct mutex lock;
+	struct v4l2_mbus_framefmt format;
+	struct clk *clock;
+	u32 clock_frequency;
+};
+
+static const char * const s5k4e5_supply_names[] = {
+	"svdda",
+	"svddio"
+};
+
+static inline struct s5k4e5 *sd_to_s5k4e5(struct v4l2_subdev *sd)
+{
+	return container_of(sd, struct s5k4e5, subdev);
+}
+
+static const struct v4l2_mbus_framefmt s5k4e5_formats[] = {
+	{
+		.code = V4L2_MBUS_FMT_SGRBG10_1X10,
+		.colorspace = V4L2_COLORSPACE_SRGB,
+		.field = V4L2_FIELD_NONE,
+	}
+};
+
+static const struct v4l2_mbus_framefmt *find_sensor_format(
+	struct v4l2_mbus_framefmt *mf)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(s5k4e5_formats); i++)
+		if (mf->code == s5k4e5_formats[i].code)
+			return &s5k4e5_formats[i];
+
+	return &s5k4e5_formats[0];
+}
+
+static int s5k4e5_enum_mbus_code(struct v4l2_subdev *sd,
+				  struct v4l2_subdev_fh *fh,
+				  struct v4l2_subdev_mbus_code_enum *code)
+{
+	if (code->index >= ARRAY_SIZE(s5k4e5_formats))
+		return -EINVAL;
+
+	code->code = s5k4e5_formats[code->index].code;
+	return 0;
+}
+
+static void s5k4e5_try_format(struct v4l2_mbus_framefmt *mf)
+{
+	const struct v4l2_mbus_framefmt *fmt;
+
+	fmt = find_sensor_format(mf);
+	mf->code = fmt->code;
+	v4l_bound_align_image(&mf->width,
+			S5K4E5_SENSOR_MIN_WIDTH + S5K4E5_WIDTH_PADDING,
+			S5K4E5_SENSOR_MAX_WIDTH + S5K4E5_WIDTH_PADDING, 0,
+			&mf->height,
+			S5K4E5_SENSOR_MIN_HEIGHT + S5K4E5_HEIGHT_PADDING,
+			S5K4E5_SENSOR_MAX_HEIGHT + S5K4E5_WIDTH_PADDING, 0,
+			0);
+}
+
+static struct v4l2_mbus_framefmt *__s5k4e5_get_format(
+		struct s5k4e5 *sensor, struct v4l2_subdev_fh *fh,
+		u32 pad, enum v4l2_subdev_format_whence which)
+{
+	if (which == V4L2_SUBDEV_FORMAT_TRY)
+		return fh ? v4l2_subdev_get_try_format(fh, pad) : NULL;
+
+	return &sensor->format;
+}
+
+static int s5k4e5_set_fmt(struct v4l2_subdev *sd,
+				  struct v4l2_subdev_fh *fh,
+				  struct v4l2_subdev_format *fmt)
+{
+	struct s5k4e5 *sensor = sd_to_s5k4e5(sd);
+	struct v4l2_mbus_framefmt *mf;
+
+	s5k4e5_try_format(&fmt->format);
+
+	mf = __s5k4e5_get_format(sensor, fh, fmt->pad, fmt->which);
+	if (mf) {
+		mutex_lock(&sensor->lock);
+		if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE)
+			*mf = fmt->format;
+		mutex_unlock(&sensor->lock);
+	}
+	return 0;
+}
+
+static int s5k4e5_get_fmt(struct v4l2_subdev *sd,
+				  struct v4l2_subdev_fh *fh,
+				  struct v4l2_subdev_format *fmt)
+{
+	struct s5k4e5 *sensor = sd_to_s5k4e5(sd);
+	struct v4l2_mbus_framefmt *mf;
+
+	mf = __s5k4e5_get_format(sensor, fh, fmt->pad, fmt->which);
+
+	mutex_lock(&sensor->lock);
+	fmt->format = *mf;
+	mutex_unlock(&sensor->lock);
+	return 0;
+}
+
+static struct v4l2_subdev_pad_ops s5k4e5_pad_ops = {
+	.enum_mbus_code	= s5k4e5_enum_mbus_code,
+	.get_fmt	= s5k4e5_get_fmt,
+	.set_fmt	= s5k4e5_set_fmt,
+};
+
+static int s5k4e5_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
+{
+	struct v4l2_mbus_framefmt *format = v4l2_subdev_get_try_format(fh, 0);
+
+	*format		= s5k4e5_formats[0];
+	format->width	= S5K4E5_DEF_PIX_WIDTH;
+	format->height	= S5K4E5_DEF_PIX_HEIGHT;
+
+	return 0;
+}
+
+static const struct v4l2_subdev_internal_ops s5k4e5_sd_internal_ops = {
+	.open = s5k4e5_open,
+};
+
+static int s5k4e5_s_power(struct v4l2_subdev *sd, int on)
+{
+	struct s5k4e5 *sensor = sd_to_s5k4e5(sd);
+	int gpio = sensor->gpio_reset;
+	int ret = 0;
+
+	if (on) {
+		sensor->clock = clk_get(sensor->dev, S5K4E5_CLK_NAME);
+		if (IS_ERR(sensor->clock))
+			return PTR_ERR(sensor->clock);
+
+		ret = clk_set_rate(sensor->clock, sensor->clock_frequency);
+		if (ret < 0)
+			goto clk_put;
+
+		ret = pm_runtime_get(sensor->dev);
+		if (ret < 0)
+			goto clk_put;
+
+		ret = regulator_bulk_enable(S5K4E5_NUM_SUPPLIES,
+					    sensor->supplies);
+		if (ret < 0)
+			goto rpm_put;
+
+		ret = clk_prepare_enable(sensor->clock);
+		if (ret < 0)
+			goto reg_dis;
+
+		if (gpio_is_valid(gpio)) {
+			gpio_set_value(gpio, 1);
+			usleep_range(600, 800);
+			gpio_set_value(gpio, 0);
+			usleep_range(10000, 11000);
+			gpio_set_value(gpio, 1);
+		}
+
+		/* Delay needed for the sensor initialization */
+		msleep(20);
+	} else {
+		if (gpio_is_valid(gpio))
+			gpio_set_value(gpio, 0);
+
+		clk_disable_unprepare(sensor->clock);
+reg_dis:
+		regulator_bulk_disable(S5K4E5_NUM_SUPPLIES,
+						sensor->supplies);
+rpm_put:
+		pm_runtime_put(sensor->dev);
+clk_put:
+		clk_put(sensor->clock);
+	}
+	return ret;
+}
+
+static struct v4l2_subdev_core_ops s5k4e5_core_ops = {
+	.s_power = s5k4e5_s_power,
+};
+
+static struct v4l2_subdev_ops s5k4e5_subdev_ops = {
+	.core = &s5k4e5_core_ops,
+	.pad = &s5k4e5_pad_ops,
+};
+
+static int s5k4e5_probe(struct i2c_client *client,
+				const struct i2c_device_id *id)
+{
+	struct device *dev = &client->dev;
+	struct s5k4e5 *sensor;
+	struct v4l2_subdev *sd;
+	int gpio, i, ret;
+
+	sensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL);
+	if (!sensor)
+		return -ENOMEM;
+
+	mutex_init(&sensor->lock);
+	sensor->gpio_reset = -EINVAL;
+	sensor->clock = ERR_PTR(-EINVAL);
+	sensor->dev = dev;
+
+	gpio = of_get_gpio_flags(dev->of_node, 0, NULL);
+	if (gpio_is_valid(gpio)) {
+		ret = devm_gpio_request_one(dev, gpio, GPIOF_OUT_INIT_LOW,
+							S5K4E5_DRV_NAME);
+		if (ret < 0)
+			return ret;
+	}
+	sensor->gpio_reset = gpio;
+
+	if (of_property_read_u32(dev->of_node, "clock-frequency",
+				 &sensor->clock_frequency)) {
+		dev_err(dev, "clock-frequency property not found at %s\n",
+						dev->of_node->full_name);
+		return -EINVAL;
+	}
+
+	for (i = 0; i < S5K4E5_NUM_SUPPLIES; i++)
+		sensor->supplies[i].supply = s5k4e5_supply_names[i];
+
+	ret = devm_regulator_bulk_get(&client->dev, S5K4E5_NUM_SUPPLIES,
+				      sensor->supplies);
+	if (ret < 0)
+		return ret;
+
+	/* Defer probing if the clock is not available yet */
+	sensor->clock = clk_get(dev, S5K4E5_CLK_NAME);
+	if (IS_ERR(sensor->clock))
+		return -EPROBE_DEFER;
+
+	sd = &sensor->subdev;
+	v4l2_i2c_subdev_init(sd, client, &s5k4e5_subdev_ops);
+	snprintf(sd->name, sizeof(sd->name), S5K4E5_DRV_NAME);
+	sensor->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
+
+	sensor->format.code = s5k4e5_formats[0].code;
+	sensor->format.width = S5K4E5_DEF_PIX_WIDTH;
+	sensor->format.height = S5K4E5_DEF_PIX_HEIGHT;
+
+	sensor->pad.flags = MEDIA_PAD_FL_SOURCE;
+	ret = media_entity_init(&sd->entity, 1, &sensor->pad, 0);
+	if (ret < 0)
+		return ret;
+
+	pm_runtime_no_callbacks(dev);
+	pm_runtime_enable(dev);
+
+	ret = v4l2_async_register_subdev(sd);
+
+	/*
+	 * Don't hold reference to the clock to avoid circular dependency
+	 * between the subdev and the host driver, in case the host is
+	 * a supplier of the clock.
+	 * clk_get()/clk_put() will be called in s_power callback.
+	 */
+	clk_put(sensor->clock);
+
+	return ret;
+}
+
+static int s5k4e5_remove(struct i2c_client *client)
+{
+	struct v4l2_subdev *sd = i2c_get_clientdata(client);
+
+	v4l2_async_unregister_subdev(sd);
+	media_entity_cleanup(&sd->entity);
+	return 0;
+}
+
+static const struct i2c_device_id s5k4e5_ids[] = {
+	{ }
+};
+
+#ifdef CONFIG_OF
+static const struct of_device_id s5k4e5_of_match[] = {
+	{ .compatible = "samsung,s5k4e5" },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, s5k4e5_of_match);
+#endif
+
+static struct i2c_driver s5k4e5_driver = {
+	.driver = {
+		.of_match_table	= of_match_ptr(s5k4e5_of_match),
+		.name		= S5K4E5_DRV_NAME,
+		.owner		= THIS_MODULE,
+	},
+	.probe		= s5k4e5_probe,
+	.remove		= s5k4e5_remove,
+	.id_table	= s5k4e5_ids,
+};
+
+module_i2c_driver(s5k4e5_driver);
+
+MODULE_DESCRIPTION("S5K4E5 image sensor subdev driver");
+MODULE_AUTHOR("Arun Kumar K <arun.kk@samsung.com>");
+MODULE_LICENSE("GPL v2");
-- 
1.7.9.5

Re: [RFC v3 00/13] Exynos5 IS driver

[Sylwester Nawrocki]

Hi Arun,

On 08/02/2013 05:02 PM, Arun Kumar K wrote:
> The patch series add support for Exynos5 camera subsystem. It
> re-uses mipi-csis and fimc-lite from exynos4-is and adds a new
> media device and fimc-is device drivers for exynos5.
> The media device supports asynchronos subdev registration for the
> fimc-is sensors and is based on the patch series from Sylwester
> for exynos4-is [1].
>
> [1]http://www.mail-archive.com/linux-media@vger.kernel.org/msg64653.html
>
> Changes from v2
> ---------------
> - Added exynos5 media device driver from Shaik to this series
> - Added ISP pipeline support in media device driver
> - Based on Sylwester's latest exynos4-is development
> - Asynchronos registration of sensor subdevs
> - Made independent IS-sensor support
> - Add s5k4e5 sensor driver
> - Addressed review comments from Sylwester, Hans, Andrzej, Sachin

This is starting to look pretty good to me, I hope we can merge this
patch set for v3.12. Let use coming two weeks for one or two review/
corrections round.
In the meantime I've done numerous fixes to the patch series [1],
especially the clock provider code was pretty buggy on the clean up
paths. Let's go through the patches and see what can be improved yet.

Thanks,
Sylwester

Re: [RFC v3 01/13] [media] exynos5-is: Adding media device driver for exynos5

[Sylwester Nawrocki]

On 08/02/2013 05:02 PM, Arun Kumar K wrote:
> From: Shaik Ameer Basha<shaik.ameer@samsung.com>
>
> This patch adds support for media device for EXYNOS5 SoCs.
> The current media device supports the following ips to connect
> through the media controller framework.
>
> * MIPI-CSIS
>    Support interconnection(subdev interface) between devices
>
> * FIMC-LITE
>    Support capture interface from device(Sensor, MIPI-CSIS) to memory
>    Support interconnection(subdev interface) between devices
>
> * FIMC-IS
>    Camera post-processing IP having multiple sub-nodes.
>
> G-Scaler will be added later to the current media device.
>
> The media device creates two kinds of pipelines for connecting
> the above mentioned IPs.
> The pipeline0 is uses Sensor, MIPI-CSIS and FIMC-LITE which captures
> image data and dumps to memory.
> Pipeline1 uses FIMC-IS components for doing post-processing
> operations on the captured image and give scaled YUV output.
>
> Pipeline0
>    +--------+     +-----------+     +-----------+     +--------+
>    | Sensor | -->  | MIPI-CSIS | -->  | FIMC-LITE | -->  | Memory |
>    +--------+     +-----------+     +-----------+     +--------+
>
> Pipeline1
>   +--------+      +--------+     +-----------+     +-----------+
>   | Memory | -->   |  ISP   | -->  |    SCC    | -->  |    SCP    |
>   +--------+      +--------+     +-----------+     +-----------+
>
> Signed-off-by: Shaik Ameer Basha<shaik.ameer@samsung.com>
> Signed-off-by: Arun Kumar K<arun.kk@samsung.com>
> ---
>   .../devicetree/bindings/media/exynos5-mdev.txt     |  153 ++
>   drivers/media/platform/exynos5-is/exynos5-mdev.c   | 1471 ++++++++++++++++++++
>   drivers/media/platform/exynos5-is/exynos5-mdev.h   |  199 +++
>   3 files changed, 1823 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/media/exynos5-mdev.txt
>   create mode 100644 drivers/media/platform/exynos5-is/exynos5-mdev.c
>   create mode 100644 drivers/media/platform/exynos5-is/exynos5-mdev.h
>
> diff --git a/Documentation/devicetree/bindings/media/exynos5-mdev.txt b/Documentation/devicetree/bindings/media/exynos5-mdev.txt
> new file mode 100644
> index 0000000..d7d419b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/exynos5-mdev.txt
> @@ -0,0 +1,153 @@
> +Samsung EXYNOS5 SoC Camera Subsystem (FIMC)

I guess (FIMC) could be omitted.

> +----------------------------------------------
> +
> +The Exynos5 SoC Camera subsystem comprises of multiple sub-devices
> +represented by separate device tree nodes. Currently this includes: FIMC-LITE,
> +MIPI CSIS and FIMC-IS.
> +
> +The sub-subdevices are defined as child nodes of the common 'camera' node which
> +also includes common properties of the whole subsystem not really specific to
> +any single sub-device, like common camera port pins or the CAMCLK clock outputs
> +for external image sensors attached to an SoC.
> +
> +Common 'camera' node
> +--------------------
> +
> +Required properties:
> +
> +- compatible	: must be "samsung,exynos5-fimc", "simple-bus"
> +- clocks	: list of clock specifiers, corresponding to entries in
> +		  the clock-names property;
> +- clock-names	: must contain "sclk_cam0", "sclk_cam1" entries,
> +		  matching entries in the clocks property.
> +
> +The pinctrl bindings defined in ../pinctrl/pinctrl-bindings.txt must be used
> +to define a required pinctrl state named "default" and optional pinctrl states:
> +"idle", "active-a", active-b". These optional states can be used to switch the
> +camera port pinmux at runtime. The "idle" state should configure both the camera
> +ports A and B into high impedance state, especially the CAMCLK clock output
> +should be inactive. For the "active-a" state the camera port A must be activated
> +and the port B deactivated and for the state "active-b" it should be the other
> +way around.
> +
> +The 'camera' node must include at least one 'fimc-lite' child node.
> +
> +'parallel-ports' node
> +---------------------
> +
> +This node should contain child 'port' nodes specifying active parallel video
> +input ports. It includes camera A and camera B inputs. 'reg' property in the
> +port nodes specifies data input - 0, 1 indicates input A, B respectively.
> +
> +Optional properties
> +
> +- samsung,camclk-out : specifies clock output for remote sensor,
> +		       0 - CAM_A_CLKOUT, 1 - CAM_B_CLKOUT;

This property is not needed any more, once the common clock bindings are
used.

> +Image sensor nodes
> +------------------
> +
> +The sensor device nodes should be added to their control bus controller (e.g.
> +I2C0) nodes and linked to a port node in the csis or the parallel-ports node,
> +using the common video interfaces bindings, defined in video-interfaces.txt.
> +The implementation of this bindings requires clock-frequency property to be
> +present in the sensor device nodes.
> +
> +Example:
> +
> +	aliases {
> +		fimc-lite0 =&fimc_lite_0
> +	};
> +
> +	/* Parallel bus IF sensor */
> +	i2c_0: i2c@13860000 {
> +		s5k6aa: sensor@3c {
> +			compatible = "samsung,s5k6aafx";
> +			reg =<0x3c>;
> +			vddio-supply =<...>;
> +
> +			clock-frequency =<24000000>;
> +			clocks =<...>;
> +			clock-names = "mclk";
> +
> +			port {
> +				s5k6aa_ep: endpoint {
> +					remote-endpoint =<&fimc0_ep>;
> +					bus-width =<8>;
> +					hsync-active =<0>;
> +					vsync-active =<1>;
> +					pclk-sample =<1>;
> +				};
> +			};
> +		};
> +	};
> +
> +	/* MIPI CSI-2 bus IF sensor */
> +	s5c73m3: sensor@0x1a {
> +		compatible = "samsung,s5c73m3";
> +		reg =<0x1a>;
> +		vddio-supply =<...>;
> +
> +		clock-frequency =<24000000>;
> +		clocks =<...>;
> +		clock-names = "mclk";
> +
> +		port {
> +			s5c73m3_1: endpoint {
> +				data-lanes =<1 2 3 4>;
> +				remote-endpoint =<&csis0_ep>;
> +			};
> +		};
> +	};
> +
> +	camera {
> +		compatible = "samsung,exynos5-fimc", "simple-bus";
> +		#address-cells =<1>;
> +		#size-cells =<1>;
> +		status = "okay";
> +
> +		pinctrl-names = "default";
> +		pinctrl-0 =<&cam_port_a_clk_active>;
> +
> +		/* parallel camera ports */
> +		parallel-ports {
> +			/* camera A input */
> +			port@0 {
> +				reg =<0>;
> +				fimc0_ep: endpoint {
> +					remote-endpoint =<&s5k6aa_ep>;
> +					bus-width =<8>;
> +					hsync-active =<0>;
> +					vsync-active =<1>;
> +					pclk-sample =<1>;
> +				};
> +			};
> +		};
> +
> +		fimc_lite_0: fimc-lite@13C00000 {
> +			compatible = "samsung,exynos5250-fimc-lite";
> +			reg =<0x13C00000 0x1000>;
> +			interrupts =<0 126 0>;
> +			clocks =<&clock 129>;
> +			clock-names = "flite";
> +			status = "okay";
> +		};
> +
> +		csis_0: csis@11880000 {
> +			compatible = "samsung,exynos4210-csis";
> +			reg =<0x11880000 0x1000>;
> +			interrupts =<0 78 0>;
> +			/* camera C input */
> +			port@3 {
> +				reg =<3>;
> +				csis0_ep: endpoint {
> +					remote-endpoint =<&s5c73m3_ep>;
> +					data-lanes =<1 2 3 4>;
> +					samsung,csis-hs-settle =<12>;
> +				};
> +			};
> +		};
> +	};
> +
> +MIPI-CSIS device binding is defined in samsung-mipi-csis.txt and FIMC-LITE
> +device binding is defined in exynos-fimc-lite.txt.
> diff --git a/drivers/media/platform/exynos5-is/exynos5-mdev.c b/drivers/media/platform/exynos5-is/exynos5-mdev.c
> new file mode 100644
> index 0000000..b59738f
> --- /dev/null
> +++ b/drivers/media/platform/exynos5-is/exynos5-mdev.c
> @@ -0,0 +1,1471 @@
> +/*
> + * EXYNOS5 SoC series camera host interface media device driver
> + *
> + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
> + * Shaik Ameer Basha<shaik.ameer@samsung.com>
> + * Arun Kumar K<arun.kk@samsung.com>
> + *
> + * This driver is based on exynos4-is media device driver developed by

nit: developed/written ?

> + * Sylwester Nawrocki<s.nawrocki@samsung.com>

nit: missing dot at end of sentence.

> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published
> + * by the Free Software Foundation, either version 2 of the License,
> + * or (at your option) any later version.
> + */
> +
> +#include<linux/bug.h>
> +#include<linux/clk.h>
> +#include<linux/clk-provider.h>
> +#include<linux/device.h>
> +#include<linux/errno.h>
> +#include<linux/i2c.h>
> +#include<linux/kernel.h>
> +#include<linux/list.h>
> +#include<linux/module.h>
> +#include<linux/of.h>
> +#include<linux/of_platform.h>
> +#include<linux/of_device.h>
> +#include<linux/of_i2c.h>
> +#include<linux/platform_device.h>
> +#include<linux/pm_runtime.h>
> +#include<linux/types.h>
> +#include<linux/slab.h>
> +#include<media/v4l2-async.h>
> +#include<media/v4l2-ctrls.h>
> +#include<media/v4l2-of.h>
> +#include<media/media-device.h>
> +#include<media/s5p_fimc.h>
> +
> +#include "exynos5-mdev.h"
> +#include "fimc-is.h"
> +
> +#define dbg(fmt, args...) \
> +	pr_debug("%s:%d: " fmt "\n", __func__, __LINE__, ##args)
> +
> +static int __fimc_md_set_camclk(struct fimc_md *fmd,
> +				struct fimc_source_info *si,
> +				bool on);

Do you really need that function, now when the clocks for sensor
are exposed through the common clock API ?

> +/**
> + * fimc_pipeline_prepare - update pipeline information with subdevice pointers
> + * @me: media entity terminating the pipeline
> + *
> + * Caller holds the graph mutex.
> + */
> +static void fimc_pipeline_prepare(struct fimc_pipeline *p,
> +				  struct media_entity *me)
> +{
> +	struct v4l2_subdev *sd;
> +	int i;
> +
> +	for (i = 0; i<  IDX_MAX; i++)
> +		p->subdevs[i] = NULL;
> +
> +	while (1) {
> +		struct media_pad *pad = NULL;
> +
> +		/* Find remote source pad */
> +		for (i = 0; i<  me->num_pads; i++) {
> +			struct media_pad *spad =&me->pads[i];
> +			if (!(spad->flags&  MEDIA_PAD_FL_SINK))
> +				continue;
> +			pad = media_entity_remote_pad(spad);
> +			if (pad)
> +				break;
> +		}
> +
> +		if (pad == NULL ||
> +		    media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV) {
> +			break;
> +		}
> +		sd = media_entity_to_v4l2_subdev(pad->entity);
> +
> +		switch (sd->grp_id) {
> +		case GRP_ID_FIMC_IS_SENSOR:
> +		case GRP_ID_SENSOR:
> +			p->subdevs[IDX_SENSOR] = sd;
> +			break;
> +		case GRP_ID_CSIS:
> +			p->subdevs[IDX_CSIS] = sd;
> +			break;
> +		case GRP_ID_FLITE:
> +			p->subdevs[IDX_FLITE] = sd;
> +			break;
> +		default:
> +			pr_warn("%s: Unknown subdev grp_id: %#x\n",
> +				__func__, sd->grp_id);
> +		}
> +		me =&sd->entity;
> +		if (me->num_pads == 1)
> +			break;
> +	}
> +
> +	/* For using FIMC-IS firmware controlled sensors, ISP subdev
> +	 * has to be initialized along with pipeline0 devices.
> +	 * So an ISP subdev from a free ISP pipeline is assigned to
> +	 * this pipeline
> +	 */

Please use proper multi-line comment style:

	/*
	 * For using FIMC-IS firmware controlled sensors, ISP subdev
	 * ...
	 */

> +	if (p->subdevs[IDX_SENSOR]->grp_id == GRP_ID_FIMC_IS_SENSOR) {
> +		struct fimc_pipeline_isp *p_isp;
> +
> +		list_for_each_entry(p_isp, p->isp_pipelines, list) {
> +			if (!p_isp->in_use) {
> +				p->subdevs[IDX_FIMC_IS] =
> +					p_isp->subdevs[IDX_ISP];
> +				p_isp->in_use = true;
> +				break;
> +			}
> +		}
> +	}
> +}
> +
> +/**
> + * __subdev_set_power - change power state of a single subdev
> + * @sd: subdevice to change power state for
> + * @on: 1 to enable power or 0 to disable
> + *
> + * Return result of s_power subdev operation or -ENXIO if sd argument
> + * is NULL. Return 0 if the subdevice does not implement s_power.
> + */
> +static int __subdev_set_power(struct v4l2_subdev *sd, int on)
> +{
> +	int *use_count;
> +	int ret;
> +
> +	if (sd == NULL)
> +		return -ENXIO;
> +
> +	use_count =&sd->entity.use_count;
> +	if (on&&  (*use_count)++>  0)
> +		return 0;
> +	else if (!on&&  (*use_count == 0 || --(*use_count)>  0))
> +		return 0;
> +	ret = v4l2_subdev_call(sd, core, s_power, on);
> +
> +	return ret != -ENOIOCTLCMD ? ret : 0;
> +}
> +
> +/**
> + * fimc_pipeline_s_power - change power state of all pipeline subdevs
> + * @fimc: fimc device terminating the pipeline
> + * @state: true to power on, false to power off
> + *
> + * Needs to be called with the graph mutex held.
> + */
> +static int fimc_pipeline_s_power(struct fimc_pipeline *p, bool state)
> +{
> +	unsigned int i;
> +	int ret;
> +	struct fimc_is_isp *isp_dev;
> +
> +	if (p->subdevs[IDX_SENSOR] == NULL)
> +		return -ENXIO;
> +
> +	/* If sensor is firmware controlled IS-sensor,
> +	 * set sensor sd to isp context
> +	 */

Wrong comment style, a dot missing :)

> +	if (p->subdevs[IDX_FIMC_IS]) {
> +		isp_dev = v4l2_get_subdevdata(p->subdevs[IDX_FIMC_IS]);
> +		isp_dev->sensor_sd = p->subdevs[IDX_SENSOR];
> +	}
> +
> +	for (i = 0; i<  IDX_MAX; i++) {
> +		unsigned int idx = state ? i : (IDX_MAX - 1) - i;
> +
> +		ret = __subdev_set_power(p->subdevs[idx], state);
> +		if (ret<  0&&  ret != -ENXIO)
> +			return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +/**
> + * fimc_md_set_camclk - peripheral sensor clock setup
> + * @sd: sensor subdev to configure sclk_cam clock for
> + * @on: 1 to enable or 0 to disable the clock
> + *
> + * There are 2 separate clock outputs available in the SoC for external
> + * image processors. These clocks are shared between all registered FIMC
> + * devices to which sensors can be attached, either directly or through
> + * the MIPI CSI receiver. The clock is allowed here to be used by
> + * multiple sensors concurrently if they use same frequency.
> + * This function should only be called when the graph mutex is held.
> + */
> +static int fimc_md_set_camclk(struct v4l2_subdev *sd, bool on)
> +{
> +	struct fimc_source_info *si = v4l2_get_subdev_hostdata(sd);
> +	struct fimc_md *fmd = entity_to_fimc_mdev(&sd->entity);
> +
> +	return __fimc_md_set_camclk(fmd, si, on);
> +}
> +
> +/**
> + * __fimc_pipeline_open - update the pipeline information, enable power
> + *                        of all pipeline subdevs and the sensor clock
> + * @me: media entity to start graph walk with
> + * @prepare: true to walk the current pipeline and acquire all subdevs
> + *
> + * Called with the graph mutex held.
> + */
> +static int __fimc_pipeline_open(struct exynos_media_pipeline *ep,
> +				struct media_entity *me, bool prepare)
> +{
> +	struct fimc_pipeline *p = to_fimc_pipeline(ep);
> +	struct v4l2_subdev *sd;
> +	int ret;
> +
> +	if (WARN_ON(p == NULL || me == NULL))
> +		return -EINVAL;
> +
> +	if (prepare)
> +		fimc_pipeline_prepare(p, me);
> +
> +	sd = p->subdevs[IDX_SENSOR];
> +	if (sd == NULL)
> +		return -EINVAL;
> +
> +	ret = fimc_md_set_camclk(sd, true);
> +	if (ret<  0)
> +		return ret;

This is not needed sensors will enable/disable their clock themselves.

> +	ret = fimc_pipeline_s_power(p, 1);
> +	if (!ret)
> +		return 0;
> +
> +	fimc_md_set_camclk(sd, false);

Ditto.

> +	return ret;
> +}
> +
> +/**
> + * __fimc_pipeline_close - disable the sensor clock and pipeline power
> + * @fimc: fimc device terminating the pipeline
> + *
> + * Disable power of all subdevs and turn the external sensor clock off.
> + */
> +static int __fimc_pipeline_close(struct exynos_media_pipeline *ep)
> +{
> +	struct fimc_pipeline *p = to_fimc_pipeline(ep);
> +	struct v4l2_subdev *sd = p ? p->subdevs[IDX_SENSOR] : NULL;
> +	int ret = 0;
> +
> +	if (WARN_ON(sd == NULL))
> +		return -EINVAL;
> +
> +	if (p->subdevs[IDX_SENSOR]) {
> +		ret = fimc_pipeline_s_power(p, 0);
> +		fimc_md_set_camclk(sd, false);
> +	}
> +
> +	if (p->subdevs[IDX_SENSOR]->grp_id == GRP_ID_FIMC_IS_SENSOR) {
> +		struct fimc_pipeline_isp *p_isp;
> +
> +		list_for_each_entry(p_isp, p->isp_pipelines, list) {
> +			if (p_isp->subdevs[IDX_ISP] ==
> +					p->subdevs[IDX_FIMC_IS]) {
> +				p->subdevs[IDX_FIMC_IS] = NULL;
> +				p_isp->in_use = false;
> +				break;
> +			}
> +		}
> +	}
> +	return ret == -ENXIO ? 0 : ret;
> +}
> +
> +/**
> + * __fimc_pipeline_s_stream - call s_stream() on pipeline subdevs
> + * @pipeline: video pipeline structure
> + * @on: passed as the s_stream() callback argument
> + */
> +static int __fimc_pipeline_s_stream(struct exynos_media_pipeline *ep, bool on)
> +{
> +	struct fimc_pipeline *p = to_fimc_pipeline(ep);
> +	int i, ret;
> +
> +	if (p->subdevs[IDX_SENSOR] == NULL)
> +		return -ENODEV;
> +
> +	for (i = 0; i<  IDX_MAX; i++) {
> +		unsigned int idx = on ? i : (IDX_MAX - 1) - i;
> +
> +		ret = v4l2_subdev_call(p->subdevs[idx], video, s_stream, on);
> +
> +		if (ret<  0&&  ret != -ENOIOCTLCMD&&  ret != -ENODEV)
> +			return ret;
> +	}
> +	return 0;
> +}
> +
> +/* Media pipeline operations for the FIMC/FIMC-LITE video device driver */
> +static const struct exynos_media_pipeline_ops exynos5_pipeline0_ops = {
> +	.open		= __fimc_pipeline_open,
> +	.close		= __fimc_pipeline_close,
> +	.set_stream	= __fimc_pipeline_s_stream,
> +};
> +
> +static struct exynos_media_pipeline *fimc_md_pipeline_create(
> +						struct fimc_md *fmd)
> +{
> +	struct fimc_pipeline *p;
> +
> +	p = kzalloc(sizeof(*p), GFP_KERNEL);
> +	if (!p)
> +		return NULL;
> +
> +	list_add_tail(&p->list,&fmd->pipelines);
> +
> +	p->isp_pipelines =&fmd->isp_pipelines;
> +	p->ep.ops =&exynos5_pipeline0_ops;
> +	return&p->ep;
> +}
> +
> +static struct exynos_media_pipeline *fimc_md_isp_pipeline_create(
> +						struct fimc_md *fmd)
> +{
> +	struct fimc_pipeline_isp *p;
> +
> +	p = kzalloc(sizeof(*p), GFP_KERNEL);
> +	if (!p)
> +		return NULL;
> +
> +	list_add_tail(&p->list,&fmd->isp_pipelines);
> +
> +	p->in_use = false;
> +	return&p->ep;
> +}
> +
> +static void fimc_md_pipelines_free(struct fimc_md *fmd)
> +{
> +	while (!list_empty(&fmd->pipelines)) {
> +		struct fimc_pipeline *p;
> +
> +		p = list_entry(fmd->pipelines.next, typeof(*p), list);
> +		list_del(&p->list);
> +		kfree(p);
> +	}
> +	while (!list_empty(&fmd->isp_pipelines)) {
> +		struct fimc_pipeline_isp *p;
> +
> +		p = list_entry(fmd->isp_pipelines.next, typeof(*p), list);
> +		list_del(&p->list);
> +		kfree(p);
> +	}
> +}
> +
> +/*
> + * Sensor subdevice helper functions
> + */
> +static void fimc_md_unregister_sensor(struct v4l2_subdev *sd)
> +{
> +	struct i2c_client *client = v4l2_get_subdevdata(sd);
> +	struct i2c_adapter *adapter;
> +
> +	if (!client)
> +		return;
> +
> +	v4l2_device_unregister_subdev(sd);
> +
> +	if (!client->dev.of_node) {
> +		adapter = client->adapter;
> +		i2c_unregister_device(client);
> +		if (adapter)
> +			i2c_put_adapter(adapter);
> +	}
> +}

You can remove this whole function, also see below.

> +#ifdef CONFIG_OF

This driver already depends on OF, you can remove that #ifdef.

> +/* Parse port node and register as a sub-device any sensor specified there. */
> +static int fimc_md_parse_port_node(struct fimc_md *fmd,
> +				   struct device_node *port,
> +				   unsigned int index)
> +{
> +	struct device_node *rem, *ep, *np;
> +	struct fimc_source_info *pd;
> +	struct v4l2_of_endpoint endpoint;
> +	u32 val;
> +
> +	pd =&fmd->sensor[index].pdata;
> +
> +	/* Assume here a port node can have only one endpoint node. */
> +	ep = of_get_next_child(port, NULL);
> +	if (!ep)
> +		return 0;
> +
> +	v4l2_of_parse_endpoint(ep,&endpoint);
> +	if (WARN_ON(endpoint.port == 0) || index>= FIMC_MAX_SENSORS)
> +		return -EINVAL;
> +
> +	pd->mux_id = (endpoint.port - 1)&  0x1;
> +
> +	rem = v4l2_of_get_remote_port_parent(ep);
> +	of_node_put(ep);
> +	if (rem == NULL) {
> +		v4l2_info(&fmd->v4l2_dev, "Remote device at %s not found\n",
> +							ep->full_name);
> +		return 0;
> +	}
> +	if (!of_property_read_u32(rem, "samsung,camclk-out",&val))
> +		pd->clk_id = val;

This 2 lines should not be needed.

> +	if (!of_property_read_u32(rem, "clock-frequency",&val))
> +		pd->frequency = val;
> +
> +	if (pd->clk_frequency == 0) {
> +		v4l2_err(&fmd->v4l2_dev, "Wrong clock frequency at node %s\n",
> +			 rem->full_name);
> +		of_node_put(rem);
> +		return -EINVAL;
> +	}

And also "clock-frequency" is now handled directly by the sensor
drivers, thus it should be safe to remove the above chunk.

> +	if (fimc_input_is_parallel(endpoint.port)) {
> +		if (endpoint.bus_type == V4L2_MBUS_PARALLEL)
> +			pd->sensor_bus_type = FIMC_BUS_TYPE_ITU_601;
> +		else
> +			pd->sensor_bus_type = FIMC_BUS_TYPE_ITU_656;
> +		pd->flags = endpoint.bus.parallel.flags;
> +	} else if (fimc_input_is_mipi_csi(endpoint.port)) {
> +		/*
> +		 * MIPI CSI-2: only input mux selection and
> +		 * the sensor's clock frequency is needed.
> +		 */
> +		pd->sensor_bus_type = FIMC_BUS_TYPE_MIPI_CSI2;
> +	} else {
> +		v4l2_err(&fmd->v4l2_dev, "Wrong port id (%u) at node %s\n",
> +			 endpoint.port, rem->full_name);
> +	}
> +
> +	np = of_get_parent(rem);
> +
> +	if (np&&  !of_node_cmp(np->name, "i2c-isp"))
> +		pd->fimc_bus_type = FIMC_BUS_TYPE_ISP_WRITEBACK;
> +	else
> +		pd->fimc_bus_type = pd->sensor_bus_type;
> +
> +	if (WARN_ON(index>= ARRAY_SIZE(fmd->sensor)))
> +		return -EINVAL;
> +
> +	fmd->sensor[index].asd.match_type = V4L2_ASYNC_MATCH_OF;
> +	fmd->sensor[index].asd.match.of.node = rem;
> +	fmd->async_subdevs[index] =&fmd->sensor[index].asd;
> +
> +	fmd->num_sensors++;
> +
> +	of_node_put(rem);
> +	return 0;
> +}
> +
> +/* Register all SoC external sub-devices */
> +static int fimc_md_of_sensors_register(struct fimc_md *fmd,
> +				       struct device_node *np)
> +{
> +	struct device_node *parent = fmd->pdev->dev.of_node;
> +	struct device_node *node, *ports;
> +	int index = 0;
> +	int ret;
> +
> +	/* Attach sensors linked to MIPI CSI-2 receivers */
> +	for_each_available_child_of_node(parent, node) {
> +		struct device_node *port;
> +
> +		if (of_node_cmp(node->name, "csis"))
> +			continue;
> +		/* The csis node can have only port subnode. */
> +		port = of_get_next_child(node, NULL);
> +		if (!port)
> +			continue;
> +
> +		ret = fimc_md_parse_port_node(fmd, port, index);
> +		if (ret<  0)
> +			return ret;
> +		index++;
> +	}
> +
> +	/* Attach sensors listed in the parallel-ports node */
> +	ports = of_get_child_by_name(parent, "parallel-ports");
> +	if (!ports)
> +		return 0;
> +
> +	for_each_child_of_node(ports, node) {
> +		ret = fimc_md_parse_port_node(fmd, node, index);
> +		if (ret<  0)
> +			break;
> +		index++;
> +	}
> +
> +	return 0;
> +}
> +
> +static int __of_get_csis_id(struct device_node *np)
> +{
> +	u32 reg = 0;
> +
> +	np = of_get_child_by_name(np, "port");
> +	if (!np)
> +		return -EINVAL;
> +	of_property_read_u32(np, "reg",&reg);
> +	return reg - FIMC_INPUT_MIPI_CSI2_0;
> +}
> +#else
> +#define fimc_md_of_sensors_register(fmd, np) (-ENOSYS)
> +#define __of_get_csis_id(np) (-ENOSYS)

And that can be dropped as well.

> +#endif
> +
> +static int fimc_md_register_sensor_entities(struct fimc_md *fmd)
> +{
> +	struct device_node *of_node = fmd->pdev->dev.of_node;
> +	int ret;
> +
> +	/*
> +	 * Runtime resume one of the FIMC entities to make sure
> +	 * the sclk_cam clocks are not globally disabled.

It's a bit mysterious to me, is this requirement still valid on Exynos5 ?
I glanced over the Exynos5250 datasheet and there seem to be no sclk_cam?
clocks dependency on any of GScaler clocks. Maybe you don't need a clock
provider in this driver, perhaps sensor drivers could use sclk_cam clocks
directly, assigned through dts ?

In case of teh exynos4 driver I've added such FIMC runtime PM handling
specifically for Exynos4x12, so FIMC-LITE could be used with sensors
using clock signal supplied on CAM_{A,B}_CLKOUT pins (sclk-cam?).

> +	 */
> +	if (!fmd->pmf)
> +		return -ENXIO;
> +
> +	ret = pm_runtime_get_sync(fmd->pmf);
> +	if (ret<  0)
> +		return ret;
> +
> +	fmd->num_sensors = 0;
> +	ret = fimc_md_of_sensors_register(fmd, of_node);
> +
> +	pm_runtime_put(fmd->pmf);

In any way this whole function could be dropped, since that runtime
PM handling is now in the clk_prepare/clk_unprepare ops below.
In exynos4-is I keep it only for S5PV210, which is still not converted
to DT. Once that happens I'm going to remove such code as well.

> +	return ret;
> +}
> +
> +/*
> + * MIPI-CSIS, FIMC-IS and FIMC-LITE platform devices registration.
> + */
> +
> +static int register_fimc_lite_entity(struct fimc_md *fmd,
> +				     struct fimc_lite *fimc_lite)
> +{
> +	struct v4l2_subdev *sd;
> +	struct exynos_media_pipeline *ep;
> +	int ret;
> +
> +	if (WARN_ON(fimc_lite->index>= FIMC_LITE_MAX_DEVS ||
> +		    fmd->fimc_lite[fimc_lite->index]))
> +		return -EBUSY;
> +
> +	sd =&fimc_lite->subdev;
> +	sd->grp_id = GRP_ID_FLITE;
> +
> +	ep = fimc_md_pipeline_create(fmd);
> +	if (!ep)
> +		return -ENOMEM;
> +
> +	v4l2_set_subdev_hostdata(sd, ep);
> +
> +	ret = v4l2_device_register_subdev(&fmd->v4l2_dev, sd);
> +	if (!ret) {
> +		fmd->fimc_lite[fimc_lite->index] = fimc_lite;
> +		if (!fmd->pmf&&  fimc_lite->pdev)
> +			fmd->pmf =&fimc_lite->pdev->dev;
> +	} else {
> +		v4l2_err(&fmd->v4l2_dev, "Failed to register FIMC.LITE%d\n",
> +			 fimc_lite->index);
> +	}
> +	return ret;
> +}
> +
> +static int register_csis_entity(struct fimc_md *fmd,
> +				struct platform_device *pdev,
> +				struct v4l2_subdev *sd)
> +{
> +	struct device_node *node = pdev->dev.of_node;
> +	int id, ret;
> +
> +	id = node ? __of_get_csis_id(node) : max(0, pdev->id);
> +
> +	if (WARN_ON(id<  0 || id>= CSIS_MAX_ENTITIES))
> +		return -ENOENT;
> +
> +	if (WARN_ON(fmd->csis[id].sd))
> +		return -EBUSY;
> +
> +	sd->grp_id = GRP_ID_CSIS;
> +	ret = v4l2_device_register_subdev(&fmd->v4l2_dev, sd);
> +	if (!ret)
> +		fmd->csis[id].sd = sd;
> +	else
> +		v4l2_err(&fmd->v4l2_dev,
> +			 "Failed to register MIPI-CSIS.%d (%d)\n", id, ret);
> +	return ret;
> +}
> +
> +static int register_fimc_is_entity(struct fimc_md *fmd,
> +				     struct fimc_is *is)
> +{
> +	struct v4l2_subdev *isp, *scc, *scp;
> +	struct exynos_media_pipeline *ep;
> +	struct fimc_pipeline_isp *p;
> +	struct video_device *vdev;
> +	int ret, i;
> +
> +	for (i = 0; i<  is->num_instance; i++) {
> +		isp = fimc_is_isp_get_sd(is, i);
> +		scc = fimc_is_scc_get_sd(is, i);
> +		scp = fimc_is_scp_get_sd(is, i);
> +		isp->grp_id = GRP_ID_FIMC_IS;
> +		scc->grp_id = GRP_ID_FIMC_IS;
> +		scp->grp_id = GRP_ID_FIMC_IS;
> +
> +		ep = fimc_md_isp_pipeline_create(fmd);
> +		if (!ep)
> +			return -ENOMEM;
> +
> +		v4l2_set_subdev_hostdata(isp, ep);
> +		v4l2_set_subdev_hostdata(scc, ep);
> +		v4l2_set_subdev_hostdata(scp, ep);
> +
> +		ret = v4l2_device_register_subdev(&fmd->v4l2_dev, isp);
> +		if (ret)
> +			v4l2_err(&fmd->v4l2_dev,
> +					"Failed to register ISP subdev\n");
> +
> +		ret = v4l2_device_register_subdev(&fmd->v4l2_dev, scc);
> +		if (ret)
> +			v4l2_err(&fmd->v4l2_dev,
> +					"Failed to register SCC subdev\n");
> +
> +		ret = v4l2_device_register_subdev(&fmd->v4l2_dev, scp);
> +		if (ret)
> +			v4l2_err(&fmd->v4l2_dev,
> +					"Failed to register SCP subdev\n");
> +
> +		p = to_fimc_isp_pipeline(ep);
> +		p->subdevs[IDX_ISP] = isp;
> +		p->subdevs[IDX_SCC] = scc;
> +		p->subdevs[IDX_SCP] = scp;
> +
> +		/* Create default links */
> +		/* vdev ->  ISP */
> +		vdev = fimc_is_isp_get_vfd(is, i);
> +		ret = media_entity_create_link(&isp->entity,
> +					ISP_SD_PAD_SINK_DMA,
> +					&vdev->entity, 0,
> +					MEDIA_LNK_FL_IMMUTABLE |
> +					MEDIA_LNK_FL_ENABLED);
> +		if (ret)
> +			return ret;
> +
> +		/* ISP ->  SCC */
> +		ret = media_entity_create_link(&isp->entity,
> +					ISP_SD_PAD_SRC,
> +					&scc->entity, SCALER_SD_PAD_SINK,
> +					MEDIA_LNK_FL_IMMUTABLE |
> +					MEDIA_LNK_FL_ENABLED);
> +		if (ret)
> +			return ret;
> +
> +		/* SCC ->  SCP */
> +		ret = media_entity_create_link(&scc->entity,
> +					SCALER_SD_PAD_SRC_FIFO,
> +					&scp->entity, SCALER_SD_PAD_SINK,
> +					MEDIA_LNK_FL_IMMUTABLE |
> +					MEDIA_LNK_FL_ENABLED);
> +		if (ret)
> +			return ret;
> +
> +		/* SCC ->  vdev */
> +		vdev = fimc_is_scc_get_vfd(is, i);
> +		ret = media_entity_create_link(&scc->entity,
> +					SCALER_SD_PAD_SRC_DMA,
> +					&vdev->entity, 0,
> +					MEDIA_LNK_FL_IMMUTABLE |
> +					MEDIA_LNK_FL_ENABLED);
> +		if (ret)
> +			return ret;
> +
> +		/* SCP ->  vdev */
> +		vdev = fimc_is_scp_get_vfd(is, i);
> +		ret = media_entity_create_link(&scp->entity,
> +					SCALER_SD_PAD_SRC_DMA,
> +					&vdev->entity, 0,
> +					MEDIA_LNK_FL_IMMUTABLE |
> +					MEDIA_LNK_FL_ENABLED);
> +		if (ret)
> +			return ret;
> +	}
> +	fmd->is = is;
> +
> +	return ret;
> +}
> +
> +static int fimc_md_register_platform_entity(struct fimc_md *fmd,
> +					    struct platform_device *pdev,
> +					    int plat_entity)
> +{
> +	struct device *dev =&pdev->dev;
> +	int ret = -EPROBE_DEFER;
> +	void *drvdata;
> +
> +	/* Lock to ensure dev->driver won't change. */
> +	device_lock(dev);
> +
> +	if (!dev->driver || !try_module_get(dev->driver->owner))
> +		goto dev_unlock;
> +
> +	drvdata = dev_get_drvdata(dev);
> +	/* Some subdev didn't probe succesfully id drvdata is NULL */
> +	if (drvdata) {
> +		switch (plat_entity) {
> +		case IDX_FLITE:
> +			ret = register_fimc_lite_entity(fmd, drvdata);
> +			break;
> +		case IDX_CSIS:
> +			ret = register_csis_entity(fmd, pdev, drvdata);
> +			break;
> +		case IDX_FIMC_IS:
> +			ret = register_fimc_is_entity(fmd, drvdata);
> +			break;
> +		default:
> +			ret = -ENODEV;
> +		}
> +	}
> +
> +	module_put(dev->driver->owner);
> +dev_unlock:
> +	device_unlock(dev);
> +	if (ret == -EPROBE_DEFER)
> +		dev_info(&fmd->pdev->dev, "deferring %s device registration\n",
> +			dev_name(dev));
> +	else if (ret<  0)
> +		dev_err(&fmd->pdev->dev, "%s device registration failed (%d)\n",
> +			dev_name(dev), ret);
> +	return ret;
> +}
> +
> +/* Register FIMC, FIMC-LITE and CSIS media entities */
> +static int fimc_md_register_of_platform_entities(struct fimc_md *fmd,
> +						 struct device_node *parent)
> +{
> +	struct device_node *node;
> +	int ret = 0;
> +
> +	for_each_available_child_of_node(parent, node) {
> +		struct platform_device *pdev;
> +		int plat_entity = -1;
> +
> +		pdev = of_find_device_by_node(node);
> +		if (!pdev)
> +			continue;
> +
> +		/* If driver of any entity isn't ready try all again later. */
> +		if (!strcmp(node->name, CSIS_OF_NODE_NAME))
> +			plat_entity = IDX_CSIS;
> +		else if (!strcmp(node->name, FIMC_LITE_OF_NODE_NAME))
> +			plat_entity = IDX_FLITE;
> +		else if (!strcmp(node->name, FIMC_IS_OF_NODE_NAME))
> +			plat_entity = IDX_FIMC_IS;
> +
> +		if (plat_entity>= 0)
> +			ret = fimc_md_register_platform_entity(fmd, pdev,
> +							plat_entity);
> +		put_device(&pdev->dev);
> +		if (ret<  0)
> +			break;
> +	}
> +
> +	return ret;
> +}
> +
> +static void fimc_md_unregister_entities(struct fimc_md *fmd)
> +{
> +	int i;
> +	struct fimc_is *is;
> +
> +	for (i = 0; i<  FIMC_LITE_MAX_DEVS; i++) {
> +		if (fmd->fimc_lite[i] == NULL)
> +			continue;
> +		v4l2_device_unregister_subdev(&fmd->fimc_lite[i]->subdev);
> +		fmd->fimc_lite[i] = NULL;
> +	}
> +	for (i = 0; i<  CSIS_MAX_ENTITIES; i++) {
> +		if (fmd->csis[i].sd == NULL)
> +			continue;
> +		v4l2_device_unregister_subdev(fmd->csis[i].sd);
> +		module_put(fmd->csis[i].sd->owner);
> +		fmd->csis[i].sd = NULL;
> +	}

> +	for (i = 0; i<  fmd->num_sensors; i++) {
> +		if (fmd->sensor[i].subdev == NULL)
> +			continue;
> +		fimc_md_unregister_sensor(fmd->sensor[i].subdev);
> +		fmd->sensor[i].subdev = NULL;
> +	}

Sensor subdev unregistration will be done in 
v4l2_async_notifier_unregister()
function. So the above could be simply:

	for (i = 0; i<  fmd->num_sensors; i++) {
		fmd->sensor[i].subdev = NULL;

> +	if (!fmd->is)
> +		return;
> +	/* Unregistering FIMC-IS entities */
> +	is = fmd->is;
> +	for (i = 0; i<  is->num_instance; i++) {
> +		struct v4l2_subdev *isp, *scc, *scp;
> +
> +		isp = fimc_is_isp_get_sd(is, i);
> +		scc = fimc_is_scc_get_sd(is, i);
> +		scp = fimc_is_scp_get_sd(is, i);
> +		v4l2_device_unregister_subdev(isp);
> +		v4l2_device_unregister_subdev(scc);
> +		v4l2_device_unregister_subdev(scp);
> +	}
> +
> +	v4l2_info(&fmd->v4l2_dev, "Unregistered all entities\n");
> +}
> +
> +/**
> + * __fimc_md_create_fimc_links - create links to all FIMC entities
> + * @fmd: fimc media device
> + * @source: the source entity to create links to all fimc entities from
> + * @sensor: sensor subdev linked to FIMC[fimc_id] entity, may be null
> + * @pad: the source entity pad index
> + * @link_mask: bitmask of the fimc devices for which link should be enabled
> + */
> +static int __fimc_md_create_fimc_sink_links(struct fimc_md *fmd,
> +					    struct media_entity *source,
> +					    struct v4l2_subdev *sensor,
> +					    int pad, int link_mask)
> +{
> +	struct fimc_source_info *si = NULL;
> +	struct media_entity *sink;
> +	unsigned int flags = 0;
> +	int i, ret = 0;
> +
> +	if (sensor) {
> +		si = v4l2_get_subdev_hostdata(sensor);
> +		/* Skip direct FIMC links in the logical FIMC-IS sensor path */
> +		if (si&&  si->fimc_bus_type == FIMC_BUS_TYPE_ISP_WRITEBACK)
> +			ret = 1;
> +	}
> +
> +	for (i = 0; i<  FIMC_LITE_MAX_DEVS; i++) {
> +		if (!fmd->fimc_lite[i])
> +			continue;
> +
> +		flags = ((1<<  i)&  link_mask) ? MEDIA_LNK_FL_ENABLED : 0;
> +
> +		sink =&fmd->fimc_lite[i]->subdev.entity;
> +		ret = media_entity_create_link(source, pad, sink,
> +					       FLITE_SD_PAD_SINK, flags);
> +		if (ret)
> +			return ret;
> +
> +		/* Notify FIMC-LITE subdev entity */
> +		ret = media_entity_call(sink, link_setup,&sink->pads[0],
> +					&source->pads[pad], flags);
> +		if (ret)
> +			break;
> +
> +		v4l2_info(&fmd->v4l2_dev, "created link [%s] ->  [%s]\n",
> +			  source->name, sink->name);
> +	}
> +	return 0;
> +}
> +
> +/* Create links from FIMC-LITE source pads to other entities */
> +static int __fimc_md_create_flite_source_links(struct fimc_md *fmd)
> +{
> +	struct media_entity *source, *sink;
> +	int i, ret = 0;
> +
> +	for (i = 0; i<  FIMC_LITE_MAX_DEVS; i++) {
> +		struct fimc_lite *fimc = fmd->fimc_lite[i];
> +
> +		if (fimc == NULL)
> +			continue;
> +
> +		source =&fimc->subdev.entity;
> +		sink =&fimc->ve.vdev.entity;
> +		/* FIMC-LITE's subdev and video node */
> +		ret = media_entity_create_link(source, FLITE_SD_PAD_SOURCE_DMA,
> +					       sink, 0,
> +					       MEDIA_LNK_FL_IMMUTABLE |
> +					       MEDIA_LNK_FL_ENABLED);
> +		if (ret)
> +			break;
> +	}
> +
> +	return ret;
> +}
> +
> +/**
> + * fimc_md_create_links - create default links between registered entities
> + *
> + * Parallel interface sensor entities are connected directly to FIMC capture
> + * entities. The sensors using MIPI CSIS bus are connected through immutable
> + * link with CSI receiver entity specified by mux_id. Any registered CSIS
> + * entity has a link to each registered FIMC capture entity. Enabled links
> + * are created by default between each subsequent registered sensor and
> + * subsequent FIMC capture entity. The number of default active links is
> + * determined by the number of available sensors or FIMC entities,
> + * whichever is less.
> + */
> +static int fimc_md_create_links(struct fimc_md *fmd)
> +{
> +	struct v4l2_subdev *csi_sensors[CSIS_MAX_ENTITIES] = { NULL };
> +	struct v4l2_subdev *sensor, *csis;
> +	struct fimc_source_info *pdata;
> +	struct media_entity *source;
> +	int i, pad, fimc_id = 0, ret = 0;
> +	u32 flags, link_mask = 0;
> +
> +	for (i = 0; i<  fmd->num_sensors; i++) {
> +		if (fmd->sensor[i].subdev == NULL)
> +			continue;
> +
> +		sensor = fmd->sensor[i].subdev;
> +		pdata = v4l2_get_subdev_hostdata(sensor);
> +		if (!pdata)
> +			continue;
> +
> +		source = NULL;
> +
> +		switch (pdata->sensor_bus_type) {
> +		case FIMC_BUS_TYPE_MIPI_CSI2:
> +			if (WARN(pdata->mux_id>= CSIS_MAX_ENTITIES,
> +				"Wrong CSI channel id: %d\n", pdata->mux_id))
> +				return -EINVAL;
> +
> +			csis = fmd->csis[pdata->mux_id].sd;
> +			if (WARN(csis == NULL,
> +				 "MIPI-CSI interface specified "
> +				 "but s5p-csis module is not loaded!\n"))
> +				return -EINVAL;
> +
> +			pad = sensor->entity.num_pads - 1;
> +			ret = media_entity_create_link(&sensor->entity, pad,
> +					&csis->entity, CSIS_PAD_SINK,
> +					      MEDIA_LNK_FL_IMMUTABLE |
> +					      MEDIA_LNK_FL_ENABLED);
> +			if (ret)
> +				return ret;
> +
> +			v4l2_info(&fmd->v4l2_dev, "created link [%s] =>  [%s]\n",
> +				  sensor->entity.name, csis->entity.name);
> +
> +			source = NULL;
> +			csi_sensors[pdata->mux_id] = sensor;
> +			break;
> +
> +		case FIMC_BUS_TYPE_ITU_601...FIMC_BUS_TYPE_ITU_656:
> +			source =&sensor->entity;
> +			pad = 0;
> +			break;
> +
> +		default:
> +			v4l2_err(&fmd->v4l2_dev, "Wrong bus_type: %x\n",
> +				 pdata->sensor_bus_type);
> +			return -EINVAL;
> +		}
> +		if (source == NULL)
> +			continue;
> +
> +		link_mask = 1<<  fimc_id++;
> +		ret = __fimc_md_create_fimc_sink_links(fmd, source, sensor,
> +						       pad, link_mask);
> +	}
> +
> +	for (i = 0; i<  CSIS_MAX_ENTITIES; i++) {
> +		if (fmd->csis[i].sd == NULL)
> +			continue;
> +
> +		source =&fmd->csis[i].sd->entity;
> +		pad = CSIS_PAD_SOURCE;
> +		sensor = csi_sensors[i];
> +
> +		link_mask = 1<<  fimc_id++;
> +		ret = __fimc_md_create_fimc_sink_links(fmd, source, sensor,
> +						       pad, link_mask);
> +	}
> +
> +	/* Create immutable links between each FIMC's subdev and video node */

s/FIMC/FIMC-LITE ?

> +	flags = MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED;
> +
> +	ret = __fimc_md_create_flite_source_links(fmd);
> +	if (ret<  0)
> +		return ret;
> +
> +	return 0;
> +}
> +
> +/*
> + * The peripheral sensor clock management.
> + */
> +static void fimc_md_put_clocks(struct fimc_md *fmd)
> +{
> +	int i = FIMC_MAX_CAMCLKS;
> +
> +	while (--i>= 0) {
> +		if (IS_ERR(fmd->camclk[i].clock))
> +			continue;
> +		clk_put(fmd->camclk[i].clock);
> +		fmd->camclk[i].clock = ERR_PTR(-EINVAL);
> +	}

Please double check if you need this sclk_cam clocks handling. We could
simply add a requirement that this driver supports only sensor subdevs
through the v4l2-async API and which controls their clock themselves.

> +}
> +
> +static int fimc_md_get_clocks(struct fimc_md *fmd)
> +{
> +	struct device *dev = NULL;
> +	char clk_name[32];
> +	struct clk *clock;
> +	int i, ret = 0;
> +
> +	for (i = 0; i<  FIMC_MAX_CAMCLKS; i++)
> +		fmd->camclk[i].clock = ERR_PTR(-EINVAL);
> +
> +	if (fmd->pdev->dev.of_node)
> +		dev =&fmd->pdev->dev;
> +
> +	for (i = 0; i<  SCLK_BAYER; i++) {
> +		snprintf(clk_name, sizeof(clk_name), "sclk_cam%u", i);
> +		clock = clk_get(dev, clk_name);
> +
> +		if (IS_ERR(clock)) {
> +			dev_err(&fmd->pdev->dev, "Failed to get clock: %s\n",
> +								clk_name);
> +			ret = PTR_ERR(clock);
> +			break;
> +		}
> +		fmd->camclk[i].clock = clock;
> +	}
> +	if (ret)
> +		fimc_md_put_clocks(fmd);
> +
> +	/* Prepare bayer clk */
> +	clock = clk_get(dev, "sclk_bayer");
> +
> +	if (IS_ERR(clock)) {
> +		dev_err(&fmd->pdev->dev, "Failed to get clock: %s\n",
> +							clk_name);

Wrong error message.

> +		ret = PTR_ERR(clock);
> +		goto err_exit;
> +	}
> +	ret = clk_prepare(clock);
> +	if (ret<  0) {
> +		clk_put(clock);
> +		fmd->camclk[SCLK_BAYER].clock = ERR_PTR(-EINVAL);
> +		goto err_exit;
> +	}
> +	fmd->camclk[SCLK_BAYER].clock = clock;

Could you explain a bit how is this SCLK_BAYER clock used ? Is it routed
to external image sensor, or is it used only inside an SoC ?

> +	return 0;
> +err_exit:
> +	fimc_md_put_clocks(fmd);
> +	return ret;
> +}
> +
> +static int __fimc_md_set_camclk(struct fimc_md *fmd,
> +				struct fimc_source_info *si,
> +				bool on)

This function seems to be unneeded.

> +{
> +	struct fimc_camclk_info *camclk;
> +	int ret = 0;
> +
> +	if (WARN_ON(si->clk_id>= FIMC_MAX_CAMCLKS) || fmd == NULL)
> +		return -EINVAL;
> +
> +	camclk =&fmd->camclk[si->clk_id];
> +
> +	dbg("camclk %d, f: %lu, use_count: %d, on: %d",
> +	    si->clk_id, si->clk_frequency, camclk->use_count, on);
> +
> +	if (on) {
> +		if (camclk->use_count>  0&&
> +		    camclk->frequency != si->clk_frequency)
> +			return -EINVAL;
> +
> +		if (camclk->use_count++ == 0) {
> +			clk_set_rate(camclk->clock, si->clk_frequency);
> +			camclk->frequency = si->clk_frequency;
> +			ret = pm_runtime_get_sync(fmd->pmf);
> +			if (ret<  0)
> +				return ret;
> +			ret = clk_prepare_enable(camclk->clock);
> +			dbg("Enabled camclk %d: f: %lu", si->clk_id,
> +			    clk_get_rate(camclk->clock));
> +		}
> +		ret = clk_prepare_enable(fmd->camclk[SCLK_BAYER].clock);
> +		return ret;
> +	}
> +
> +	if (WARN_ON(camclk->use_count == 0))
> +		return 0;
> +
> +	if (--camclk->use_count == 0) {
> +		clk_disable_unprepare(camclk->clock);
> +		pm_runtime_put(fmd->pmf);
> +		dbg("Disabled camclk %d", si->clk_id);
> +	}
> +	clk_disable_unprepare(fmd->camclk[SCLK_BAYER].clock);
> +	return ret;
> +}
> +
> +static int __fimc_md_modify_pipeline(struct media_entity *entity, bool enable)
> +{
> +	struct exynos_video_entity *ve;
> +	struct fimc_pipeline *p;
> +	struct video_device *vdev;
> +	int ret;
> +
> +	vdev = media_entity_to_video_device(entity);
> +	if (vdev->entity.use_count == 0)
> +		return 0;
> +
> +	ve = vdev_to_exynos_video_entity(vdev);
> +	p = to_fimc_pipeline(ve->pipe);
> +	/*
> +	 * Nothing to do if we are disabling the pipeline, some link
> +	 * has been disconnected and p->subdevs array is cleared now.
> +	 */
> +	if (!enable&&  p->subdevs[IDX_SENSOR] == NULL)
> +		return 0;
> +
> +	if (enable)
> +		ret = __fimc_pipeline_open(ve->pipe, entity, true);
> +	else
> +		ret = __fimc_pipeline_close(ve->pipe);
> +
> +	if (ret == 0&&  !enable)
> +		memset(p->subdevs, 0, sizeof(p->subdevs));
> +
> +	return ret;
> +}
> +
> +/* Locking: called with entity->parent->graph_mutex mutex held. */
> +static int __fimc_md_modify_pipelines(struct media_entity *entity, bool enable)
> +{
> +	struct media_entity *entity_err = entity;
> +	struct media_entity_graph graph;
> +	int ret;
> +
> +	/*
> +	 * Walk current graph and call the pipeline open/close routine for each
> +	 * opened video node that belongs to the graph of entities connected
> +	 * through active links. This is needed as we cannot power on/off the
> +	 * subdevs in random order.
> +	 */
> +	media_entity_graph_walk_start(&graph, entity);
> +
> +	while ((entity = media_entity_graph_walk_next(&graph))) {
> +		if (media_entity_type(entity) != MEDIA_ENT_T_DEVNODE)
> +			continue;
> +
> +		ret  = __fimc_md_modify_pipeline(entity, enable);
> +
> +		if (ret<  0)
> +			goto err;
> +	}
> +
> +	return 0;
> + err:
> +	media_entity_graph_walk_start(&graph, entity_err);
> +
> +	while ((entity_err = media_entity_graph_walk_next(&graph))) {
> +		if (media_entity_type(entity_err) != MEDIA_ENT_T_DEVNODE)
> +			continue;
> +
> +		__fimc_md_modify_pipeline(entity_err, !enable);
> +
> +		if (entity_err == entity)
> +			break;
> +	}
> +
> +	return ret;
> +}
> +
> +static int fimc_md_link_notify(struct media_link *link, unsigned int flags,
> +				unsigned int notification)
> +{
> +	struct media_entity *sink = link->sink->entity;
> +	int ret = 0;
> +
> +	/* Before link disconnection */
> +	if (notification == MEDIA_DEV_NOTIFY_PRE_LINK_CH) {
> +		if (!(flags&  MEDIA_LNK_FL_ENABLED))
> +			ret = __fimc_md_modify_pipelines(sink, false);
> +		else
> +			; /* TODO: Link state change validation */
> +	/* After link activation */
> +	} else if (notification == MEDIA_DEV_NOTIFY_POST_LINK_CH&&
> +		   (link->flags&  MEDIA_LNK_FL_ENABLED)) {
> +		ret = __fimc_md_modify_pipelines(sink, true);
> +	}
> +
> +	return ret ? -EPIPE : 0;
> +}
> +
> +#ifdef CONFIG_OF

You don't need #ifdef.

> +struct cam_clk {
> +	struct clk_hw hw;
> +	struct fimc_md *fmd;
> +};
> +#define to_cam_clk(_hw) container_of(_hw, struct cam_clk, hw)

I've improved this clock provider code a bit in the meantime and the
above got moved to the header file. I'll post v2 next week, it might
be worth to have a look at it since it includes a few quite essential
bug fixes.

> +static int cam_clk_prepare(struct clk_hw *hw)
> +{
> +	struct cam_clk *camclk = to_cam_clk(hw);
> +	int ret = pm_runtime_get_sync(camclk->fmd->pmf);
> +
> +	return ret<  0 ? ret : 0;
> +}
> +
> +static void cam_clk_unprepare(struct clk_hw *hw)
> +{
> +	struct cam_clk *camclk = to_cam_clk(hw);
> +	pm_runtime_put_sync(camclk->fmd->pmf);
> +}
> +
> +static const struct clk_ops cam_clk_ops = {
> +	.prepare = cam_clk_prepare,
> +	.unprepare = cam_clk_unprepare,
> +};
> +
> +static const char *cam_clk_p_names[] = { "sclk_cam0", "sclk_cam1" };
> +
> +static int fimc_md_register_clk_provider(struct fimc_md *fmd)
> +{
> +	struct cam_clk_provider *clk_provider =&fmd->clk_provider;
> +	struct device *dev =&fmd->pdev->dev;
> +	struct device_node *node;
> +	unsigned int nclocks;
> +
> +	node = of_get_child_by_name(dev->of_node, "clock-controller");
> +	if (!node) {
> +		dev_warn(dev, "clock-controller node at %s not found\n",
> +					dev->of_node->full_name);
> +		return 0;
> +	}
> +	/* Instantiate the clocks */
> +	for (nclocks = 0; nclocks<  SCLK_BAYER; nclocks++) {
> +		struct clk_init_data init;
> +		char clk_name[16];
> +		struct clk *clk;
> +		struct cam_clk *camclk;
> +
> +		camclk = devm_kzalloc(dev, sizeof(*camclk), GFP_KERNEL);
> +		if (!camclk)
> +			return -ENOMEM;
> +
> +		snprintf(clk_name, sizeof(clk_name), "cam_clkout%d", nclocks);
> +
> +		init.name = clk_name;
> +		init.ops =&cam_clk_ops;
> +		init.flags = CLK_SET_RATE_PARENT;
> +		init.parent_names =&cam_clk_p_names[nclocks];
> +		init.num_parents = 1;
> +		camclk->hw.init =&init;
> +		camclk->fmd = fmd;
> +
> +		clk = devm_clk_register(dev,&camclk->hw);
> +		if (IS_ERR(clk)) {
> +			kfree(camclk);
> +			return PTR_ERR(clk);
> +		}
> +		clk_provider->clks[nclocks] = clk;
> +	}
> +
> +	clk_provider->clk_data.clks = clk_provider->clks;
> +	clk_provider->clk_data.clk_num = nclocks;
> +
> +	return of_clk_add_provider(node, of_clk_src_onecell_get,
> +					&clk_provider->clk_data);
> +}
> +#else
> +#define fimc_md_register_clk_provider(fmd) (0)
> +#endif
> +
> +static int subdev_notifier_bound(struct v4l2_async_notifier *notifier,
> +				 struct v4l2_subdev *subdev,
> +				 struct v4l2_async_subdev *asd)
> +{
> +	struct fimc_md *fmd = notifier_to_fimc_md(notifier);
> +	struct fimc_sensor_info *si = NULL;
> +	int i;
> +
> +	/* Find platform data for this sensor subdev */
> +	for (i = 0; i<  ARRAY_SIZE(fmd->sensor); i++) {
> +		if (fmd->sensor[i].asd.match.of.node == subdev->dev->of_node)
> +			si =&fmd->sensor[i];
> +	}
> +
> +	if (si == NULL)
> +		return -EINVAL;
> +
> +	v4l2_set_subdev_hostdata(subdev,&si->pdata);
> +
> +	if (si->pdata.fimc_bus_type == FIMC_BUS_TYPE_ISP_WRITEBACK)
> +		subdev->grp_id = GRP_ID_FIMC_IS_SENSOR;
> +	else
> +		subdev->grp_id = GRP_ID_SENSOR;
> +
> +	si->subdev = subdev;
> +
> +	v4l2_info(&fmd->v4l2_dev, "Registered sensor subdevice: %s (%d)\n",
> +		  subdev->name, fmd->num_sensors);
> +
> +	fmd->num_sensors++;
> +
> +	return 0;
> +}
> +
> +static int subdev_notifier_complete(struct v4l2_async_notifier *notifier)
> +{
> +	struct fimc_md *fmd = notifier_to_fimc_md(notifier);
> +	int ret;
> +
> +	mutex_lock(&fmd->media_dev.graph_mutex);
> +
> +	ret = fimc_md_create_links(fmd);
> +	if (ret<  0)
> +		goto unlock;
> +
> +	ret = v4l2_device_register_subdev_nodes(&fmd->v4l2_dev);
> +unlock:
> +	mutex_unlock(&fmd->media_dev.graph_mutex);
> +	return ret;
> +}
> +
> +static int fimc_md_probe(struct platform_device *pdev)
> +{
> +	struct device *dev =&pdev->dev;
> +	struct v4l2_device *v4l2_dev;
> +	struct fimc_md *fmd;
> +	int ret;
> +
> +	fmd = devm_kzalloc(dev, sizeof(*fmd), GFP_KERNEL);
> +	if (!fmd)
> +		return -ENOMEM;
> +
> +	spin_lock_init(&fmd->slock);
> +	fmd->pdev = pdev;
> +	INIT_LIST_HEAD(&fmd->pipelines);
> +	INIT_LIST_HEAD(&fmd->isp_pipelines);
> +
> +	strlcpy(fmd->media_dev.model, "SAMSUNG EXYNOS5 IS",
> +		sizeof(fmd->media_dev.model));
> +	fmd->media_dev.link_notify = fimc_md_link_notify;
> +	fmd->media_dev.dev = dev;
> +
> +	v4l2_dev =&fmd->v4l2_dev;
> +	v4l2_dev->mdev =&fmd->media_dev;
> +	strlcpy(v4l2_dev->name, "exynos5-fimc-md", sizeof(v4l2_dev->name));
> +
> +	ret = fimc_md_register_clk_provider(fmd);
> +	if (ret<  0) {
> +		v4l2_err(v4l2_dev, "clock provider registration failed\n");
> +		return ret;
> +	}
> +
> +	ret = v4l2_device_register(dev,&fmd->v4l2_dev);
> +	if (ret<  0) {
> +		v4l2_err(v4l2_dev, "Failed to register v4l2_device: %d\n", ret);
> +		return ret;
> +	}
> +
> +	ret = media_device_register(&fmd->media_dev);
> +	if (ret<  0) {
> +		v4l2_err(v4l2_dev, "Failed to register media dev: %d\n", ret);
> +		goto err_md;
> +	}
> +
> +	ret = fimc_md_get_clocks(fmd);
> +	if (ret)
> +		goto err_clk;
> +
> +	fmd->user_subdev_api = (dev->of_node != NULL);

Oh, please get rid of this "subdev_user_api" mess! ;-)

> +	platform_set_drvdata(pdev, fmd);
> +
> +	/* Protect the media graph while we're registering entities */
> +	mutex_lock(&fmd->media_dev.graph_mutex);
> +
> +	ret = fimc_md_register_of_platform_entities(fmd, dev->of_node);
> +	if (ret)
> +		goto err_unlock;
> +
> +	ret = fimc_md_register_sensor_entities(fmd);
> +	if (ret)
> +		goto err_unlock;
> +
> +	mutex_unlock(&fmd->media_dev.graph_mutex);
> +
> +	fmd->subdev_notifier.subdevs = fmd->async_subdevs;
> +	fmd->subdev_notifier.num_subdevs = fmd->num_sensors;
> +	fmd->subdev_notifier.bound = subdev_notifier_bound;
> +	fmd->subdev_notifier.complete = subdev_notifier_complete;
> +	fmd->num_sensors = 0;
> +
> +	ret = v4l2_async_notifier_register(&fmd->v4l2_dev,
> +					&fmd->subdev_notifier);
> +	if (ret)
> +		goto err_clk;
> +
> +	return 0;
> +
> +err_unlock:
> +	mutex_unlock(&fmd->media_dev.graph_mutex);
> +err_clk:
> +	fimc_md_put_clocks(fmd);
> +	fimc_md_unregister_entities(fmd);
> +	media_device_unregister(&fmd->media_dev);
> +err_md:
> +	v4l2_device_unregister(&fmd->v4l2_dev);
> +	fimc_md_unregister_clk_provider(fmd);
> +	return ret;
> +}
> +
> +static int fimc_md_remove(struct platform_device *pdev)
> +{
> +	struct fimc_md *fmd = platform_get_drvdata(pdev);
> +
> +	v4l2_async_notifier_unregister(&fmd->subdev_notifier);
> +
> +	fimc_md_unregister_entities(fmd);
> +	fimc_md_pipelines_free(fmd);
> +	media_device_unregister(&fmd->media_dev);
> +	fimc_md_put_clocks(fmd);
> +
> +	return 0;
> +}
> +
> +static struct platform_device_id fimc_driver_ids[] __always_unused = {
> +	{ .name = "exynos5-fimc-md" },
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(platform, fimc_driver_ids);
> +
> +static const struct of_device_id fimc_md_of_match[] = {
> +	{ .compatible = "samsung,exynos5-fimc" },
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, fimc_md_of_match);
> +
> +static struct platform_driver fimc_md_driver = {
> +	.probe		= fimc_md_probe,
> +	.remove		= fimc_md_remove,
> +	.driver = {
> +		.of_match_table = fimc_md_of_match,
> +		.name		= "exynos5-fimc-md",
> +		.owner		= THIS_MODULE,
> +	}
> +};
> +
> +static int __init fimc_md_init(void)
> +{
> +	request_module("s5p-csis");
> +	return platform_driver_register(&fimc_md_driver);
> +}
> +
> +static void __exit fimc_md_exit(void)
> +{
> +	platform_driver_unregister(&fimc_md_driver);
> +}
> +
> +module_init(fimc_md_init);
> +module_exit(fimc_md_exit);
> +
> +MODULE_AUTHOR("Shaik Ameer Basha<shaik.ameer@samsung.com>");
> +MODULE_DESCRIPTION("EXYNOS5 FIMC media device driver");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/media/platform/exynos5-is/exynos5-mdev.h b/drivers/media/platform/exynos5-is/exynos5-mdev.h
> new file mode 100644
> index 0000000..7fada6c
> --- /dev/null
> +++ b/drivers/media/platform/exynos5-is/exynos5-mdev.h
> @@ -0,0 +1,199 @@
> +/*
> + * Copyright (C) 2011 - 2012 Samsung Electronics Co., Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef EXYNOS5_MDEVICE_H_
> +#define EXYNOS5_MDEVICE_H_
> +
> +#include<linux/clk.h>
> +#include<linux/platform_device.h>
> +#include<linux/mutex.h>
> +#include<media/media-device.h>
> +#include<media/media-entity.h>
> +#include<media/s5p_fimc.h>
> +#include<media/v4l2-device.h>
> +#include<media/v4l2-subdev.h>
> +
> +#include "fimc-lite.h"
> +#include "mipi-csis.h"
> +
> +#define FIMC_OF_NODE_NAME	"fimc"

That's unused.

> +#define FIMC_LITE_OF_NODE_NAME	"fimc-lite"
> +#define CSIS_OF_NODE_NAME	"csis"
> +#define FIMC_IS_OF_NODE_NAME	"fimc-is"
> +
> +#define FIMC_MAX_SENSORS	8

I guess it's safe to lower this number to 4 for now.

> +enum fimc_subdev_index {
> +	IDX_SENSOR,
> +	IDX_CSIS,
> +	IDX_FLITE,
> +	IDX_FIMC_IS,
> +	IDX_MAX,
> +};
> +
> +enum fimc_isp_subdev_index {
> +	IDX_ISP,
> +	IDX_SCC,
> +	IDX_SCP,
> +	IDX_IS_MAX,
> +};
> +
> +enum fimc_sensor_clks {
> +	SCLK_CAM0,
> +	SCLK_CAM1,
> +	SCLK_BAYER,
> +	FIMC_MAX_CAMCLKS,
> +};
> +
> +struct fimc_pipeline {
> +	struct exynos_media_pipeline ep;
> +	struct list_head list;
> +	struct media_entity *vdev_entity;
> +	struct v4l2_subdev *subdevs[IDX_MAX];
> +	struct list_head *isp_pipelines;
> +};
> +
> +struct fimc_pipeline_isp {
> +	struct exynos_media_pipeline ep;
> +	struct list_head list;
> +	struct v4l2_subdev *subdevs[IDX_IS_MAX];
> +	bool in_use;
> +};
> +
> +struct fimc_csis_info {
> +	struct v4l2_subdev *sd;
> +	int id;
> +};
> +
> +struct fimc_camclk_info {
> +	struct clk *clock;
> +	int use_count;
> +	unsigned long frequency;
> +};
> +
> +/**
> + * struct fimc_sensor_info - image data source subdev information
> + * @pdata: sensor's atrributes passed as media device's platform data
> + * @asd: asynchronous subdev registration data structure
> + * @subdev: image sensor v4l2 subdev
> + * @host: fimc device the sensor is currently linked to
> + *
> + * This data structure applies to image sensor and the writeback subdevs.
> + */
> +struct fimc_sensor_info {
> +	struct fimc_source_info pdata;
> +	struct v4l2_async_subdev asd;
> +	struct v4l2_subdev *subdev;
> +	struct fimc_dev *host;
> +};
> +
> +/**
> + * struct fimc_md - fimc media device information
> + * @csis: MIPI CSIS subdevs data
> + * @sensor: array of registered sensor subdevs
> + * @num_sensors: actual number of registered sensors
> + * @camclk: external sensor clock information
> + * @fimc: array of registered fimc devices
> + * @is: fimc-is data structure
> + * @pmf: handle to the CAMCLK clock control FIMC helper device

Is it needed ? If so shouldn't it be GScaler instead. I suppose
only FIMC-LITE needs to be active though. So there is likely no need
for that helper device logic.

> + * @media_dev: top level media device
> + * @v4l2_dev: top level v4l2_device holding up the subdevs
> + * @pdev: platform device this media device is hooked up into
> + * @user_subdev_api: true if subdevs are not configured by the host driver
> + * @slock: spinlock protecting @sensor array
> + */
> +struct fimc_md {
> +	struct fimc_csis_info csis[CSIS_MAX_ENTITIES];
> +	struct fimc_sensor_info sensor[FIMC_MAX_SENSORS];
> +	int num_sensors;
> +	struct fimc_camclk_info camclk[FIMC_MAX_CAMCLKS];
> +	struct fimc_lite *fimc_lite[FIMC_LITE_MAX_DEVS];
> +	struct fimc_is *is;
> +	struct device *pmf;
> +	struct media_device media_dev;
> +	struct v4l2_device v4l2_dev;
> +	struct platform_device *pdev;
> +	struct cam_clk_provider {
> +		struct clk *clks[FIMC_MAX_CAMCLKS];
> +		struct clk_onecell_data clk_data;
> +		struct device_node *of_node;
> +	} clk_provider;
> +
> +	struct v4l2_async_notifier subdev_notifier;
> +	struct v4l2_async_subdev *async_subdevs[FIMC_MAX_SENSORS];
> +
> +	bool user_subdev_api;
> +	spinlock_t slock;
> +	struct list_head pipelines;
> +	struct list_head isp_pipelines;
> +};
> +
> +#define is_subdev_pad(pad) (pad == NULL || \
> +	media_entity_type(pad->entity) == MEDIA_ENT_T_V4L2_SUBDEV)
> +
> +#define me_subtype(me) \
> +	((me->type)&  (MEDIA_ENT_TYPE_MASK | MEDIA_ENT_SUBTYPE_MASK))
> +
> +#define subdev_has_devnode(__sd) (__sd->flags&  V4L2_SUBDEV_FL_HAS_DEVNODE)
> +
> +#define to_fimc_pipeline(_ep) container_of(_ep, struct fimc_pipeline, ep)
> +#define to_fimc_isp_pipeline(_ep) \
> +	container_of(_ep, struct fimc_pipeline_isp, ep)
> +
> +static inline struct fimc_md *entity_to_fimc_mdev(struct media_entity *me)
> +{
> +	return me->parent == NULL ? NULL :
> +		container_of(me->parent, struct fimc_md, media_dev);
> +}
> +
> +static inline struct fimc_md *notifier_to_fimc_md(struct v4l2_async_notifier *n)
> +{
> +	return container_of(n, struct fimc_md, subdev_notifier);
> +}
> +
> +static inline void fimc_md_graph_lock(struct exynos_video_entity *ve)
> +{
> +	mutex_lock(&ve->vdev.entity.parent->graph_mutex);
> +}
> +
> +static inline void fimc_md_graph_unlock(struct exynos_video_entity *ve)
> +{
> +	mutex_unlock(&ve->vdev.entity.parent->graph_mutex);
> +}
> +
> +#ifdef CONFIG_OF

No need for #ifdef...

> +static inline bool fimc_md_is_isp_available(struct device_node *node)
> +{
> +	node = of_get_child_by_name(node, FIMC_IS_OF_NODE_NAME);
> +	return node ? of_device_is_available(node) : false;
> +}
> +
> +static inline void fimc_md_unregister_clk_provider(struct fimc_md *fmd)
> +{
> +	if (fmd->clk_provider.of_node)
> +		of_clk_del_provider(fmd->clk_provider.of_node);
> +}
> +#else
> +
> +#define fimc_md_is_isp_available(node) (false)
> +#define fimc_md_unregister_clk_provider(fmd) (0)

...and these two.

> +#endif /* CONFIG_OF */
> +
> +static inline struct v4l2_subdev *__fimc_md_get_subdev(
> +				struct exynos_media_pipeline *ep,
> +				unsigned int index)
> +{
> +	struct fimc_pipeline *p = to_fimc_pipeline(ep);
> +
> +	if (!p || index>= IDX_MAX)
> +		return NULL;
> +	else
> +		return p->subdevs[index];
> +}
> +
> +#endif

Re: [RFC v3 02/13] [media] exynos5-fimc-is: Add Exynos5 FIMC-IS device tree bindings documentation

[Sylwester Nawrocki]

On 08/02/2013 05:02 PM, Arun Kumar K wrote:
> The patch adds the DT binding documentation for Samsung
> Exynos5 SoC series imaging subsystem (FIMC-IS).
>
> Signed-off-by: Arun Kumar K<arun.kk@samsung.com>
> ---
>   .../devicetree/bindings/media/exynos5-fimc-is.txt  |   52 ++++++++++++++++++++
>   1 file changed, 52 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
>
> diff --git a/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt b/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
> new file mode 100644
> index 0000000..49a373a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
> @@ -0,0 +1,52 @@
> +Samsung EXYNOS5 SoC series Imaging Subsystem (FIMC-IS)
> +------------------------------------------------------
> +
> +The camera subsystem on Samsung Exynos5 SoC has some changes relative
> +to previous SoC versions. Exynos5 has almost similar MIPI-CSIS and
> +FIMC-LITE IPs but has a much improved version of FIMC-IS which can
> +handle sensor controls and camera post-processing operations. The
> +Exynos5 FIMC-IS has a dedicated ARM Cortex A5 processor, many
> +post-processing blocks (ISP, DRC, FD, ODC, DIS, 3DNR) and two
> +dedicated scalers (SCC and SCP).
> +
> +fimc-is node
> +------------
> +
> +Required properties:
> +
> +- compatible        : must be "samsung,exynos5250-fimc-is"
> +- reg               : physical base address and size of the memory mapped
> +                      registers
> +- interrupt-parent  : Parent interrupt controller

s/Parent/parent ?

> +- interrupts        : fimc-is interrupt to the parent combiner
> +- clocks            : list of clock specifiers, corresponding to entries in
> +                      clock-names property;
> +- clock-names       : must contain "isp", "mcu_isp", "isp_div0", "isp_div1",
> +                      "isp_divmpwm", "mcu_isp_div0", "mcu_isp_div1" entries,
> +                      matching entries in the clocks property.
> +
> +pmu subnode
> +-----------
> +
> +Required properties:
> + - reg : should contain PMU physical base address and size of the memory
> +         mapped registers.
> +
> +i2c-isp (ISP I2C bus controller) nodes
> +------------------------------------------
> +
> +Required properties:
> +
> +- compatible	: should be "samsung,exynos4212-i2c-isp" for Exynos4212,
> +		  Exynos4412 and Exynos5250 SoCs;
> +- reg		: physical base address and length of the registers set;
> +- clocks	: must contain gate clock specifier for this controller;
> +- clock-names	: must contain "i2c_isp" entry.
> +
> +For the above nodes it is required to specify a pinctrl state named "default",
> +according to the pinctrl bindings defined in ../pinctrl/pinctrl-bindings.txt.
> +
> +Device tree nodes of the image sensors' controlled directly by the FIMC-IS
> +firmware must be child nodes of their corresponding ISP I2C bus controller node.
> +The data link of these image sensors must be specified using the common video
> +interfaces bindings, defined in video-interfaces.txt.

This one looks good to me. Feel free to add

  Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

I'm adding the Device Tree maintainers at Cc so we can possibly get 
their Ack.

--
Thanks,
Sylwester

Re: [RFC v3 03/13] [media] exynos5-fimc-is: Add driver core files

[Sylwester Nawrocki]

On 08/02/2013 05:02 PM, Arun Kumar K wrote:
> This driver is for the FIMC-IS IP available in Samsung Exynos5
> SoC onwards. This patch adds the core files for the new driver.
>
> Signed-off-by: Arun Kumar K<arun.kk@samsung.com>
> Signed-off-by: Kilyeon Im<kilyeon.im@samsung.com>
> ---
>   drivers/media/platform/exynos5-is/fimc-is-core.c |  394 ++++++++++++++++++++++
>   drivers/media/platform/exynos5-is/fimc-is-core.h |  122 +++++++
>   2 files changed, 516 insertions(+)
>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.c
>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.h
>
> diff --git a/drivers/media/platform/exynos5-is/fimc-is-core.c b/drivers/media/platform/exynos5-is/fimc-is-core.c
> new file mode 100644
> index 0000000..7b7762b
> --- /dev/null
> +++ b/drivers/media/platform/exynos5-is/fimc-is-core.c
> @@ -0,0 +1,394 @@
> +/*
> + * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
> +*
> + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
> + * Arun Kumar K<arun.kk@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include<linux/bug.h>
> +#include<linux/ctype.h>
> +#include<linux/device.h>
> +#include<linux/debugfs.h>
> +#include<linux/delay.h>
> +#include<linux/errno.h>
> +#include<linux/err.h>
> +#include<linux/firmware.h>
> +#include<linux/fs.h>
> +#include<linux/gpio.h>
> +#include<linux/interrupt.h>
> +#include<linux/kernel.h>
> +#include<linux/list.h>
> +#include<linux/module.h>
> +#include<linux/types.h>
> +#include<linux/platform_device.h>
> +#include<linux/pm_runtime.h>
> +#include<linux/slab.h>
> +#include<linux/videodev2.h>
> +#include<linux/of.h>
> +#include<linux/of_gpio.h>
> +#include<linux/of_address.h>
> +#include<linux/of_platform.h>
> +#include<linux/of_irq.h>
> +#include<linux/pinctrl/consumer.h>
> +
> +#include<media/v4l2-device.h>
> +#include<media/v4l2-ioctl.h>
> +#include<media/v4l2-mem2mem.h>
> +#include<media/v4l2-of.h>
> +#include<media/videobuf2-core.h>
> +#include<media/videobuf2-dma-contig.h>
> +
> +#include "fimc-is.h"
> +#include "fimc-is-i2c.h"
> +
> +#define CLK_MCU_ISP_DIV0_FREQ	(200 * 1000000)
> +#define CLK_MCU_ISP_DIV1_FREQ	(100 * 1000000)
> +#define CLK_ISP_DIV0_FREQ	(134 * 1000000)
> +#define CLK_ISP_DIV1_FREQ	(68 * 1000000)
> +#define CLK_ISP_DIVMPWM_FREQ	(34 * 1000000)
> +
> +static char *fimc_is_clock_name[] = {
> +	[IS_CLK_ISP]		= "isp",
> +	[IS_CLK_MCU_ISP]	= "mcu_isp",
> +	[IS_CLK_ISP_DIV0]	= "isp_div0",
> +	[IS_CLK_ISP_DIV1]	= "isp_div1",
> +	[IS_CLK_ISP_DIVMPWM]	= "isp_divmpwm",
> +	[IS_CLK_MCU_ISP_DIV0]	= "mcu_isp_div0",
> +	[IS_CLK_MCU_ISP_DIV1]	= "mcu_isp_div1",
> +};
> +
> +static void fimc_is_put_clocks(struct fimc_is *is)
> +{
> +	int i;
> +
> +	for (i = 0; i<  IS_CLK_MAX_NUM; i++) {
> +		if (IS_ERR(is->clock[i]))
> +			continue;
> +		clk_unprepare(is->clock[i]);
> +		clk_put(is->clock[i]);
> +		is->clock[i] = NULL;
> +	}
> +}
> +
> +static int fimc_is_get_clocks(struct fimc_is *is)
> +{
> +	struct device *dev =&is->pdev->dev;
> +	int i, ret;
> +
> +	for (i = 0; i<  IS_CLK_MAX_NUM; i++) {
> +		is->clock[i] = clk_get(dev, fimc_is_clock_name[i]);
> +		if (IS_ERR(is->clock[i]))
> +			goto err;
> +		ret = clk_prepare(is->clock[i]);
> +		if (ret<  0) {
> +			clk_put(is->clock[i]);
> +			is->clock[i] = ERR_PTR(-EINVAL);
> +			goto err;
> +		}
> +	}
> +	return 0;
> +err:
> +	fimc_is_put_clocks(is);
> +	pr_err("Failed to get clock: %s\n", fimc_is_clock_name[i]);
> +	return -ENXIO;
> +}
> +
> +static int fimc_is_configure_clocks(struct fimc_is *is)
> +{
> +	int i, ret;
> +
> +	for (i = 0; i<  IS_CLK_MAX_NUM; i++)
> +		is->clock[i] = ERR_PTR(-EINVAL);
> +
> +	ret = fimc_is_get_clocks(is);
> +	if (ret)
> +		return ret;
> +
> +	/* Set rates */
> +	ret = clk_set_rate(is->clock[IS_CLK_MCU_ISP_DIV0],
> +			CLK_MCU_ISP_DIV0_FREQ);
> +	if (ret)
> +		return ret;
> +	ret = clk_set_rate(is->clock[IS_CLK_MCU_ISP_DIV1],
> +			CLK_MCU_ISP_DIV1_FREQ);
> +	if (ret)
> +		return ret;
> +	ret = clk_set_rate(is->clock[IS_CLK_ISP_DIV0], CLK_ISP_DIV0_FREQ);
> +	if (ret)
> +		return ret;
> +	ret = clk_set_rate(is->clock[IS_CLK_ISP_DIV1], CLK_ISP_DIV1_FREQ);
> +	if (ret)
> +		return ret;
> +	ret = clk_set_rate(is->clock[IS_CLK_ISP_DIVMPWM],
> +			CLK_ISP_DIVMPWM_FREQ);
> +	return ret;
> +}
> +
> +static void fimc_is_pipelines_destroy(struct fimc_is *is)
> +{
> +	int i;
> +
> +	for (i = 0; i<  is->num_instance; i++)
> +		fimc_is_pipeline_destroy(&is->pipeline[i]);
> +}
> +
> +static int fimc_is_parse_sensor_config(struct fimc_is *is, unsigned int index,
> +						struct device_node *node)
> +{
> +	struct fimc_is_sensor *sensor =&is->sensor[index];
> +	u32 tmp = 0;
> +	int ret;
> +
> +	sensor->drvdata = exynos5_is_sensor_get_drvdata(node);
> +	if (!sensor->drvdata) {
> +		dev_err(&is->pdev->dev, "no driver data found for: %s\n",
> +							 node->full_name);
> +		return -EINVAL;
> +	}
> +
> +	node = v4l2_of_get_next_endpoint(node, NULL);
> +	if (!node)
> +		return -ENXIO;
> +
> +	node = v4l2_of_get_remote_port(node);
> +	if (!node)
> +		return -ENXIO;
> +
> +	/* Use MIPI-CSIS channel id to determine the ISP I2C bus index. */
> +	ret = of_property_read_u32(node, "reg",&tmp);
> +	if (ret<  0) {
> +		dev_err(&is->pdev->dev, "reg property not found at: %s\n",
> +							 node->full_name);
> +		return ret;
> +	}
> +
> +	sensor->i2c_bus = tmp - FIMC_INPUT_MIPI_CSI2_0;
> +	return 0;
> +}
> +
> +static int fimc_is_parse_sensor(struct fimc_is *is)
> +{
> +	struct device_node *i2c_bus, *child;
> +	int ret, index = 0;
> +
> +	for_each_compatible_node(i2c_bus, NULL, FIMC_IS_I2C_COMPATIBLE) {
> +		for_each_available_child_of_node(i2c_bus, child) {
> +			ret = fimc_is_parse_sensor_config(is, index, child);
> +
> +			if (ret<  0 || index>= FIMC_IS_NUM_SENSORS) {
> +				of_node_put(child);
> +				return ret;
> +			}
> +			index++;
> +		}
> +	}
> +	return 0;
> +}
> +
> +static int fimc_is_probe(struct platform_device *pdev)
> +{
> +	struct device *dev =&pdev->dev;
> +	struct resource *res;
> +	struct fimc_is *is;
> +	void __iomem *regs;
> +	struct device_node *node;
> +	int irq, ret;
> +	int i;
> +
> +	pr_debug("FIMC-IS Probe Enter\n");

dev_dbg() ?

> +	if (!pdev->dev.of_node)
> +		return -ENODEV;
> +
> +	is = devm_kzalloc(&pdev->dev, sizeof(*is), GFP_KERNEL);
> +	if (!is)
> +		return -ENOMEM;
> +
> +	is->pdev = pdev;
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	regs = devm_ioremap_resource(dev, res);
> +	if (IS_ERR(regs))
> +		return PTR_ERR(regs);
> +
> +	/* Get the PMU base */
> +	node = of_get_child_by_name(dev->of_node, "pmu");
> +	if (!node)
> +		return -ENODEV;
> +	is->pmu_regs = of_iomap(node, 0);
> +	if (!is->pmu_regs)
> +		return -ENOMEM;
> +
> +	irq = irq_of_parse_and_map(dev->of_node, 0);
> +	if (irq<  0) {
> +		dev_err(dev, "Failed to get IRQ\n");
> +		return irq;
> +	}
> +
> +	ret = of_property_read_u32(pdev->dev.of_node, "num-instance",
> +			&is->num_instance);
> +	if (ret&&  !is->num_instance) {
> +		dev_err(dev, "Error num instances\n");

Hmm, what is this property ? I can't see it listed in the binding document.

> +		return -EINVAL;
> +	}
> +
> +	ret = fimc_is_configure_clocks(is);
> +	if (ret<  0) {
> +		dev_err(dev, "Clock config failed\n");

s/Clock config/clocks configration ?

> +		goto err_clk;
> +	}
> +
> +	platform_set_drvdata(pdev, is);
> +	pm_runtime_enable(dev);
> +
> +	ret = pm_runtime_get_sync(dev);
> +	if (ret<  0)
> +		goto err_pm;
> +
> +	is->alloc_ctx = vb2_dma_contig_init_ctx(dev);
> +	if (IS_ERR(is->alloc_ctx)) {
> +		ret = PTR_ERR(is->alloc_ctx);
> +		goto err_vb;
> +	}
> +
> +	/* Get IS-sensor contexts */
> +	ret = fimc_is_parse_sensor(is);
> +	if (ret<  0)
> +		goto err_vb;
> +
> +	/* Initialize FIMC Pipeline */
> +	for (i = 0; i<  is->num_instance; i++) {
> +		ret = fimc_is_pipeline_init(&is->pipeline[i], i, is);
> +		if (ret<  0)
> +			goto err_sd;
> +	}
> +
> +	/* Initialize FIMC Interface */
> +	ret = fimc_is_interface_init(&is->interface, regs, irq);
> +	if (ret<  0)
> +		goto err_sd;
> +
> +	pm_runtime_put(dev);
> +
> +	dev_dbg(dev, "FIMC-IS registered successfully\n");
> +
> +	return 0;
> +
> +err_sd:
> +	fimc_is_pipelines_destroy(is);
> +err_vb:
> +	vb2_dma_contig_cleanup_ctx(is->alloc_ctx);
> +err_pm:
> +	pm_runtime_put(dev);
> +err_clk:
> +	fimc_is_put_clocks(is);
> +
> +	return ret;
> +}
> +
> +int fimc_is_clk_enable(struct fimc_is *is)
> +{
> +	int ret;
> +
> +	ret = clk_enable(is->clock[IS_CLK_ISP]);
> +	if (ret)
> +		return ret;
> +	ret = clk_enable(is->clock[IS_CLK_MCU_ISP]);
> +	return ret;
> +}
> +
> +void fimc_is_clk_disable(struct fimc_is *is)
> +{
> +	clk_disable(is->clock[IS_CLK_ISP]);
> +	clk_disable(is->clock[IS_CLK_MCU_ISP]);
> +}
> +
> +static int fimc_is_pm_resume(struct device *dev)
> +{
> +	struct fimc_is *is = dev_get_drvdata(dev);
> +	int ret;
> +
> +	ret = fimc_is_clk_enable(is);
> +	if (ret<  0) {
> +		dev_err(dev, "Could not enable clocks\n");
> +		return ret;
> +	}
> +	return 0;
> +}
> +
> +static int fimc_is_pm_suspend(struct device *dev)
> +{
> +	struct fimc_is *is = dev_get_drvdata(dev);
> +
> +	fimc_is_clk_disable(is);
> +	return 0;
> +}
> +
> +static int fimc_is_runtime_resume(struct device *dev)
> +{
> +	return fimc_is_pm_resume(dev);
> +}
> +
> +static int fimc_is_runtime_suspend(struct device *dev)
> +{
> +	return fimc_is_pm_suspend(dev);
> +}
> +
> +#ifdef CONFIG_PM_SLEEP
> +static int fimc_is_resume(struct device *dev)
> +{
> +	return fimc_is_pm_resume(dev);

You're using same function for system sleep and runtime PM, fimc_is_resume()
should not attempt to disable the clocks if they are already disabled, i.e.
the device is not active.

> +}
> +
> +static int fimc_is_suspend(struct device *dev)
> +{
> +	return fimc_is_pm_suspend(dev);
> +}
> +#endif /* CONFIG_PM_SLEEP */
> +
> +static int fimc_is_remove(struct platform_device *pdev)
> +{
> +	struct fimc_is *is = platform_get_drvdata(pdev);
> +	struct device *dev =&pdev->dev;
> +
> +	pm_runtime_disable(dev);
> +	pm_runtime_set_suspended(dev);
> +	fimc_is_pipelines_destroy(is);
> +	vb2_dma_contig_cleanup_ctx(is->alloc_ctx);
> +	fimc_is_put_clocks(is);
> +	return 0;
> +}
> +
> +static const struct dev_pm_ops fimc_is_pm_ops = {
> +	SET_SYSTEM_SLEEP_PM_OPS(fimc_is_suspend, fimc_is_resume)
> +	SET_RUNTIME_PM_OPS(fimc_is_runtime_suspend, fimc_is_runtime_resume,
> +			   NULL)
> +};
> +
> +static const struct of_device_id exynos5_fimc_is_match[] = {
> +	{
> +		.compatible = "samsung,exynos5250-fimc-is",
> +	},
> +	{},
> +};
> +MODULE_DEVICE_TABLE(of, exynos5_fimc_is_match);
> +
> +static struct platform_driver fimc_is_driver = {
> +	.probe		= fimc_is_probe,
> +	.remove		= fimc_is_remove,
> +	.driver = {
> +		.name	= FIMC_IS_DRV_NAME,
> +		.owner	= THIS_MODULE,
> +		.pm	=&fimc_is_pm_ops,
> +		.of_match_table = exynos5_fimc_is_match,
> +	}
> +};
> +module_platform_driver(fimc_is_driver);
> +
> +MODULE_LICENSE("GPL");
> +MODULE_AUTHOR("Arun Kumar K<arun.kk@samsung.com>");
> +MODULE_DESCRIPTION("Samsung Exynos5 (FIMC-IS) Imaging Subsystem driver");
> diff --git a/drivers/media/platform/exynos5-is/fimc-is-core.h b/drivers/media/platform/exynos5-is/fimc-is-core.h
> new file mode 100644
> index 0000000..45b56cc
> --- /dev/null
> +++ b/drivers/media/platform/exynos5-is/fimc-is-core.h
> @@ -0,0 +1,122 @@
> +/*
> + * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
> + *
> + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
> + *  Arun Kumar K<arun.kk@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +#ifndef FIMC_IS_CORE_H_
> +#define FIMC_IS_CORE_H_
> +
> +#include<linux/bug.h>
> +#include<linux/clk.h>
> +#include<linux/device.h>
> +#include<linux/errno.h>
> +#include<linux/firmware.h>
> +#include<linux/interrupt.h>
> +#include<linux/kernel.h>
> +#include<linux/list.h>
> +#include<linux/module.h>
> +#include<linux/types.h>
> +#include<linux/platform_device.h>
> +#include<linux/pm_runtime.h>
> +#include<linux/slab.h>
> +#include<linux/videodev2.h>
> +
> +#include<asm/barrier.h>
> +#include<linux/sizes.h>
> +#include<linux/io.h>
> +#include<linux/irqreturn.h>
> +#include<linux/platform_device.h>
> +#include<linux/sched.h>
> +#include<linux/spinlock.h>
> +
> +#include<media/media-entity.h>
> +#include<media/videobuf2-core.h>
> +#include<media/v4l2-ctrls.h>
> +#include<media/v4l2-device.h>
> +#include<media/v4l2-mem2mem.h>
> +#include<media/v4l2-mediabus.h>
> +#include<media/s5p_fimc.h>
> +
> +#define FIMC_IS_DRV_NAME		"exynos5-fimc-is"
> +
> +#define FIMC_IS_COMMAND_TIMEOUT		(3 * HZ)
> +#define FIMC_IS_STARTUP_TIMEOUT		(3 * HZ)
> +#define FIMC_IS_SHUTDOWN_TIMEOUT	(10 * HZ)
> +
> +#define FW_SHARED_OFFSET		(0x8c0000)
> +#define DEBUG_CNT			(500*1024)

nit: please add space around '*'.

> +#define DEBUG_OFFSET			(0x840000)
> +#define DEBUGCTL_OFFSET			(0x8bd000)
> +#define DEBUG_FCOUNT			(0x8c64c0)
> +
> +#define FIMC_IS_MAX_INSTANCES		1
> +
> +#define FIMC_IS_NUM_SENSORS		2
> +#define FIMC_IS_NUM_PIPELINES		1
> +
> +#define FIMC_IS_MAX_PLANES		3
> +#define FIMC_IS_NUM_SCALERS		2
> +
> +enum fimc_is_clks {
> +	IS_CLK_ISP,
> +	IS_CLK_MCU_ISP,
> +	IS_CLK_ISP_DIV0,
> +	IS_CLK_ISP_DIV1,
> +	IS_CLK_ISP_DIVMPWM,
> +	IS_CLK_MCU_ISP_DIV0,
> +	IS_CLK_MCU_ISP_DIV1,
> +	IS_CLK_MAX_NUM
> +};
> +
> +/* Video capture states */
> +enum fimc_is_video_state {
> +	STATE_INIT,
> +	STATE_BUFS_ALLOCATED,
> +	STATE_RUNNING,
> +};
> +
> +enum fimc_is_scaler_id {
> +	SCALER_SCC,
> +	SCALER_SCP
> +};
> +
> +enum fimc_is_sensor_pos {
> +	SENSOR_CAM0,
> +	SENSOR_CAM1
> +};
> +
> +struct fimc_is_buf {
> +	struct list_head list;
> +	struct vb2_buffer *vb;
> +	unsigned int paddr[FIMC_IS_MAX_PLANES];
> +};
> +
> +struct fimc_is_meminfo {
> +	unsigned int fw_paddr;
> +	unsigned int fw_vaddr;
> +	unsigned int region_paddr;
> +	unsigned int region_vaddr;
> +	unsigned int shared_paddr;
> +	unsigned int shared_vaddr;
> +};
> +
> +/**
> + * struct fimc_is_fmt - the driver's internal color format data
> + * @name: format description
> + * @fourcc: the fourcc code for this format
> + * @depth: number of bytes per pixel
> + * @num_planes: number of planes for this color format
> + */
> +struct fimc_is_fmt {
> +	char		*name;
> +	unsigned int	fourcc;
> +	unsigned int	depth[FIMC_IS_MAX_PLANES];
> +	unsigned int	num_planes;
> +};
> +
> +#endif

Otherwise looks good.

Thanks,
Sylwester

Re: [RFC v3 04/13] [media] exynos5-fimc-is: Add common driver header files

[Sylwester Nawrocki]

On 08/02/2013 05:02 PM, Arun Kumar K wrote:
> This patch adds all the common header files used by the fimc-is
> driver. It includes the commands for interfacing with the firmware
> and error codes from IS firmware, metadata and command parameter
> definitions.
>
> Signed-off-by: Arun Kumar K<arun.kk@samsung.com>
> Signed-off-by: Kilyeon Im<kilyeon.im@samsung.com>
> ---
>   drivers/media/platform/exynos5-is/fimc-is-cmd.h    |  187 +++
>   drivers/media/platform/exynos5-is/fimc-is-err.h    |  257 +++++
>   .../media/platform/exynos5-is/fimc-is-metadata.h   |  767 +++++++++++++
>   drivers/media/platform/exynos5-is/fimc-is-param.h  | 1212 ++++++++++++++++++++
>   4 files changed, 2423 insertions(+)
>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-cmd.h
>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-err.h
>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-metadata.h
>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-param.h
>
[...]
> diff --git a/drivers/media/platform/exynos5-is/fimc-is-metadata.h b/drivers/media/platform/exynos5-is/fimc-is-metadata.h
> new file mode 100644
> index 0000000..2f6339d
> --- /dev/null
> +++ b/drivers/media/platform/exynos5-is/fimc-is-metadata.h
> @@ -0,0 +1,767 @@
> +/*
> + * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
> + *
> + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
> + * Kil-yeon Lim<kilyeon.im@samsung.com>
> + * Arun Kumar K<arun.kk@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef FIMC_IS_METADATA_H_
> +#define FIMC_IS_METADATA_H_
> +
> +struct rational {
> +	uint32_t num;
> +	uint32_t den;
> +};
> +
> +#define CAMERA2_MAX_AVAILABLE_MODE	21
> +#define CAMERA2_MAX_FACES		16
> +
> +/*
> + * Controls/dynamic metadata
> + */
> +
> +enum metadata_mode {
> +	METADATA_MODE_NONE,
> +	METADATA_MODE_FULL
> +};
> +
> +struct camera2_request_ctl {
> +	uint32_t		id;
> +	enum metadata_mode	metadatamode;
> +	uint8_t			outputstreams[16];
> +	uint32_t		framecount;
> +};
> +
> +struct camera2_request_dm {
> +	uint32_t		id;
> +	enum metadata_mode	metadatamode;
> +	uint32_t		framecount;
> +};
> +
> +
> +
> +enum optical_stabilization_mode {
> +	OPTICAL_STABILIZATION_MODE_OFF,
> +	OPTICAL_STABILIZATION_MODE_ON
> +};
> +
> +enum lens_facing {
> +	LENS_FACING_BACK,
> +	LENS_FACING_FRONT
> +};
> +
> +struct camera2_lens_ctl {
> +	uint32_t				focus_distance;
> +	float					aperture;
> +	float					focal_length;
> +	float					filter_density;
> +	enum optical_stabilization_mode		optical_stabilization_mode;
> +};
> +
> +struct camera2_lens_dm {
> +	uint32_t				focus_distance;
> +	float					aperture;
> +	float					focal_length;
> +	float					filter_density;
> +	enum optical_stabilization_mode		optical_stabilization_mode;
> +	float					focus_range[2];
> +};
> +
> +struct camera2_lens_sm {
> +	float				minimum_focus_distance;
> +	float				hyper_focal_distance;
> +	float				available_focal_length[2];
> +	float				available_apertures;
> +	/* assuming 1 aperture */
> +	float				available_filter_densities;
> +	/* assuming 1 ND filter value */
> +	enum optical_stabilization_mode	available_optical_stabilization;
> +	/* assuming 1 */
> +	uint32_t			shading_map_size;
> +	float				shading_map[3][40][30];
> +	uint32_t			geometric_correction_map_size;
> +	float				geometric_correction_map[2][3][40][30];
> +	enum lens_facing		facing;
> +	float				position[2];
> +};
> +
> +enum sensor_colorfilter_arrangement {
> +	SENSOR_COLORFILTER_ARRANGEMENT_RGGB,
> +	SENSOR_COLORFILTER_ARRANGEMENT_GRBG,
> +	SENSOR_COLORFILTER_ARRANGEMENT_GBRG,
> +	SENSOR_COLORFILTER_ARRANGEMENT_BGGR,
> +	SENSOR_COLORFILTER_ARRANGEMENT_RGB
> +};
> +
> +enum sensor_ref_illuminant {
> +	SENSOR_ILLUMINANT_DAYLIGHT = 1,
> +	SENSOR_ILLUMINANT_FLUORESCENT = 2,
> +	SENSOR_ILLUMINANT_TUNGSTEN = 3,
> +	SENSOR_ILLUMINANT_FLASH = 4,
> +	SENSOR_ILLUMINANT_FINE_WEATHER = 9,
> +	SENSOR_ILLUMINANT_CLOUDY_WEATHER = 10,
> +	SENSOR_ILLUMINANT_SHADE = 11,
> +	SENSOR_ILLUMINANT_DAYLIGHT_FLUORESCENT = 12,
> +	SENSOR_ILLUMINANT_DAY_WHITE_FLUORESCENT = 13,
> +	SENSOR_ILLUMINANT_COOL_WHITE_FLUORESCENT = 14,
> +	SENSOR_ILLUMINANT_WHITE_FLUORESCENT = 15,
> +	SENSOR_ILLUMINANT_STANDARD_A = 17,
> +	SENSOR_ILLUMINANT_STANDARD_B = 18,
> +	SENSOR_ILLUMINANT_STANDARD_C = 19,
> +	SENSOR_ILLUMINANT_D55 = 20,
> +	SENSOR_ILLUMINANT_D65 = 21,
> +	SENSOR_ILLUMINANT_D75 = 22,
> +	SENSOR_ILLUMINANT_D50 = 23,
> +	SENSOR_ILLUMINANT_ISO_STUDIO_TUNGSTEN = 24
> +};
> +
> +struct camera2_sensor_ctl {
> +	/* unit : nano */
> +	uint64_t	exposure_time;
> +	/* unit : nano(It's min frame duration */
> +	uint64_t	frame_duration;
> +	/* unit : percent(need to change ISO value?) */
> +	uint32_t	sensitivity;
> +};
> +
> +struct camera2_sensor_dm {
> +	uint64_t	exposure_time;
> +	uint64_t	frame_duration;
> +	uint32_t	sensitivity;
> +	uint64_t	timestamp;
> +};
> +
> +struct camera2_sensor_sm {
> +	uint32_t	exposure_time_range[2];
> +	uint32_t	max_frame_duration;
> +	/* list of available sensitivities. */
> +	uint32_t	available_sensitivities[10];
> +	enum sensor_colorfilter_arrangement colorfilter_arrangement;
> +	float		physical_size[2];
> +	uint32_t	pixel_array_size[2];
> +	uint32_t	active_array_size[4];
> +	uint32_t	white_level;
> +	uint32_t	black_level_pattern[4];
> +	struct rational	color_transform1[9];
> +	struct rational	color_transform2[9];
> +	enum sensor_ref_illuminant	reference_illuminant1;
> +	enum sensor_ref_illuminant	reference_illuminant2;
> +	struct rational	forward_matrix1[9];
> +	struct rational	forward_matrix2[9];
> +	struct rational	calibration_transform1[9];
> +	struct rational	calibration_transform2[9];
> +	struct rational	base_gain_factor;
> +	uint32_t	max_analog_sensitivity;
> +	float		noise_model_coefficients[2];
> +	uint32_t	orientation;
> +};
> +
> +
> +
> +enum flash_mode {
> +	CAM2_FLASH_MODE_OFF = 1,
> +	CAM2_FLASH_MODE_SINGLE,
> +	CAM2_FLASH_MODE_TORCH,
> +	CAM2_FLASH_MODE_BEST
> +};
> +
> +struct camera2_flash_ctl {
> +	enum flash_mode		flash_mode;
> +	uint32_t		firing_power;
> +	uint64_t		firing_time;
> +};
> +
> +struct camera2_flash_dm {
> +	enum flash_mode		flash_mode;
> +	/* 10 is max power */
> +	uint32_t		firing_power;
> +	/* unit : microseconds */
> +	uint64_t		firing_time;
> +	/* 1 : stable, 0 : unstable */
> +	uint32_t		firing_stable;
> +	/* 1 : success, 0 : fail */
> +	uint32_t		decision;
> +};
> +
> +struct camera2_flash_sm {
> +	uint32_t	available;
> +	uint64_t	charge_duration;
> +};
> +
> +enum processing_mode {
> +	PROCESSING_MODE_OFF = 1,
> +	PROCESSING_MODE_FAST,
> +	PROCESSING_MODE_HIGH_QUALITY
> +};
> +
> +
> +struct camera2_hotpixel_ctl {
> +	enum processing_mode	mode;
> +};
> +
> +struct camera2_hotpixel_dm {
> +	enum processing_mode	mode;
> +};
> +
> +struct camera2_demosaic_ctl {
> +	enum processing_mode	mode;
> +};
> +
> +struct camera2_demosaic_dm {
> +	enum processing_mode	mode;
> +};
> +
> +struct camera2_noise_reduction_ctl {
> +	enum processing_mode	mode;
> +	uint32_t		strength;
> +};
> +
> +struct camera2_noise_reduction_dm {
> +	enum processing_mode	mode;
> +	uint32_t		strength;
> +};
> +
> +struct camera2_shading_ctl {
> +	enum processing_mode	mode;
> +};
> +
> +struct camera2_shading_dm {
> +	enum processing_mode	mode;
> +};
> +
> +struct camera2_geometric_ctl {
> +	enum processing_mode	mode;
> +};
> +
> +struct camera2_geometric_dm {
> +	enum processing_mode	mode;
> +};
> +
> +enum color_correction_mode {
> +	COLOR_CORRECTION_MODE_FAST = 1,
> +	COLOR_CORRECTION_MODE_HIGH_QUALITY,
> +	COLOR_CORRECTION_MODE_TRANSFORM_MATRIX,
> +	COLOR_CORRECTION_MODE_EFFECT_MONO,
> +	COLOR_CORRECTION_MODE_EFFECT_NEGATIVE,
> +	COLOR_CORRECTION_MODE_EFFECT_SOLARIZE,
> +	COLOR_CORRECTION_MODE_EFFECT_SEPIA,
> +	COLOR_CORRECTION_MODE_EFFECT_POSTERIZE,
> +	COLOR_CORRECTION_MODE_EFFECT_WHITEBOARD,
> +	COLOR_CORRECTION_MODE_EFFECT_BLACKBOARD,
> +	COLOR_CORRECTION_MODE_EFFECT_AQUA
> +};
> +
> +
> +struct camera2_color_correction_ctl {
> +	enum color_correction_mode	mode;
> +	float				transform[9];
> +	uint32_t			hue;
> +	uint32_t			saturation;
> +	uint32_t			brightness;
> +};
> +
> +struct camera2_color_correction_dm {
> +	enum color_correction_mode	mode;
> +	float				transform[9];
> +	uint32_t			hue;
> +	uint32_t			saturation;
> +	uint32_t			brightness;
> +};
> +
> +struct camera2_color_correction_sm {
> +	/* assuming 10 supported modes */
> +	uint8_t			available_modes[CAMERA2_MAX_AVAILABLE_MODE];
> +	uint32_t		hue_range[2];
> +	uint32_t		saturation_range[2];
> +	uint32_t		brightness_range[2];
> +};
> +
> +enum tonemap_mode {
> +	TONEMAP_MODE_FAST = 1,
> +	TONEMAP_MODE_HIGH_QUALITY,
> +	TONEMAP_MODE_CONTRAST_CURVE
> +};
> +
> +struct camera2_tonemap_ctl {
> +	enum tonemap_mode		mode;
> +	/* assuming maxCurvePoints = 64 */
> +	float				curve_red[64];
> +	float				curve_green[64];
> +	float				curve_blue[64];
> +};
> +
> +struct camera2_tonemap_dm {
> +	enum tonemap_mode		mode;
> +	/* assuming maxCurvePoints = 64 */
> +	float				curve_red[64];
> +	float				curve_green[64];
> +	float				curve_blue[64];

So all those floating point numbers are now not really used in
the driver but we need them for proper data structures/offsets
declarations of the firmware interface ?

> +};
> +
> +struct camera2_tonemap_sm {
> +	uint32_t	max_curve_points;
> +};
> +
> +struct camera2_edge_ctl {
> +	enum processing_mode	mode;
> +	uint32_t		strength;
> +};
> +
> +struct camera2_edge_dm {
> +	enum processing_mode	mode;
> +	uint32_t		strength;
> +};
> +
> +enum scaler_formats {
> +	SCALER_FORMAT_BAYER_RAW,
> +	SCALER_FORMAT_YV12,
> +	SCALER_FORMAT_NV21,
> +	SCALER_FORMAT_JPEG,
> +	SCALER_FORMAT_UNKNOWN
> +};
> +
> +struct camera2_scaler_ctl {
> +	uint32_t	crop_region[3];
> +};
> +
> +struct camera2_scaler_dm {
> +	uint32_t	crop_region[3];
> +};
> +
> +struct camera2_scaler_sm {
> +	enum scaler_formats available_formats[4];
> +	/* assuming # of availableFormats = 4 */
> +	uint32_t	available_raw_sizes;
> +	uint64_t	available_raw_min_durations;
> +	/* needs check */
> +	uint32_t	available_processed_sizes[8];
> +	uint64_t	available_processed_min_durations[8];
> +	uint32_t	available_jpeg_sizes[8][2];
> +	uint64_t	available_jpeg_min_durations[8];
> +	uint32_t	available_max_digital_zoom[8];
> +};
> +
> +struct camera2_jpeg_ctl {
> +	uint32_t	quality;
> +	uint32_t	thumbnail_size[2];
> +	uint32_t	thumbnail_quality;
> +	double		gps_coordinates[3];
> +	uint32_t	gps_processing_method;
> +	uint64_t	gps_timestamp;
> +	uint32_t	orientation;
> +};
> +
> +struct camera2_jpeg_dm {
> +	uint32_t	quality;
> +	uint32_t	thumbnail_size[2];
> +	uint32_t	thumbnail_quality;
> +	double		gps_coordinates[3];
> +	uint32_t	gps_processing_method;
> +	uint64_t	gps_timestamp;
> +	uint32_t	orientation;
> +};
> +
> +struct camera2_jpeg_sm {
> +	uint32_t	available_thumbnail_sizes[8][2];
> +	uint32_t	maxsize;
> +	/* assuming supported size=8 */
> +};
> +
> +enum face_detect_mode {
> +	FACEDETECT_MODE_OFF = 1,
> +	FACEDETECT_MODE_SIMPLE,
> +	FACEDETECT_MODE_FULL
> +};
> +
> +enum stats_mode {
> +	STATS_MODE_OFF = 1,
> +	STATS_MODE_ON
> +};
> +
> +struct camera2_stats_ctl {
> +	enum face_detect_mode	face_detect_mode;
> +	enum stats_mode		histogram_mode;
> +	enum stats_mode		sharpness_map_mode;
> +};
> +
> +
> +struct camera2_stats_dm {
> +	enum face_detect_mode	face_detect_mode;
> +	uint32_t		face_rectangles[CAMERA2_MAX_FACES][4];
> +	uint8_t			face_scores[CAMERA2_MAX_FACES];
> +	uint32_t		face_landmarks[CAMERA2_MAX_FACES][6];
> +	uint32_t		face_ids[CAMERA2_MAX_FACES];
> +	enum stats_mode		histogram_mode;
> +	uint32_t		histogram[3 * 256];
> +	enum stats_mode		sharpness_map_mode;
> +};
> +
> +
> +struct camera2_stats_sm {
> +	uint8_t		available_face_detect_modes[CAMERA2_MAX_AVAILABLE_MODE];
> +	/* assuming supported modes = 3 */
> +	uint32_t	max_face_count;
> +	uint32_t	histogram_bucket_count;
> +	uint32_t	max_histogram_count;
> +	uint32_t	sharpness_map_size[2];
> +	uint32_t	max_sharpness_map_value;
> +};
> +
> +enum aa_capture_intent {
> +	AA_CAPTURE_INTENT_CUSTOM = 0,
> +	AA_CAPTURE_INTENT_PREVIEW,
> +	AA_CAPTURE_INTENT_STILL_CAPTURE,
> +	AA_CAPTURE_INTENT_VIDEO_RECORD,
> +	AA_CAPTURE_INTENT_VIDEO_SNAPSHOT,
> +	AA_CAPTURE_INTENT_ZERO_SHUTTER_LAG
> +};
> +
> +enum aa_mode {
> +	AA_CONTROL_OFF = 1,
> +	AA_CONTROL_AUTO,
> +	AA_CONTROL_USE_SCENE_MODE
> +};
> +
> +enum aa_scene_mode {
> +	AA_SCENE_MODE_UNSUPPORTED = 1,
> +	AA_SCENE_MODE_FACE_PRIORITY,
> +	AA_SCENE_MODE_ACTION,
> +	AA_SCENE_MODE_PORTRAIT,
> +	AA_SCENE_MODE_LANDSCAPE,
> +	AA_SCENE_MODE_NIGHT,
> +	AA_SCENE_MODE_NIGHT_PORTRAIT,
> +	AA_SCENE_MODE_THEATRE,
> +	AA_SCENE_MODE_BEACH,
> +	AA_SCENE_MODE_SNOW,
> +	AA_SCENE_MODE_SUNSET,
> +	AA_SCENE_MODE_STEADYPHOTO,
> +	AA_SCENE_MODE_FIREWORKS,
> +	AA_SCENE_MODE_SPORTS,
> +	AA_SCENE_MODE_PARTY,
> +	AA_SCENE_MODE_CANDLELIGHT,
> +	AA_SCENE_MODE_BARCODE,
> +	AA_SCENE_MODE_NIGHT_CAPTURE
> +};
> +
> +enum aa_effect_mode {
> +	AA_EFFECT_OFF = 1,
> +	AA_EFFECT_MONO,
> +	AA_EFFECT_NEGATIVE,
> +	AA_EFFECT_SOLARIZE,
> +	AA_EFFECT_SEPIA,
> +	AA_EFFECT_POSTERIZE,
> +	AA_EFFECT_WHITEBOARD,
> +	AA_EFFECT_BLACKBOARD,
> +	AA_EFFECT_AQUA
> +};
> +
> +enum aa_aemode {
> +	AA_AEMODE_OFF = 1,
> +	AA_AEMODE_LOCKED,
> +	AA_AEMODE_ON,
> +	AA_AEMODE_ON_AUTO_FLASH,
> +	AA_AEMODE_ON_ALWAYS_FLASH,
> +	AA_AEMODE_ON_AUTO_FLASH_REDEYE
> +};
> +
> +enum aa_ae_flashmode {
> +	/* all flash control stop */
> +	AA_FLASHMODE_OFF = 1,
> +	/* internal 3A can control flash */
> +	AA_FLASHMODE_ON,
> +	/* internal 3A can do auto flash algorithm */
> +	AA_FLASHMODE_AUTO,
> +	/* internal 3A can fire flash by auto result */
> +	AA_FLASHMODE_CAPTURE,
> +	/* internal 3A can control flash forced */
> +	AA_FLASHMODE_ON_ALWAYS
> +
> +};
> +
> +enum aa_ae_antibanding_mode {
> +	AA_AE_ANTIBANDING_OFF = 1,
> +	AA_AE_ANTIBANDING_50HZ,
> +	AA_AE_ANTIBANDING_60HZ,
> +	AA_AE_ANTIBANDING_AUTO
> +};
> +
> +enum aa_awbmode {
> +	AA_AWBMODE_OFF = 1,
> +	AA_AWBMODE_LOCKED,
> +	AA_AWBMODE_WB_AUTO,
> +	AA_AWBMODE_WB_INCANDESCENT,
> +	AA_AWBMODE_WB_FLUORESCENT,
> +	AA_AWBMODE_WB_WARM_FLUORESCENT,
> +	AA_AWBMODE_WB_DAYLIGHT,
> +	AA_AWBMODE_WB_CLOUDY_DAYLIGHT,
> +	AA_AWBMODE_WB_TWILIGHT,
> +	AA_AWBMODE_WB_SHADE
> +};
> +
> +enum aa_afmode {
> +	AA_AFMODE_OFF = 1,
> +	AA_AFMODE_AUTO,
> +	AA_AFMODE_MACRO,
> +	AA_AFMODE_CONTINUOUS_VIDEO,
> +	AA_AFMODE_CONTINUOUS_PICTURE,
> +	AA_AFMODE_EDOF
> +};
> +
> +enum aa_afstate {
> +	AA_AFSTATE_INACTIVE = 1,
> +	AA_AFSTATE_PASSIVE_SCAN,
> +	AA_AFSTATE_ACTIVE_SCAN,
> +	AA_AFSTATE_AF_ACQUIRED_FOCUS,
> +	AA_AFSTATE_AF_FAILED_FOCUS
> +};
> +
> +enum ae_state {
> +	AE_STATE_INACTIVE = 1,
> +	AE_STATE_SEARCHING,
> +	AE_STATE_CONVERGED,
> +	AE_STATE_LOCKED,
> +	AE_STATE_FLASH_REQUIRED,
> +	AE_STATE_PRECAPTURE
> +};
> +
> +enum awb_state {
> +	AWB_STATE_INACTIVE = 1,
> +	AWB_STATE_SEARCHING,
> +	AWB_STATE_CONVERGED,
> +	AWB_STATE_LOCKED
> +};
> +
> +enum aa_isomode {
> +	AA_ISOMODE_AUTO = 1,
> +	AA_ISOMODE_MANUAL,
> +};
> +
> +struct camera2_aa_ctl {
> +	enum aa_capture_intent		capture_intent;
> +	enum aa_mode			mode;
> +	enum aa_scene_mode		scene_mode;
> +	uint32_t			video_stabilization_mode;
> +	enum aa_aemode			ae_mode;
> +	uint32_t			ae_regions[5];
> +	/* 5 per region(x1,y1,x2,y2,weight). Currently assuming 1 region. */
> +	int32_t				ae_exp_compensation;
> +	uint32_t			ae_target_fps_range[2];
> +	enum aa_ae_antibanding_mode	ae_anti_banding_mode;
> +	enum aa_ae_flashmode		ae_flash_mode;
> +	enum aa_awbmode			awb_mode;
> +	uint32_t			awb_regions[5];
> +	/* 5 per region(x1,y1,x2,y2,weight). Currently assuming 1 region. */
> +	enum aa_afmode			af_mode;
> +	uint32_t			af_regions[5];
> +	/* 5 per region(x1,y1,x2,y2,weight). Currently assuming 1 region. */
> +	uint32_t			af_trigger;
> +	enum aa_isomode			iso_mode;
> +	uint32_t			iso_value;
> +
> +};
> +
> +struct camera2_aa_dm {
> +	enum aa_mode				mode;
> +	enum aa_effect_mode			effect_mode;
> +	enum aa_scene_mode			scene_mode;
> +	uint32_t				video_stabilization_mode;
> +	enum aa_aemode				ae_mode;
> +	uint32_t				ae_regions[5];
> +	/* 5 per region(x1,y1,x2,y2,weight). Currently assuming 1 region. */
> +	enum ae_state				ae_state;
> +	enum aa_ae_flashmode			ae_flash_mode;
> +	enum aa_awbmode				awb_mode;
> +	uint32_t				awb_regions[5];
> +	enum awb_state				awb_state;
> +	/* 5 per region(x1,y1,x2,y2,weight). Currently assuming 1 region. */
> +	enum aa_afmode				af_mode;
> +	uint32_t				af_regions[5];
> +	/* 5 per region(x1,y1,x2,y2,weight). Currently assuming 1 region */
> +	enum aa_afstate				af_state;
> +	enum aa_isomode				iso_mode;
> +	uint32_t				iso_value;
> +};
> +
> +struct camera2_aa_sm {
> +	uint8_t	available_scene_modes[CAMERA2_MAX_AVAILABLE_MODE];
> +	uint8_t	available_effects[CAMERA2_MAX_AVAILABLE_MODE];
> +	/* Assuming # of available scene modes = 10 */
> +	uint32_t max_regions;
> +	uint8_t ae_available_modes[CAMERA2_MAX_AVAILABLE_MODE];
> +	/* Assuming # of available ae modes = 8 */
> +	struct rational	ae_compensation_step;
> +	int32_t	ae_compensation_range[2];
> +	uint32_t ae_available_target_fps_ranges[CAMERA2_MAX_AVAILABLE_MODE][2];
> +	uint8_t	 ae_available_antibanding_modes[CAMERA2_MAX_AVAILABLE_MODE];
> +	uint8_t	awb_available_modes[CAMERA2_MAX_AVAILABLE_MODE];
> +	/* Assuming # of awbAvailableModes = 10 */
> +	uint8_t	af_available_modes[CAMERA2_MAX_AVAILABLE_MODE];
> +	/* Assuming # of afAvailableModes = 4 */
> +	uint8_t	available_video_stabilization_modes[4];
> +	/* Assuming # of availableVideoStabilizationModes = 4 */
> +	uint32_t iso_range[2];
> +};
> +
> +struct camera2_lens_usm {
> +	/* Frame delay between sending command and applying frame data */
> +	uint32_t	focus_distance_frame_delay;
> +};
> +
> +struct camera2_sensor_usm {
> +	/* Frame delay between sending command and applying frame data */
> +	uint32_t	exposure_time_frame_delay;
> +	uint32_t	frame_duration_frame_delay;
> +	uint32_t	sensitivity_frame_delay;
> +};
> +
> +struct camera2_flash_usm {
> +	/* Frame delay between sending command and applying frame data */
> +	uint32_t	flash_mode_frame_delay;
> +	uint32_t	firing_power_frame_delay;
> +	uint64_t	firing_time_frame_delay;
> +};
> +
> +struct camera2_ctl {
> +	struct camera2_request_ctl		request;
> +	struct camera2_lens_ctl			lens;
> +	struct camera2_sensor_ctl		sensor;
> +	struct camera2_flash_ctl		flash;
> +	struct camera2_hotpixel_ctl		hotpixel;
> +	struct camera2_demosaic_ctl		demosaic;
> +	struct camera2_noise_reduction_ctl	noise;
> +	struct camera2_shading_ctl		shading;
> +	struct camera2_geometric_ctl		geometric;
> +	struct camera2_color_correction_ctl	color;
> +	struct camera2_tonemap_ctl		tonemap;
> +	struct camera2_edge_ctl			edge;
> +	struct camera2_scaler_ctl		scaler;
> +	struct camera2_jpeg_ctl			jpeg;
> +	struct camera2_stats_ctl		stats;
> +	struct camera2_aa_ctl			aa;
> +};
> +
> +struct camera2_dm {
> +	struct camera2_request_dm		request;
> +	struct camera2_lens_dm			lens;
> +	struct camera2_sensor_dm		sensor;
> +	struct camera2_flash_dm			flash;
> +	struct camera2_hotpixel_dm		hotpixel;
> +	struct camera2_demosaic_dm		demosaic;
> +	struct camera2_noise_reduction_dm	noise;
> +	struct camera2_shading_dm		shading;
> +	struct camera2_geometric_dm		geometric;
> +	struct camera2_color_correction_dm	color;
> +	struct camera2_tonemap_dm		tonemap;
> +	struct camera2_edge_dm			edge;
> +	struct camera2_scaler_dm		scaler;
> +	struct camera2_jpeg_dm			jpeg;
> +	struct camera2_stats_dm			stats;
> +	struct camera2_aa_dm			aa;
> +};
> +
> +struct camera2_sm {
> +	struct camera2_lens_sm			lens;
> +	struct camera2_sensor_sm		sensor;
> +	struct camera2_flash_sm			flash;
> +	struct camera2_color_correction_sm	color;
> +	struct camera2_tonemap_sm		tonemap;
> +	struct camera2_scaler_sm		scaler;
> +	struct camera2_jpeg_sm			jpeg;
> +	struct camera2_stats_sm			stats;
> +	struct camera2_aa_sm			aa;
> +
> +	/* User-defined(ispfw specific) static metadata. */
> +	struct camera2_lens_usm			lensud;
> +	struct camera2_sensor_usm		sensor_ud;
> +	struct camera2_flash_usm		flash_ud;
> +};
> +
> +/*
> + * User-defined control for lens.
> + */
> +struct camera2_lens_uctl {
> +	struct camera2_lens_ctl ctl;
> +
> +	/* It depends by af algorithm(normally 255 or 1023) */
> +	uint32_t        max_pos;
> +	/* Some actuator support slew rate control. */
> +	uint32_t        slew_rate;
> +};
> +
> +/*
> + * User-defined metadata for lens.
> + */
> +struct camera2_lens_udm {
> +	/* It depends by af algorithm(normally 255 or 1023) */
> +	uint32_t        max_pos;
> +	/* Some actuator support slew rate control. */
> +	uint32_t        slew_rate;
> +};
> +
> +/*
> + * User-defined control for sensor.
> + */
> +struct camera2_sensor_uctl {
> +	struct camera2_sensor_ctl ctl;
> +	/* Dynamic frame duration.
> +	 * This feature is decided to max. value between
> +	 * 'sensor.exposureTime'+alpha and 'sensor.frameDuration'.
> +	 */
> +	uint64_t        dynamic_frame_duration;
> +};
> +
> +struct camera2_scaler_uctl {
> +	/* Target address for next frame.
> +	 * [0] invalid address, stop
> +	 * [others] valid address
> +	 */
> +	uint32_t scc_target_address[4];
> +	uint32_t scp_target_address[4];
> +};
> +
> +struct camera2_flash_uctl {
> +	struct camera2_flash_ctl ctl;
> +};
> +
> +struct camera2_uctl {
> +	/* Set sensor, lens, flash control for next frame.
> +	 * This flag can be combined.
> +	 * [0 bit] lens
> +	 * [1 bit] sensor
> +	 * [2 bit] flash
> +	 */
> +	uint32_t u_update_bitmap;
> +
> +	/* For debugging */
> +	uint32_t u_frame_number;
> +
> +	/* isp fw specific control(user-defined) of lens. */
> +	struct camera2_lens_uctl	lens_ud;
> +	/* isp fw specific control(user-defined) of sensor. */
> +	struct camera2_sensor_uctl	sensor_ud;
> +	/* isp fw specific control(user-defined) of flash. */

nit: please add spaces before '('.

> +	struct camera2_flash_uctl	flash_ud;
> +
> +	struct camera2_scaler_uctl	scaler_ud;
> +};
> +
> +struct camera2_udm {
> +	struct camera2_lens_udm		lens;
> +};
> +
> +struct camera2_shot {
> +	/* standard area */
> +	struct camera2_ctl	ctl;
> +	struct camera2_dm	dm;
> +	/* user defined area */
> +	struct camera2_uctl	uctl;
> +	struct camera2_udm	udm;
> +	/* magic : 23456789 */
> +	uint32_t		magicnumber;
> +};
> +#endif
> diff --git a/drivers/media/platform/exynos5-is/fimc-is-param.h b/drivers/media/platform/exynos5-is/fimc-is-param.h
> new file mode 100644
> index 0000000..0beb43e
> --- /dev/null
> +++ b/drivers/media/platform/exynos5-is/fimc-is-param.h
> @@ -0,0 +1,1212 @@
> +/*
> + * Samsung Exynos5 SoC series FIMC-IS driver
> + *
> + * Copyright (c) 2013 Samsung Electronics Co., Ltd
> + * Kil-yeon Lim<kilyeon.im@samsung.com>
> + * Arun Kumar K<arun.kk@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef FIMC_IS_PARAM_H
> +#define FIMC_IS_PARAM_H
> +
> +#define MAGIC_NUMBER 0x01020304
> +
> +#define PARAMETER_MAX_SIZE    128  /* in byte */

s/byte/bytes ?

> +#define PARAMETER_MAX_MEMBER  (PARAMETER_MAX_SIZE/4)
> +
> +enum is_param_set_bit {
> +	PARAM_GLOBAL_SHOTMODE = 0,
> +	PARAM_SENSOR_CONTROL,
> +	PARAM_SENSOR_OTF_INPUT,
> +	PARAM_SENSOR_OTF_OUTPUT,
> +	PARAM_SENSOR_FRAME_RATE,
> +	PARAM_SENSOR_DMA_OUTPUT,
> +	PARAM_BUFFER_CONTROL,
> +	PARAM_BUFFER_OTF_INPUT,
> +	PARAM_BUFFER_OTF_OUTPUT,
> +	PARAM_ISP_CONTROL,
> +	PARAM_ISP_OTF_INPUT = 10,
> +	PARAM_ISP_DMA1_INPUT,
> +	PARAM_ISP_DMA2_INPUT,
> +	PARAM_ISP_AA,
> +	PARAM_ISP_FLASH,
> +	PARAM_ISP_AWB,
> +	PARAM_ISP_IMAGE_EFFECT,
> +	PARAM_ISP_ISO,
> +	PARAM_ISP_ADJUST,
> +	PARAM_ISP_METERING,
> +	PARAM_ISP_AFC = 20,
> +	PARAM_ISP_OTF_OUTPUT,
> +	PARAM_ISP_DMA1_OUTPUT,
> +	PARAM_ISP_DMA2_OUTPUT,
> +	PARAM_DRC_CONTROL,
> +	PARAM_DRC_OTF_INPUT,
> +	PARAM_DRC_DMA_INPUT,
> +	PARAM_DRC_OTF_OUTPUT,
> +	PARAM_SCALERC_CONTROL,
> +	PARAM_SCALERC_OTF_INPUT,
> +	PARAM_SCALERC_IMAGE_EFFECT = 30,
> +	PARAM_SCALERC_INPUT_CROP,
> +	PARAM_SCALERC_OUTPUT_CROP,
> +	PARAM_SCALERC_OTF_OUTPUT,
> +	PARAM_SCALERC_DMA_OUTPUT = 34,
> +	PARAM_ODC_CONTROL,
> +	PARAM_ODC_OTF_INPUT,
> +	PARAM_ODC_OTF_OUTPUT,
> +	PARAM_DIS_CONTROL,
> +	PARAM_DIS_OTF_INPUT,
> +	PARAM_DIS_OTF_OUTPUT = 40,
> +	PARAM_TDNR_CONTROL,
> +	PARAM_TDNR_OTF_INPUT,
> +	PARAM_TDNR_1ST_FRAME,
> +	PARAM_TDNR_OTF_OUTPUT,
> +	PARAM_TDNR_DMA_OUTPUT,
> +	PARAM_SCALERP_CONTROL,
> +	PARAM_SCALERP_OTF_INPUT,
> +	PARAM_SCALERP_IMAGE_EFFECT,
> +	PARAM_SCALERP_INPUT_CROP,
> +	PARAM_SCALERP_OUTPUT_CROP = 50,
> +	PARAM_SCALERP_ROTATION,
> +	PARAM_SCALERP_FLIP,
> +	PARAM_SCALERP_OTF_OUTPUT,
> +	PARAM_SCALERP_DMA_OUTPUT,
> +	PARAM_FD_CONTROL,
> +	PARAM_FD_OTF_INPUT,
> +	PARAM_FD_DMA_INPUT,
> +	PARAM_FD_CONFIG = 58,
> +	PARAM_END,
> +};
> +
> +/* ----------------------  Input  ----------------------------------- */
> +enum control_command {
> +	CONTROL_COMMAND_STOP	= 0,
> +	CONTROL_COMMAND_START	= 1,
> +	CONTROL_COMMAND_TEST	= 2
> +};
> +
> +enum bypass_command {
> +	CONTROL_BYPASS_DISABLE		= 0,
> +	CONTROL_BYPASS_ENABLE		= 1
> +};
> +
> +enum control_error {
> +	CONTROL_ERROR_NONE		= 0
> +};
> +
> +enum otf_input_command {
> +	OTF_INPUT_COMMAND_DISABLE	= 0,
> +	OTF_INPUT_COMMAND_ENABLE	= 1
> +};
> +
> +enum otf_input_format {
> +	OTF_INPUT_FORMAT_BAYER		= 0, /* 1 Channel */
> +	OTF_INPUT_FORMAT_YUV444		= 1, /* 3 Channel */
> +	OTF_INPUT_FORMAT_YUV422		= 2, /* 3 Channel */
> +	OTF_INPUT_FORMAT_YUV420		= 3, /* 3 Channel */
> +	OTF_INPUT_FORMAT_STRGEN_COLORBAR_BAYER = 10,
> +	OTF_INPUT_FORMAT_BAYER_DMA	= 11,
> +};
> +
> +enum otf_input_bitwidth {
> +	OTF_INPUT_BIT_WIDTH_14BIT	= 14,
> +	OTF_INPUT_BIT_WIDTH_12BIT	= 12,
> +	OTF_INPUT_BIT_WIDTH_11BIT	= 11,
> +	OTF_INPUT_BIT_WIDTH_10BIT	= 10,
> +	OTF_INPUT_BIT_WIDTH_9BIT	= 9,
> +	OTF_INPUT_BIT_WIDTH_8BIT	= 8
> +};
> +
> +enum otf_input_order {
> +	OTF_INPUT_ORDER_BAYER_GR_BG	= 0,
> +	OTF_INPUT_ORDER_BAYER_RG_GB	= 1,
> +	OTF_INPUT_ORDER_BAYER_BG_GR	= 2,
> +	OTF_INPUT_ORDER_BAYER_GB_RG	= 3
> +};
> +
> +enum otf_intput_error {
> +	OTF_INPUT_ERROR_NONE		= 0 /* Input setting is done */
> +};
> +
> +enum dma_input_command {
> +	DMA_INPUT_COMMAND_DISABLE	= 0,
> +	DMA_INPUT_COMMAND_ENABLE	= 1,
> +	DMA_INPUT_COMMAND_BUF_MNGR	= 2,
> +	DMA_INPUT_COMMAND_RUN_SINGLE	= 3,
> +};
> +
> +enum dma_inut_format {
> +	DMA_INPUT_FORMAT_BAYER		= 0,
> +	DMA_INPUT_FORMAT_YUV444		= 1,
> +	DMA_INPUT_FORMAT_YUV422		= 2,
> +	DMA_INPUT_FORMAT_YUV420		= 3,
> +};

> +enum dma_input_bitwidth {
> +	DMA_INPUT_BIT_WIDTH_14BIT	= 14,
> +	DMA_INPUT_BIT_WIDTH_12BIT	= 12,
> +	DMA_INPUT_BIT_WIDTH_11BIT	= 11,
> +	DMA_INPUT_BIT_WIDTH_10BIT	= 10,
> +	DMA_INPUT_BIT_WIDTH_9BIT	= 9,
> +	DMA_INPUT_BIT_WIDTH_8BIT	= 8
> +};
> +
> +enum dma_input_plane {
> +	DMA_INPUT_PLANE_3	= 3,
> +	DMA_INPUT_PLANE_2	= 2,
> +	DMA_INPUT_PLANE_1	= 1
> +};

Are these two enums really needed ? Couldn't plain numbers be used ?
It makes little sense to me to define natural numbers like this.

> +enum dma_input_order {
> +	/* (for DMA_INPUT_PLANE_3) */
> +	DMA_INPUT_ORDER_NONE	= 0,
> +	/* (only valid at DMA_INPUT_PLANE_2) */
> +	DMA_INPUT_ORDER_CBCR	= 1,
> +	/* (only valid at DMA_INPUT_PLANE_2) */
> +	DMA_INPUT_ORDER_CRCB	= 2,
> +	/* (only valid at DMA_INPUT_PLANE_1&  DMA_INPUT_FORMAT_YUV444) */
> +	DMA_INPUT_ORDER_YCBCR	= 3,
> +	/* (only valid at DMA_INPUT_FORMAT_YUV422&  DMA_INPUT_PLANE_1) */
> +	DMA_INPUT_ORDER_YYCBCR	= 4,
> +	/* (only valid at DMA_INPUT_FORMAT_YUV422&  DMA_INPUT_PLANE_1) */
> +	DMA_INPUT_ORDER_YCBYCR	= 5,
> +	/* (only valid at DMA_INPUT_FORMAT_YUV422&  DMA_INPUT_PLANE_1) */
> +	DMA_INPUT_ORDER_YCRYCB	= 6,
> +	/* (only valid at DMA_INPUT_FORMAT_YUV422&  DMA_INPUT_PLANE_1) */
> +	DMA_INPUT_ORDER_CBYCRY	= 7,
> +	/* (only valid at DMA_INPUT_FORMAT_YUV422&  DMA_INPUT_PLANE_1) */
> +	DMA_INPUT_ORDER_CRYCBY	= 8,
> +	/* (only valid at DMA_INPUT_FORMAT_BAYER) */
> +	DMA_INPUT_ORDER_GR_BG	= 9
> +};
> +
> +enum dma_input_error {
> +	DMA_INPUT_ERROR_NONE	= 0 /*  DMA input setting is done */
> +};
> +
> +/* ----------------------  Output  ----------------------------------- */
> +enum otf_output_crop {
> +	OTF_OUTPUT_CROP_DISABLE		= 0,
> +	OTF_OUTPUT_CROP_ENABLE		= 1
> +};
> +
> +enum otf_output_command {
> +	OTF_OUTPUT_COMMAND_DISABLE	= 0,
> +	OTF_OUTPUT_COMMAND_ENABLE	= 1
> +};
> +
> +enum orf_output_format {
> +	OTF_OUTPUT_FORMAT_YUV444	= 1,
> +	OTF_OUTPUT_FORMAT_YUV422	= 2,
> +	OTF_OUTPUT_FORMAT_YUV420	= 3,
> +	OTF_OUTPUT_FORMAT_RGB		= 4
> +};
> +
> +enum otf_output_bitwidth {
> +	OTF_OUTPUT_BIT_WIDTH_14BIT	= 14,
> +	OTF_OUTPUT_BIT_WIDTH_12BIT	= 12,
> +	OTF_OUTPUT_BIT_WIDTH_11BIT	= 11,
> +	OTF_OUTPUT_BIT_WIDTH_10BIT	= 10,
> +	OTF_OUTPUT_BIT_WIDTH_9BIT	= 9,
> +	OTF_OUTPUT_BIT_WIDTH_8BIT	= 8
> +};
> +
> +enum otf_output_order {
> +	OTF_OUTPUT_ORDER_BAYER_GR_BG	= 0,
> +};
> +
> +enum otf_output_error {
> +	OTF_OUTPUT_ERROR_NONE = 0 /* Output Setting is done */
> +};
> +
> +enum dma_output_command {
> +	DMA_OUTPUT_COMMAND_DISABLE	= 0,
> +	DMA_OUTPUT_COMMAND_ENABLE	= 1,
> +	DMA_OUTPUT_COMMAND_BUF_MNGR	= 2,
> +	DMA_OUTPUT_UPDATE_MASK_BITS	= 3
> +};
> +
> +enum dma_output_format {
> +	DMA_OUTPUT_FORMAT_BAYER		= 0,
> +	DMA_OUTPUT_FORMAT_YUV444	= 1,
> +	DMA_OUTPUT_FORMAT_YUV422	= 2,
> +	DMA_OUTPUT_FORMAT_YUV420	= 3,
> +	DMA_OUTPUT_FORMAT_RGB		= 4
> +};
> +
> +enum dma_output_bitwidth {
> +	DMA_OUTPUT_BIT_WIDTH_14BIT	= 14,
> +	DMA_OUTPUT_BIT_WIDTH_12BIT	= 12,
> +	DMA_OUTPUT_BIT_WIDTH_11BIT	= 11,
> +	DMA_OUTPUT_BIT_WIDTH_10BIT	= 10,
> +	DMA_OUTPUT_BIT_WIDTH_9BIT	= 9,
> +	DMA_OUTPUT_BIT_WIDTH_8BIT	= 8
> +};
> +
> +enum dma_output_plane {
> +	DMA_OUTPUT_PLANE_3		= 3,
> +	DMA_OUTPUT_PLANE_2		= 2,
> +	DMA_OUTPUT_PLANE_1		= 1
> +};

Ditto.

> +enum dma_output_order {
> +	DMA_OUTPUT_ORDER_NONE		= 0,
> +	/* (for DMA_OUTPUT_PLANE_3) */
> +	DMA_OUTPUT_ORDER_CBCR		= 1,
> +	/* (only valid at DMA_INPUT_PLANE_2) */
> +	DMA_OUTPUT_ORDER_CRCB		= 2,
> +	/* (only valid at DMA_OUTPUT_PLANE_2) */
> +	DMA_OUTPUT_ORDER_YYCBCR		= 3,
> +	/* (only valid at DMA_OUTPUT_FORMAT_YUV422&  DMA_OUTPUT_PLANE_1) */
> +	DMA_OUTPUT_ORDER_YCBYCR		= 4,
> +	/* (only valid at DMA_OUTPUT_FORMAT_YUV422&  DMA_OUTPUT_PLANE_1) */
> +	DMA_OUTPUT_ORDER_YCRYCB		= 5,
> +	/* (only valid at DMA_OUTPUT_FORMAT_YUV422&  DMA_OUTPUT_PLANE_1) */
> +	DMA_OUTPUT_ORDER_CBYCRY		= 6,
> +	/* (only valid at DMA_OUTPUT_FORMAT_YUV422&  DMA_OUTPUT_PLANE_1) */
> +	DMA_OUTPUT_ORDER_CRYCBY		= 7,
> +	/* (only valid at DMA_OUTPUT_FORMAT_YUV422&  DMA_OUTPUT_PLANE_1) */
> +	DMA_OUTPUT_ORDER_YCBCR		= 8,
> +	/* (only valid at DMA_OUTPUT_FORMAT_YUV444&  DMA_OUPUT_PLANE_1) */
> +	DMA_OUTPUT_ORDER_CRYCB		= 9,
> +	/* (only valid at DMA_OUTPUT_FORMAT_YUV444&  DMA_OUPUT_PLANE_1) */
> +	DMA_OUTPUT_ORDER_CRCBY		= 10,
> +	/* (only valid at DMA_OUTPUT_FORMAT_YUV444&  DMA_OUPUT_PLANE_1) */
> +	DMA_OUTPUT_ORDER_CBYCR		= 11,
> +	/* (only valid at DMA_OUTPUT_FORMAT_YUV444&  DMA_OUPUT_PLANE_1) */
> +	DMA_OUTPUT_ORDER_YCRCB		= 12,
> +	/* (only valid at DMA_OUTPUT_FORMAT_YUV444&  DMA_OUPUT_PLANE_1) */
> +	DMA_OUTPUT_ORDER_CBCRY		= 13,
> +	/* (only valid at DMA_OUTPUT_FORMAT_YUV444&  DMA_OUPUT_PLANE_1) */
> +	DMA_OUTPUT_ORDER_BGR		= 14,
> +	/* (only valid at DMA_OUTPUT_FORMAT_RGB) */
> +	DMA_OUTPUT_ORDER_GB_BG		= 15
> +	/* (only valid at DMA_OUTPUT_FORMAT_BAYER) */
> +};
> +
> +enum dma_output_notify_dma_done {
> +	DMA_OUTPUT_NOTIFY_DMA_DONE_DISABLE	= 0,
> +	DMA_OUTPUT_NOTIFY_DMA_DONE_ENBABLE	= 1,
> +};
> +
> +enum dma_output_error {
> +	DMA_OUTPUT_ERROR_NONE		= 0 /* DMA output setting is done */
> +};
> +
> +/* ----------------------  Global  ----------------------------------- */
> +enum global_shotmode_error {
> +	GLOBAL_SHOTMODE_ERROR_NONE	= 0 /* shot-mode setting is done */
> +};
> +
> +/* -------------------------  AA  ------------------------------------ */
> +enum isp_lock_command {
> +	ISP_AA_COMMAND_START	= 0,
> +	ISP_AA_COMMAND_STOP	= 1
> +};
> +
> +enum isp_lock_target {
> +	ISP_AA_TARGET_AF	= 1,
> +	ISP_AA_TARGET_AE	= 2,
> +	ISP_AA_TARGET_AWB	= 4
> +};
> +
> +enum isp_af_mode {
> +	ISP_AF_MANUAL = 0,
> +	ISP_AF_SINGLE,
> +	ISP_AF_CONTINUOUS,
> +	ISP_AF_REGION,
> +	ISP_AF_SLEEP,
> +	ISP_AF_INIT,
> +	ISP_AF_SET_CENTER_WINDOW,
> +	ISP_AF_SET_TOUCH_WINDOW,
> +	ISP_AF_SET_FACE_WINDOW
> +};
> +
> +enum isp_af_scene {
> +	ISP_AF_SCENE_NORMAL		= 0,
> +	ISP_AF_SCENE_MACRO		= 1
> +};
> +
> +enum isp_af_touch {
> +	ISP_AF_TOUCH_DISABLE = 0,
> +	ISP_AF_TOUCH_ENABLE
> +};
> +
> +enum isp_af_face {
> +	ISP_AF_FACE_DISABLE = 0,
> +	ISP_AF_FACE_ENABLE
> +};
> +
> +enum isp_af_reponse {
> +	ISP_AF_RESPONSE_PREVIEW = 0,
> +	ISP_AF_RESPONSE_MOVIE
> +};
> +
> +enum isp_af_sleep {
> +	ISP_AF_SLEEP_OFF		= 0,
> +	ISP_AF_SLEEP_ON			= 1
> +};
> +
> +enum isp_af_continuous {
> +	ISP_AF_CONTINUOUS_DISABLE	= 0,
> +	ISP_AF_CONTINUOUS_ENABLE	= 1
> +};
> +
> +enum isp_af_error {
> +	ISP_AF_ERROR_NONE		= 0, /* AF mode change is done */
> +	ISP_AF_EROOR_NO_LOCK_DONE	= 1  /* AF lock is done */
> +};
> +
> +/* -------------------------  Flash  ------------------------------------- */
> +enum isp_flash_command {
> +	ISP_FLASH_COMMAND_DISABLE	= 0,
> +	ISP_FLASH_COMMAND_MANUALON	= 1, /* (forced flash) */
> +	ISP_FLASH_COMMAND_AUTO		= 2,
> +	ISP_FLASH_COMMAND_TORCH		= 3,   /* 3 sec */
> +	ISP_FLASH_COMMAND_FLASH_ON	= 4,
> +	ISP_FLASH_COMMAND_CAPTURE	= 5,
> +	ISP_FLASH_COMMAND_TRIGGER	= 6,
> +	ISP_FLASH_COMMAND_CALIBRATION	= 7
> +};
> +
> +enum isp_flash_redeye {
> +	ISP_FLASH_REDEYE_DISABLE	= 0,
> +	ISP_FLASH_REDEYE_ENABLE		= 1
> +};
> +
> +enum isp_flash_error {
> +	ISP_FLASH_ERROR_NONE		= 0 /* Flash setting is done */
> +};
> +
> +/* --------------------------  AWB  ------------------------------------ */
> +enum isp_awb_command {
> +	ISP_AWB_COMMAND_AUTO		= 0,
> +	ISP_AWB_COMMAND_ILLUMINATION	= 1,
> +	ISP_AWB_COMMAND_MANUAL	= 2
> +};
> +
> +enum isp_awb_illumination {
> +	ISP_AWB_ILLUMINATION_DAYLIGHT		= 0,
> +	ISP_AWB_ILLUMINATION_CLOUDY		= 1,
> +	ISP_AWB_ILLUMINATION_TUNGSTEN		= 2,
> +	ISP_AWB_ILLUMINATION_FLUORESCENT	= 3
> +};
> +
> +enum isp_awb_error {
> +	ISP_AWB_ERROR_NONE		= 0 /* AWB setting is done */
> +};
> +
> +/* --------------------------  Effect  ----------------------------------- */
> +enum isp_imageeffect_command {
> +	ISP_IMAGE_EFFECT_DISABLE		= 0,
> +	ISP_IMAGE_EFFECT_MONOCHROME		= 1,
> +	ISP_IMAGE_EFFECT_NEGATIVE_MONO		= 2,
> +	ISP_IMAGE_EFFECT_NEGATIVE_COLOR		= 3,
> +	ISP_IMAGE_EFFECT_SEPIA			= 4,
> +	ISP_IMAGE_EFFECT_AQUA			= 5,
> +	ISP_IMAGE_EFFECT_EMBOSS			= 6,
> +	ISP_IMAGE_EFFECT_EMBOSS_MONO		= 7,
> +	ISP_IMAGE_EFFECT_SKETCH			= 8,
> +	ISP_IMAGE_EFFECT_RED_YELLOW_POINT	= 9,
> +	ISP_IMAGE_EFFECT_GREEN_POINT		= 10,
> +	ISP_IMAGE_EFFECT_BLUE_POINT		= 11,
> +	ISP_IMAGE_EFFECT_MAGENTA_POINT		= 12,
> +	ISP_IMAGE_EFFECT_WARM_VINTAGE		= 13,
> +	ISP_IMAGE_EFFECT_COLD_VINTAGE		= 14,
> +	ISP_IMAGE_EFFECT_POSTERIZE		= 15,
> +	ISP_IMAGE_EFFECT_SOLARIZE		= 16,
> +	ISP_IMAGE_EFFECT_WASHED			= 17,
> +	ISP_IMAGE_EFFECT_CCM			= 18,
> +};

Hmm, I guess we will need a private v4l2 control for those.

> +enum isp_imageeffect_error {
> +	ISP_IMAGE_EFFECT_ERROR_NONE	= 0 /* Image effect setting is done */
> +};
> +
> +/* ---------------------------  ISO  ------------------------------------ */
> +enum isp_iso_command {
> +	ISP_ISO_COMMAND_AUTO		= 0,
> +	ISP_ISO_COMMAND_MANUAL		= 1
> +};
> +
> +enum iso_error {
> +	ISP_ISO_ERROR_NONE		= 0 /* ISO setting is done */
> +};
> +
> +/* --------------------------  Adjust  ----------------------------------- */
> +enum iso_adjust_command {
> +	ISP_ADJUST_COMMAND_AUTO			= 0,
> +	ISP_ADJUST_COMMAND_MANUAL_CONTRAST	= (1<<  0),
> +	ISP_ADJUST_COMMAND_MANUAL_SATURATION	= (1<<  1),
> +	ISP_ADJUST_COMMAND_MANUAL_SHARPNESS	= (1<<  2),
> +	ISP_ADJUST_COMMAND_MANUAL_EXPOSURE	= (1<<  3),
> +	ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS	= (1<<  4),
> +	ISP_ADJUST_COMMAND_MANUAL_HUE		= (1<<  5),
> +	ISP_ADJUST_COMMAND_MANUAL_HOTPIXEL	= (1<<  6),
> +	ISP_ADJUST_COMMAND_MANUAL_NOISEREDUCTION = (1<<  7),
> +	ISP_ADJUST_COMMAND_MANUAL_SHADING	= (1<<  8),
> +	ISP_ADJUST_COMMAND_MANUAL_GAMMA		= (1<<  9),
> +	ISP_ADJUST_COMMAND_MANUAL_EDGEENHANCEMENT = (1<<  10),
> +	ISP_ADJUST_COMMAND_MANUAL_SCENE		= (1<<  11),
> +	ISP_ADJUST_COMMAND_MANUAL_FRAMETIME	= (1<<  12),
> +	ISP_ADJUST_COMMAND_MANUAL_ALL		= 0x1FFF
> +};
> +
> +enum isp_adjust_scene_index {
> +	ISP_ADJUST_SCENE_NORMAL			= 0,
> +	ISP_ADJUST_SCENE_NIGHT_PREVIEW		= 1,
> +	ISP_ADJUST_SCENE_NIGHT_CAPTURE		= 2
> +};
> +
> +
> +enum isp_adjust_error {
> +	ISP_ADJUST_ERROR_NONE		= 0 /* Adjust setting is done */
> +};
> +
> +/* -------------------------  Metering  ---------------------------------- */
> +enum isp_metering_command {
> +	ISP_METERING_COMMAND_AVERAGE		= 0,
> +	ISP_METERING_COMMAND_SPOT		= 1,
> +	ISP_METERING_COMMAND_MATRIX		= 2,
> +	ISP_METERING_COMMAND_CENTER		= 3,
> +	ISP_METERING_COMMAND_EXPOSURE_MODE	= (1<<  8)
> +};
> +
> +enum isp_exposure_mode {
> +	ISP_EXPOSUREMODE_OFF		= 1,
> +	ISP_EXPOSUREMODE_AUTO		= 2
> +};
> +
> +enum isp_metering_error {
> +	ISP_METERING_ERROR_NONE	= 0 /* Metering setting is done */
> +};
> +
> +/* --------------------------  AFC  ----------------------------------- */
> +enum isp_afc_command {
> +	ISP_AFC_COMMAND_DISABLE		= 0,
> +	ISP_AFC_COMMAND_AUTO		= 1,
> +	ISP_AFC_COMMAND_MANUAL		= 2
> +};
> +
> +enum isp_afc_manual {
> +	ISP_AFC_MANUAL_50HZ		= 50,
> +	ISP_AFC_MANUAL_60HZ		= 60
> +};
> +
> +enum isp_afc_error {
> +	ISP_AFC_ERROR_NONE	= 0 /* AFC setting is done */
> +};
> +
> +enum isp_scene_command {
> +	ISP_SCENE_NONE		= 0,
> +	ISP_SCENE_PORTRAIT	= 1,
> +	ISP_SCENE_LANDSCAPE     = 2,
> +	ISP_SCENE_SPORTS        = 3,
> +	ISP_SCENE_PARTYINDOOR	= 4,
> +	ISP_SCENE_BEACHSNOW	= 5,
> +	ISP_SCENE_SUNSET	= 6,
> +	ISP_SCENE_DAWN		= 7,
> +	ISP_SCENE_FALL		= 8,
> +	ISP_SCENE_NIGHT		= 9,
> +	ISP_SCENE_AGAINSTLIGHTWLIGHT	= 10,
> +	ISP_SCENE_AGAINSTLIGHTWOLIGHT	= 11,
> +	ISP_SCENE_FIRE			= 12,
> +	ISP_SCENE_TEXT			= 13,
> +	ISP_SCENE_CANDLE		= 14
> +};
> +
> +/* --------------------------  Scaler  --------------------------------- */
> +enum scaler_imageeffect_command {
> +	SCALER_IMAGE_EFFECT_COMMNAD_DISABLE	= 0,
> +	SCALER_IMAGE_EFFECT_COMMNAD_SEPIA_CB	= 1,
> +	SCALER_IMAGE_EFFECT_COMMAND_SEPIA_CR	= 2,
> +	SCALER_IMAGE_EFFECT_COMMAND_NEGATIVE	= 3,
> +	SCALER_IMAGE_EFFECT_COMMAND_ARTFREEZE	= 4,
> +	SCALER_IMAGE_EFFECT_COMMAND_EMBOSSING	= 5,
> +	SCALER_IMAGE_EFFECT_COMMAND_SILHOUETTE	= 6
> +};
> +
> +enum scaler_imageeffect_error {
> +	SCALER_IMAGE_EFFECT_ERROR_NONE		= 0
> +};
> +
> +enum scaler_crop_command {
> +	SCALER_CROP_COMMAND_DISABLE		= 0,
> +	SCALER_CROP_COMMAND_ENABLE		= 1
> +};
> +
> +enum scaler_crop_error {
> +	SCALER_CROP_ERROR_NONE			= 0 /* crop setting is done */
> +};
> +
> +enum scaler_scaling_command {
> +	SCALER_SCALING_COMMNAD_DISABLE		= 0,
> +	SCALER_SCALING_COMMAND_UP		= 1,
> +	SCALER_SCALING_COMMAND_DOWN		= 2
> +};
> +
> +enum scaler_scaling_error {
> +	SCALER_SCALING_ERROR_NONE		= 0
> +};
> +
> +enum scaler_rotation_command {
> +	SCALER_ROTATION_COMMAND_DISABLE		= 0,
> +	SCALER_ROTATION_COMMAND_CLOCKWISE90	= 1
> +};
> +
> +enum scaler_rotation_error {
> +	SCALER_ROTATION_ERROR_NONE		= 0
> +};
> +
> +enum scaler_flip_command {
> +	SCALER_FLIP_COMMAND_NORMAL		= 0,
> +	SCALER_FLIP_COMMAND_X_MIRROR		= 1,
> +	SCALER_FLIP_COMMAND_Y_MIRROR		= 2,
> +	SCALER_FLIP_COMMAND_XY_MIRROR		= 3 /* (180 rotation) */
> +};
> +
> +enum scaler_flip_error {
> +	SCALER_FLIP_ERROR_NONE			= 0 /* flip setting is done */
> +};
> +
> +/* --------------------------  3DNR  ----------------------------------- */
> +enum tdnr_1st_frame_command {
> +	TDNR_1ST_FRAME_COMMAND_NOPROCESSING	= 0,
> +	TDNR_1ST_FRAME_COMMAND_2DNR		= 1
> +};
> +
> +enum tdnr_1st_frame_error {
> +	TDNR_1ST_FRAME_ERROR_NONE		= 0
> +		/*1st frame setting is done*/

Misaligned comment, missing space around '*'.

> +};
> +
> +/* ----------------------------  FD  ------------------------------------- */
> +enum fd_config_command {
> +	FD_CONFIG_COMMAND_MAXIMUM_NUMBER	= 0x1,
> +	FD_CONFIG_COMMAND_ROLL_ANGLE		= 0x2,
> +	FD_CONFIG_COMMAND_YAW_ANGLE		= 0x4,
> +	FD_CONFIG_COMMAND_SMILE_MODE		= 0x8,
> +	FD_CONFIG_COMMAND_BLINK_MODE		= 0x10,
> +	FD_CONFIG_COMMAND_EYES_DETECT		= 0x20,
> +	FD_CONFIG_COMMAND_MOUTH_DETECT		= 0x40,
> +	FD_CONFIG_COMMAND_ORIENTATION		= 0x80,
> +	FD_CONFIG_COMMAND_ORIENTATION_VALUE	= 0x100
> +};
> +
> +enum fd_config_roll_angle {
> +	FD_CONFIG_ROLL_ANGLE_BASIC		= 0,
> +	FD_CONFIG_ROLL_ANGLE_PRECISE_BASIC	= 1,
> +	FD_CONFIG_ROLL_ANGLE_SIDES		= 2,
> +	FD_CONFIG_ROLL_ANGLE_PRECISE_SIDES	= 3,
> +	FD_CONFIG_ROLL_ANGLE_FULL		= 4,
> +	FD_CONFIG_ROLL_ANGLE_PRECISE_FULL	= 5,
> +};
> +
> +enum fd_config_yaw_angle {
> +	FD_CONFIG_YAW_ANGLE_0			= 0,
> +	FD_CONFIG_YAW_ANGLE_45			= 1,
> +	FD_CONFIG_YAW_ANGLE_90			= 2,
> +	FD_CONFIG_YAW_ANGLE_45_90		= 3,
> +};
> +
> +enum fd_config_smile_mode {
> +	FD_CONFIG_SMILE_MODE_DISABLE		= 0,
> +	FD_CONFIG_SMILE_MODE_ENABLE		= 1
> +};
> +
> +enum fd_config_blink_mode {
> +	FD_CONFIG_BLINK_MODE_DISABLE		= 0,
> +	FD_CONFIG_BLINK_MODE_ENABLE		= 1
> +};
> +
> +enum fd_config_eye_result {
> +	FD_CONFIG_EYES_DETECT_DISABLE		= 0,
> +	FD_CONFIG_EYES_DETECT_ENABLE		= 1
> +};
> +
> +enum fd_config_mouth_result {
> +	FD_CONFIG_MOUTH_DETECT_DISABLE		= 0,
> +	FD_CONFIG_MOUTH_DETECT_ENABLE		= 1
> +};
> +
> +enum fd_config_orientation {
> +	FD_CONFIG_ORIENTATION_DISABLE		= 0,
> +	FD_CONFIG_ORIENTATION_ENABLE		= 1
> +};
> +
> +struct param_control {
> +	u32	cmd;
> +	u32	bypass;
> +	u32	buffer_address;
> +	u32	buffer_number;
> +	/* 0: continuous, 1: single */
> +	u32	run_mode;
> +	u32	reserved[PARAMETER_MAX_MEMBER-6];
> +	u32	err;
> +};
> +
> +struct param_otf_input {
> +	u32	cmd;
> +	u32	width;
> +	u32	height;
> +	u32	format;
> +	u32	bitwidth;
> +	u32	order;
> +	u32	crop_offset_x;
> +	u32	crop_offset_y;
> +	u32	crop_width;
> +	u32	crop_height;
> +	u32	frametime_min;
> +	u32	frametime_max;
> +	u32	reserved[PARAMETER_MAX_MEMBER-13];
> +	u32	err;
> +};
> +
> +struct param_dma_input {
> +	u32	cmd;
> +	u32	width;
> +	u32	height;
> +	u32	format;
> +	u32	bitwidth;
> +	u32	plane;
> +	u32	order;
> +	u32	buffer_number;
> +	u32	buffer_address;
> +	u32	bayer_crop_offset_x;
> +	u32	bayer_crop_offset_y;
> +	u32	bayer_crop_width;
> +	u32	bayer_crop_height;
> +	u32	dma_crop_offset_x;
> +	u32	dma_crop_offset_y;
> +	u32	dma_crop_width;
> +	u32	dma_crop_height;
> +	u32	user_min_frametime;
> +	u32	user_max_frametime;
> +	u32	wide_frame_gap;
> +	u32	frame_gap;
> +	u32	line_gap;
> +	u32	reserved[PARAMETER_MAX_MEMBER-23];
> +	u32	err;
> +};
> +
> +struct param_otf_output {
> +	u32	cmd;
> +	u32	width;
> +	u32	height;
> +	u32	format;
> +	u32	bitwidth;
> +	u32	order;
> +	u32	crop_offset_x;
> +	u32	crop_offset_y;
> +	u32	reserved[PARAMETER_MAX_MEMBER-9];
> +	u32	err;
> +};
> +
> +struct param_dma_output {
> +	u32	cmd;
> +	u32	width;
> +	u32	height;
> +	u32	format;
> +	u32	bitwidth;
> +	u32	plane;
> +	u32	order;
> +	u32	buffer_number;
> +	u32	buffer_address;
> +	u32	notify_dma_done;
> +	u32	dma_out_mask;
> +	u32	reserved[PARAMETER_MAX_MEMBER-12];
> +	u32	err;
> +};
> +
> +struct param_global_shotmode {
> +	u32	cmd;
> +	u32	skip_frames;
> +	u32	reserved[PARAMETER_MAX_MEMBER-3];
> +	u32	err;
> +};
> +
> +struct param_sensor_framerate {
> +	u32	frame_rate;
> +	u32	reserved[PARAMETER_MAX_MEMBER-2];
> +	u32	err;
> +};
> +
> +struct param_isp_aa {
> +	u32	cmd;
> +	u32	target;
> +	u32	mode;
> +	u32	scene;
> +	u32	af_touch;
> +	u32	af_face;
> +	u32	af_response;
> +	u32	sleep;
> +	u32	touch_x;
> +	u32	touch_y;
> +	u32	manual_af_setting;
> +	/*0: Legacy, 1: Camera 2.0*/
> +	u32	cam_api2p0;
> +	/* For android.control.afRegions in Camera 2.0,
> +	Resolution based on YUV output size*/

Wrong multi-line comment style.

> +	u32	af_region_left;
> +	/* For android.control.afRegions in Camera 2.0,
> +	Resolution based on YUV output size*/

Ditto.

> +	u32	af_region_top;
> +	/* For android.control.afRegions in Camera 2.0,
> +	Resolution based on YUV output size*/

Ditto.

> +	u32	af_region_right;
> +	/* For android.control.afRegions in Camera 2.0,
> +	Resolution based on YUV output size*/

Ditto.

> +	u32	af_region_bottom;
> +	u32	reserved[PARAMETER_MAX_MEMBER-17];

Spaces missing around '-'. Please fix all occurrences like this.

> +	u32	err;
> +};
> +
> +struct param_isp_flash {
> +	u32	cmd;
> +	u32	redeye;
> +	u32	flash_intensity;
> +	u32	reserved[PARAMETER_MAX_MEMBER-4];
> +	u32	err;
> +};
> +
> +struct param_isp_awb {
> +	u32	cmd;
> +	u32	illumination;
> +	u32	reserved[PARAMETER_MAX_MEMBER-3];
> +	u32	err;
> +};
> +
> +struct param_isp_imageeffect {
> +	u32	cmd;
> +	u32	reserved[PARAMETER_MAX_MEMBER-2];
> +	u32	err;
> +};
> +
> +struct param_isp_iso {
> +	u32	cmd;
> +	u32	value;
> +	u32	reserved[PARAMETER_MAX_MEMBER-3];
> +	u32	err;
> +};
> +
> +struct param_isp_adjust {
> +	u32	cmd;
> +	s32	contrast;
> +	s32	saturation;
> +	s32	sharpness;
> +	s32	exposure;
> +	s32	brightness;
> +	s32	hue;
> +	/* 0 or 1 */
> +	u32	hotpixel_enable;
> +	/* -127 ~ 127 */
> +	s32	noise_reduction_strength;
> +	/* 0 or 1 */
> +	u32	shading_correction_enable;
> +	/* 0 or 1 */
> +	u32	user_gamma_enable;
> +	/* -127 ~ 127 */
> +	s32	edge_enhancement_strength;
> +	/* ISP_AdjustSceneIndexEnum */
> +	u32	user_scene_mode;
> +	u32	min_frametime;
> +	u32	max_frametime;
> +	u32	reserved[PARAMETER_MAX_MEMBER-16];
> +	u32	err;
> +};
> +
> +struct param_isp_metering {
> +	u32	cmd;
> +	u32	win_pos_x;
> +	u32	win_pos_y;
> +	u32	win_width;
> +	u32	win_height;
> +	u32	exposure_mode;
> +	/* 0: Legacy, 1: Camera 2.0 */
> +	u32	cam_api2p0;
> +	u32	reserved[PARAMETER_MAX_MEMBER-8];
> +	u32	err;
> +};
> +
> +struct param_isp_afc {
> +	u32	cmd;
> +	u32	manual;
> +	u32	reserved[PARAMETER_MAX_MEMBER-3];
> +	u32	err;
> +};
> +
> +struct param_scaler_imageeffect {
> +	u32	cmd;
> +	u32	reserved[PARAMETER_MAX_MEMBER-2];
> +	u32	err;

Please use either tabs or spaces consistently.

> +};
> +
> +struct param_scaler_input_crop {
> +	u32  cmd;
> +	u32  pos_x;
> +	u32  pos_y;
> +	u32  crop_width;
> +	u32  crop_height;
> +	u32  in_width;
> +	u32  in_height;
> +	u32  out_width;
> +	u32  out_height;
> +	u32  reserved[PARAMETER_MAX_MEMBER-10];
> +	u32  err;
> +};
> +
> +struct param_scaler_output_crop {
> +	u32  cmd;
> +	u32  pos_x;
> +	u32  pos_y;
> +	u32  crop_width;
> +	u32  crop_height;
> +	u32  format;
> +	u32  reserved[PARAMETER_MAX_MEMBER-7];
> +	u32  err;
> +};
> +
> +struct param_scaler_rotation {
> +	u32	cmd;
> +	u32	reserved[PARAMETER_MAX_MEMBER-2];
> +	u32	err;
> +};
> +
> +struct param_scaler_flip {
> +	u32	cmd;
> +	u32	reserved[PARAMETER_MAX_MEMBER-2];
> +	u32	err;
> +};
> +
> +struct param_3dnr_1stframe {
> +	u32	cmd;
> +	u32	reserved[PARAMETER_MAX_MEMBER-2];
> +	u32	err;
> +};
> +
> +struct param_fd_config {
> +	u32	cmd;
> +	u32	max_number;
> +	u32	roll_angle;
> +	u32	yaw_angle;
> +	s32	smile_mode;
> +	s32	blink_mode;
> +	u32	eye_detect;
> +	u32	mouth_detect;
> +	u32	orientation;
> +	u32	orientation_value;
> +	u32	reserved[PARAMETER_MAX_MEMBER-11];
> +	u32	err;
> +};
> +
> +struct global_param {
> +	struct param_global_shotmode	shotmode; /* 0 */

What this /* 0 */ comment is supposed to mean ?

> +};
> +
> +/* To be added */

What ? Where ? When ? :)

> +struct sensor_param {
> +	struct param_control		control;
> +	struct param_otf_input		otf_input;
> +	struct param_otf_output		otf_output;
> +	struct param_sensor_framerate	frame_rate;
> +	struct param_dma_output		dma_output;
> +};
> +
> +struct buffer_param {
> +	struct param_control	control;
> +	struct param_otf_input	otf_input;
> +	struct param_otf_output	otf_output;
> +};
> +
> +struct isp_param {
> +	struct param_control		control;
> +	struct param_otf_input		otf_input;
> +	struct param_dma_input		dma1_input;
> +	struct param_dma_input		dma2_input;
> +	struct param_isp_aa		aa;
> +	struct param_isp_flash		flash;
> +	struct param_isp_awb		awb;
> +	struct param_isp_imageeffect	effect;
> +	struct param_isp_iso		iso;
> +	struct param_isp_adjust		adjust;
> +	struct param_isp_metering	metering;
> +	struct param_isp_afc		afc;
> +	struct param_otf_output		otf_output;
> +	struct param_dma_output		dma1_output;
> +	struct param_dma_output		dma2_output;
> +};
> +
> +struct drc_param {
> +	struct param_control		control;
> +	struct param_otf_input		otf_input;
> +	struct param_dma_input		dma_input;
> +	struct param_otf_output		otf_output;
> +};
> +
> +struct scalerc_param {
> +	struct param_control		control;
> +	struct param_otf_input		otf_input;
> +	struct param_scaler_imageeffect	effect;
> +	struct param_scaler_input_crop	input_crop;
> +	struct param_scaler_output_crop	 output_crop;
> +	struct param_otf_output		otf_output;
> +	struct param_dma_output		dma_output;
> +};
> +
> +struct odc_param {
> +	struct param_control		control;
> +	struct param_otf_input		otf_input;
> +	struct param_otf_output		otf_output;
> +};
> +
> +struct dis_param {
> +	struct param_control		control;
> +	struct param_otf_input		otf_input;
> +	struct param_otf_output		otf_output;
> +};
> +
> +struct tdnr_param {
> +	struct param_control		control;
> +	struct param_otf_input		otf_input;
> +	struct param_3dnr_1stframe	frame;
> +	struct param_otf_output		otf_output;
> +	struct param_dma_output		dma_output;
> +};
> +
> +struct scalerp_param {
> +	struct param_control			control;
> +	struct param_otf_input			otf_input;
> +	struct param_scaler_imageeffect		effect;
> +	struct param_scaler_input_crop		input_crop;
> +	struct param_scaler_output_crop		output_crop;
> +	struct param_scaler_rotation		rotation;
> +	struct param_scaler_flip		flip;
> +	struct param_otf_output			otf_output;
> +	struct param_dma_output			dma_output;
> +};
> +
> +struct fd_param {
> +	struct param_control			control;
> +	struct param_otf_input			otf_input;
> +	struct param_dma_input			dma_input;
> +	struct param_fd_config			config;
> +};
> +
> +struct is_param_region {
> +	struct global_param	global;
> +	struct sensor_param	sensor;
> +	struct buffer_param	buf;
> +	struct isp_param	isp;
> +	struct drc_param	drc;
> +	struct scalerc_param	scalerc;
> +	struct odc_param	odc;
> +	struct dis_param	dis;
> +	struct tdnr_param	tdnr;
> +	struct scalerp_param	scalerp;
> +	struct fd_param		fd;
> +};
> +
> +#define	NUMBER_OF_GAMMA_CURVE_POINTS	32
> +
> +struct is_sensor_tune {
> +	u32 exposure;
> +	u32 analog_gain;
> +	u32 frame_rate;
> +	u32 actuator_pos;
> +};
> +
> +struct is_tune_gammacurve {
> +	u32 num_pts_x[NUMBER_OF_GAMMA_CURVE_POINTS];
> +	u32 num_pts_y_r[NUMBER_OF_GAMMA_CURVE_POINTS];
> +	u32 num_pts_y_g[NUMBER_OF_GAMMA_CURVE_POINTS];
> +	u32 num_pts_y_b[NUMBER_OF_GAMMA_CURVE_POINTS];
> +};
> +
> +struct is_isp_tune {
> +	/* Brightness level : range 0~100, default : 7 */
> +	u32 brightness_level;
> +	/* Contrast level : range -127~127, default : 0 */
> +	s32 contrast_level;
> +	/* Saturation level : range -127~127, default : 0 */
> +	s32 saturation_level;
> +	s32 gamma_level;
> +	struct is_tune_gammacurve gamma_curve[4];
> +	/* Hue : range -127~127, default : 0 */
> +	s32 hue;
> +	/* Sharpness blur : range -127~127, default : 0 */
> +	s32 sharpness_blur;
> +	/* Despeckle : range -127~127, default : 0 */
> +	s32 despeckle;
> +	/* Edge color supression : range -127~127, default : 0 */
> +	s32 edge_color_supression;
> +	/* Noise reduction : range -127~127, default : 0 */

nit: I would remove spaces before ':' above.

> +	s32 noise_reduction;
> +	/* (32*4 + 9)*4 = 548 bytes */

Is this useful for anything ? Any problem with using sizeof() ?

> +};
> +
> +struct is_tune_region {
> +	struct is_sensor_tune sensor_tune;
> +	struct is_isp_tune isp_tune;
> +};
> +
> +struct rational_t {
> +	u32 num;
> +	u32 den;
> +};
> +
> +struct srational_t {
> +	s32 num;
> +	s32 den;
> +};
> +
> +#define FLASH_FIRED_SHIFT	0
> +#define FLASH_NOT_FIRED		0
> +#define FLASH_FIRED		1
> +
> +#define FLASH_STROBE_SHIFT				1
> +#define FLASH_STROBE_NO_DETECTION			0
> +#define FLASH_STROBE_RESERVED				1
> +#define FLASH_STROBE_RETURN_LIGHT_NOT_DETECTED		2
> +#define FLASH_STROBE_RETURN_LIGHT_DETECTED		3
> +
> +#define FLASH_MODE_SHIFT			3
> +#define FLASH_MODE_UNKNOWN			0
> +#define FLASH_MODE_COMPULSORY_FLASH_FIRING	1
> +#define FLASH_MODE_COMPULSORY_FLASH_SUPPRESSION	2
> +#define FLASH_MODE_AUTO_MODE			3
> +
> +#define FLASH_FUNCTION_SHIFT		5
> +#define FLASH_FUNCTION_PRESENT		0
> +#define FLASH_FUNCTION_NONE		1
> +
> +#define FLASH_RED_EYE_SHIFT		6
> +#define FLASH_RED_EYE_DISABLED		0
> +#define FLASH_RED_EYE_SUPPORTED		1
> +
> +struct exif_attribute {
> +	struct rational_t exposure_time;
> +	struct srational_t shutter_speed;
> +	u32 iso_speed_rating;
> +	u32 flash;
> +	struct srational_t brightness;
> +};
> +
> +struct is_frame_header {
> +	u32 valid;
> +	u32 bad_mark;
> +	u32 captured;
> +	u32 frame_number;
> +	struct exif_attribute	exif;
> +};
> +
> +struct is_fd_rect {

Would it be an option to use struct v4l2_rect instead ? It has
same layout. I planned to make such change in exynos4-is is well.
We could add some comment on what left/top/width/height fields
mean exactly in struct is_face_marker.

> +	u32 offset_x;
> +	u32 offset_y;
> +	u32 width;
> +	u32 height;
> +};
> +
> +struct is_face_marker {
> +	u32	frame_number;

nit: it's probably better to use spaces instead of tabs after those
u32s in this case.

> +	struct is_fd_rect face;
> +	struct is_fd_rect left_eye;
> +	struct is_fd_rect right_eye;
> +	struct is_fd_rect mouth;
> +	u32	roll_angle;
> +	u32	yaw_angle;
> +	u32	confidence;
> +	u32	stracked;
> +	u32	tracked_faceid;
> +	u32	smile_level;
> +	u32	blink_level;
> +};

Thanks,
Sylwester

Re: [RFC v3 05/13] [media] exynos5-fimc-is: Add register definition and context header

[Sylwester Nawrocki]

On 08/02/2013 05:02 PM, Arun Kumar K wrote:
> This patch adds the register definition file for the fimc-is driver
> and also the header file containing the main context for the driver.
>
> Signed-off-by: Arun Kumar K<arun.kk@samsung.com>
> Signed-off-by: Kilyeon Im<kilyeon.im@samsung.com>
> ---
>   drivers/media/platform/exynos5-is/fimc-is-regs.h |  105 +++++++++++++++
>   drivers/media/platform/exynos5-is/fimc-is.h      |  153 ++++++++++++++++++++++
>   2 files changed, 258 insertions(+)
>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-regs.h
>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is.h
>
> diff --git a/drivers/media/platform/exynos5-is/fimc-is-regs.h b/drivers/media/platform/exynos5-is/fimc-is-regs.h
> new file mode 100644
> index 0000000..06aa466
> --- /dev/null
> +++ b/drivers/media/platform/exynos5-is/fimc-is-regs.h
> @@ -0,0 +1,105 @@
> +/*
> + * Samsung Exynos5 SoC series FIMC-IS driver
> + *
> + * Copyright (c) 2013 Samsung Electronics Co., Ltd
> + * Arun Kumar K<arun.kk@samsung.com>
> + * Kil-yeon Lim<kilyeon.im@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef FIMC_IS_REGS_H
> +#define FIMC_IS_REGS_H
> +
> +/* WDT_ISP register */
> +#define WDT			0x00170000
> +/* MCUCTL register */
> +#define MCUCTL			0x00180000
> +/* MCU Controller Register */
> +#define MCUCTLR				(MCUCTL+0x00)
> +#define MCUCTLR_AXI_ISPX_AWCACHE(x)	((x)<<  16)
> +#define MCUCTLR_AXI_ISPX_ARCACHE(x)	((x)<<  12)
> +#define MCUCTLR_MSWRST			(1<<  0)
> +/* Boot Base OFfset Address Register */
> +#define BBOAR				(MCUCTL+0x04)
> +#define BBOAR_BBOA(x)			((x)<<  0)
> +
> +/* Interrupt Generation Register 0 from Host CPU to VIC */
> +#define INTGR0				(MCUCTL+0x08)
> +#define INTGR0_INTGC(n)			(1<<  ((n) + 16))
> +#define INTGR0_INTGD(n)			(1<<  (n))
> +
> +/* Interrupt Clear Register 0 from Host CPU to VIC */
> +#define INTCR0				(MCUCTL+0x0c)
> +#define INTCR0_INTCC(n)			(1<<  ((n) + 16))
> +#define INTCR0_INTCD(n)			(1<<  (n))
> +
> +/* Interrupt Mask Register 0 from Host CPU to VIC */
> +#define INTMR0				(MCUCTL+0x10)
> +#define INTMR0_INTMC(n)			(1<<  ((n) + 16))
> +#define INTMR0_INTMD(n)			(1<<  (n))
> +
> +/* Interrupt Status Register 0 from Host CPU to VIC */
> +#define INTSR0				(MCUCTL+0x14)
> +#define INTSR0_GET_INTSD(n, x)		(((x)>>  (n))&  0x1)
> +#define INTSR0_GET_INTSC(n, x)		(((x)>>  ((n) + 16))&  0x1)
> +
> +/* Interrupt Mask Status Register 0 from Host CPU to VIC */
> +#define INTMSR0				(MCUCTL+0x18)
> +#define INTMSR0_GET_INTMSD(n, x)	(((x)>>  (n))&  0x1)
> +#define INTMSR0_GET_INTMSC(n, x)	(((x)>>  ((n) + 16))&  0x1)
> +
> +/* Interrupt Generation Register 1 from ISP CPU to Host IC */
> +#define INTGR1				(MCUCTL+0x1c)
> +#define INTGR1_INTGC(n)			(1<<  (n))
> +
> +/* Interrupt Clear Register 1 from ISP CPU to Host IC */
> +#define INTCR1				(MCUCTL+0x20)
> +#define INTCR1_INTCC(n)			(1<<  (n))
> +
> +/* Interrupt Mask Register 1 from ISP CPU to Host IC */
> +#define INTMR1				(MCUCTL+0x24)
> +#define INTMR1_INTMC(n)			(1<<  (n))
> +
> +/* Interrupt Status Register 1 from ISP CPU to Host IC */
> +#define INTSR1				(MCUCTL+0x28)
> +/* Interrupt Mask Status Register 1 from ISP CPU to Host IC */
> +#define INTMSR1				(MCUCTL+0x2c)
> +/* Interrupt Clear Register 2 from ISP BLK's interrupts to Host IC */
> +#define INTCR2				(MCUCTL+0x30)
> +#define INTCR2_INTCC(n)			(1<<  (n))
> +
> +/* Interrupt Mask Register 2 from ISP BLK's interrupts to Host IC */
> +#define INTMR2				(MCUCTL+0x34)
> +#define INTMR2_INTMCIS(n)		(1<<  (n))
> +
> +/* Interrupt Status Register 2 from ISP BLK's interrupts to Host IC */
> +#define INTSR2				(MCUCTL+0x38)
> +/* Interrupt Mask Status Register 2 from ISP BLK's interrupts to Host IC */
> +#define INTMSR2				(MCUCTL+0x3c)
> +/* General Purpose Output Control Register (0~17) */
> +#define GPOCTLR				(MCUCTL+0x40)
> +#define GPOCTLR_GPOG(n, x)		((x)<<  (n))
> +
> +/* General Purpose Pad Output Enable Register (0~17) */
> +#define GPOENCTLR			(MCUCTL+0x44)
> +#define GPOENCTLR_GPOEN0(n, x)		((x)<<  (n))
> +
> +/* General Purpose Input Control Register (0~17) */
> +#define GPICTLR				(MCUCTL+0x48)
> +
> +/* IS Shared Registers between ISP CPU and HOST CPU */
> +#define ISSR(n)			(MCUCTL + 0x80 + (n))
> +
> +/* PMU for FIMC-IS*/
> +#define PMUREG_CMU_RESET_ISP_SYS_PWR_REG	0x1584
> +#define PMUREG_ISP_ARM_CONFIGURATION		0x2280
> +#define PMUREG_ISP_ARM_STATUS			0x2284
> +#define PMUREG_ISP_ARM_OPTION			0x2288
> +#define PMUREG_ISP_LOW_POWER_OFF		0x0004
> +#define PMUREG_ISP_CONFIGURATION		0x4020
> +#define PMUREG_ISP_STATUS			0x4024
> +
> +#endif
> diff --git a/drivers/media/platform/exynos5-is/fimc-is.h b/drivers/media/platform/exynos5-is/fimc-is.h
> new file mode 100644
> index 0000000..a7379dc
> --- /dev/null
> +++ b/drivers/media/platform/exynos5-is/fimc-is.h
> @@ -0,0 +1,153 @@
> +/*
> + * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
> + *
> + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
> + *  Arun Kumar K<arun.kk@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef FIMC_IS_H_
> +#define FIMC_IS_H_
> +
> +#include "fimc-is-err.h"
> +#include "fimc-is-core.h"
> +#include "fimc-is-param.h"
> +#include "fimc-is-pipeline.h"
> +#include "fimc-is-interface.h"
> +
> +#define fimc_interface_to_is(p) container_of(p, struct fimc_is, interface)
> +#define fimc_sensor_to_is(p) container_of(p, struct fimc_is, sensor)
> +
> +/* Macros used by media dev to get the subdev and vfd */
> +/* is -->  driver data from pdev
> + * pid -->  pipeline index */

Wrong multi-line comment style. And perhaps s/--> /- ?

> +#define fimc_is_isp_get_sd(is, pid) (&is->pipeline[pid].isp.subdev)
> +#define fimc_is_isp_get_vfd(is, pid) (&is->pipeline[pid].isp.vfd)
> +#define fimc_is_scc_get_sd(is, pid) \
> +	(&is->pipeline[pid].scaler[SCALER_SCC].subdev)
> +#define fimc_is_scc_get_vfd(is, pid) \
> +	(&is->pipeline[pid].scaler[SCALER_SCC].vfd)
> +#define fimc_is_scp_get_sd(is, pid) \
> +	(&is->pipeline[pid].scaler[SCALER_SCP].subdev)
> +#define fimc_is_scp_get_vfd(is, pid) \
> +	(&is->pipeline[pid].scaler[SCALER_SCP].vfd)
> +/* is -->  driver data from pdev
> + * sid -->  sensor index */
> +#define fimc_is_sensor_get_sd(is, sid) (&is->sensor[sid].subdev)
> +
> +
> +/**
> + * struct fimc_is - fimc lite structure

s/fimc lite/fimc-is driver private data ?

> + * @pdev: pointer to FIMC-IS platform device
> + * @pdata: platform data for FIMC-IS
> + * @alloc_ctx: videobuf2 memory allocator context
> + * @clk: FIMC-IS clocks

Actually it's 'clock'.

> + * @pmu_regs: PMU reg base address
> + * @minfo: internal memory organization info
> + * @sensor: FIMC-IS sensor context
> + * @pipeline: hardware pipeline context
> + * @interface: hardware interface context
> + */
> +struct fimc_is {
> +	struct platform_device		*pdev;
> +
> +	struct vb2_alloc_ctx		*alloc_ctx;
> +	struct clk			*clock[IS_CLK_MAX_NUM];
> +	void __iomem			*pmu_regs;
> +
> +	struct fimc_is_meminfo		minfo;
> +
> +	int				num_instance;

It's undocumented, what it is really used for ?

> +	struct fimc_is_sensor		sensor[FIMC_IS_NUM_SENSORS];
> +	struct fimc_is_pipeline		pipeline[FIMC_IS_NUM_PIPELINES];
> +	struct fimc_is_interface	interface;
> +};
> +
> +/* Queue operations for ISP */
> +static inline void fimc_is_isp_wait_queue_add(struct fimc_is_isp *isp,
> +		struct fimc_is_buf *buf)
> +{
> +	list_add_tail(&buf->list,&isp->wait_queue);
> +	isp->wait_queue_cnt++;
> +}
> +
> +static inline struct fimc_is_buf *fimc_is_isp_wait_queue_get(
> +		struct fimc_is_isp *isp)
> +{
> +	struct fimc_is_buf *buf;
> +	buf = list_entry(isp->wait_queue.next,
> +			struct fimc_is_buf, list);
> +	list_del(&buf->list);
> +	isp->wait_queue_cnt--;
> +	return buf;
> +}
> +
> +static inline void fimc_is_isp_run_queue_add(struct fimc_is_isp *isp,
> +		struct fimc_is_buf *buf)
> +{
> +	list_add_tail(&buf->list,&isp->run_queue);
> +	isp->run_queue_cnt++;
> +}
> +
> +static inline struct fimc_is_buf *fimc_is_isp_run_queue_get(
> +		struct fimc_is_isp *isp)
> +{
> +	struct fimc_is_buf *buf;
> +	buf = list_entry(isp->run_queue.next,
> +			struct fimc_is_buf, list);
> +	list_del(&buf->list);
> +	isp->run_queue_cnt--;
> +	return buf;
> +}
> +
> +/* Queue operations for SCALER */

It would be much neater to define some generic data structure and have
single queue operations for both ISP and SCALER. Maybe it would help
rewriting those as macros ? But this is something that could be well
done in a follow up patch(es).

> +static inline void fimc_is_scaler_wait_queue_add(struct fimc_is_scaler *scp,
> +		struct fimc_is_buf *buf)
> +{
> +	list_add_tail(&buf->list,&scp->wait_queue);
> +	scp->wait_queue_cnt++;
> +}
> +
> +static inline struct fimc_is_buf *fimc_is_scaler_wait_queue_get(
> +		struct fimc_is_scaler *scp)
> +{
> +	struct fimc_is_buf *buf;
> +	buf = list_entry(scp->wait_queue.next,
> +			struct fimc_is_buf, list);
> +	list_del(&buf->list);
> +	scp->wait_queue_cnt--;
> +	return buf;
> +}
> +
> +static inline void fimc_is_scaler_run_queue_add(struct fimc_is_scaler *scp,
> +		struct fimc_is_buf *buf)
> +{
> +	list_add_tail(&buf->list,&scp->run_queue);
> +	scp->run_queue_cnt++;
> +}
> +
> +static inline struct fimc_is_buf *fimc_is_scaler_run_queue_get(
> +		struct fimc_is_scaler *scp)
> +{
> +	struct fimc_is_buf *buf;
> +	buf = list_entry(scp->run_queue.next,
> +			struct fimc_is_buf, list);
> +	list_del(&buf->list);
> +	scp->run_queue_cnt--;
> +	return buf;
> +}
> +
> +static inline void pmu_is_write(u32 v, struct fimc_is *is, unsigned int offset)
> +{
> +	writel(v, is->pmu_regs + offset);
> +}
> +
> +static inline u32 pmu_is_read(struct fimc_is *is, unsigned int offset)
> +{
> +	return readl(is->pmu_regs + offset);
> +}
> +
> +#endif

--
Thanks,
Sylwester

Re: [RFC v3 07/13] [media] exynos5-fimc-is: Add scaler subdev

[Sylwester Nawrocki]

On 08/02/2013 05:02 PM, Arun Kumar K wrote:
> FIMC-IS has two hardware scalers named as scaler-codec and
> scaler-preview. This patch adds the common code handling the
> video nodes and subdevs of both the scalers.
>
> Signed-off-by: Arun Kumar K<arun.kk@samsung.com>
> Signed-off-by: Kilyeon Im<kilyeon.im@samsung.com>
> ---
>   drivers/media/platform/exynos5-is/fimc-is-scaler.c |  458 ++++++++++++++++++++
>   drivers/media/platform/exynos5-is/fimc-is-scaler.h |  112 +++++
>   2 files changed, 570 insertions(+)
>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-scaler.c
>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-scaler.h
>
> diff --git a/drivers/media/platform/exynos5-is/fimc-is-scaler.c b/drivers/media/platform/exynos5-is/fimc-is-scaler.c
> new file mode 100644
> index 0000000..7cff186
> --- /dev/null
> +++ b/drivers/media/platform/exynos5-is/fimc-is-scaler.c
> @@ -0,0 +1,458 @@
> +/*
> + * Samsung EXYNOS5250 FIMC-IS (Imaging Subsystem) driver
> + *
> + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
> + *  Arun Kumar K<arun.kk@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include<media/v4l2-ioctl.h>
> +#include<media/videobuf2-dma-contig.h>
> +
> +#include "fimc-is.h"
> +
> +#define IS_SCALER_DRV_NAME "fimc-is-scaler"
> +
> +static const struct fimc_is_fmt formats[] = {
> +	{
> +		.name           = "YUV 4:2:0 3p MultiPlanar",
> +		.fourcc         = V4L2_PIX_FMT_YUV420M,
> +		.depth		= {8, 2, 2},
> +		.num_planes     = 3,
> +	},
> +	{
> +		.name           = "YUV 4:2:0 2p MultiPlanar",
> +		.fourcc         = V4L2_PIX_FMT_NV12M,
> +		.depth		= {8, 4},
> +		.num_planes     = 2,
> +	},
> +	{
> +		.name           = "YUV 4:2:2 1p MultiPlanar",
> +		.fourcc         = V4L2_PIX_FMT_NV16,
> +		.depth		= {16},
> +		.num_planes     = 1,
> +	},
> +};
> +#define NUM_FORMATS ARRAY_SIZE(formats)
> +
> +static const struct fimc_is_fmt *find_format(struct v4l2_format *f)
> +{
> +	unsigned int i;
> +
> +	for (i = 0; i<  NUM_FORMATS; i++) {
> +		if (formats[i].fourcc == f->fmt.pix_mp.pixelformat)
> +			return&formats[i];
> +	}
> +	return NULL;
> +}
> +
> +static int scaler_video_capture_start_streaming(struct vb2_queue *vq,
> +					unsigned int count)
> +{
> +	struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
> +	int ret;
> +
> +	/* Scaler start */
> +	ret = fimc_is_pipeline_scaler_start(ctx->pipeline,
> +			ctx->scaler_id,
> +			(unsigned int **)ctx->buf_paddr,
> +			vq->num_buffers,
> +			ctx->fmt->num_planes);
> +	if (ret) {
> +		pr_err("Scaler start failed.\n");

Please avoid pr_*() and use v4l2_err() or dev_err() where possible.

> +		return -EINVAL;
> +	}
> +
> +	set_bit(STATE_RUNNING,&ctx->capture_state);
> +	return 0;
> +}
> +
> +static int scaler_video_capture_stop_streaming(struct vb2_queue *vq)
> +{
> +	struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
> +	int ret;
> +
> +	/* Scaler stop */

Isn't the function name below obvious enough to not require this comment ?

> +	ret = fimc_is_pipeline_scaler_stop(ctx->pipeline, ctx->scaler_id);
> +	if (ret)
> +		pr_debug("Scaler already stopped.\n");
> +
> +	clear_bit(STATE_RUNNING,&ctx->capture_state);
> +	return 0;
> +}
> +
> +static int scaler_video_capture_queue_setup(struct vb2_queue *vq,
> +			const struct v4l2_format *pfmt,
> +			unsigned int *num_buffers, unsigned int *num_planes,
> +			unsigned int sizes[], void *allocators[])
> +{
> +	struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
> +	const struct fimc_is_fmt *fmt = ctx->fmt;
> +	unsigned int wh;
> +	int i;
> +
> +	if (!fmt)
> +		return -EINVAL;
> +
> +	*num_planes = fmt->num_planes;
> +	wh = ctx->width * ctx->height;
> +
> +	for (i = 0; i<  *num_planes; i++) {
> +		allocators[i] = ctx->alloc_ctx;
> +		sizes[i] = (wh * fmt->depth[i]) / 8;
> +	}
> +	return 0;
> +}
> +
> +static int scaler_video_capture_buffer_init(struct vb2_buffer *vb)
> +{
> +	struct vb2_queue *vq = vb->vb2_queue;
> +	struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
> +	struct fimc_is_buf *buf;
> +	const struct fimc_is_fmt *fmt;
> +	int i;
> +
> +	buf =&ctx->capture_bufs[vb->v4l2_buf.index];

I don't like such usage of vb->v4l2_buf.index. It would be nice to get
rid of this pattern and leave v4l2_buf.index out for videobuf2 and
user space. Or can't it really be avoided ?

> +	/* Initialize buffer */
> +	buf->vb = vb;
> +	fmt = ctx->fmt;
> +	for (i = 0; i<  fmt->num_planes; i++)
> +		buf->paddr[i] = vb2_dma_contig_plane_dma_addr(vb, i);
> +
> +	ctx->cap_buf_cnt++;
> +	return 0;
> +}
> +
> +static void scaler_video_capture_buffer_queue(struct vb2_buffer *vb)
> +{
> +	struct vb2_queue *vq = vb->vb2_queue;
> +	struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
> +	struct fimc_is_buf *buf;
> +
> +	buf =&ctx->capture_bufs[vb->v4l2_buf.index];
> +
> +	/* Add buffer to the wait queue */
> +	pr_debug("Add buffer %d in Scaler %d\n",
> +			vb->v4l2_buf.index, ctx->scaler_id);
> +	fimc_is_pipeline_buf_lock(ctx->pipeline);
> +	fimc_is_scaler_wait_queue_add(ctx, buf);
> +	fimc_is_pipeline_buf_unlock(ctx->pipeline);
> +}
> +
> +static void scaler_lock(struct vb2_queue *vq)
> +{
> +	struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
> +	mutex_lock(&ctx->video_lock);
> +}
> +
> +static void scaler_unlock(struct vb2_queue *vq)
> +{
> +	struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
> +	mutex_unlock(&ctx->video_lock);
> +}
> +
> +static const struct vb2_ops scaler_video_capture_qops = {
> +	.queue_setup		= scaler_video_capture_queue_setup,
> +	.buf_init		= scaler_video_capture_buffer_init,
> +	.buf_queue		= scaler_video_capture_buffer_queue,
> +	.wait_prepare		= scaler_unlock,
> +	.wait_finish		= scaler_lock,

Can't you use vb2_ops_wait_prepare/vb2_ops_wait_finish as in case of
the isp subdev ?

> +	.start_streaming	= scaler_video_capture_start_streaming,
> +	.stop_streaming		= scaler_video_capture_stop_streaming,
> +};
> +
> +static const struct v4l2_file_operations scaler_video_capture_fops = {
> +	.owner		= THIS_MODULE,
> +	.open		= v4l2_fh_open,
> +	.release	= vb2_fop_release,
> +	.poll		= vb2_fop_poll,
> +	.unlocked_ioctl	= video_ioctl2,
> +	.mmap		= vb2_fop_mmap,
> +};
> +
> +/*
> + * Video node ioctl operations
> + */
> +static int scaler_querycap_capture(struct file *file, void *priv,
> +					struct v4l2_capability *cap)
> +{
> +	strncpy(cap->driver, IS_SCALER_DRV_NAME, sizeof(cap->driver) - 1);
> +	strncpy(cap->card, IS_SCALER_DRV_NAME, sizeof(cap->card) - 1);
> +	snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
> +			IS_SCALER_DRV_NAME);
> +	cap->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_CAPTURE_MPLANE;
> +	cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
> +	return 0;
> +}
> +
> +static int scaler_enum_fmt_mplane(struct file *file, void *priv,
> +				     struct v4l2_fmtdesc *f)
> +{
> +	const struct fimc_is_fmt *fmt;
> +
> +	if (f->index>= NUM_FORMATS)
> +		return -EINVAL;
> +
> +	fmt =&formats[f->index];
> +	strlcpy(f->description, fmt->name, sizeof(f->description));
> +	f->pixelformat = fmt->fourcc;
> +	return 0;
> +}
> +
> +static int scaler_g_fmt_mplane(struct file *file, void *priv,
> +				  struct v4l2_format *f)
> +{
> +	struct fimc_is_scaler *ctx = video_drvdata(file);
> +	struct v4l2_pix_format_mplane *pixm =&f->fmt.pix_mp;
> +	const struct fimc_is_fmt *fmt = ctx->fmt;
> +	int i;
> +
> +	for (i = 0; i<  fmt->num_planes; i++) {
> +		struct v4l2_plane_pix_format *plane_fmt =&pixm->plane_fmt[i];
> +		plane_fmt->bytesperline = (ctx->width * fmt->depth[i]) / 8;
> +		plane_fmt->sizeimage = plane_fmt->bytesperline * ctx->height;
> +		memset(plane_fmt->reserved, 0, sizeof(plane_fmt->reserved));
> +	}
> +
> +	pixm->num_planes = fmt->num_planes;
> +	pixm->pixelformat = fmt->fourcc;
> +	pixm->width = ctx->width;
> +	pixm->height = ctx->height;
> +	pixm->field = V4L2_FIELD_NONE;
> +	pixm->colorspace = V4L2_COLORSPACE_JPEG;
> +	memset(pixm->reserved, 0, sizeof(pixm->reserved));
> +
> +	return 0;
> +}
> +
> +static int scaler_try_fmt_mplane(struct file *file, void *priv,
> +				  struct v4l2_format *f)
> +{
> +	const struct fimc_is_fmt *fmt;
> +	struct v4l2_pix_format_mplane *pixm =&f->fmt.pix_mp;
> +	u32 i;
> +
> +	fmt = find_format(f);
> +	if (!fmt)
> +		fmt =&formats[0];
> +
> +	v4l_bound_align_image(&pixm->width, SCALER_MIN_WIDTH,
> +			SCALER_MAX_WIDTH, 0,
> +			&pixm->height, SCALER_MIN_HEIGHT,
> +			SCALER_MAX_HEIGHT, 0, 0);
> +
> +	for (i = 0; i<  fmt->num_planes; i++) {
> +		struct v4l2_plane_pix_format *plane_fmt =&pixm->plane_fmt[i];
> +
> +		plane_fmt->bytesperline = (pixm->width * fmt->depth[i]) / 8;
> +		plane_fmt->sizeimage = (pixm->width * pixm->height *
> +					fmt->depth[i]) / 8;
> +		memset(plane_fmt->reserved, 0, sizeof(plane_fmt->reserved));
> +	}
> +	pixm->num_planes = fmt->num_planes;
> +	pixm->pixelformat = fmt->fourcc;
> +	pixm->colorspace = V4L2_COLORSPACE_JPEG;
> +	pixm->field = V4L2_FIELD_NONE;
> +	memset(pixm->reserved, 0, sizeof(pixm->reserved));
> +
> +	return 0;
> +}
> +
> +static int scaler_s_fmt_mplane(struct file *file, void *priv,
> +				struct v4l2_format *f)
> +{
> +	struct fimc_is_scaler *ctx = video_drvdata(file);

nit: You could add:

	struct v4l2_pix_format_mplane *pixm =&f->fmt.pix_mp;

> +	const struct fimc_is_fmt *fmt;
> +	int ret;
> +
> +	ret = scaler_try_fmt_mplane(file, priv, f);
> +	if (ret)
> +		return ret;
> +
> +	/* Get format type */
> +	fmt = find_format(f);
> +	if (!fmt) {
> +		fmt =&formats[0];
> +		f->fmt.pix_mp.pixelformat = fmt->fourcc;
> +		f->fmt.pix_mp.num_planes = fmt->num_planes;

And then use it here and below.

> +	}
> +
> +	/* Save values to context */
> +	ctx->fmt = fmt;
> +	ctx->width = f->fmt.pix_mp.width;
> +	ctx->height = f->fmt.pix_mp.height;
> +	ctx->pipeline->scaler_width[ctx->scaler_id] = ctx->width;
> +	ctx->pipeline->scaler_height[ctx->scaler_id] = ctx->height;
> +	set_bit(STATE_INIT,&ctx->capture_state);
> +	return 0;
> +}
> +
> +static int scaler_reqbufs(struct file *file, void *priv,
> +		struct v4l2_requestbuffers *reqbufs)
> +{
> +	struct fimc_is_scaler *ctx = video_drvdata(file);
> +	int ret;
> +
> +	reqbufs->count = max_t(u32, FIMC_IS_SCALER_REQ_BUFS_MIN,
> +			reqbufs->count);
> +	ret = vb2_reqbufs(&ctx->vbq, reqbufs);
> +	if (ret) {
> +		pr_err("vb2 req buffers failed\n");
> +		return ret;
> +	}
> +
> +	ctx->cap_buf_cnt = 0;
> +	set_bit(STATE_BUFS_ALLOCATED,&ctx->capture_state);
> +	return 0;
> +}
> +
> +static const struct v4l2_ioctl_ops scaler_video_capture_ioctl_ops = {
> +	.vidioc_querycap		= scaler_querycap_capture,
> +	.vidioc_enum_fmt_vid_cap_mplane	= scaler_enum_fmt_mplane,
> +	.vidioc_try_fmt_vid_cap_mplane	= scaler_try_fmt_mplane,
> +	.vidioc_s_fmt_vid_cap_mplane	= scaler_s_fmt_mplane,
> +	.vidioc_g_fmt_vid_cap_mplane	= scaler_g_fmt_mplane,
> +	.vidioc_reqbufs			= scaler_reqbufs,
> +	.vidioc_querybuf		= vb2_ioctl_querybuf,
> +	.vidioc_qbuf			= vb2_ioctl_qbuf,
> +	.vidioc_dqbuf			= vb2_ioctl_dqbuf,
> +	.vidioc_expbuf			= vb2_ioctl_expbuf,
> +	.vidioc_streamon		= vb2_ioctl_streamon,
> +	.vidioc_streamoff		= vb2_ioctl_streamoff,
> +};
> +
> +static int scaler_subdev_registered(struct v4l2_subdev *sd)
> +{
> +	struct fimc_is_scaler *ctx = v4l2_get_subdevdata(sd);
> +	struct vb2_queue *q =&ctx->vbq;
> +	struct video_device *vfd =&ctx->vfd;
> +	int ret;
> +
> +	mutex_init(&ctx->video_lock);
> +
> +	memset(vfd, 0, sizeof(*vfd));
> +	if (ctx->scaler_id == SCALER_SCC)
> +		snprintf(vfd->name, sizeof(vfd->name), "fimc-is-scaler.codec");
> +	else
> +		snprintf(vfd->name, sizeof(vfd->name),
> +				"fimc-is-scaler.preview");
> +
> +	vfd->fops =&scaler_video_capture_fops;
> +	vfd->ioctl_ops =&scaler_video_capture_ioctl_ops;
> +	vfd->v4l2_dev = sd->v4l2_dev;
> +	vfd->release = video_device_release_empty;
> +	vfd->lock =&ctx->video_lock;
> +	vfd->queue = q;
> +	vfd->vfl_dir = VFL_DIR_RX;
> +	set_bit(V4L2_FL_USE_FH_PRIO,&vfd->flags);
> +
> +	memset(q, 0, sizeof(*q));
> +	q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
> +	q->io_modes = VB2_MMAP | VB2_DMABUF;
> +	q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
> +	q->ops =&scaler_video_capture_qops;
> +	q->mem_ops =&vb2_dma_contig_memops;
> +	q->drv_priv = ctx;
> +
> +	ret = vb2_queue_init(q);
> +	if (ret<  0)
> +		return ret;
> +
> +	ctx->vd_pad.flags = MEDIA_PAD_FL_SINK;
> +	ret = media_entity_init(&vfd->entity, 1,&ctx->vd_pad, 0);
> +	if (ret<  0)
> +		return ret;
> +
> +	video_set_drvdata(vfd, ctx);
> +
> +	ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
> +	if (ret<  0) {
> +		media_entity_cleanup(&vfd->entity);
> +		return ret;
> +	}
> +
> +	v4l2_info(sd->v4l2_dev, "Registered %s as /dev/%s\n",
> +		  vfd->name, video_device_node_name(vfd));
> +	return 0;
> +}
> +
> +static void scaler_subdev_unregistered(struct v4l2_subdev *sd)
> +{
> +	struct fimc_is_scaler *ctx = v4l2_get_subdevdata(sd);
> +
> +	if (ctx&&  video_is_registered(&ctx->vfd))
> +		video_unregister_device(&ctx->vfd);
> +}
> +
> +static const struct v4l2_subdev_internal_ops scaler_subdev_internal_ops = {
> +	.registered = scaler_subdev_registered,
> +	.unregistered = scaler_subdev_unregistered,
> +};
> +
> +static struct v4l2_subdev_ops scaler_subdev_ops;
> +
> +int fimc_is_scaler_subdev_create(struct fimc_is_scaler *ctx,
> +		enum fimc_is_scaler_id scaler_id,
> +		struct vb2_alloc_ctx *alloc_ctx,
> +		struct fimc_is_pipeline *pipeline)
> +{
> +	struct v4l2_ctrl_handler *handler =&ctx->ctrl_handler;
> +	struct v4l2_subdev *sd =&ctx->subdev;
> +	int ret;
> +
> +	/* Set context data */
> +	ctx->scaler_id = scaler_id;
> +	ctx->alloc_ctx = alloc_ctx;
> +	ctx->pipeline = pipeline;
> +	ctx->fmt =&formats[0];
> +	ctx->width = SCALER_DEF_WIDTH;
> +	ctx->height = SCALER_DEF_HEIGHT;
> +	init_waitqueue_head(&ctx->event_q);
> +	INIT_LIST_HEAD(&ctx->wait_queue);
> +	INIT_LIST_HEAD(&ctx->run_queue);
> +
> +	/* Initialize scaler subdev */
> +	v4l2_subdev_init(sd,&scaler_subdev_ops);
> +	sd->owner = THIS_MODULE;
> +	sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE;

This should be:

	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;

Please check if the flags are not being overwritten for the other subdevs.

> +	if (scaler_id == SCALER_SCC)
> +		snprintf(sd->name, sizeof(sd->name), "fimc-is-scc");
> +	else
> +		snprintf(sd->name, sizeof(sd->name), "fimc-is-scp");
> +
> +	ctx->subdev_pads[SCALER_SD_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
> +	ctx->subdev_pads[SCALER_SD_PAD_SRC_FIFO].flags = MEDIA_PAD_FL_SOURCE;
> +	ctx->subdev_pads[SCALER_SD_PAD_SRC_DMA].flags = MEDIA_PAD_FL_SOURCE;
> +	ret = media_entity_init(&sd->entity, ISP_SD_PADS_NUM,
> +			ctx->subdev_pads, 0);
> +	if (ret<  0)
> +		return ret;
> +
> +	ret = v4l2_ctrl_handler_init(handler, 1);
> +	if (handler->error)
> +		goto err_ctrl;
> +
> +	sd->ctrl_handler = handler;
> +	sd->internal_ops =&scaler_subdev_internal_ops;
> +	v4l2_set_subdevdata(sd, ctx);
> +
> +	return 0;
> +err_ctrl:
> +	media_entity_cleanup(&sd->entity);
> +	v4l2_ctrl_handler_free(handler);
> +	return ret;
> +}
> +
> +void fimc_is_scaler_subdev_destroy(struct fimc_is_scaler *ctx)
> +{
> +	struct v4l2_subdev *sd =&ctx->subdev;
> +
> +	v4l2_device_unregister_subdev(sd);
> +	media_entity_cleanup(&sd->entity);
> +	v4l2_ctrl_handler_free(&ctx->ctrl_handler);
> +	v4l2_set_subdevdata(sd, NULL);
> +}
> +
> diff --git a/drivers/media/platform/exynos5-is/fimc-is-scaler.h b/drivers/media/platform/exynos5-is/fimc-is-scaler.h
> new file mode 100644
> index 0000000..6d3d831
> --- /dev/null
> +++ b/drivers/media/platform/exynos5-is/fimc-is-scaler.h
> @@ -0,0 +1,112 @@
> +/*
> + * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
> + *
> + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
> + *  Arun Kumar K<arun.kk@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +#ifndef FIMC_IS_SCALER_H_
> +#define FIMC_IS_SCALER_H_
> +
> +#include<linux/sizes.h>
> +#include<linux/io.h>
> +#include<linux/irqreturn.h>
> +#include<linux/platform_device.h>
> +#include<linux/sched.h>
> +#include<linux/spinlock.h>
> +#include<linux/types.h>
> +#include<linux/videodev2.h>
> +
> +#include<media/media-entity.h>
> +#include<media/videobuf2-core.h>
> +#include<media/v4l2-device.h>
> +#include<media/v4l2-mediabus.h>
> +#include<media/s5p_fimc.h>
> +
> +#include "fimc-is-core.h"
> +
> +#define SCALER_SD_PAD_SINK	0
> +#define SCALER_SD_PAD_SRC_FIFO	1
> +#define SCALER_SD_PAD_SRC_DMA	2
> +#define SCALER_SD_PADS_NUM	3
> +
> +#define SCALER_MAX_BUFS		32
> +#define SCALER_MAX_PLANES	3
> +
> +#define FIMC_IS_SCALER_REQ_BUFS_MIN	2
> +
> +#define SCALER_DEF_WIDTH	1280
> +#define SCALER_DEF_HEIGHT	720
> +#define SCALER_MAX_WIDTH	4808
> +#define SCALER_MAX_HEIGHT	3356
> +#define SCALER_MIN_WIDTH	32
> +#define SCALER_MIN_HEIGHT	32
> +
> +/**
> + * struct fimc_is_scaler - fimc-is scaler structure
> + * @vfd: video device node
> + * @fh: v4l2 file handle
> + * @alloc_ctx: videobuf2 memory allocator context
> + * @subdev: fimc-is-scaler subdev
> + * @vd_pad: media pad for the output video node
> + * @subdev_pads: the subdev media pads
> + * @ctrl_handler: v4l2 control handler
> + * @video_lock: video lock mutex
> + * @event_q: notifies scaler events
> + * @pipeline: pipeline instance for this scaler context
> + * @scaler_id: distinguishes scaler preview or scaler codec
> + * @vbq: vb2 buffers queue for ISP output video node
> + * @wait_queue: list holding buffers waiting to be queued to HW
> + * @wait_queue_cnt: wait queue number of buffers
> + * @run_queue: list holding buffers queued to HW
> + * @run_queue_cnt: run queue number of buffers
> + * @capture_bufs: scaler capture buffers array
> + * @cap_buf_cnt: number of capture buffers in use
> + * @fmt: capture plane format for scaler
> + * @width: user configured output width
> + * @height: user configured output height
> + * @capture_state: state of the capture video node operations
> + * @buf_paddr: holds the physical address of capture buffers
> + */
> +struct fimc_is_scaler {
> +	struct video_device		vfd;
> +	struct v4l2_fh			fh;
> +	struct vb2_alloc_ctx		*alloc_ctx;
> +	struct v4l2_subdev		subdev;
> +	struct media_pad		vd_pad;
> +	struct media_pad		subdev_pads[SCALER_SD_PADS_NUM];
> +	struct v4l2_mbus_framefmt	subdev_fmt;
> +	struct v4l2_ctrl_handler	ctrl_handler;
> +
> +	struct mutex		video_lock;
> +	wait_queue_head_t	event_q;
> +
> +	struct fimc_is_pipeline	*pipeline;
> +	enum fimc_is_scaler_id	scaler_id;
> +
> +	struct vb2_queue	vbq;
> +	struct list_head	wait_queue;
> +	unsigned int		wait_queue_cnt;
> +	struct list_head	run_queue;
> +	unsigned int		run_queue_cnt;
> +
> +	struct fimc_is_buf	capture_bufs[SCALER_MAX_BUFS];
> +	unsigned int		cap_buf_cnt;
> +
> +	const struct fimc_is_fmt *fmt;
> +	unsigned int		width;
> +	unsigned int		height;
> +	unsigned long		capture_state;
> +	unsigned int		buf_paddr[SCALER_MAX_BUFS][SCALER_MAX_PLANES];
> +};
> +
> +int fimc_is_scaler_subdev_create(struct fimc_is_scaler *ctx,
> +		enum fimc_is_scaler_id scaler_id,
> +		struct vb2_alloc_ctx *alloc_ctx,
> +		struct fimc_is_pipeline *pipeline);
> +void fimc_is_scaler_subdev_destroy(struct fimc_is_scaler *scaler);
> +
> +#endif /* FIMC_IS_SCALER_H_ */

Re: [RFC v3 06/13] [media] exynos5-fimc-is: Add isp subdev

[Sylwester Nawrocki]

On 08/02/2013 05:02 PM, Arun Kumar K wrote:
> fimc-is driver takes video data input from the ISP video node
> which is added in this patch. This node accepts Bayer input
> buffers which is given from the IS sensors.
>
> Signed-off-by: Arun Kumar K<arun.kk@samsung.com>
> Signed-off-by: Kilyeon Im<kilyeon.im@samsung.com>
> ---
>   drivers/media/platform/exynos5-is/fimc-is-isp.c |  509 +++++++++++++++++++++++
>   drivers/media/platform/exynos5-is/fimc-is-isp.h |   93 +++++
>   2 files changed, 602 insertions(+)
>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-isp.c
>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-isp.h
>
> diff --git a/drivers/media/platform/exynos5-is/fimc-is-isp.c b/drivers/media/platform/exynos5-is/fimc-is-isp.c
> new file mode 100644
> index 0000000..e97e473
> --- /dev/null
> +++ b/drivers/media/platform/exynos5-is/fimc-is-isp.c
> @@ -0,0 +1,509 @@
> +/*
> + * Samsung EXYNOS5250 FIMC-IS (Imaging Subsystem) driver
> + *
> + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
> + *  Arun Kumar K<arun.kk@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include<media/v4l2-ioctl.h>
> +#include<media/videobuf2-dma-contig.h>
> +
> +#include "fimc-is.h"
> +
> +#define ISP_DRV_NAME "fimc-is-isp"
> +
> +static const struct fimc_is_fmt formats[] = {
> +	{
> +		.name           = "Bayer GR-BG 8bits",
> +		.fourcc         = V4L2_PIX_FMT_SGRBG8,
> +		.depth		= { 8 },
> +		.num_planes     = 1,
> +	},
> +	{
> +		.name           = "Bayer GR-BG 10bits",
> +		.fourcc         = V4L2_PIX_FMT_SGRBG10,
> +		.depth		= { 16 },
> +		.num_planes     = 1,
> +	},
> +	{
> +		.name           = "Bayer GR-BG 12bits",
> +		.fourcc         = V4L2_PIX_FMT_SGRBG12,
> +		.depth		= { 16 },
> +		.num_planes     = 1,
> +	},
> +};
> +#define NUM_FORMATS ARRAY_SIZE(formats)
> +
> +static const struct fimc_is_fmt *find_format(struct v4l2_format *f)
> +{
> +	unsigned int i;
> +
> +	for (i = 0; i<  NUM_FORMATS; i++) {
> +		if (formats[i].fourcc == f->fmt.pix_mp.pixelformat)
> +			return&formats[i];
> +	}

CodingStyle: braces are not needed.

> +	return NULL;
> +}
> +
> +static int isp_video_output_start_streaming(struct vb2_queue *vq,
> +					unsigned int count)
> +{
> +	struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
> +
> +	set_bit(STATE_RUNNING,&isp->output_state);
> +	return 0;
> +}
> +
> +static int isp_video_output_stop_streaming(struct vb2_queue *vq)
> +{
> +	struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
> +
> +	clear_bit(STATE_RUNNING,&isp->output_state);
> +	return 0;
> +}
> +
> +static int isp_video_output_queue_setup(struct vb2_queue *vq,
> +			const struct v4l2_format *pfmt,
> +			unsigned int *num_buffers, unsigned int *num_planes,
> +			unsigned int sizes[], void *allocators[])
> +{
> +	struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
> +	const struct fimc_is_fmt *fmt = isp->fmt;
> +	unsigned int wh, i;
> +
> +	if (!fmt)
> +		return -EINVAL;
> +
> +	*num_planes = fmt->num_planes;
> +	wh = isp->width * isp->height;
> +
> +	for (i = 0; i<  *num_planes; i++) {
> +		allocators[i] = isp->alloc_ctx;
> +		sizes[i] = (wh * fmt->depth[i]) / 8;
> +	}
> +	return 0;
> +}
> +
> +static int isp_video_output_buffer_init(struct vb2_buffer *vb)
> +{
> +	struct vb2_queue *vq = vb->vb2_queue;
> +	struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
> +	struct fimc_is_buf *buf;
> +
> +	buf =&isp->output_bufs[vb->v4l2_buf.index];
> +	/* Initialize buffer */
> +	buf->vb = vb;
> +	buf->paddr[0] = vb2_dma_contig_plane_dma_addr(vb, 0);
> +	isp->out_buf_cnt++;
> +	return 0;
> +}
> +
> +static void isp_video_output_buffer_queue(struct vb2_buffer *vb)
> +{
> +	struct vb2_queue *vq = vb->vb2_queue;
> +	struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
> +	struct fimc_is_buf *buf;
> +
> +	buf =&isp->output_bufs[vb->v4l2_buf.index];
> +
> +	fimc_is_pipeline_buf_lock(isp->pipeline);
> +	fimc_is_isp_wait_queue_add(isp, buf);
> +	fimc_is_pipeline_buf_unlock(isp->pipeline);
> +
> +	/* Call shot command */
> +	fimc_is_pipeline_shot(isp->pipeline);
> +}
> +
> +static const struct vb2_ops isp_video_output_qops = {
> +	.queue_setup	 = isp_video_output_queue_setup,
> +	.buf_init	 = isp_video_output_buffer_init,
> +	.buf_queue	 = isp_video_output_buffer_queue,
> +	.wait_prepare	 = vb2_ops_wait_prepare,
> +	.wait_finish	 = vb2_ops_wait_finish,
> +	.start_streaming = isp_video_output_start_streaming,
> +	.stop_streaming	 = isp_video_output_stop_streaming,
> +};
> +
> +static const struct v4l2_file_operations isp_video_output_fops = {
> +	.owner		= THIS_MODULE,
> +	.open		= v4l2_fh_open,
> +	.release	= vb2_fop_release,
> +	.poll		= vb2_fop_poll,
> +	.unlocked_ioctl	= video_ioctl2,
> +	.mmap		= vb2_fop_mmap,
> +};
> +
> +/*
> + * Video node ioctl operations
> + */
> +static int isp_querycap_output(struct file *file, void *priv,
> +					struct v4l2_capability *cap)
> +{
> +	strncpy(cap->driver, ISP_DRV_NAME, sizeof(cap->driver) - 1);
> +	strncpy(cap->card, ISP_DRV_NAME, sizeof(cap->card) - 1);
> +	snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
> +			ISP_DRV_NAME);
> +	cap->device_caps = V4L2_CAP_STREAMING;
> +	cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
> +	return 0;
> +}
> +
> +static int isp_enum_fmt_mplane(struct file *file, void *priv,
> +				     struct v4l2_fmtdesc *f)
> +{
> +	const struct fimc_is_fmt *fmt;
> +
> +	if (f->index>= NUM_FORMATS)
> +		return -EINVAL;
> +
> +	fmt =&formats[f->index];
> +	strlcpy(f->description, fmt->name, sizeof(f->description));
> +	f->pixelformat = fmt->fourcc;
> +
> +	return 0;
> +}
> +
> +static int isp_g_fmt_mplane(struct file *file, void *fh,
> +				  struct v4l2_format *f)
> +{
> +	struct fimc_is_isp *isp = video_drvdata(file);
> +	struct v4l2_pix_format_mplane *pixm =&f->fmt.pix_mp;
> +	struct v4l2_plane_pix_format *plane_fmt =&pixm->plane_fmt[0];
> +	const struct fimc_is_fmt *fmt = isp->fmt;
> +
> +	plane_fmt->bytesperline = (isp->width * fmt->depth[0]) / 8;
> +	plane_fmt->sizeimage = plane_fmt->bytesperline * isp->height;
> +	memset(plane_fmt->reserved, 0, sizeof(plane_fmt->reserved));
> +
> +	pixm->num_planes = fmt->num_planes;
> +	pixm->pixelformat = fmt->fourcc;
> +	pixm->width = isp->width;
> +	pixm->height = isp->height;
> +	pixm->field = V4L2_FIELD_NONE;
> +	pixm->colorspace = V4L2_COLORSPACE_JPEG;
> +	memset(pixm->reserved, 0, sizeof(pixm->reserved));
> +
> +	return 0;
> +}
> +
> +static int isp_try_fmt_mplane(struct file *file, void *fh,
> +		struct v4l2_format *f)
> +{
> +	const struct fimc_is_fmt *fmt;
> +	struct v4l2_pix_format_mplane *pixm =&f->fmt.pix_mp;
> +	struct v4l2_plane_pix_format *plane_fmt =&pixm->plane_fmt[0];
> +
> +	fmt = find_format(f);
> +	if (!fmt)
> +		fmt = (struct fimc_is_fmt *)&formats[0];
> +
> +	v4l_bound_align_image(&pixm->width,
> +			ISP_MIN_WIDTH + SENSOR_WIDTH_PADDING,
> +			ISP_MAX_WIDTH + SENSOR_WIDTH_PADDING, 0,
> +			&pixm->height,
> +			ISP_MIN_HEIGHT + SENSOR_HEIGHT_PADDING,
> +			ISP_MAX_HEIGHT + SENSOR_HEIGHT_PADDING, 0,
> +			0);
> +
> +	plane_fmt->bytesperline = (pixm->width * fmt->depth[0]) / 8;
> +	plane_fmt->sizeimage = (pixm->width * pixm->height *
> +				fmt->depth[0]) / 8;
> +	memset(plane_fmt->reserved, 0, sizeof(plane_fmt->reserved));
> +
> +	pixm->num_planes = fmt->num_planes;
> +	pixm->pixelformat = fmt->fourcc;
> +	pixm->colorspace = V4L2_COLORSPACE_JPEG;
> +	pixm->field = V4L2_FIELD_NONE;
> +	memset(pixm->reserved, 0, sizeof(pixm->reserved));
> +
> +	return 0;
> +}
> +
> +static int isp_s_fmt_mplane(struct file *file, void *priv,
> +		struct v4l2_format *f)
> +{
> +	struct fimc_is_isp *isp = video_drvdata(file);

nit: It would make sense to add:

	struct v4l2_pix_format_mplane *pixm =&f->fmt.pix_mp;

And use it below instead of f->fmt.pix_mp.

> +	const struct fimc_is_fmt *fmt;
> +	int ret;
> +
> +	ret = isp_try_fmt_mplane(file, priv, f);
> +	if (ret)
> +		return ret;
> +
> +	/* Get format type */
> +	fmt = find_format(f);
> +	if (!fmt) {
> +		fmt = (struct fimc_is_fmt *)&formats[0];

Casting is not needed.

> +		f->fmt.pix_mp.pixelformat = fmt->fourcc;
> +		f->fmt.pix_mp.num_planes = fmt->num_planes;
> +	}
> +
> +	isp->fmt = fmt;
> +	isp->width = f->fmt.pix_mp.width;
> +	isp->height = f->fmt.pix_mp.height;
> +	isp->size_image = f->fmt.pix_mp.plane_fmt[0].sizeimage;
> +	set_bit(STATE_INIT,&isp->output_state);
> +	return 0;
> +}
> +
> +static int isp_reqbufs(struct file *file, void *priv,
> +		struct v4l2_requestbuffers *reqbufs)
> +{
> +	struct fimc_is_isp *isp = video_drvdata(file);
> +	int ret;
> +
> +	reqbufs->count = max_t(u32, FIMC_IS_ISP_REQ_BUFS_MIN, reqbufs->count);
> +	ret = vb2_reqbufs(&isp->vbq, reqbufs);
> +	if (ret) {
> +		pr_err("vb2 req buffers failed\n");

Please use v4l2_err() or dev_err() so we can get some hint which device
emits the logs.

> +		return ret;
> +	}

I think you should check reqbufs->count here if it didn't get adjusted
by vb2_reqbufs() to a value lower than FIMC_IS_ISP_REQ_BUFS_MIN. And in
such case you would do something like:

	reqbufs->count = 0;
	vb2_reqbufs(&isp->vbq, reqbufs);
	return -EERROR;

> +	isp->out_buf_cnt = 0;
> +	set_bit(STATE_BUFS_ALLOCATED,&isp->output_state);
> +	return 0;
> +}
> +
> +static const struct v4l2_ioctl_ops isp_video_output_ioctl_ops = {
> +	.vidioc_querycap		= isp_querycap_output,
> +	.vidioc_enum_fmt_vid_out_mplane	= isp_enum_fmt_mplane,
> +	.vidioc_try_fmt_vid_out_mplane	= isp_try_fmt_mplane,
> +	.vidioc_s_fmt_vid_out_mplane	= isp_s_fmt_mplane,
> +	.vidioc_g_fmt_vid_out_mplane	= isp_g_fmt_mplane,
> +	.vidioc_reqbufs			= isp_reqbufs,
> +	.vidioc_querybuf		= vb2_ioctl_querybuf,
> +	.vidioc_qbuf			= vb2_ioctl_qbuf,
> +	.vidioc_dqbuf			= vb2_ioctl_dqbuf,
> +	.vidioc_streamon		= vb2_ioctl_streamon,
> +	.vidioc_streamoff		= vb2_ioctl_streamoff,
> +};
> +
> +static int isp_subdev_registered(struct v4l2_subdev *sd)
> +{
> +	struct fimc_is_isp *isp = v4l2_get_subdevdata(sd);
> +	struct vb2_queue *q =&isp->vbq;
> +	struct video_device *vfd =&isp->vfd;
> +	int ret;
> +
> +	mutex_init(&isp->video_lock);
> +
> +	memset(vfd, 0, sizeof(*vfd));
> +	snprintf(vfd->name, sizeof(vfd->name), "fimc-is-isp.output");
> +
> +	vfd->fops =&isp_video_output_fops;
> +	vfd->ioctl_ops =&isp_video_output_ioctl_ops;
> +	vfd->v4l2_dev = sd->v4l2_dev;
> +	vfd->release = video_device_release_empty;
> +	vfd->lock =&isp->video_lock;
> +	vfd->queue = q;
> +	vfd->vfl_dir = VFL_DIR_TX;
> +	set_bit(V4L2_FL_USE_FH_PRIO,&vfd->flags);
> +
> +	memset(q, 0, sizeof(*q));
> +	q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
> +	q->io_modes = VB2_MMAP | VB2_DMABUF;
> +	q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
> +	q->ops =&isp_video_output_qops;
> +	q->mem_ops =&vb2_dma_contig_memops;
> +	q->drv_priv = isp;
> +
> +	ret = vb2_queue_init(q);
> +	if (ret<  0)
> +		return ret;
> +
> +	isp->vd_pad.flags = MEDIA_PAD_FL_SINK;
> +	ret = media_entity_init(&vfd->entity, 1,&isp->vd_pad, 0);
> +	if (ret<  0)
> +		return ret;
> +
> +	video_set_drvdata(vfd, isp);
> +
> +	ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
> +	if (ret<  0) {
> +		media_entity_cleanup(&vfd->entity);
> +		return ret;
> +	}
> +
> +	v4l2_info(sd->v4l2_dev, "Registered %s as /dev/%s\n",
> +		  vfd->name, video_device_node_name(vfd));
> +	return 0;
> +}
> +
> +static void isp_subdev_unregistered(struct v4l2_subdev *sd)
> +{
> +	struct fimc_is_isp *isp = v4l2_get_subdevdata(sd);
> +
> +	if (isp&&  video_is_registered(&isp->vfd))
> +		video_unregister_device(&isp->vfd);
> +}
> +
> +static const struct v4l2_subdev_internal_ops isp_subdev_internal_ops = {
> +	.registered = isp_subdev_registered,
> +	.unregistered = isp_subdev_unregistered,
> +};
> +
> +static struct fimc_is_sensor *fimc_is_get_sensor(struct fimc_is *is,
> +		int sensor_id)
> +{
> +	int i;
> +
> +	for (i = 0; i<  FIMC_IS_NUM_SENSORS; i++) {
> +		if (is->sensor[i].drvdata->id == sensor_id)
> +			return&is->sensor[i];
> +	}
> +	return NULL;
> +}
> +
> +static int isp_s_power(struct v4l2_subdev *sd, int on)
> +{
> +	struct fimc_is_isp *isp = v4l2_get_subdevdata(sd);
> +	struct fimc_is *is = isp->pipeline->is;
> +	struct v4l2_subdev *sensor_sd = isp->sensor_sd;
> +	struct fimc_is_sensor *sensor;
> +	const struct sensor_drv_data *sdata;
> +	struct media_pad *pad;
> +	struct v4l2_subdev_format fmt;
> +	int ret;
> +
> +	if (!sensor_sd)
> +		return -EINVAL;
> +
> +	if (on) {
> +		ret = pm_runtime_get_sync(&is->pdev->dev);
> +		if (ret<  0)
> +			return ret;
> +
> +		sdata = exynos5_is_sensor_get_drvdata(sensor_sd->dev->of_node);
> +		sensor = fimc_is_get_sensor(is, sdata->id);
> +		/* Retrieve the sensor format */
> +		pad =&sensor_sd->entity.pads[0];

w00t ?

> +		fmt.pad = 0;
> +		fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
> +		ret = v4l2_subdev_call(sensor_sd, pad, get_fmt, NULL,&fmt);

Pad is just a name of the callback pointers data structure:

struct v4l2_subdev {
	...
	const struct v4l2_subdev_ops *ops;
	...
};

struct v4l2_subdev_ops {
	const struct v4l2_subdev_core_ops	*core;
	const struct v4l2_subdev_tuner_ops	*tuner;
	const struct v4l2_subdev_audio_ops	*audio;
	const struct v4l2_subdev_video_ops	*video;
	const struct v4l2_subdev_vbi_ops	*vbi;
	const struct v4l2_subdev_ir_ops		*ir;
	const struct v4l2_subdev_sensor_ops	*sensor;
	const struct v4l2_subdev_pad_ops	*pad;
};

#define v4l2_subdev_call(sd, o, f, args...)				\
	(!(sd) ? -ENODEV : (((sd)->ops->o && (sd)->ops->o->f) ?	\
		(sd)->ops->o->f((sd) , ##args) : -ENOIOCTLCMD))


> +		if (ret)
> +			return ret;
> +
> +		sensor->width = fmt.format.width - SENSOR_WIDTH_PADDING;
> +		sensor->height = fmt.format.height - SENSOR_HEIGHT_PADDING;
> +		sensor->pixel_width = fmt.format.width;
> +		sensor->pixel_height = fmt.format.height;

Shouldn't this get_fmt call be done in STREAMON handler, after
media_entity_pipeline_start() gets called ? Why do you need it here ?

> +		ret = fimc_is_pipeline_open(isp->pipeline, sensor);
> +		if (ret)
> +			pr_err("Pipeline open failed\n");
> +	} else {
> +		ret = fimc_is_pipeline_close(isp->pipeline);
> +		if (ret)
> +			pr_err("Pipeline close failed\n");
> +		pm_runtime_put_sync(&is->pdev->dev);
> +	}
> +
> +	return ret;
> +}
> +
> +static struct v4l2_subdev_core_ops isp_core_ops = {
> +	.s_power = isp_s_power,
> +};
> +
> +static int isp_s_stream(struct v4l2_subdev *sd, int enable)
> +{
> +	struct fimc_is_isp *isp = v4l2_get_subdevdata(sd);
> +	struct fimc_is *is = isp->pipeline->is;
> +	struct v4l2_subdev *sensor_sd = isp->sensor_sd;
> +	const struct sensor_drv_data *sdata;
> +	struct fimc_is_sensor *sensor;
> +	int ret;
> +
> +	if (!sensor_sd)
> +		return -EINVAL;
> +
> +	if (enable) {
> +		sdata = exynos5_is_sensor_get_drvdata(sensor_sd->dev->of_node);
> +		sensor = fimc_is_get_sensor(is, sdata->id);
> +		/* Check sensor resolution match */
> +		if ((sensor->pixel_width != isp->width) ||
> +			(sensor->pixel_height != isp->height)) {
> +			pr_err("Resolution mismatch\n");
> +			return -EPIPE;
> +		}
> +		ret = fimc_is_pipeline_start(isp->pipeline);
> +		if (ret)
> +			pr_err("Pipeline start failed.\n");

Please use v4l2_err(sd, ...);	

> +	} else {
> +		ret = fimc_is_pipeline_stop(isp->pipeline);
> +		if (ret)
> +			pr_err("Pipeline stop failed.\n");

Ditto.

> +	}
> +
> +	return ret;
> +}
> +
> +static const struct v4l2_subdev_video_ops isp_video_ops = {
> +	.s_stream       = isp_s_stream,
> +};
> +
> +static struct v4l2_subdev_ops isp_subdev_ops = {
> +	.core =&isp_core_ops,
> +	.video =&isp_video_ops,
> +};
> +
> +int fimc_is_isp_subdev_create(struct fimc_is_isp *isp,
> +		struct vb2_alloc_ctx *alloc_ctx,
> +		struct fimc_is_pipeline *pipeline)
> +{
> +	struct v4l2_ctrl_handler *handler =&isp->ctrl_handler;
> +	struct v4l2_subdev *sd =&isp->subdev;
> +	int ret;
> +
> +	/* Init context vars */

This comment don't seem to be really helpful.

> +	isp->alloc_ctx = alloc_ctx;
> +	isp->pipeline = pipeline;
> +	isp->fmt =&formats[1];
> +	INIT_LIST_HEAD(&isp->wait_queue);
> +	INIT_LIST_HEAD(&isp->run_queue);
> +	isp->width = ISP_DEF_WIDTH;
> +	isp->height = ISP_DEF_HEIGHT;
> +
> +	v4l2_subdev_init(sd,&isp_subdev_ops);
> +	sd->owner = THIS_MODULE;
> +	sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
> +	snprintf(sd->name, sizeof(sd->name), ISP_DRV_NAME);
> +
> +	isp->subdev_pads[ISP_SD_PAD_SINK_DMA].flags = MEDIA_PAD_FL_SINK;
> +	isp->subdev_pads[ISP_SD_PAD_SINK_OTF].flags = MEDIA_PAD_FL_SINK;
> +	isp->subdev_pads[ISP_SD_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE;
> +	ret = media_entity_init(&sd->entity, ISP_SD_PADS_NUM,
> +			isp->subdev_pads, 0);
> +	if (ret<  0)
> +		return ret;
> +
> +	ret = v4l2_ctrl_handler_init(handler, 1);
> +	if (handler->error)
> +		goto err_ctrl;
> +
> +	sd->ctrl_handler = handler;
> +	sd->internal_ops =&isp_subdev_internal_ops;
> +	v4l2_set_subdevdata(sd, isp);
> +
> +	return 0;
> +
> +err_ctrl:
> +	media_entity_cleanup(&sd->entity);
> +	v4l2_ctrl_handler_free(handler);
> +	return ret;
> +}

--
Regards,
Sylwester

Re: [RFC v3 08/13] [media] exynos5-fimc-is: Add sensor interface

[Sylwester Nawrocki]

On 08/02/2013 05:02 PM, Arun Kumar K wrote:
> Some sensors to be used with fimc-is are exclusively controlled
> by the fimc-is firmware. This minimal sensor driver provides
> the required info for the firmware to configure the sensors
> sitting on I2C bus.
>
> Signed-off-by: Arun Kumar K<arun.kk@samsung.com>
> ---
>   drivers/media/platform/exynos5-is/fimc-is-sensor.c |   46 +++++++++++++
>   drivers/media/platform/exynos5-is/fimc-is-sensor.h |   69 ++++++++++++++++++++
>   2 files changed, 115 insertions(+)
>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-sensor.c
>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-sensor.h
>
> diff --git a/drivers/media/platform/exynos5-is/fimc-is-sensor.c b/drivers/media/platform/exynos5-is/fimc-is-sensor.c
> new file mode 100644
> index 0000000..3e4aae9
> --- /dev/null
> +++ b/drivers/media/platform/exynos5-is/fimc-is-sensor.c
> @@ -0,0 +1,46 @@
> +/*
> + * Samsung EXYNOS5250 FIMC-IS (Imaging Subsystem) driver
> + *
> + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
> + * Authors:  Sylwester Nawrocki<s.nawrocki@samsung.com>
> + *           Arun Kumar K<arun.kk@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include "fimc-is-sensor.h"
> +
> +static const struct sensor_drv_data s5k6a3_drvdata = {
> +	.id		= FIMC_IS_SENSOR_ID_S5K6A3,
> +	.open_timeout	= S5K6A3_OPEN_TIMEOUT,
> +	.setfile_name	= "setfile_6a3.bin",
> +};
> +
> +static const struct sensor_drv_data s5k4e5_drvdata = {
> +	.id		= FIMC_IS_SENSOR_ID_S5K4E5,
> +	.open_timeout	= S5K4E5_OPEN_TIMEOUT,
> +	.setfile_name	= "setfile_4e5.bin",
> +};
> +
> +static const struct of_device_id fimc_is_sensor_of_ids[] = {
> +	{
> +		.compatible	= "samsung,s5k6a3",
> +		.data		=&s5k6a3_drvdata,
> +	},
> +	{
> +		.compatible	= "samsung,s5k4e5",
> +		.data		=&s5k4e5_drvdata,
> +	},
> +	{  }
> +};
> +
> +const struct sensor_drv_data *exynos5_is_sensor_get_drvdata(
> +			struct device_node *node)
> +{
> +	const struct of_device_id *of_id;
> +
> +	of_id = of_match_node(fimc_is_sensor_of_ids, node);
> +	return of_id ? of_id->data : NULL;
> +}
> diff --git a/drivers/media/platform/exynos5-is/fimc-is-sensor.h b/drivers/media/platform/exynos5-is/fimc-is-sensor.h
> new file mode 100644
> index 0000000..51e18ea
> --- /dev/null
> +++ b/drivers/media/platform/exynos5-is/fimc-is-sensor.h
> @@ -0,0 +1,69 @@
> +/*
> + * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
> + *
> + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
> + *
> + * Authors:  Sylwester Nawrocki<s.nawrocki@samsung.com>
> + *	     Younghwan Joo<yhwan.joo@samsung.com>
> + *	     Arun Kumar K<arun.kk@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +#ifndef FIMC_IS_SENSOR_H_
> +#define FIMC_IS_SENSOR_H_
> +
> +#include<linux/of.h>
> +#include<linux/types.h>
> +
> +#define S5K6A3_OPEN_TIMEOUT		2000 /* ms */
> +#define S5K6A3_SENSOR_WIDTH		1392
> +#define S5K6A3_SENSOR_HEIGHT		1392
> +
> +#define S5K4E5_OPEN_TIMEOUT		2000 /* ms */
> +#define S5K4E5_SENSOR_WIDTH		2560
> +#define S5K4E5_SENSOR_HEIGHT		1920
> +
> +#define SENSOR_WIDTH_PADDING		16
> +#define SENSOR_HEIGHT_PADDING		10
> +
> +enum fimc_is_sensor_id {
> +	FIMC_IS_SENSOR_ID_S5K3H2 = 1,
> +	FIMC_IS_SENSOR_ID_S5K6A3,
> +	FIMC_IS_SENSOR_ID_S5K4E5,
> +	FIMC_IS_SENSOR_ID_S5K3H7,
> +	FIMC_IS_SENSOR_ID_CUSTOM,
> +	FIMC_IS_SENSOR_ID_END
> +};
> +
> +#define IS_SENSOR_CTRL_BUS_I2C0		0
> +#define IS_SENSOR_CTRL_BUS_I2C1		1

Are these two constants used anywhere ?

> +struct sensor_drv_data {
> +	enum fimc_is_sensor_id id;
> +	/* sensor open timeout in ms */
> +	unsigned short open_timeout;
> +	char *setfile_name;
> +};
> +
> +/**
> + * struct fimc_is_sensor - fimc-is sensor data structure
> + * @drvdata: a pointer to the sensor's parameters data structure
> + * @i2c_bus: ISP I2C bus index (0...1)
> + * @test_pattern: true to enable video test pattern
> + */
> +struct fimc_is_sensor {
> +	const struct sensor_drv_data *drvdata;
> +	unsigned int i2c_bus;

> +	unsigned int width;
> +	unsigned int height;
> +	unsigned int pixel_width;
> +	unsigned int pixel_height;

What is difference between width/height and pixel_width/pixel_height ?
Would be good to add some documentation for these fields.

> +	u8 test_pattern;
> +};
> +
> +const struct sensor_drv_data *exynos5_is_sensor_get_drvdata(
> +			struct device_node *node);
> +
> +#endif /* FIMC_IS_SENSOR_H_ */

Thanks,
Sylwester

Re: [RFC v3 13/13] V4L: Add driver for s5k4e5 image sensor

[Sylwester Nawrocki]

On 08/02/2013 05:02 PM, Arun Kumar K wrote:
> This patch adds subdev driver for Samsung S5K4E5 raw image sensor.
> Like s5k6a3, it is also another fimc-is firmware controlled
> sensor. This minimal sensor driver doesn't do any I2C communications
> as its done by ISP firmware. It can be updated if needed to a
> regular sensor driver by adding the I2C communication.
>
> Signed-off-by: Arun Kumar K<arun.kk@samsung.com>
> ---
>   drivers/media/i2c/Kconfig  |    8 +
>   drivers/media/i2c/Makefile |    1 +
>   drivers/media/i2c/s5k4e5.c |  362 ++++++++++++++++++++++++++++++++++++++++++++

Hmm, we also need the device tree binding documentation file.

>   3 files changed, 371 insertions(+)
>   create mode 100644 drivers/media/i2c/s5k4e5.c
[...]
> new file mode 100644
> index 0000000..a713c6a
> --- /dev/null
> +++ b/drivers/media/i2c/s5k4e5.c
> @@ -0,0 +1,362 @@
> +/*
> + * Samsung S5K4E5 image sensor driver
> + *
> + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
> + * Author: Arun Kumar K<arun.kk@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include<linux/clk.h>
> +#include<linux/delay.h>
> +#include<linux/device.h>
> +#include<linux/errno.h>
> +#include<linux/gpio.h>
> +#include<linux/i2c.h>
> +#include<linux/kernel.h>
> +#include<linux/module.h>
> +#include<linux/of_gpio.h>
> +#include<linux/pm_runtime.h>
> +#include<linux/regulator/consumer.h>
> +#include<linux/slab.h>
> +#include<linux/videodev2.h>
> +#include<media/v4l2-async.h>
> +#include<media/v4l2-subdev.h>
> +
> +#define S5K4E5_SENSOR_MAX_WIDTH		2560
> +#define S5K4E5_SENSOR_MAX_HEIGHT	1920
> +#define S5K4E5_SENSOR_MIN_WIDTH		32
> +#define S5K4E5_SENSOR_MIN_HEIGHT	32
> +
> +#define S5K4E5_WIDTH_PADDING		16
> +#define S5K4E5_HEIGHT_PADDING		10
> +
> +#define S5K4E5_DEF_PIX_WIDTH		1296
> +#define S5K4E5_DEF_PIX_HEIGHT		732

Please see my comments to patch 12/13 WRT to these defines.

> +#define S5K4E5_DRV_NAME			"S5K4E5"
> +#define S5K4E5_CLK_NAME			"mclk"
> +
> +#define S5K4E5_NUM_SUPPLIES		2
> +
> +/**
> + * struct s5k4e5 - fimc-is sensor data structure

s/fimc-is/s5k4e5 ?

> + * @dev: pointer to this I2C client device structure
> + * @subdev: the image sensor's v4l2 subdev
> + * @pad: subdev media source pad
> + * @supplies: image sensor's voltage regulator supplies
> + * @gpio_reset: GPIO connected to the sensor's reset pin
> + * @lock: mutex protecting the structure's members below
> + * @format: media bus format at the sensor's source pad
> + */
> +struct s5k4e5 {
> +	struct device *dev;
> +	struct v4l2_subdev subdev;
> +	struct media_pad pad;
> +	struct regulator_bulk_data supplies[S5K4E5_NUM_SUPPLIES];
> +	int gpio_reset;
> +	struct mutex lock;
> +	struct v4l2_mbus_framefmt format;
> +	struct clk *clock;
> +	u32 clock_frequency;
> +};
> +
> +static const char * const s5k4e5_supply_names[] = {
> +	"svdda",
> +	"svddio"
> +};
[...]
> +static int s5k4e5_probe(struct i2c_client *client,
> +				const struct i2c_device_id *id)
> +{
> +	struct device *dev =&client->dev;
> +	struct s5k4e5 *sensor;
> +	struct v4l2_subdev *sd;
> +	int gpio, i, ret;
> +
> +	sensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL);
> +	if (!sensor)
> +		return -ENOMEM;
> +
> +	mutex_init(&sensor->lock);
> +	sensor->gpio_reset = -EINVAL;
> +	sensor->clock = ERR_PTR(-EINVAL);
> +	sensor->dev = dev;
> +
> +	gpio = of_get_gpio_flags(dev->of_node, 0, NULL);
> +	if (gpio_is_valid(gpio)) {
> +		ret = devm_gpio_request_one(dev, gpio, GPIOF_OUT_INIT_LOW,
> +							S5K4E5_DRV_NAME);
> +		if (ret<  0)
> +			return ret;
> +	}
> +	sensor->gpio_reset = gpio;
> +
> +	if (of_property_read_u32(dev->of_node, "clock-frequency",
> +				&sensor->clock_frequency)) {
> +		dev_err(dev, "clock-frequency property not found at %s\n",
> +						dev->of_node->full_name);
> +		return -EINVAL;

I would make "clock-frequency" property optional and instead of returning
error use some default frequency value when this property is not specified
in DT. This also need to be put into the DT binding document.

> +	}
> +
> +	for (i = 0; i<  S5K4E5_NUM_SUPPLIES; i++)
> +		sensor->supplies[i].supply = s5k4e5_supply_names[i];
> +
> +	ret = devm_regulator_bulk_get(&client->dev, S5K4E5_NUM_SUPPLIES,
> +				      sensor->supplies);
> +	if (ret<  0)
> +		return ret;
> +
> +	/* Defer probing if the clock is not available yet */
> +	sensor->clock = clk_get(dev, S5K4E5_CLK_NAME);
> +	if (IS_ERR(sensor->clock))
> +		return -EPROBE_DEFER;
> +
> +	sd =&sensor->subdev;
> +	v4l2_i2c_subdev_init(sd, client,&s5k4e5_subdev_ops);
> +	snprintf(sd->name, sizeof(sd->name), S5K4E5_DRV_NAME);

Unfortunately this line needs to be removed, the subdev name should
be unique and should have I2C bus number and I2C slave address appended
to it. It's already being done in v4l2_i2c_subdev_init() function.

	snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
		client->driver->driver.name, i2c_adapter_id(client->adapter),
		client->addr);

I've also dropped such overriding for the s5k6a3 sensor.

> +	sensor->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
> +
> +	sensor->format.code = s5k4e5_formats[0].code;
> +	sensor->format.width = S5K4E5_DEF_PIX_WIDTH;
> +	sensor->format.height = S5K4E5_DEF_PIX_HEIGHT;
> +
> +	sensor->pad.flags = MEDIA_PAD_FL_SOURCE;
> +	ret = media_entity_init(&sd->entity, 1,&sensor->pad, 0);
> +	if (ret<  0)
> +		return ret;
> +
> +	pm_runtime_no_callbacks(dev);
> +	pm_runtime_enable(dev);
> +
> +	ret = v4l2_async_register_subdev(sd);
> +
> +	/*
> +	 * Don't hold reference to the clock to avoid circular dependency
> +	 * between the subdev and the host driver, in case the host is
> +	 * a supplier of the clock.
> +	 * clk_get()/clk_put() will be called in s_power callback.
> +	 */
> +	clk_put(sensor->clock);
> +
> +	return ret;
> +}
[...]
> +static struct i2c_driver s5k4e5_driver = {
> +	.driver = {
> +		.of_match_table	= of_match_ptr(s5k4e5_of_match),
> +		.name		= S5K4E5_DRV_NAME,
> +		.owner		= THIS_MODULE,
> +	},
> +	.probe		= s5k4e5_probe,
> +	.remove		= s5k4e5_remove,
> +	.id_table	= s5k4e5_ids,
> +};

Otherwise looks good to me.

--
Regards,
Sylwester

Re: [RFC v3 12/13] V4L: s5k6a3: Change sensor min/max resolutions

[Sylwester Nawrocki]

Hi Arun,

On 08/02/2013 05:02 PM, Arun Kumar K wrote:
> s5k6a3 sensor has actual pixel resolution of 1408x1402 against
> the active resolution 1392x1392. The real resolution is needed
> when raw sensor SRGB data is dumped to memory by fimc-lite.
>
> Signed-off-by: Arun Kumar K<arun.kk@samsung.com>
> ---
>   drivers/media/i2c/s5k6a3.c |   14 ++++++++++----
>   1 file changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/media/i2c/s5k6a3.c b/drivers/media/i2c/s5k6a3.c
> index ccbb4fc..d81638d 100644
> --- a/drivers/media/i2c/s5k6a3.c
> +++ b/drivers/media/i2c/s5k6a3.c
> @@ -30,6 +30,9 @@
>   #define S5K6A3_SENSOR_MIN_WIDTH		32
>   #define S5K6A3_SENSOR_MIN_HEIGHT	32
>
> +#define S5K6A3_WIDTH_PADDING		16
> +#define S5K6A3_HEIGHT_PADDING		10

How about instead defining MAX and ACTIVE sizes, e.g.

#define S5K6A3_SENSOR_MAX_WIDTH			1408
#define S5K6A3_SENSOR_MAX_HEIGHT		1402

#define S5K6A3_SENSOR_ACTIVE_WIDTH		1392	
#define S5K6A3_SENSOR_ACTIVE_HEIGHT		1392

>   #define S5K6A3_DEF_PIX_WIDTH		1296
>   #define S5K6A3_DEF_PIX_HEIGHT		732

I'm going to remove "_PIX" from those macros in next iteration.

> @@ -107,10 +110,13 @@ static void s5k6a3_try_format(struct v4l2_mbus_framefmt *mf)
>
>   	fmt = find_sensor_format(mf);
>   	mf->code = fmt->code;
> -	v4l_bound_align_image(&mf->width, S5K6A3_SENSOR_MIN_WIDTH,
> -			      S5K6A3_SENSOR_MAX_WIDTH, 0,
> -			&mf->height, S5K6A3_SENSOR_MIN_HEIGHT,
> -			      S5K6A3_SENSOR_MAX_HEIGHT, 0, 0);
> +	v4l_bound_align_image(&mf->width,
> +			S5K6A3_SENSOR_MIN_WIDTH + S5K6A3_WIDTH_PADDING,
> +			S5K6A3_SENSOR_MAX_WIDTH + S5K6A3_WIDTH_PADDING, 0,
> +			&mf->height,
> +			S5K6A3_SENSOR_MIN_HEIGHT + S5K6A3_HEIGHT_PADDING,
> +			S5K6A3_SENSOR_MAX_HEIGHT + S5K6A3_HEIGHT_PADDING, 0,
> +			0);

Then this would become:

	v4l_bound_align_image(&mf->width,
			S5K6A3_SENSOR_MIN_WIDTH + S5K6A3_WIDTH_PADDING,
			S5K6A3_SENSOR_MAX_WIDTH, 0,
			&mf->height,
			S5K6A3_SENSOR_MIN_HEIGHT + S5K6A3_HEIGHT_PADDING,
			S5K6A3_SENSOR_MAX_HEIGHT, 0,
			0);

I'm not sure about minimal width/height, perhaps we could just define it as:

#define S5K6A3_SENSOR_MIN_WIDTH		(32 + 10)
#define S5K6A3_SENSOR_MIN_HEIGHT	(32 + 8)

? I'll also double check with the documentation if the original 32x23 value
is really correct.

--
Regards,
Sylwester

Re: [RFC v3 11/13] [media] exynos5-is: Add Kconfig and Makefile

[Sylwester Nawrocki]

On 08/02/2013 05:02 PM, Arun Kumar K wrote:
> Adds Kconfig and Makefile for exynos5-is driver files.
>
> Signed-off-by: Shaik Ameer Basha<shaik.ameer@samsung.com>
> Signed-off-by: Kilyeon Im<kilyeon.im@samsung.com>
> Signed-off-by: Arun Kumar K<arun.kk@samsung.com>
> ---
>   drivers/media/platform/Kconfig             |    1 +
>   drivers/media/platform/Makefile            |    1 +
>   drivers/media/platform/exynos5-is/Kconfig  |   19 +++++++++++++++++++
>   drivers/media/platform/exynos5-is/Makefile |    7 +++++++
>   4 files changed, 28 insertions(+)
>   create mode 100644 drivers/media/platform/exynos5-is/Kconfig
>   create mode 100644 drivers/media/platform/exynos5-is/Makefile
>
> diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
> index 08de865..4b0475e 100644
> --- a/drivers/media/platform/Kconfig
> +++ b/drivers/media/platform/Kconfig
> @@ -123,6 +123,7 @@ config VIDEO_S3C_CAMIF
>
>   source "drivers/media/platform/soc_camera/Kconfig"
>   source "drivers/media/platform/exynos4-is/Kconfig"
> +source "drivers/media/platform/exynos5-is/Kconfig"
>   source "drivers/media/platform/s5p-tv/Kconfig"
>
>   endif # V4L_PLATFORM_DRIVERS
> diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile
> index eee28dd..b1225e5 100644
> --- a/drivers/media/platform/Makefile
> +++ b/drivers/media/platform/Makefile
> @@ -37,6 +37,7 @@ obj-$(CONFIG_VIDEO_SAMSUNG_S5P_TV)	+= s5p-tv/
>
>   obj-$(CONFIG_VIDEO_SAMSUNG_S5P_G2D)	+= s5p-g2d/
>   obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC)	+= exynos-gsc/
> +obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS5_MDEV)	+= exynos5-is/
>
>   obj-$(CONFIG_BLACKFIN)                  += blackfin/
>
> diff --git a/drivers/media/platform/exynos5-is/Kconfig b/drivers/media/platform/exynos5-is/Kconfig
> new file mode 100644
> index 0000000..99d5edf
> --- /dev/null
> +++ b/drivers/media/platform/exynos5-is/Kconfig
> @@ -0,0 +1,19 @@
> +config VIDEO_SAMSUNG_EXYNOS5_MDEV

Wouldn't VIDEO_SAMSUNG_EXYNOS5_CAMERA be a better symbol name ?

> +	bool "Samsung Exynos5 Media Device driver"
> +	depends on VIDEO_V4L2&&  VIDEO_V4L2_SUBDEV_API&&  PM_RUNTIME&&  VIDEO_SAMSUNG_EXYNOS4_IS

nit: It might make sense to put "depends on VIDEO_SAMSUNG_EXYNOS4_IS"
      in a separate line so it stands out a bit.

> +	help
> +	  This is a v4l2 based media controller driver for
> +	  Exynos5 SoC.
> +
> +if VIDEO_SAMSUNG_EXYNOS5_MDEV
> +
> +config VIDEO_SAMSUNG_EXYNOS5_FIMC_IS
> +	tristate "Samsung Exynos5 SoC FIMC-IS driver"
> +	depends on I2C&&  OF
> +	depends on VIDEO_EXYNOS4_FIMC_IS
> +	select VIDEOBUF2_DMA_CONTIG
> +	help
> +	  This is a V4L2 driver for Samsung Exynos5 SoC series Imaging
> +	  Subsystem known as FIMC-IS.
> +
> +endif #VIDEO_SAMSUNG_EXYNOS5_MDEV
> diff --git a/drivers/media/platform/exynos5-is/Makefile b/drivers/media/platform/exynos5-is/Makefile
> new file mode 100644
> index 0000000..c4e37e0
> --- /dev/null
> +++ b/drivers/media/platform/exynos5-is/Makefile
> @@ -0,0 +1,7 @@
> +ccflags-y += -Idrivers/media/platform/exynos4-is
> +exynos5-fimc-is-objs := fimc-is-core.o fimc-is-isp.o fimc-is-scaler.o
> +exynos5-fimc-is-objs += fimc-is-pipeline.o fimc-is-interface.o fimc-is-sensor.o
> +exynos-mdevice-objs := exynos5-mdev.o
> +
> +obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS5_FIMC_IS) += exynos5-fimc-is.o
> +obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS5_MDEV) += exynos-mdevice.o

--
Thanks,
Sylwester

Re: [RFC v3 09/13] [media] exynos5-fimc-is: Add the hardware pipeline control

[Sylwester Nawrocki]

Hi Arun,

On 08/02/2013 05:02 PM, Arun Kumar K wrote:
> This patch adds the crucial hardware pipeline control for the
> fimc-is driver. All the subdev nodes will call this pipeline
> interfaces to reach the hardware. Responsibilities of this module
> involves configuring and maintaining the hardware pipeline involving
> multiple sub-ips like ISP, DRC, Scalers, ODC, 3DNR, FD etc.
>
> Signed-off-by: Arun Kumar K<arun.kk@samsung.com>
> Signed-off-by: Kilyeon Im<kilyeon.im@samsung.com>
> ---
>   .../media/platform/exynos5-is/fimc-is-pipeline.c   | 1961 ++++++++++++++++++++
>   .../media/platform/exynos5-is/fimc-is-pipeline.h   |  129 ++
>   2 files changed, 2090 insertions(+)
>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-pipeline.c
>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-pipeline.h
>
> diff --git a/drivers/media/platform/exynos5-is/fimc-is-pipeline.c b/drivers/media/platform/exynos5-is/fimc-is-pipeline.c
> new file mode 100644
> index 0000000..070f1dc
> --- /dev/null
> +++ b/drivers/media/platform/exynos5-is/fimc-is-pipeline.c
> @@ -0,0 +1,1961 @@
> +/*
> + * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
> +*
> + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
> + * Arun Kumar K<arun.kk@samsung.com>
> + * Kil-yeon Lim<kilyeon.im@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include "fimc-is.h"
> +#include "fimc-is-pipeline.h"
> +#include "fimc-is-metadata.h"
> +#include "fimc-is-regs.h"
> +#include "fimc-is-cmd.h"
> +#include<media/videobuf2-dma-contig.h>
> +#include<linux/delay.h>
> +
> +/* Default setting values */
> +#define DEFAULT_PREVIEW_STILL_WIDTH		(1280) /* sensor margin : 16 */
> +#define DEFAULT_PREVIEW_STILL_HEIGHT		(720) /* sensor margin : 12 */

Is this comment about the margin still valid ?

> +#define DEFAULT_CAPTURE_VIDEO_WIDTH		(1920)
> +#define DEFAULT_CAPTURE_VIDEO_HEIGHT		(1080)
> +#define DEFAULT_CAPTURE_STILL_WIDTH		(2560)
> +#define DEFAULT_CAPTURE_STILL_HEIGHT		(1920)
> +#define DEFAULT_CAPTURE_STILL_CROP_WIDTH	(2560)
> +#define DEFAULT_CAPTURE_STILL_CROP_HEIGHT	(1440)
> +#define DEFAULT_PREVIEW_VIDEO_WIDTH		(640)
> +#define DEFAULT_PREVIEW_VIDEO_HEIGHT		(480)

Please remove unnecessary parentheses.

> +static void *fw_cookie;
> +static void *shot_cookie;

Can't these be embedded into some driver private data structure ?

> +/* Init params for pipeline devices */
> +static const struct sensor_param init_sensor_param = {
> +	.frame_rate = {
> +		.frame_rate = 30,
> +	},
> +};
> +
> +static const struct isp_param init_isp_param = {
> +	.control = {
> +		.cmd = CONTROL_COMMAND_START,
> +		.bypass = CONTROL_BYPASS_DISABLE,
> +		.err = CONTROL_ERROR_NONE,
> +	},
> +	.otf_input = {
> +		.cmd = OTF_INPUT_COMMAND_DISABLE,
> +		.width = DEFAULT_CAPTURE_STILL_WIDTH,
> +		.height = DEFAULT_CAPTURE_STILL_HEIGHT,
> +		.format = OTF_INPUT_FORMAT_BAYER,
> +		.bitwidth = OTF_INPUT_BIT_WIDTH_10BIT,
> +		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
> +		.crop_offset_x = 0,
> +		.crop_offset_y = 0,
> +		.crop_width = 0,
> +		.crop_height = 0,
> +		.frametime_min = 0,
> +		.frametime_max = 33333,
> +		.err = OTF_INPUT_ERROR_NONE,
> +	},
> +	.dma1_input = {
> +		.cmd = DMA_INPUT_COMMAND_DISABLE,
> +		.width = 0,
> +		.height = 0,
> +		.format = 0,
> +		.bitwidth = 0,
> +		.plane = 0,
> +		.order = 0,
> +		.buffer_number = 0,
> +		.buffer_address = 0,
> +		.err = 0,
> +	},
> +	.dma2_input = {
> +		.cmd = DMA_INPUT_COMMAND_DISABLE,
> +		.width = 0, .height = 0,
> +		.format = 0, .bitwidth = 0, .plane = 0,
> +		.order = 0, .buffer_number = 0, .buffer_address = 0,
> +		.err = 0,
> +	},
> +	.aa = {
> +		.cmd = ISP_AA_COMMAND_START,
> +		.target = ISP_AA_TARGET_AF | ISP_AA_TARGET_AE |
> +						ISP_AA_TARGET_AWB,
> +		.mode = ISP_AF_CONTINUOUS,
> +		.scene = 0,
> +		.sleep = 0,
> +		.af_face = 0,
> +		.touch_x = 0, .touch_y = 0,
> +		.manual_af_setting = 0,
> +		.err = ISP_AF_ERROR_NONE,
> +	},
> +	.flash = {
> +		.cmd = ISP_FLASH_COMMAND_DISABLE,
> +		.redeye = ISP_FLASH_REDEYE_DISABLE,
> +		.err = ISP_FLASH_ERROR_NONE,
> +	},
> +	.awb = {
> +		.cmd = ISP_AWB_COMMAND_AUTO,
> +		.illumination = 0,
> +		.err = ISP_AWB_ERROR_NONE,
> +	},
> +	.effect = {
> +		.cmd = ISP_IMAGE_EFFECT_DISABLE,
> +		.err = ISP_IMAGE_EFFECT_ERROR_NONE,
> +	},
> +	.iso = {
> +		.cmd = ISP_ISO_COMMAND_AUTO,
> +		.value = 0,
> +		.err = ISP_ISO_ERROR_NONE,
> +	},
> +	.adjust = {
> +		.cmd = ISP_ADJUST_COMMAND_AUTO,
> +		.contrast = 0,
> +		.saturation = 0,
> +		.sharpness = 0,
> +		.exposure = 0,
> +		.brightness = 0,
> +		.hue = 0,
> +		.err = ISP_ADJUST_ERROR_NONE,
> +	},
> +	.metering = {
> +		.cmd = ISP_METERING_COMMAND_CENTER,
> +		.win_pos_x = 0, .win_pos_y = 0,
> +		.win_width = DEFAULT_CAPTURE_STILL_WIDTH,
> +		.win_height = DEFAULT_CAPTURE_STILL_HEIGHT,
> +		.err = ISP_METERING_ERROR_NONE,
> +	},
> +	.afc = {
> +		.cmd = ISP_AFC_COMMAND_AUTO,
> +		.manual = 0, .err = ISP_AFC_ERROR_NONE,
> +	},
> +	.otf_output = {
> +		.cmd = OTF_OUTPUT_COMMAND_ENABLE,
> +		.width = DEFAULT_CAPTURE_STILL_WIDTH,
> +		.height = DEFAULT_CAPTURE_STILL_HEIGHT,
> +		.format = OTF_OUTPUT_FORMAT_YUV444,
> +		.bitwidth = OTF_OUTPUT_BIT_WIDTH_12BIT,
> +		.order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
> +		.crop_offset_x = 0,
> +		.crop_offset_y = 0,
> +		.err = OTF_OUTPUT_ERROR_NONE,
> +	},
> +	.dma1_output = {
> +		.cmd = DMA_OUTPUT_COMMAND_DISABLE,
> +		.dma_out_mask = 0,
> +		.width = DEFAULT_CAPTURE_STILL_WIDTH,
> +		.height = DEFAULT_CAPTURE_STILL_HEIGHT,
> +		.format = DMA_INPUT_FORMAT_YUV444,
> +		.bitwidth = DMA_INPUT_BIT_WIDTH_8BIT,
> +		.plane = DMA_INPUT_PLANE_1,
> +		.order = DMA_INPUT_ORDER_YCBCR,
> +		.buffer_number = 0,
> +		.buffer_address = 0,
> +		.err = DMA_OUTPUT_ERROR_NONE,
> +	},
> +	.dma2_output = {
> +		.cmd = DMA_OUTPUT_COMMAND_DISABLE,
> +		.width = DEFAULT_CAPTURE_STILL_WIDTH,
> +		.height = DEFAULT_CAPTURE_STILL_HEIGHT,
> +		.format = DMA_OUTPUT_FORMAT_BAYER,
> +		.bitwidth = DMA_OUTPUT_BIT_WIDTH_12BIT,
> +		.plane = DMA_OUTPUT_PLANE_1,
> +		.order = DMA_OUTPUT_ORDER_GB_BG,
> +		.buffer_number = 0,
> +		.buffer_address = 0,
> +		.dma_out_mask = 0xFFFFFFFF,
> +		.err = DMA_OUTPUT_ERROR_NONE,
> +	},
> +};
> +
> +static const struct drc_param init_drc_param = {
> +	.control = {
> +		.cmd = CONTROL_COMMAND_START,
> +		.bypass = CONTROL_BYPASS_ENABLE,
> +		.err = CONTROL_ERROR_NONE,
> +	},
> +	.otf_input = {
> +		.cmd = OTF_INPUT_COMMAND_ENABLE,
> +		.width = DEFAULT_CAPTURE_STILL_WIDTH,
> +		.height = DEFAULT_CAPTURE_STILL_HEIGHT,
> +		.format = OTF_INPUT_FORMAT_YUV444,
> +		.bitwidth = OTF_INPUT_BIT_WIDTH_12BIT,
> +		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
> +		.err = OTF_INPUT_ERROR_NONE,
> +	},
> +	.dma_input = {
> +		.cmd = DMA_INPUT_COMMAND_DISABLE,
> +		.width = DEFAULT_CAPTURE_STILL_WIDTH,
> +		.height = DEFAULT_CAPTURE_STILL_HEIGHT,
> +		.format = DMA_INPUT_FORMAT_YUV444,
> +		.bitwidth = DMA_INPUT_BIT_WIDTH_8BIT,
> +		.plane = DMA_INPUT_PLANE_1,
> +		.order = DMA_INPUT_ORDER_YCBCR,
> +		.buffer_number = 0,
> +		.buffer_address = 0,
> +		.err = 0,
> +	},
> +	.otf_output = {
> +		.cmd = OTF_OUTPUT_COMMAND_ENABLE,
> +		.width = DEFAULT_CAPTURE_STILL_WIDTH,
> +		.height = DEFAULT_CAPTURE_STILL_HEIGHT,
> +		.format = OTF_OUTPUT_FORMAT_YUV444,
> +		.bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
> +		.order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
> +		.crop_offset_x = 0,
> +		.crop_offset_y = 0,
> +		.err = OTF_OUTPUT_ERROR_NONE,
> +	},
> +};
> +
> +static const struct scalerc_param init_scalerc_param = {
> +	.control = {
> +		.cmd = CONTROL_COMMAND_START,
> +		.bypass = CONTROL_BYPASS_ENABLE,
> +		.err = CONTROL_ERROR_NONE,
> +	},
> +	.otf_input = {
> +		.cmd = OTF_INPUT_COMMAND_ENABLE,
> +		.width = DEFAULT_CAPTURE_STILL_WIDTH,
> +		.height = DEFAULT_CAPTURE_STILL_HEIGHT,
> +		.format = OTF_INPUT_FORMAT_YUV444,
> +		.bitwidth = OTF_INPUT_BIT_WIDTH_12BIT,
> +		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
> +		.crop_offset_x = 0,
> +		.crop_offset_y = 0,
> +		.crop_width = 0,
> +		.crop_height = 0,
> +		.err = OTF_INPUT_ERROR_NONE,
> +	},
> +	.effect = {
> +		.cmd = 0,
> +		.err = 0,
> +	},
> +	.input_crop = {
> +		.cmd = OTF_INPUT_COMMAND_ENABLE,
> +		.pos_x = 0,
> +		.pos_y = 0,
> +		.crop_width = DEFAULT_CAPTURE_STILL_CROP_WIDTH,
> +		.crop_height = DEFAULT_CAPTURE_STILL_CROP_HEIGHT,
> +		.in_width = DEFAULT_CAPTURE_STILL_WIDTH,
> +		.in_height = DEFAULT_CAPTURE_STILL_HEIGHT,
> +		.out_width = DEFAULT_CAPTURE_VIDEO_WIDTH,
> +		.out_height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
> +		.err = 0,
> +	},
> +	.output_crop = {
> +		.cmd = SCALER_CROP_COMMAND_DISABLE,
> +		.pos_x = 0,
> +		.pos_y = 0,
> +		.crop_width = DEFAULT_CAPTURE_STILL_WIDTH,
> +		.crop_height = DEFAULT_CAPTURE_STILL_HEIGHT,
> +		.format = DMA_OUTPUT_FORMAT_YUV420,
> +		.err = 0,
> +	},
> +	.otf_output = {
> +		.cmd = OTF_OUTPUT_COMMAND_ENABLE,
> +		.width = DEFAULT_CAPTURE_VIDEO_WIDTH,
> +		.height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
> +		.format = OTF_OUTPUT_FORMAT_YUV444,
> +		.bitwidth = OTF_OUTPUT_BIT_WIDTH_8BIT,
> +		.order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
> +		.crop_offset_x = 0,
> +		.crop_offset_y = 0,
> +		.err = OTF_OUTPUT_ERROR_NONE,
> +	},
> +	.dma_output = {
> +		.cmd = DMA_OUTPUT_COMMAND_DISABLE,
> +		.width = DEFAULT_CAPTURE_STILL_WIDTH,
> +		.height = DEFAULT_CAPTURE_STILL_HEIGHT,
> +		.format = DMA_OUTPUT_FORMAT_YUV420,
> +		.bitwidth = DMA_OUTPUT_BIT_WIDTH_8BIT,
> +		.plane = DMA_OUTPUT_PLANE_3,
> +		.order = DMA_OUTPUT_ORDER_NONE,
> +		.buffer_number = 0,
> +		.buffer_address = 0,
> +		.dma_out_mask = 0xffff,
> +		.err = DMA_OUTPUT_ERROR_NONE,
> +	},
> +};
> +
> +static const struct odc_param init_odc_param = {
> +	.control = {
> +		.cmd = CONTROL_COMMAND_START,
> +		.bypass = CONTROL_BYPASS_ENABLE,
> +		.err = CONTROL_ERROR_NONE,
> +	},
> +	.otf_input = {
> +		.cmd = OTF_INPUT_COMMAND_ENABLE,
> +		.width = DEFAULT_CAPTURE_VIDEO_WIDTH,
> +		.height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
> +		.format = OTF_INPUT_FORMAT_YUV444,
> +		.bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
> +		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
> +		.crop_offset_x = 0,
> +		.crop_offset_y = 0,
> +		.crop_width = 0,
> +		.crop_height = 0,
> +		.err = OTF_INPUT_ERROR_NONE,
> +	},
> +	.otf_output = {
> +		.cmd = OTF_OUTPUT_COMMAND_ENABLE,
> +		.width = DEFAULT_CAPTURE_VIDEO_WIDTH,
> +		.height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
> +		.format = OTF_OUTPUT_FORMAT_YUV422,
> +		.bitwidth = OTF_OUTPUT_BIT_WIDTH_8BIT,
> +		.order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
> +		.crop_offset_x = 0,
> +		.crop_offset_y = 0,
> +		.err = OTF_OUTPUT_ERROR_NONE,
> +	},
> +};
> +
> +static const struct dis_param init_dis_param = {
> +	.control = {
> +		.cmd = CONTROL_COMMAND_START,
> +		.bypass = CONTROL_BYPASS_ENABLE,
> +		.err = CONTROL_ERROR_NONE,
> +	},
> +	.otf_input = {
> +		.cmd = OTF_INPUT_COMMAND_ENABLE,
> +		.width = DEFAULT_CAPTURE_VIDEO_WIDTH,
> +		.height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
> +		.format = OTF_INPUT_FORMAT_YUV422,
> +		.bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
> +		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
> +		.crop_offset_x = 0,
> +		.crop_offset_y = 0,
> +		.crop_width = 0,
> +		.crop_height = 0,
> +		.err = OTF_INPUT_ERROR_NONE,
> +	},
> +	.otf_output = {
> +		.cmd = OTF_OUTPUT_COMMAND_ENABLE,
> +		.width = DEFAULT_CAPTURE_VIDEO_WIDTH,
> +		.height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
> +		.format = OTF_OUTPUT_FORMAT_YUV422,
> +		.bitwidth = OTF_OUTPUT_BIT_WIDTH_8BIT,
> +		.order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
> +		.crop_offset_x = 0,
> +		.crop_offset_y = 0,
> +		.err = OTF_OUTPUT_ERROR_NONE,
> +	},
> +};
> +static const struct tdnr_param init_tdnr_param = {
> +	.control = {
> +		.cmd = CONTROL_COMMAND_START,
> +		.bypass = CONTROL_BYPASS_ENABLE,
> +		.err = CONTROL_ERROR_NONE,
> +	},
> +	.otf_input = {
> +		.cmd = OTF_INPUT_COMMAND_ENABLE,
> +		.width = DEFAULT_CAPTURE_VIDEO_WIDTH,
> +		.height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
> +		.format = OTF_INPUT_FORMAT_YUV422,
> +		.bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
> +		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
> +		.err = OTF_INPUT_ERROR_NONE,
> +	},
> +	.frame = {
> +		.cmd = 0,
> +		.err = 0,
> +	},
> +	.otf_output = {
> +		.cmd = OTF_OUTPUT_COMMAND_ENABLE,
> +		.width = DEFAULT_CAPTURE_VIDEO_WIDTH,
> +		.height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
> +		.format = OTF_OUTPUT_FORMAT_YUV444,
> +		.bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
> +		.order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
> +		.crop_offset_x = 0,
> +		.crop_offset_y = 0,
> +		.err = OTF_OUTPUT_ERROR_NONE,
> +	},
> +	.dma_output = {
> +		.cmd = DMA_OUTPUT_COMMAND_DISABLE,
> +		.width = DEFAULT_CAPTURE_VIDEO_WIDTH,
> +		.height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
> +		.format = DMA_OUTPUT_FORMAT_YUV420,
> +		.bitwidth = DMA_OUTPUT_BIT_WIDTH_8BIT,
> +		.plane = DMA_OUTPUT_PLANE_2,
> +		.order = DMA_OUTPUT_ORDER_CBCR,
> +		.buffer_number = 0,
> +		.buffer_address = 0,
> +		.dma_out_mask = 0xffff,
> +		.err = DMA_OUTPUT_ERROR_NONE,
> +	},
> +};
> +
> +static const struct scalerp_param init_scalerp_param = {
> +	.control = {
> +		.cmd = CONTROL_COMMAND_START,
> +		.bypass = CONTROL_BYPASS_ENABLE,
> +		.err = CONTROL_ERROR_NONE,
> +	},
> +	.otf_input = {
> +		.cmd = OTF_INPUT_COMMAND_ENABLE,
> +		.width = DEFAULT_CAPTURE_VIDEO_WIDTH,
> +		.height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
> +		.format = OTF_INPUT_FORMAT_YUV444,
> +		.bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
> +		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
> +		.crop_offset_x = 0,
> +		.crop_offset_y = 0,
> +		.crop_width = 0,
> +		.crop_height = 0,
> +		.err = OTF_INPUT_ERROR_NONE,
> +	},
> +	.effect = {
> +		.cmd = 0,
> +		.err = 0,
> +	},
> +	.input_crop = {
> +		.cmd = OTF_INPUT_COMMAND_ENABLE,
> +		.pos_x = 0,
> +		.pos_y = 0,
> +		.crop_width = DEFAULT_CAPTURE_VIDEO_WIDTH,
> +		.crop_height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
> +		.in_width = DEFAULT_CAPTURE_VIDEO_WIDTH,
> +		.in_height = DEFAULT_CAPTURE_VIDEO_HEIGHT,
> +		.out_width = DEFAULT_PREVIEW_STILL_WIDTH,
> +		.out_height = DEFAULT_PREVIEW_STILL_HEIGHT,
> +		.err = 0,
> +	},
> +	.output_crop = {
> +		.cmd = SCALER_CROP_COMMAND_DISABLE,
> +		.pos_x = 0,
> +		.pos_y = 0,
> +		.crop_width = DEFAULT_PREVIEW_STILL_WIDTH,
> +		.crop_height = DEFAULT_PREVIEW_STILL_HEIGHT,
> +		.format = OTF_OUTPUT_FORMAT_YUV420,
> +		.err = 0,
> +	},
> +	.rotation = {
> +		.cmd = 0,
> +		.err = 0,
> +	},
> +	.flip = {
> +		.cmd = 0,
> +		.err = 0,
> +	},
> +	.otf_output = {
> +		.cmd = OTF_OUTPUT_COMMAND_ENABLE,
> +		.width = DEFAULT_PREVIEW_STILL_WIDTH,
> +		.height = DEFAULT_PREVIEW_STILL_HEIGHT,
> +		.format = OTF_INPUT_FORMAT_YUV444,
> +		.bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
> +		.order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
> +		.crop_offset_x = 0,
> +		.crop_offset_y = 0,
> +		.err = OTF_OUTPUT_ERROR_NONE,
> +	},
> +	.dma_output = {
> +		.cmd = DMA_OUTPUT_COMMAND_DISABLE,
> +		.width = DEFAULT_PREVIEW_STILL_WIDTH,
> +		.height = DEFAULT_PREVIEW_STILL_HEIGHT,
> +		.format = OTF_OUTPUT_FORMAT_YUV420,
> +		.bitwidth = DMA_OUTPUT_BIT_WIDTH_8BIT,
> +		.plane = DMA_OUTPUT_PLANE_3,
> +		.order = DMA_OUTPUT_ORDER_NONE,
> +		.buffer_number = 0,
> +		.buffer_address = 0,
> +		.dma_out_mask = 0xffff,
> +		.err = DMA_OUTPUT_ERROR_NONE,
> +	},
> +};
> +
> +static const struct fd_param init_fd_param = {
> +	.control = {
> +		.cmd = CONTROL_COMMAND_STOP,
> +		.bypass = CONTROL_BYPASS_DISABLE,
> +		.err = CONTROL_ERROR_NONE,
> +	},
> +	.otf_input = {
> +		.cmd = OTF_INPUT_COMMAND_ENABLE,
> +		.width = DEFAULT_PREVIEW_STILL_WIDTH,
> +		.height = DEFAULT_PREVIEW_STILL_HEIGHT,
> +		.format = OTF_INPUT_FORMAT_YUV444,
> +		.bitwidth = OTF_INPUT_BIT_WIDTH_8BIT,
> +		.order = OTF_INPUT_ORDER_BAYER_GR_BG,
> +		.err = OTF_INPUT_ERROR_NONE,
> +	},
> +	.dma_input = {
> +		.cmd = DMA_INPUT_COMMAND_DISABLE,
> +		.width = 0, .height = 0,
> +		.format = 0, .bitwidth = 0, .plane = 0,
> +		.order = 0, .buffer_number = 0, .buffer_address = 0,
> +		.err = 0,
> +	},
> +	.config = {
> +		.cmd = FD_CONFIG_COMMAND_MAXIMUM_NUMBER |
> +			FD_CONFIG_COMMAND_ROLL_ANGLE |
> +			FD_CONFIG_COMMAND_YAW_ANGLE |
> +			FD_CONFIG_COMMAND_SMILE_MODE |
> +			FD_CONFIG_COMMAND_BLINK_MODE |
> +			FD_CONFIG_COMMAND_EYES_DETECT |
> +			FD_CONFIG_COMMAND_MOUTH_DETECT |
> +			FD_CONFIG_COMMAND_ORIENTATION |
> +			FD_CONFIG_COMMAND_ORIENTATION_VALUE,
> +		.max_number = CAMERA2_MAX_FACES,
> +		.roll_angle = FD_CONFIG_ROLL_ANGLE_FULL,
> +		.yaw_angle = FD_CONFIG_YAW_ANGLE_45_90,
> +		.smile_mode = FD_CONFIG_SMILE_MODE_DISABLE,
> +		.blink_mode = FD_CONFIG_BLINK_MODE_DISABLE,
> +		.eye_detect = FD_CONFIG_EYES_DETECT_ENABLE,
> +		.mouth_detect = FD_CONFIG_MOUTH_DETECT_DISABLE,
> +		.orientation = FD_CONFIG_ORIENTATION_DISABLE,
> +		.orientation_value = 0,
> +		.err = ERROR_FD_NONE,
> +	},
> +};

How about removing all explicit initializations to 0, perhaps including
*_ERROR_NONE etc. Static variables are implicitly initialized to 0.
What do you think ? This driver is really _huge_ and I don't want to see
any unnecessary code packed into it.

> +static int fimc_is_pipeline_create_subdevs(struct fimc_is_pipeline *pipeline)
> +{
> +	struct fimc_is *is = pipeline->is;
> +	int ret;
> +
> +	/* ISP */
> +	ret = fimc_is_isp_subdev_create(&pipeline->isp,
> +			is->alloc_ctx, pipeline);
> +	if (ret<  0)
> +		return ret;
> +
> +	/* SCC scaler */
> +	ret = fimc_is_scaler_subdev_create(&pipeline->scaler[SCALER_SCC],
> +			SCALER_SCC, is->alloc_ctx, pipeline);
> +	if (ret<  0)
> +		return ret;
> +
> +	/* SCP scaler */
> +	ret = fimc_is_scaler_subdev_create(&pipeline->scaler[SCALER_SCP],
> +			SCALER_SCP, is->alloc_ctx, pipeline);
> +	if (ret<  0)
> +		return ret;
> +
> +	return ret;
> +}
> +
> +static int fimc_is_pipeline_unregister_subdevs(struct fimc_is_pipeline *p)
> +{
> +	fimc_is_isp_subdev_destroy(&p->isp);
> +	fimc_is_scaler_subdev_destroy(&p->scaler[SCALER_SCC]);
> +	fimc_is_scaler_subdev_destroy(&p->scaler[SCALER_SCP]);
> +
> +	return 0;
> +}
> +
> +int fimc_is_pipeline_init(struct fimc_is_pipeline *pipeline,
> +			unsigned int instance, void *is_ctx)
> +{
> +	struct fimc_is *is = is_ctx;
> +	unsigned int i;
> +	int ret;
> +
> +	if (test_bit(PIPELINE_INIT,&pipeline->state)) {
> +		pr_debug("Pipeline init already done.\n");
> +		return -EINVAL;
> +	}
> +
> +	/* Initialize context variables */
> +	pipeline->instance = instance;
> +	pipeline->is = is;
> +	pipeline->minfo =&is->minfo;
> +	pipeline->state = 0;
> +	pipeline->force_down = false;
> +	for (i = 0; i<  FIMC_IS_NUM_COMPS; i++)
> +		pipeline->comp_state[i] = 0;
> +
> +	spin_lock_init(&pipeline->slock_buf);
> +	init_waitqueue_head(&pipeline->wait_q);
> +	mutex_init(&pipeline->pipe_lock);
> +	mutex_init(&pipeline->pipe_scl_lock);
> +
> +	ret = fimc_is_pipeline_create_subdevs(pipeline);
> +	if (ret) {
> +		pr_err("Subdev creation failed\n");
> +		return -EINVAL;
> +	}
> +
> +	/* Setting default width&  height for scc&  scp */
> +	pipeline->scaler_width[SCALER_SCC] = DEFAULT_CAPTURE_VIDEO_WIDTH;
> +	pipeline->scaler_height[SCALER_SCC] = DEFAULT_CAPTURE_VIDEO_HEIGHT;
> +	pipeline->scaler_width[SCALER_SCP] = DEFAULT_PREVIEW_VIDEO_WIDTH;
> +	pipeline->scaler_height[SCALER_SCP] = DEFAULT_PREVIEW_VIDEO_HEIGHT;
> +
> +	set_bit(PIPELINE_INIT,&pipeline->state);
> +	return 0;
> +}
> +
> +int fimc_is_pipeline_destroy(struct fimc_is_pipeline *pipeline)
> +{
> +	if (!pipeline)
> +		return -EINVAL;
> +
> +	if (!test_bit(PIPELINE_INIT,&pipeline->state)) {
> +		pr_debug("Pipeline not inited.\n");

s/inited/initialized ?

> +		return -EINVAL;
> +	}
> +	return fimc_is_pipeline_unregister_subdevs(pipeline);
> +}
> +
> +static int fimc_is_pipeline_initmem(struct fimc_is_pipeline *pipeline,
> +		struct vb2_alloc_ctx *alloc_ctx)
> +{
> +	struct fimc_is_meminfo *minfo = pipeline->minfo;
> +	dma_addr_t *fw_phy_addr;
> +	unsigned int offset;
> +
> +	/* Allocate memory */
> +	pr_debug("Allocating memory : %d\n",
> +			FIMC_IS_A5_MEM_SIZE + FIMC_IS_A5_SEN_SIZE);
> +	fw_cookie = vb2_dma_contig_memops.alloc(alloc_ctx,
> +			FIMC_IS_A5_MEM_SIZE + FIMC_IS_A5_SEN_SIZE,
> +			GFP_KERNEL);
> +
> +	if (IS_ERR(fw_cookie)) {
> +		pr_err("Error in allocating FW memory.\n");

dev_err()

> +		return -ENOMEM;
> +	}
> +
> +	fw_phy_addr = vb2_dma_contig_memops.cookie(fw_cookie);
> +	/* FW memory should be 64MB aligned */
> +	if (*fw_phy_addr&  FIMC_IS_FW_BASE_MASK) {
> +		pr_err("FW memory not 64MB aligned.\n");

dev_err()

> +		vb2_dma_contig_memops.put(fw_cookie);
> +		return -EIO;
> +	}
> +	minfo->fw_paddr = *fw_phy_addr;
> +
> +	minfo->fw_vaddr =
> +		(unsigned int) vb2_dma_contig_memops.vaddr(fw_cookie);
> +
> +	pr_debug("FW |Phy Addr : 0x%08x, Virt Addr : 0x%08x\n",
> +			minfo->fw_paddr, minfo->fw_vaddr);
> +
> +	/* Assigning memory regions */
> +	offset = FIMC_IS_A5_MEM_SIZE - FIMC_IS_REGION_SIZE;
> +	minfo->region_paddr = minfo->fw_paddr + offset;
> +	minfo->region_vaddr = minfo->fw_vaddr + offset;
> +	pipeline->is_region = (struct is_region *)minfo->region_vaddr;
> +
> +	minfo->shared_paddr = minfo->fw_paddr +
> +		((unsigned int)&pipeline->is_region->shared[0] -
> +		 minfo->fw_vaddr);
> +	minfo->shared_vaddr = minfo->fw_vaddr +
> +		((unsigned int)&pipeline->is_region->shared[0] -
> +		 minfo->fw_vaddr);
> +
> +	/* Allocate shot buffer */
> +	shot_cookie = vb2_dma_contig_memops.alloc(alloc_ctx,
> +			sizeof(struct camera2_shot), GFP_KERNEL);
> +	if (IS_ERR(shot_cookie)) {
> +		pr_err("Error in allocating temp memory.\n");

dev_err()

> +		return -ENOMEM;
> +	}
> +	fw_phy_addr = vb2_dma_contig_memops.cookie(shot_cookie);
> +	pipeline->shot_paddr = *fw_phy_addr;
> +	pipeline->shot_vaddr =
> +		(unsigned int) vb2_dma_contig_memops.vaddr(shot_cookie);

Hmm, can't you use dma_alloc_coherent() for those 2 memory regions, like
exynos4-is does ? See function fimc_is_alloc_cpu_memory() in drivers/media/
exynos4-is/fimc-is.c. What is "shot" memory region used for ? Does it need
to come from same allocator as the video buffers ?

> +	return 0;
> +}
> +
> +static void fimc_is_pipeline_freemem(struct fimc_is_pipeline *pipeline)
> +{
> +	if (fw_cookie)
> +		vb2_dma_contig_memops.put(fw_cookie);
> +	if (shot_cookie)
> +		vb2_dma_contig_memops.put(shot_cookie);
> +}
> +
> +static int fimc_is_pipeline_load_firmware(struct fimc_is_pipeline *pipeline)
> +{
> +	struct firmware *fw_blob;
> +	struct fimc_is *is = pipeline->is;
> +	int ret;
> +
> +	ret = request_firmware((const struct firmware **)&fw_blob,

Why such casting ? Just add 'const' qualifier at the above fw_blob
declaration and remove the casting.

> +			"fimc-is-fw.bin",&is->pdev->dev);

No, please add a macro definition for the firmware name. And it should be
something like "exynos5_fimc_is_fw.bin", to not confuse it with exynos4
fimc-is firmware file (which is exynos4_fimc_is_fw.bin).

> +	if (ret != 0) {
> +		pr_err("Firmware file not found\n");
> +		return -EINVAL;
> +	}
> +	pr_debug("Firmware size : %d\n", fw_blob->size);

dev_dbg() ?

> +	if (fw_blob->size>  FIMC_IS_A5_MEM_SIZE + FIMC_IS_A5_SEN_SIZE) {
> +		pr_err("Firmware file too big.\n");

dev_err()

> +		release_firmware(fw_blob);
> +		return -ENOMEM;
> +	}
> +
> +	memcpy((void *)pipeline->minfo->fw_vaddr, fw_blob->data, fw_blob->size);

Unnecessary casting to void *.

> +	wmb();
> +	release_firmware(fw_blob);
> +
> +	return 0;
> +}
> +
> +static void fimc_is_pipeline_forcedown(struct fimc_is_pipeline *pipeline,
> +		bool on)
> +{
> +	struct fimc_is *is = pipeline->is;
> +	if (on) {
> +		pr_debug("Set low poweroff mode\n");
> +		pmu_is_write(0x0, is, PMUREG_ISP_ARM_OPTION);
> +		pmu_is_write(0x1CF82000, is, PMUREG_ISP_LOW_POWER_OFF);

> +		pipeline->force_down = true;
> +	} else {
> +		pr_debug("Clear low poweroff mode\n");
> +		pmu_is_write(0xFFFFFFFF, is, PMUREG_ISP_ARM_OPTION);

Please make hex numbers lower case.

> +		pmu_is_write(0x8, is, PMUREG_ISP_LOW_POWER_OFF);
> +		pipeline->force_down = false;
> +	}
> +}
> +
> +static int fimc_is_pipeline_power(struct fimc_is_pipeline *pipeline, int on)
> +{
> +	int ret = 0;
> +	u32 timeout;
> +	struct fimc_is *is = pipeline->is;
> +	struct device *dev =&is->pdev->dev;
> +
> +	if (on) {
> +		/* force poweroff setting */
> +		if (pipeline->force_down)
> +			fimc_is_pipeline_forcedown(pipeline, false);
> +
> +		/* FIMC-IS local power enable */
> +		ret = pm_runtime_get_sync(dev);

No need to check return value ?

> +		/* A5 start address setting */
> +		writel(pipeline->minfo->fw_paddr, is->interface.regs + BBOAR);
> +
> +		/* A5 power on*/
> +		pmu_is_write(0x1, is, PMUREG_ISP_ARM_CONFIGURATION);
> +
> +		/* enable A5 */
> +		pmu_is_write(0x00018000, is, PMUREG_ISP_ARM_OPTION);
> +		timeout = 1000;
> +		while ((pmu_is_read(is, PMUREG_ISP_ARM_STATUS)&  0x1) != 0x1) {
> +			if (timeout == 0)
> +				pr_err("A5 power on failed\n");

dev_err()

> +			timeout--;
> +			udelay(1);
> +		}
> +	} else {
> +		/* disable A5 */
> +		pmu_is_write(0x10000, is, PMUREG_ISP_ARM_OPTION);
> +		/* A5 power off*/
> +		pmu_is_write(0x0, is, PMUREG_ISP_ARM_CONFIGURATION);
> +
> +		/* Check A5 power off status register */
> +		timeout = 1000;
> +		while (pmu_is_read(is, PMUREG_ISP_ARM_STATUS)&  0x1) {
> +			if (timeout == 0) {
> +				pr_err("A5 power off failed\n");

dev_err()

> +				fimc_is_pipeline_forcedown(pipeline, true);
> +			}
> +			timeout--;
> +			udelay(1);
> +		}
> +
> +		pmu_is_write(0x0, is, PMUREG_CMU_RESET_ISP_SYS_PWR_REG);
> +
> +		/* FIMC-IS local power down */
> +		pm_runtime_put_sync(dev);
> +	}
> +
> +	return ret;
> +}
> +
> +static int fimc_is_pipeline_load_setfile(struct fimc_is_pipeline *pipeline,
> +		unsigned int setfile_addr,
> +		unsigned char *setfile_name)
> +{
> +	struct fimc_is *is = pipeline->is;
> +	struct firmware *fw_blob;
> +	int ret;
> +
> +	ret = request_firmware((const struct firmware **)&fw_blob,

Again, casting ugliness.

> +			setfile_name,&is->pdev->dev);
> +	if (ret != 0) {
> +		pr_err("Setfile %s not found\n", setfile_name);

dev_err(), please. I'm a bit tired of commenting on this excessive pr_*
usage. Please really make sure dev_err()/v4l2_err() is used where possible.

> +		return -EINVAL;
> +	}
> +
> +	memcpy((void *)pipeline->minfo->fw_vaddr + setfile_addr,

That casting just doesn't make sense. pipeline->minfo->fw_vaddr and
setfile_addr are both of unsigned int type and you don't need to cast
to void *.

> +			fw_blob->data, fw_blob->size);
> +	wmb();
> +	release_firmware(fw_blob);
> +
> +	return 0;
> +}
> +
> +static int fimc_is_pipeline_setfile(struct fimc_is_pipeline *pipeline)
> +{
> +	struct fimc_is *is = pipeline->is;
> +	struct fimc_is_sensor *sensor = pipeline->sensor;
> +	int ret;
> +	unsigned int setfile_addr;
> +
> +	/* Get setfile addr from HW */
> +	ret = fimc_is_itf_get_setfile_addr(&is->interface,
> +			pipeline->instance,&setfile_addr);
> +	if (ret<  0) {
> +		pr_err("Get setfile addr failed.\n");

dev_err()

> +		return ret;
> +	}
> +
> +	if (!sensor->drvdata->setfile_name)
> +		return -EINVAL;
> +
> +	/* Load setfile */
> +	ret = fimc_is_pipeline_load_setfile(pipeline, setfile_addr,
> +			sensor->drvdata->setfile_name);
> +	if (ret<  0) {
> +		pr_err("Load setfile failed.\n");

dev_err()

> +		return ret;
> +	}
> +
> +	/* Send HW command */
> +	ret = fimc_is_itf_load_setfile(&is->interface, pipeline->instance);
> +	if (ret<  0) {
> +		pr_err("HW Load setfile failed.\n");

dev_err()

> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static int fimc_is_pipeline_isp_setparams(struct fimc_is_pipeline *pipeline,
> +		unsigned int enable)
> +{
> +	struct isp_param *isp_param =&pipeline->is_region->parameter.isp;
> +	struct fimc_is *is = pipeline->is;
> +	unsigned int indexes, lindex, hindex;
> +	unsigned int sensor_width, sensor_height, scc_width, scc_height;
> +	unsigned int crop_x, crop_y, isp_width, isp_height;
> +	unsigned int sensor_ratio, output_ratio;
> +	int ret;
> +
> +	/* Crop calculation */
> +	sensor_width = pipeline->sensor_width;
> +	sensor_height = pipeline->sensor_height;
> +	scc_width = pipeline->scaler_width[SCALER_SCC];
> +	scc_height = pipeline->scaler_height[SCALER_SCC];
> +	isp_width = sensor_width;
> +	isp_height = sensor_height;
> +	crop_x = crop_y = 0;
> +
> +	sensor_ratio = sensor_width * 1000 / sensor_height;
> +	output_ratio = scc_width * 1000 / scc_height;
> +
> +	if (sensor_ratio == output_ratio) {
> +		isp_width = sensor_width;
> +		isp_height = sensor_height;
> +	} else if (sensor_ratio<  output_ratio) {
> +		isp_height = (sensor_width * scc_height) / scc_width;
> +		isp_height = ALIGN(isp_height, 2);
> +		crop_y = ((sensor_height - isp_height)>>  1)&  0xFFFFFFFE;

nit: Use ~1U instead of 0xFFFFFFFE.


> +	} else {
> +		isp_width = (sensor_height * scc_width) / scc_height;
> +		isp_width = ALIGN(isp_width, 4);
> +		crop_x =  ((sensor_width - isp_width)>>  1)&  0xFFFFFFFE;

Ditto.

> +	}
> +	pipeline->isp_width = isp_width;
> +	pipeline->isp_height = isp_height;
> +
> +	indexes = hindex = lindex = 0;
> +
> +	isp_param->otf_output.cmd = OTF_OUTPUT_COMMAND_ENABLE;
> +	isp_param->otf_output.width = pipeline->sensor_width;
> +	isp_param->otf_output.height = pipeline->sensor_height;
> +	isp_param->otf_output.format = OTF_OUTPUT_FORMAT_YUV444;
> +	isp_param->otf_output.bitwidth = OTF_OUTPUT_BIT_WIDTH_12BIT;
> +	isp_param->otf_output.order = OTF_INPUT_ORDER_BAYER_GR_BG;
> +	lindex |= LOWBIT_OF(PARAM_ISP_OTF_OUTPUT);
> +	hindex |= HIGHBIT_OF(PARAM_ISP_OTF_OUTPUT);
> +	indexes++;

All right, let's stop this hindex/lindex/indexes madness. I've already
commented on that IIRC. Nevertheless, this should be replaced with proper
bitmap operations. A similar issue has been fixed in commit


> +	isp_param->dma1_output.cmd = DMA_OUTPUT_COMMAND_DISABLE;
> +	lindex |= LOWBIT_OF(PARAM_ISP_DMA1_OUTPUT);
> +	hindex |= HIGHBIT_OF(PARAM_ISP_DMA1_OUTPUT);
> +	indexes++;
> +
> +	isp_param->dma2_output.cmd = DMA_OUTPUT_COMMAND_DISABLE;
> +	lindex |= LOWBIT_OF(PARAM_ISP_DMA2_OUTPUT);
> +	hindex |= HIGHBIT_OF(PARAM_ISP_DMA2_OUTPUT);
> +	indexes++;
> +
> +	if (enable)
> +		isp_param->control.bypass = CONTROL_BYPASS_DISABLE;
> +	else
> +		isp_param->control.bypass = CONTROL_BYPASS_ENABLE;
> +	isp_param->control.cmd = CONTROL_COMMAND_START;
> +	isp_param->control.run_mode = 1;
> +	lindex |= LOWBIT_OF(PARAM_ISP_CONTROL);
> +	hindex |= HIGHBIT_OF(PARAM_ISP_CONTROL);
> +	indexes++;
> +
> +	isp_param->dma1_input.cmd = DMA_INPUT_COMMAND_BUF_MNGR;
> +	isp_param->dma1_input.width = sensor_width;
> +	isp_param->dma1_input.height = sensor_height;
> +	isp_param->dma1_input.dma_crop_offset_x = crop_x;
> +	isp_param->dma1_input.dma_crop_offset_y = crop_y;
> +	isp_param->dma1_input.dma_crop_width = isp_width;
> +	isp_param->dma1_input.dma_crop_height = isp_height;
> +	isp_param->dma1_input.bayer_crop_offset_x = 0;
> +	isp_param->dma1_input.bayer_crop_offset_y = 0;
> +	isp_param->dma1_input.bayer_crop_width = 0;
> +	isp_param->dma1_input.bayer_crop_height = 0;
> +	isp_param->dma1_input.user_min_frametime = 0;
> +	isp_param->dma1_input.user_max_frametime = 66666;
> +	isp_param->dma1_input.wide_frame_gap = 1;
> +	isp_param->dma1_input.frame_gap = 4096;
> +	isp_param->dma1_input.line_gap = 45;
> +	isp_param->dma1_input.order = DMA_INPUT_ORDER_GR_BG;
> +	isp_param->dma1_input.plane = 1;
> +	isp_param->dma1_input.buffer_number = 1;
> +	isp_param->dma1_input.buffer_address = 0;
> +	isp_param->dma1_input.reserved[1] = 0;
> +	isp_param->dma1_input.reserved[2] = 0;
> +	if (pipeline->isp.fmt->fourcc == V4L2_PIX_FMT_SGRBG8)
> +		isp_param->dma1_input.bitwidth = DMA_INPUT_BIT_WIDTH_8BIT;
> +	else if (pipeline->isp.fmt->fourcc == V4L2_PIX_FMT_SGRBG10)
> +		isp_param->dma1_input.bitwidth = DMA_INPUT_BIT_WIDTH_10BIT;
> +	else
> +		isp_param->dma1_input.bitwidth = DMA_INPUT_BIT_WIDTH_12BIT;
> +	lindex |= LOWBIT_OF(PARAM_ISP_DMA1_INPUT);
> +	hindex |= HIGHBIT_OF(PARAM_ISP_DMA1_INPUT);
> +	indexes++;
> +
> +	lindex = 0xFFFFFFFF;
> +	hindex = 0xFFFFFFFF;

Hmm, is this a workaround for some firmware bug ? You're setting individual
bits of lindex, hindex only to set them all to 1 just before using those
variables ? WTH ? :)


Anyway, instead of doing this:

	lindex |= LOWBIT_OF(A);
	hindex |= HIGHBIT_OF(A);
	indexes++;

	lindex |= LOWBIT_OF(B);
	hindex |= HIGHBIT_OF(B);
	indexes++;

	...

	fimc_is_itf_set_param(..., indexes, lindex, hindex);


You could do:

	u32 index[2];

	__set_bit(A, index);

	__set_bit(B, index);

	...

	indexes = hweight32(index[0]);
	indexes += hweight32(index[1]);

	fimc_is_itf_set_param(..., indexes, index[0], index[1]);

I.e. the bit operations work well with arbitrary length bitmaps.

BTW, the firmware interface seems pretty odd with it's requirement to
pass bitmask and number of bits set in this bitmaks separately. Does
it ever allow 'indexes' to be different than number of bits set in
lindex, hindex ? What happens in such case ?

> +	wmb();
> +	ret = fimc_is_itf_set_param(&is->interface, pipeline->instance,
> +			indexes, lindex, hindex);
> +	if (ret) {
> +		pr_err("fimc_is_itf_set_param failed\n");

dev_err()

> +		return -EINVAL;
> +	}
> +
> +	set_bit(COMP_ENABLE,&pipeline->comp_state[IS_ISP]);
> +
> +	return 0;
> +}
> +
> +static int fimc_is_pipeline_drc_setparams(struct fimc_is_pipeline *pipeline,
> +		unsigned int enable)
> +{
> +	struct drc_param *drc_param =&pipeline->is_region->parameter.drc;
> +	struct fimc_is *is = pipeline->is;
> +	int ret;
> +	unsigned int indexes, lindex, hindex;
> +
> +	indexes = hindex = lindex = 0;
> +	if (enable)
> +		drc_param->control.bypass = CONTROL_BYPASS_DISABLE;
> +	else
> +		drc_param->control.bypass = CONTROL_BYPASS_ENABLE;
> +	lindex |= LOWBIT_OF(PARAM_DRC_CONTROL);
> +	hindex |= HIGHBIT_OF(PARAM_DRC_CONTROL);
> +	indexes++;
> +
> +	drc_param->otf_input.cmd = OTF_INPUT_COMMAND_ENABLE;
> +	drc_param->otf_input.width = pipeline->isp_width;
> +	drc_param->otf_input.height = pipeline->isp_height;
> +	lindex |= LOWBIT_OF(PARAM_DRC_OTF_INPUT);
> +	hindex |= HIGHBIT_OF(PARAM_DRC_OTF_INPUT);
> +	indexes++;
> +
> +	drc_param->otf_output.cmd = OTF_OUTPUT_COMMAND_ENABLE;
> +	drc_param->otf_output.width = pipeline->isp_width;
> +	drc_param->otf_output.height = pipeline->isp_height;
> +	lindex |= LOWBIT_OF(PARAM_DRC_OTF_OUTPUT);
> +	hindex |= HIGHBIT_OF(PARAM_DRC_OTF_OUTPUT);
> +	indexes++;
> +
> +	wmb();
> +	ret = fimc_is_itf_set_param(&is->interface, pipeline->instance,
> +			indexes, lindex, hindex);
> +	if (ret) {
> +		pr_err("fimc_is_itf_set_param failed\n");

dev_err()

> +		return -EINVAL;
> +	}
> +	if (enable)
> +		set_bit(COMP_ENABLE,&pipeline->comp_state[IS_DRC]);
> +	else
> +		clear_bit(COMP_ENABLE,&pipeline->comp_state[IS_DRC]);
> +
> +	return 0;
> +}
> +
> +static int fimc_is_pipeline_scc_setparams(struct fimc_is_pipeline *pipeline,
> +		unsigned int enable)
> +{
> +	struct scalerc_param *scc_param =
> +		&pipeline->is_region->parameter.scalerc;
> +	struct fimc_is *is = pipeline->is;
> +	int ret;
> +	unsigned int indexes, lindex, hindex;
> +	unsigned int scc_width, scc_height;
> +
> +	scc_width = pipeline->scaler_width[SCALER_SCC];
> +	scc_height = pipeline->scaler_height[SCALER_SCC];
> +
> +	indexes = hindex = lindex = 0;
> +	if (enable)
> +		scc_param->control.bypass = CONTROL_BYPASS_DISABLE;
> +	else
> +		scc_param->control.bypass = CONTROL_BYPASS_ENABLE;
> +	lindex |= LOWBIT_OF(PARAM_SCALERC_CONTROL);
> +	hindex |= HIGHBIT_OF(PARAM_SCALERC_CONTROL);
> +	indexes++;
> +
> +	scc_param->otf_input.cmd = OTF_INPUT_COMMAND_ENABLE;
> +	scc_param->otf_input.width = pipeline->isp_width;
> +	scc_param->otf_input.height = pipeline->isp_height;
> +	lindex |= LOWBIT_OF(PARAM_SCALERC_OTF_INPUT);
> +	hindex |= HIGHBIT_OF(PARAM_SCALERC_OTF_INPUT);
> +	indexes++;
> +
> +	/* SCC OUTPUT */
> +	scc_param->input_crop.cmd = SCALER_CROP_COMMAND_ENABLE;
> +	scc_param->input_crop.pos_x = 0;
> +	scc_param->input_crop.pos_y = 0;
> +	scc_param->input_crop.crop_width = pipeline->isp_width;
> +	scc_param->input_crop.crop_height = pipeline->isp_height;
> +	scc_param->input_crop.in_width = pipeline->isp_width;
> +	scc_param->input_crop.in_height = pipeline->isp_height;
> +	scc_param->input_crop.out_width = scc_width;
> +	scc_param->input_crop.out_height = scc_height;
> +	lindex |= LOWBIT_OF(PARAM_SCALERC_INPUT_CROP);
> +	hindex |= HIGHBIT_OF(PARAM_SCALERC_INPUT_CROP);
> +	indexes++;
> +
> +	scc_param->output_crop.cmd = SCALER_CROP_COMMAND_DISABLE;
> +	scc_param->output_crop.pos_x = 0;
> +	scc_param->output_crop.pos_y = 0;
> +	scc_param->output_crop.crop_width = scc_width;
> +	scc_param->output_crop.crop_height = scc_height;
> +	lindex |= LOWBIT_OF(PARAM_SCALERC_OUTPUT_CROP);
> +	hindex |= HIGHBIT_OF(PARAM_SCALERC_OUTPUT_CROP);
> +	indexes++;
> +
> +	scc_param->otf_output.cmd = OTF_OUTPUT_COMMAND_ENABLE;
> +	scc_param->otf_output.width = scc_width;
> +	scc_param->otf_output.height = scc_height;
> +	lindex |= LOWBIT_OF(PARAM_SCALERC_OTF_OUTPUT);
> +	hindex |= HIGHBIT_OF(PARAM_SCALERC_OTF_OUTPUT);
> +	indexes++;
> +
> +	scc_param->dma_output.width = scc_width;
> +	scc_param->dma_output.height = scc_height;
> +	lindex |= LOWBIT_OF(PARAM_SCALERC_DMA_OUTPUT);
> +	hindex |= HIGHBIT_OF(PARAM_SCALERC_DMA_OUTPUT);
> +	indexes++;
> +
> +	wmb();
> +	ret = fimc_is_itf_set_param(&is->interface, pipeline->instance,
> +			indexes, lindex, hindex);
> +	if (ret) {
> +		pr_err("fimc_is_itf_set_param failed\n");

> +		return -EINVAL;
> +	}
> +	set_bit(COMP_ENABLE,&pipeline->comp_state[IS_SCC]);
> +	return 0;
> +}
> +
> +static int fimc_is_pipeline_odc_setparams(struct fimc_is_pipeline *pipeline,
> +		unsigned int enable)
> +{
> +	struct odc_param *odc_param =&pipeline->is_region->parameter.odc;
> +	struct fimc_is *is = pipeline->is;
> +	int ret;
> +	unsigned int indexes, lindex, hindex;
> +	unsigned int scc_width, scc_height;
> +
> +	scc_width = pipeline->scaler_width[SCALER_SCC];
> +	scc_height = pipeline->scaler_height[SCALER_SCC];
> +
> +	indexes = hindex = lindex = 0;
> +	if (enable)
> +		odc_param->control.bypass = CONTROL_BYPASS_DISABLE;
> +	else
> +		odc_param->control.bypass = CONTROL_BYPASS_ENABLE;
> +	lindex |= LOWBIT_OF(PARAM_ODC_CONTROL);
> +	hindex |= HIGHBIT_OF(PARAM_ODC_CONTROL);
> +	indexes++;
> +
> +	odc_param->otf_input.width = scc_width;
> +	odc_param->otf_input.height = scc_height;
> +	lindex |= LOWBIT_OF(PARAM_ODC_OTF_INPUT);
> +	hindex |= HIGHBIT_OF(PARAM_ODC_OTF_INPUT);
> +	indexes++;
> +
> +	odc_param->otf_output.width = scc_width;
> +	odc_param->otf_output.height = scc_height;
> +	lindex |= LOWBIT_OF(PARAM_ODC_OTF_OUTPUT);
> +	hindex |= HIGHBIT_OF(PARAM_ODC_OTF_OUTPUT);
> +	indexes++;
> +
> +	wmb();
> +	ret = fimc_is_itf_set_param(&is->interface, pipeline->instance,
> +			indexes, lindex, hindex);
> +	if (ret) {
> +		pr_err("fimc_is_itf_set_param failed\n");

dev_err()

> +		return -EINVAL;
> +	}
> +	if (enable)
> +		set_bit(COMP_ENABLE,&pipeline->comp_state[IS_ODC]);
> +	else
> +		clear_bit(COMP_ENABLE,&pipeline->comp_state[IS_ODC]);
> +
> +	return 0;
> +}
> +
> +static int fimc_is_pipeline_dis_setparams(struct fimc_is_pipeline *pipeline,
> +		unsigned int enable)
> +{
> +	struct dis_param *dis_param =&pipeline->is_region->parameter.dis;
> +	struct fimc_is *is = pipeline->is;
> +	int ret;
> +	unsigned int indexes, lindex, hindex;
> +	unsigned int scc_width, scc_height;
> +
> +	scc_width = pipeline->scaler_width[SCALER_SCC];
> +	scc_height = pipeline->scaler_height[SCALER_SCC];
> +
> +	indexes = hindex = lindex = 0;
> +	if (enable)
> +		dis_param->control.bypass = CONTROL_BYPASS_DISABLE;
> +	else
> +		dis_param->control.bypass = CONTROL_BYPASS_ENABLE;
> +	lindex |= LOWBIT_OF(PARAM_DIS_CONTROL);
> +	hindex |= HIGHBIT_OF(PARAM_DIS_CONTROL);
> +	indexes++;
> +
> +	/* DIS INPUT */
> +	dis_param->otf_input.width = scc_width;
> +	dis_param->otf_input.height = scc_height;
> +	lindex |= LOWBIT_OF(PARAM_DIS_OTF_INPUT);
> +	hindex |= HIGHBIT_OF(PARAM_DIS_OTF_INPUT);
> +	indexes++;
> +
> +	/* DIS OUTPUT */
> +	dis_param->otf_output.width = scc_width;
> +	dis_param->otf_output.height = scc_height;
> +	lindex |= LOWBIT_OF(PARAM_DIS_OTF_OUTPUT);
> +	hindex |= HIGHBIT_OF(PARAM_DIS_OTF_OUTPUT);
> +	indexes++;
> +
> +	wmb();
> +	ret = fimc_is_itf_set_param(&is->interface, pipeline->instance,
> +			indexes, lindex, hindex);
> +	if (ret) {
> +		pr_err("fimc_is_itf_set_param failed\n");

dev_err()

> +		return -EINVAL;
> +	}
> +	if (enable)
> +		set_bit(COMP_ENABLE,&pipeline->comp_state[IS_DIS]);
> +	else
> +		clear_bit(COMP_ENABLE,&pipeline->comp_state[IS_DIS]);
> +
> +	return 0;
> +}
> +
> +static int fimc_is_pipeline_3dnr_setparams(struct fimc_is_pipeline *pipeline,
> +		unsigned int enable)
> +{
> +	struct tdnr_param *tdnr_param =&pipeline->is_region->parameter.tdnr;
> +	struct fimc_is *is = pipeline->is;
> +	int ret;
> +	unsigned int indexes, lindex, hindex;
> +	unsigned int scc_width, scc_height;
> +
> +	scc_width = pipeline->scaler_width[SCALER_SCC];
> +	scc_height = pipeline->scaler_height[SCALER_SCC];
> +
> +	indexes = hindex = lindex = 0;
> +	if (enable)
> +		tdnr_param->control.bypass = CONTROL_BYPASS_DISABLE;
> +	else
> +		tdnr_param->control.bypass = CONTROL_BYPASS_ENABLE;
> +	lindex |= LOWBIT_OF(PARAM_TDNR_CONTROL);
> +	hindex |= HIGHBIT_OF(PARAM_TDNR_CONTROL);
> +	indexes++;
> +
> +	tdnr_param->otf_input.width = scc_width;
> +	tdnr_param->otf_input.height = scc_height;
> +	lindex |= LOWBIT_OF(PARAM_TDNR_OTF_INPUT);
> +	hindex |= HIGHBIT_OF(PARAM_TDNR_OTF_INPUT);
> +	indexes++;
> +
> +	tdnr_param->dma_output.width = scc_width;
> +	tdnr_param->dma_output.height = scc_height;
> +	lindex |= LOWBIT_OF(PARAM_TDNR_DMA_OUTPUT);
> +	hindex |= HIGHBIT_OF(PARAM_TDNR_DMA_OUTPUT);
> +	indexes++;
> +
> +	tdnr_param->otf_output.width = scc_width;
> +	tdnr_param->otf_output.height = scc_height;
> +	lindex |= LOWBIT_OF(PARAM_TDNR_OTF_OUTPUT);
> +	hindex |= HIGHBIT_OF(PARAM_TDNR_OTF_OUTPUT);
> +	indexes++;
> +
> +	wmb();
> +	ret = fimc_is_itf_set_param(&is->interface, pipeline->instance,
> +			indexes, lindex, hindex);
> +	if (ret) {
> +		pr_err("fimc_is_itf_set_param failed\n");

dev_err()

> +		return -EINVAL;
> +	}
> +	if (enable)
> +		set_bit(COMP_ENABLE,&pipeline->comp_state[IS_TDNR]);
> +	else
> +		clear_bit(COMP_ENABLE,&pipeline->comp_state[IS_TDNR]);
> +
> +	return 0;
> +}
> +
> +static int fimc_is_pipeline_scp_setparams(struct fimc_is_pipeline *pipeline,
> +		unsigned int enable)
> +{
> +	struct scalerp_param *scp_param =
> +		&pipeline->is_region->parameter.scalerp;
> +	struct fimc_is *is = pipeline->is;
> +	int ret;
> +	unsigned int indexes, lindex, hindex;
> +	unsigned int scc_width, scc_height;
> +	unsigned int scp_width, scp_height;
> +
> +	scc_width = pipeline->scaler_width[SCALER_SCC];
> +	scc_height = pipeline->scaler_height[SCALER_SCC];
> +	scp_width = pipeline->scaler_width[SCALER_SCP];
> +	scp_height = pipeline->scaler_height[SCALER_SCP];
> +
> +	indexes = hindex = lindex = 0;
> +	if (enable)
> +		scp_param->control.bypass = CONTROL_BYPASS_DISABLE;
> +	else
> +		scp_param->control.bypass = CONTROL_BYPASS_ENABLE;
> +	lindex |= LOWBIT_OF(PARAM_SCALERP_CONTROL);
> +	hindex |= HIGHBIT_OF(PARAM_SCALERP_CONTROL);
> +	indexes++;
> +
> +	/* SCP Input */
> +	scp_param->otf_input.width = scc_width;
> +	scp_param->otf_input.height = scc_height;
> +	lindex |= LOWBIT_OF(PARAM_SCALERP_OTF_INPUT);
> +	hindex |= HIGHBIT_OF(PARAM_SCALERP_OTF_INPUT);
> +	indexes++;
> +
> +	/* SCP Output */
> +	scp_param->input_crop.cmd = SCALER_CROP_COMMAND_ENABLE;
> +	scp_param->input_crop.pos_x = 0;
> +	scp_param->input_crop.pos_y = 0;
> +	scp_param->input_crop.crop_width = scc_width;
> +	scp_param->input_crop.crop_height = scc_height;
> +	scp_param->input_crop.in_width = scc_width;
> +	scp_param->input_crop.in_height = scc_height;
> +	scp_param->input_crop.out_width = scp_width;
> +	scp_param->input_crop.out_height = scp_height;
> +	lindex |= LOWBIT_OF(PARAM_SCALERP_INPUT_CROP);
> +	hindex |= HIGHBIT_OF(PARAM_SCALERP_INPUT_CROP);
> +	indexes++;
> +
> +	scp_param->output_crop.cmd = SCALER_CROP_COMMAND_DISABLE;
> +	lindex |= LOWBIT_OF(PARAM_SCALERP_OUTPUT_CROP);
> +	hindex |= HIGHBIT_OF(PARAM_SCALERP_OUTPUT_CROP);
> +	indexes++;
> +
> +	scp_param->otf_output.width = scp_width;
> +	scp_param->otf_output.height = scp_height;
> +	lindex |= LOWBIT_OF(PARAM_SCALERP_OTF_OUTPUT);
> +	hindex |= HIGHBIT_OF(PARAM_SCALERP_OTF_OUTPUT);
> +	indexes++;
> +
> +	scp_param->dma_output.width = scp_width;
> +	scp_param->dma_output.height = scp_height;
> +	lindex |= LOWBIT_OF(PARAM_SCALERP_DMA_OUTPUT);
> +	hindex |= HIGHBIT_OF(PARAM_SCALERP_DMA_OUTPUT);
> +	indexes++;
> +
> +	wmb();
> +	ret = fimc_is_itf_set_param(&is->interface, pipeline->instance,
> +			indexes, lindex, hindex);
> +	if (ret) {
> +		pr_err("fimc_is_itf_set_param failed\n");

dev_err()

And would be better to use __func__ instead.

> +		return -EINVAL;
> +	}
> +	set_bit(COMP_ENABLE,&pipeline->comp_state[IS_SCP]);
> +
> +	return 0;
> +}
> +
> +static int fimc_is_pipeline_fd_setparams(struct fimc_is_pipeline *pipeline,
> +		unsigned int enable)
> +{
> +	struct fd_param *fd_param =&pipeline->is_region->parameter.fd;
> +	struct fimc_is *is = pipeline->is;
> +	int ret;
> +	unsigned int indexes, lindex, hindex;
> +
> +	indexes = hindex = lindex = 0;
> +	if (enable)
> +		fd_param->control.bypass = CONTROL_BYPASS_DISABLE;
> +	else
> +		fd_param->control.bypass = CONTROL_BYPASS_ENABLE;
> +	lindex |= LOWBIT_OF(PARAM_FD_CONTROL);
> +	hindex |= HIGHBIT_OF(PARAM_FD_CONTROL);
> +	indexes++;
> +
> +	fd_param->otf_input.width = pipeline->scaler_width[SCALER_SCP];
> +	fd_param->otf_input.height = pipeline->scaler_height[SCALER_SCP];
> +	lindex |= LOWBIT_OF(PARAM_FD_OTF_INPUT);
> +	hindex |= HIGHBIT_OF(PARAM_FD_OTF_INPUT);
> +	indexes++;
> +
> +	wmb();
> +	ret = fimc_is_itf_set_param(&is->interface, pipeline->instance,
> +			indexes, lindex, hindex);
> +	if (ret) {
> +		pr_err("fimc_is_itf_set_param failed\n");

dev_err(), __func__

> +		return -EINVAL;
> +	}
> +	if (enable)
> +		set_bit(COMP_ENABLE,&pipeline->comp_state[IS_FD]);
> +	else
> +		clear_bit(COMP_ENABLE,&pipeline->comp_state[IS_FD]);
> +
> +	return 0;
> +}
> +
> +void fimc_is_pipeline_buf_lock(struct fimc_is_pipeline *pipeline)
> +{
> +	spin_lock_irqsave(&pipeline->slock_buf, pipeline->slock_flags);
> +}
> +
> +void fimc_is_pipeline_buf_unlock(struct fimc_is_pipeline *pipeline)
> +{
> +	spin_unlock_irqrestore(&pipeline->slock_buf, pipeline->slock_flags);
> +}
> +
> +int fimc_is_pipeline_setparams(struct fimc_is_pipeline *pipeline)
> +{
> +	int ret;
> +
> +	/* Enabling basic components in pipeline */
> +	ret = fimc_is_pipeline_isp_setparams(pipeline, true);
> +	ret |= fimc_is_pipeline_drc_setparams(pipeline, false);
> +	ret |= fimc_is_pipeline_scc_setparams(pipeline, true);
> +	ret |= fimc_is_pipeline_odc_setparams(pipeline, false);
> +	ret |= fimc_is_pipeline_dis_setparams(pipeline, false);
> +	ret |= fimc_is_pipeline_3dnr_setparams(pipeline, false);
> +	ret |= fimc_is_pipeline_scp_setparams(pipeline, true);
> +	ret |= fimc_is_pipeline_fd_setparams(pipeline, false);

No, don't use this |= pattern, either return any error immediately or
check return value of previous call before proceeding.

> +	if (ret<  0)
> +		pr_err("Pipeline setparam failed.\n");

dev_err()

> +	return ret;
> +}
> +
> +int fimc_is_pipeline_scaler_start(struct fimc_is_pipeline *pipeline,
> +		enum fimc_is_scaler_id scaler_id,
> +		unsigned int **buf_paddr,
> +		unsigned int num_bufs,
> +		unsigned int num_planes)
> +{
> +	struct fimc_is *is = pipeline->is;
> +	struct scalerp_param *scp_param =
> +		&pipeline->is_region->parameter.scalerp;
> +	struct scalerc_param *scc_param =
> +		&pipeline->is_region->parameter.scalerc;
> +	struct param_dma_output *dma_output;
> +	const struct fimc_is_fmt *fmt;
> +	unsigned int region_index;
> +	unsigned long *comp_state;
> +	int ret;
> +	unsigned int pipe_start_flag = 0;
> +	unsigned int i, j, buf_index, buf_mask = 0;
> +	unsigned int indexes, lindex, hindex;
> +
> +	if (!test_bit(PIPELINE_OPEN,&pipeline->state)) {
> +		pr_err("Pipeline not opened.\n");
> +		return -EINVAL;
> +	}
> +
> +	mutex_lock(&pipeline->pipe_scl_lock);
> +
> +	if (test_bit(PIPELINE_START,&pipeline->state)) {
> +		/* Pipeline is started.
> +		 * Stop it now to set params and start again */

Wrong multi-line comment style.

> +		ret = fimc_is_pipeline_stop(pipeline);
> +		if (ret) {
> +			pr_err("Not able to stop pipeline\n");

dev_err()

> +			goto exit;
> +		}
> +		pipe_start_flag = 1;
> +	}
> +
> +	indexes = lindex = hindex = 0;
> +
> +	if (scaler_id == SCALER_SCC) {
> +		dma_output =&scc_param->dma_output;
> +		region_index = FIMC_IS_SCC_REGION_INDEX;
> +		comp_state =&pipeline->comp_state[IS_SCC];
> +		fmt = pipeline->scaler[SCALER_SCC].fmt;
> +		lindex |= LOWBIT_OF(PARAM_SCALERC_DMA_OUTPUT);
> +		hindex |= HIGHBIT_OF(PARAM_SCALERC_DMA_OUTPUT);
> +	} else {
> +		dma_output =&scp_param->dma_output;
> +		comp_state =&pipeline->comp_state[IS_SCP];
> +		fmt = pipeline->scaler[SCALER_SCC].fmt;
> +		region_index = FIMC_IS_SCP_REGION_INDEX;
> +		lindex |= LOWBIT_OF(PARAM_SCALERP_DMA_OUTPUT);
> +		hindex |= HIGHBIT_OF(PARAM_SCALERP_DMA_OUTPUT);
> +	}
> +	indexes++;
> +
> +	for (i = 0; i<  num_bufs; i++) {
> +		for (j = 0; j<  num_planes; j++) {
> +			buf_index = i * num_planes + j;
> +			pipeline->is_region->shared[region_index + buf_index] =
> +				(unsigned int)&buf_paddr[i][j];
> +		}
> +		buf_mask |= (1<<  i);
> +	}
> +
> +	dma_output->cmd = DMA_OUTPUT_COMMAND_ENABLE;
> +	dma_output->dma_out_mask = buf_mask;
> +	dma_output->buffer_number = num_bufs;
> +	dma_output->plane = num_planes;
> +	if ((fmt->fourcc == V4L2_PIX_FMT_YUV420M) ||
> +			(fmt->fourcc == V4L2_PIX_FMT_NV12M))
> +		dma_output->format = DMA_OUTPUT_FORMAT_YUV420;
> +	else if (fmt->fourcc == V4L2_PIX_FMT_NV16)
> +		dma_output->format = DMA_OUTPUT_FORMAT_YUV422;
> +
> +	dma_output->buffer_address = pipeline->minfo->shared_paddr +
> +				region_index * sizeof(unsigned int);
> +
> +	ret = fimc_is_itf_set_param(&is->interface, pipeline->instance,
> +			indexes, lindex, hindex);
> +	if (ret)
> +		pr_err("fimc_is_itf_set_param is fail\n");
> +	else
> +		set_bit(COMP_START, comp_state);
> +
> +	if (pipe_start_flag) {
> +		ret = fimc_is_pipeline_start(pipeline);
> +		if (ret) {
> +			pr_err("Not able to start pipeline back\n");
> +			goto exit;
> +		}
> +	}
> +
> +exit:
> +	mutex_unlock(&pipeline->pipe_scl_lock);
> +	return ret;
> +}
> +
> +int fimc_is_pipeline_scaler_stop(struct fimc_is_pipeline *pipeline,
> +		enum fimc_is_scaler_id scaler_id)
> +{
> +	struct fimc_is *is = pipeline->is;
> +	struct scalerp_param *scp_param =
> +		&pipeline->is_region->parameter.scalerp;
> +	struct scalerc_param *scc_param =
> +		&pipeline->is_region->parameter.scalerc;
> +	struct param_dma_output *dma_output;
> +	unsigned int pipe_start_flag = 0;
> +	unsigned int indexes, lindex, hindex;
> +	unsigned long *comp_state;
> +	int ret;
> +
> +	if (!test_bit(PIPELINE_OPEN,&pipeline->state))
> +		return -EINVAL;
> +
> +	mutex_lock(&pipeline->pipe_scl_lock);
> +
> +	if (test_bit(PIPELINE_START,&pipeline->state)) {
> +		/* Pipeline is started.
> +		 * Stop it now to set params and start again */

CodingStyle.

> +		ret = fimc_is_pipeline_stop(pipeline);
> +		if (ret) {
> +			pr_err("Not able to stop pipeline\n");

dev_err()

> +			goto exit;
> +		}
> +		pipe_start_flag = 1;
> +	}
> +
> +	comp_state = (scaler_id == SCALER_SCC) ?
> +		&pipeline->comp_state[IS_SCC] :&pipeline->comp_state[IS_SCP];
> +
> +	if (!test_bit(COMP_START, comp_state)) {
> +		pr_debug("Scaler not started\n");
> +		ret = 0;
> +		goto exit;
> +	}
> +
> +	indexes = lindex = hindex = 0;
> +
> +	if (scaler_id == SCALER_SCC) {
> +		dma_output =&scc_param->dma_output;
> +		lindex |= LOWBIT_OF(PARAM_SCALERC_DMA_OUTPUT);
> +		hindex |= HIGHBIT_OF(PARAM_SCALERC_DMA_OUTPUT);
> +	} else {
> +		dma_output =&scp_param->dma_output;
> +		lindex |= LOWBIT_OF(PARAM_SCALERP_DMA_OUTPUT);
> +		hindex |= HIGHBIT_OF(PARAM_SCALERP_DMA_OUTPUT);
> +	}
> +	indexes++;
> +	dma_output->cmd = DMA_OUTPUT_COMMAND_DISABLE;
> +
> +	ret = fimc_is_itf_set_param(&is->interface, pipeline->instance,
> +			indexes, lindex, hindex);
> +	if (ret<  0)
> +		pr_err("fimc_is_itf_set_param is fail\n");

dev_err()

> +	else
> +		clear_bit(COMP_START, comp_state);
> +
> +	if (pipe_start_flag) {
> +		ret = fimc_is_pipeline_start(pipeline);
> +		if (ret) {
> +			pr_err("Not able to start pipeline back\n");

dev_err()

> +			return -EINVAL;
> +		}
> +	}
> +
> +exit:
> +	mutex_unlock(&pipeline->pipe_scl_lock);
> +	return ret;
> +}
> +
> +void fimc_is_pipeline_config_shot(struct fimc_is_pipeline *pipeline)
> +{
> +	struct camera2_shot *shot =
> +		(struct camera2_shot *)pipeline->shot_vaddr;
> +
> +	shot->magicnumber = 0x23456789;

It's an explicit magic number, but maybe we could have #define for it ?

> +	shot->ctl.aa.mode = AA_CONTROL_AUTO;
> +	shot->ctl.aa.ae_mode = AA_AEMODE_ON;
> +}
> +
> +int fimc_is_pipeline_shot(struct fimc_is_pipeline *pipeline)
> +{
> +	struct fimc_is *is = pipeline->is;
> +	int ret;
> +	unsigned int rcount;
> +	struct camera2_shot *shot =
> +		(struct camera2_shot *)pipeline->shot_vaddr;

Why is this casting needed ?

> +	struct fimc_is_buf *scc_buf, *scp_buf, *bayer_buf;
> +
> +	if (!test_bit(PIPELINE_START,&pipeline->state)) {
> +		/* Pipeline not started yet */

Please remove this comment and braces.

> +		return -EINVAL;
> +	}
> +
> +	if (test_bit(PIPELINE_RUN,&pipeline->state)) {
> +		/* Pipeline busy. Caller need to wait */

Ditto.

> +		return -EBUSY;
> +	}
> +
> +	fimc_is_pipeline_buf_lock(pipeline);
> +
> +	if (list_empty(&pipeline->isp.wait_queue)) {
> +		/* No more bayer buffers */
> +		wake_up(&pipeline->wait_q);
> +		fimc_is_pipeline_buf_unlock(pipeline);
> +		return 0;
> +	}
> +
> +	/* Set the state as RUN */

Please remove this comment.

> +	set_bit(PIPELINE_RUN,&pipeline->state);
> +
> +	/* Get bayer input buffer */
> +	bayer_buf = fimc_is_isp_wait_queue_get(&pipeline->isp);
> +	if (!bayer_buf) {
> +		fimc_is_pipeline_buf_unlock(pipeline);
> +		goto err_exit;
> +	}
> +	fimc_is_isp_run_queue_add(&pipeline->isp, bayer_buf);
> +
> +	/* Get SCC buffer */
> +	if (test_bit(COMP_START,&pipeline->comp_state[IS_SCC])&&
> +		!list_empty(&pipeline->scaler[SCALER_SCC].wait_queue)) {
> +		scc_buf = fimc_is_scaler_wait_queue_get(
> +				&pipeline->scaler[SCALER_SCC]);
> +		if (scc_buf) {
> +			fimc_is_scaler_run_queue_add(
> +					&pipeline->scaler[SCALER_SCC],
> +					scc_buf);
> +			shot->uctl.scaler_ud.scc_target_address[0] =
> +							scc_buf->paddr[0];
> +			shot->uctl.scaler_ud.scc_target_address[1] =
> +							scc_buf->paddr[1];
> +			shot->uctl.scaler_ud.scc_target_address[2] =
> +							scc_buf->paddr[2];
> +			set_bit(COMP_RUN,&pipeline->comp_state[IS_SCC]);
> +		}
> +	} else {
> +		pr_debug("No SCC buffer available\n");
> +		shot->uctl.scaler_ud.scc_target_address[0] = 0;
> +		shot->uctl.scaler_ud.scc_target_address[1] = 0;
> +		shot->uctl.scaler_ud.scc_target_address[2] = 0;
> +	}
> +
> +	/* Get SCP buffer */
> +	if (test_bit(COMP_START,&pipeline->comp_state[IS_SCP])&&
> +		!list_empty(&pipeline->scaler[SCALER_SCP].wait_queue)) {
> +		scp_buf = fimc_is_scaler_wait_queue_get(
> +				&pipeline->scaler[SCALER_SCP]);
> +		if (scp_buf) {
> +			fimc_is_scaler_run_queue_add(
> +					&pipeline->scaler[SCALER_SCP],
> +					scp_buf);
> +			shot->uctl.scaler_ud.scp_target_address[0] =
> +							scp_buf->paddr[0];
> +			shot->uctl.scaler_ud.scp_target_address[1] =
> +							scp_buf->paddr[1];
> +			shot->uctl.scaler_ud.scp_target_address[2] =
> +							scp_buf->paddr[2];

			for (i = 0; i < 3; i++)
				shot->uctl.scaler_ud.scp_target_address[i] =
							scp_buf->paddr[i];

Please avoid such silly loop unrollings.

> +			set_bit(COMP_RUN,&pipeline->comp_state[IS_SCP]);
> +		}
> +	} else {
> +		pr_debug("No SCP buffer available\n");
> +		shot->uctl.scaler_ud.scp_target_address[0] = 0;
> +		shot->uctl.scaler_ud.scp_target_address[1] = 0;
> +		shot->uctl.scaler_ud.scp_target_address[2] = 0;

		for (i = 0; i < 3; i++)
			shot->uctl.scaler_ud.scp_target_address[i] = 0;
> +	}
> +	fimc_is_pipeline_buf_unlock(pipeline);
> +
> +	/* Send shot command */
> +	pipeline->fcount++;
> +	rcount = pipeline->fcount;
> +	shot->ctl.request.framecount = pipeline->fcount;
> +	pr_debug("Shot command fcount : %d, Bayer addr : 0x%08x\n",
> +			pipeline->fcount, bayer_buf->paddr[0]);
> +	ret = fimc_is_itf_shot_nblk(&is->interface, pipeline->instance,
> +			bayer_buf->paddr[0],
> +			pipeline->shot_paddr,
> +			pipeline->fcount,
> +			rcount);
> +	if (ret<  0) {
> +		pr_err("Shot command failed.\n");
> +		goto err_exit;
> +	}
> +	return 0;
> +
> +err_exit:
> +	clear_bit(PIPELINE_RUN,&pipeline->state);
> +	clear_bit(COMP_RUN,&pipeline->comp_state[IS_SCC]);
> +	clear_bit(COMP_RUN,&pipeline->comp_state[IS_SCP]);
> +	return -EINVAL;
> +}
> +
> +int fimc_is_pipeline_start(struct fimc_is_pipeline *pipeline)
> +{
> +	int ret;
> +	struct fimc_is *is = pipeline->is;
> +
> +	/* Check if open or not */
> +	if (!test_bit(PIPELINE_OPEN,&pipeline->state)) {
> +		pr_err("Pipeline not open.\n");

dev_err()

> +		return -EINVAL;
> +	}
> +
> +	mutex_lock(&pipeline->pipe_lock);
> +
> +	/* Check if already started */
> +	if (test_bit(PIPELINE_START,&pipeline->state)) {
> +		pr_debug("Pipeline already started.\n");
> +		mutex_unlock(&pipeline->pipe_lock);

goto error_exit instead ?

> +		return 0;
> +	}
> +
> +	/* Set pipeline component params */
> +	ret = fimc_is_pipeline_setparams(pipeline);
> +	if (ret<  0) {
> +		pr_err("Set params failed\n");
> +		goto err_exit;
> +	}
> +
> +	/* Send preview still command */
> +	ret = fimc_is_itf_preview_still(&is->interface, pipeline->instance);
> +	if (ret) {
> +		pr_err("Preview still command failed\n");

dev_err()

> +		goto err_exit;
> +	}
> +
> +	/* Confiture shot memory to A5 */
> +	ret = fimc_is_itf_cfg_mem(&is->interface, pipeline->instance,
> +			pipeline->shot_paddr, sizeof(struct camera2_shot));
> +	if (ret<  0) {
> +		pr_err("Config A5 mem failed.\n");

dev_err()

> +		goto err_exit;
> +	}
> +
> +	/* Set shot params */
> +	fimc_is_pipeline_config_shot(pipeline);
> +
> +	/* Process ON command */
> +	ret = fimc_is_itf_process_on(&is->interface, pipeline->instance);
> +	if (ret) {
> +		pr_err("Process on failed\n");

dev_err()

> +		goto err_exit;
> +	}
> +
> +	/* Stream ON */
> +	ret = fimc_is_itf_stream_on(&is->interface, pipeline->instance);
> +	if (ret<  0) {
> +		pr_err("Stream On failed.\n");

dev_err()

> +		goto err_exit;
> +	}
> +
> +	/* Set state to START */
> +	set_bit(PIPELINE_START,&pipeline->state);
> +
> +	mutex_unlock(&pipeline->pipe_lock);
> +	return 0;
> +
> +err_exit:
> +	mutex_unlock(&pipeline->pipe_lock);
> +	return ret;
> +}
> +
> +int fimc_is_pipeline_stop(struct fimc_is_pipeline *pipeline)
> +{
> +	int ret;
> +	struct fimc_is *is = pipeline->is;
> +
> +	mutex_lock(&pipeline->pipe_lock);
> +
> +	/* Check if started */
> +	if (!test_bit(PIPELINE_OPEN,&pipeline->state) ||
> +		!test_bit(PIPELINE_START,&pipeline->state)) {
> +		pr_debug("Pipeline not open/started.\n");
> +		ret = -EINVAL;
> +		goto err_exit;
> +	}
> +
> +	/* Wait if any operation is in progress */
> +	ret = wait_event_timeout(pipeline->wait_q,
> +			!test_bit(PIPELINE_RUN,&pipeline->state),
> +			FIMC_IS_COMMAND_TIMEOUT);
> +	if (!ret) {
> +		pr_err("Pipeline timeout");

dev_err(), dev_err(), dev_err(), dev_err(), dev_err(), ...

> +		ret = -EBUSY;
> +		goto err_exit;
> +	}
> +
> +	/* Wait for scaler operations if any to complete */
> +	ret = wait_event_timeout(pipeline->scaler[SCALER_SCC].event_q,
> +			!test_bit(COMP_RUN,&pipeline->comp_state[IS_SCC]),
> +			FIMC_IS_COMMAND_TIMEOUT);
> +	if (!ret) {
> +		pr_err("SCC timeout");
> +		ret = -EBUSY;
> +		goto err_exit;
> +	}
> +	ret = wait_event_timeout(pipeline->scaler[SCALER_SCP].event_q,
> +			!test_bit(COMP_RUN,&pipeline->comp_state[IS_SCP]),
> +			FIMC_IS_COMMAND_TIMEOUT);
> +	if (!ret) {
> +		pr_err("SCP timeout");
> +		ret = -EBUSY;
> +		goto err_exit;
> +	}
> +
> +
> +	/* Process OFF */
> +	ret = fimc_is_itf_process_off(&is->interface, pipeline->instance);
> +	if (ret) {
> +		pr_err("Process off failed\n");
> +		ret = -EINVAL;
> +		goto err_exit;
> +	}
> +
> +	/* Stream OFF */
> +	ret = fimc_is_itf_stream_off(&is->interface, pipeline->instance);
> +	if (ret<  0) {
> +		pr_err("Stream Off failed.\n");
> +		ret = -EINVAL;
> +		goto err_exit;
> +	}
> +
> +	/* Clear state */
> +	clear_bit(PIPELINE_START,&pipeline->state);
> +
> +	mutex_unlock(&pipeline->pipe_lock);
> +	return 0;

These two lines can be removed.

> +
> +err_exit:
> +	mutex_unlock(&pipeline->pipe_lock);
> +	return ret;
> +}
> +
> +int fimc_is_pipeline_open(struct fimc_is_pipeline *pipeline,
> +			struct fimc_is_sensor *sensor)
> +{
> +	struct fimc_is *is = pipeline->is;
> +	struct is_region *region;
> +	int ret;
> +
> +	pr_debug("Pipeline open, instance : %d\n", pipeline->instance);
> +
> +	if (!sensor)
> +		return -EINVAL;
> +
> +	mutex_lock(&pipeline->pipe_lock);
> +
> +	/* Check if already open */

Please remove this comment.

> +	if (test_bit(PIPELINE_OPEN,&pipeline->state)) {
> +		pr_err("Pipeline already open.\n");

All pr_err() should be converted to dev_err() in this function.

> +		ret = -EINVAL;
> +		goto err_exit;
> +	}
> +
> +	/* Init pipeline params */
> +	pipeline->fcount = 0;
> +	pipeline->sensor = sensor;
> +	pipeline->sensor_width = sensor->width;
> +	pipeline->sensor_height = sensor->height;
> +
> +	/* Init memory */
> +	ret = fimc_is_pipeline_initmem(pipeline, is->alloc_ctx);
> +	if (ret<  0) {
> +		pr_err("Pipeline memory init failed.\n");
> +		goto err_exit;
> +	}
> +
> +	/* Load firmware */
> +	ret = fimc_is_pipeline_load_firmware(pipeline);
> +	if (ret<  0) {
> +		pr_err("Firmware load failed.\n");
> +		goto err_fw;
> +	}
> +
> +	/* Power ON */
> +	ret = fimc_is_pipeline_power(pipeline, 1);
> +	if (ret<  0) {
> +		pr_err("A5 power on failed.\n");
> +		goto err_fw;
> +	}
> +
> +	/* Wait for FW Init to complete */
> +	ret = fimc_is_itf_wait_init_state(&is->interface);
> +	if (ret<  0) {
> +		pr_err("FW init failed.\n");
> +		goto err_fw;
> +	}
> +
> +	/* Open Sensor */
> +	region = pipeline->is_region;
> +	ret = fimc_is_itf_open_sensor(&is->interface,
> +			pipeline->instance,
> +			sensor->drvdata->id,
> +			sensor->i2c_bus,
> +			pipeline->minfo->shared_paddr);
> +	if (ret<  0) {
> +		pr_err("Open sensor failed\n");
> +		goto err_exit;
> +	}
> +
> +	pr_debug("Magic Number : %x\n",
> +			pipeline->is_region->shared[MAX_SHARED_COUNT-1]);

CodingStyle: should have spaces around '-'.

> +
> +	/* Copy init params to FW region */
> +	memset(&region->parameter, 0x0, sizeof(struct is_param_region));
> +
> +	memcpy(&region->parameter.sensor,&init_sensor_param,
> +			sizeof(struct sensor_param));
> +	memcpy(&region->parameter.isp,&init_isp_param,
> +			sizeof(struct isp_param));
> +	memcpy(&region->parameter.drc,&init_drc_param,
> +			sizeof(struct drc_param));
> +	memcpy(&region->parameter.scalerc,&init_scalerc_param,
> +			sizeof(struct scalerc_param));
> +	memcpy(&region->parameter.odc,&init_odc_param,
> +			sizeof(struct odc_param));
> +	memcpy(&region->parameter.dis,&init_dis_param,
> +			sizeof(struct dis_param));
> +	memcpy(&region->parameter.tdnr,&init_tdnr_param,
> +			sizeof(struct tdnr_param));
> +	memcpy(&region->parameter.scalerp,&init_scalerp_param,
> +			sizeof(struct scalerp_param));
> +	memcpy(&region->parameter.fd,&init_fd_param,
> +			sizeof(struct fd_param));
> +
> +	/* Load setfile */
> +	ret = fimc_is_pipeline_setfile(pipeline);
> +	if (ret<  0)
> +		goto err_exit;
> +
> +	/* Stream off */
> +	ret = fimc_is_itf_stream_off(&is->interface, pipeline->instance);
> +	if (ret<  0)
> +		goto err_exit;
> +
> +	/* Process off */
> +	ret = fimc_is_itf_process_off(&is->interface, pipeline->instance);
> +	if (ret<  0)
> +		goto err_exit;
> +
> +	/* Set state to OPEN */
> +	set_bit(PIPELINE_OPEN,&pipeline->state);
> +
> +	mutex_unlock(&pipeline->pipe_lock);
> +	return 0;
> +
> +err_fw:
> +	fimc_is_pipeline_freemem(pipeline);
> +err_exit:
> +	mutex_unlock(&pipeline->pipe_lock);
> +	return ret;
> +}
> +
> +int fimc_is_pipeline_close(struct fimc_is_pipeline *pipeline)
> +{
> +	int ret;
> +	struct fimc_is *is = pipeline->is;
> +
> +	mutex_lock(&pipeline->pipe_lock);
> +
> +	/* Check if opened */
> +	if (!test_bit(PIPELINE_OPEN,&pipeline->state)) {
> +		pr_err("Pipeline not opened\n");
> +		ret = -EINVAL;
> +		goto err_exit;
> +	}
> +
> +	/* Stop pipeline */
> +	if (test_bit(PIPELINE_START,&pipeline->state)) {
> +		pr_err("Cannot close pipeline when its started\n");
> +		ret = -EINVAL;
> +		goto err_exit;
> +	}
> +
> +	/* FW power off command */
> +	ret = fimc_is_itf_power_down(&is->interface, pipeline->instance);
> +	if (ret)
> +		pr_err("FW power down error\n");
> +
> +	/* Pipeline power off*/
> +	fimc_is_pipeline_power(pipeline, 0);
> +
> +	/* Free memory */
> +	fimc_is_pipeline_freemem(pipeline);
> +
> +	clear_bit(PIPELINE_OPEN,&pipeline->state);
> +	mutex_unlock(&pipeline->pipe_lock);
> +	return 0;
> +
> +err_exit:
> +	mutex_unlock(&pipeline->pipe_lock);
> +	return ret;
> +}
> diff --git a/drivers/media/platform/exynos5-is/fimc-is-pipeline.h b/drivers/media/platform/exynos5-is/fimc-is-pipeline.h
> new file mode 100644
> index 0000000..2c5cff9
> --- /dev/null
> +++ b/drivers/media/platform/exynos5-is/fimc-is-pipeline.h
> @@ -0,0 +1,129 @@
> +/*
> + * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
> + *
> + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
> + *  Arun Kumar K<arun.kk@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +#ifndef FIMC_IS_PIPELINE_H_
> +#define FIMC_IS_PIPELINE_H_
> +
> +#include "fimc-is-core.h"
> +#include "fimc-is-sensor.h"
> +#include "fimc-is-isp.h"
> +#include "fimc-is-scaler.h"
> +
> +#define FIMC_IS_A5_MEM_SIZE		(0x00A00000)
> +#define FIMC_IS_A5_SEN_SIZE		(0x00100000)
> +#define FIMC_IS_REGION_SIZE		(0x5000)
> +#define FIMC_IS_SETFILE_SIZE		(0xc0d8)
> +#define FIMC_IS_TDNR_MEM_SIZE		(1920*1080*4)
> +#define FIMC_IS_DEBUG_REGION_ADDR	(0x00840000)
> +#define FIMC_IS_SHARED_REGION_ADDR	(0x008C0000)

Please remove parentheses where they are not necessary.

> +#define FIMC_IS_SCP_REGION_INDEX	400
> +#define FIMC_IS_SCC_REGION_INDEX	447
> +
> +#define MAX_ODC_INTERNAL_BUF_WIDTH	(2560)  /* 4808 in HW */
> +#define MAX_ODC_INTERNAL_BUF_HEIGHT	(1920)  /* 3356 in HW */
> +#define SIZE_ODC_INTERNAL_BUF \
> +	(MAX_ODC_INTERNAL_BUF_WIDTH * MAX_ODC_INTERNAL_BUF_HEIGHT * 3)
> +
> +#define MAX_DIS_INTERNAL_BUF_WIDTH	(2400)
> +#define MAX_DIS_INTERNAL_BUF_HEIGHT	(1360)
> +#define SIZE_DIS_INTERNAL_BUF \
> +	(MAX_DIS_INTERNAL_BUF_WIDTH * MAX_DIS_INTERNAL_BUF_HEIGHT * 2)
> +
> +#define MAX_3DNR_INTERNAL_BUF_WIDTH	(1920)
> +#define MAX_3DNR_INTERNAL_BUF_HEIGHT	(1088)
> +#define SIZE_DNR_INTERNAL_BUF \
> +	(MAX_3DNR_INTERNAL_BUF_WIDTH * MAX_3DNR_INTERNAL_BUF_HEIGHT * 2)
> +
> +#define NUM_ODC_INTERNAL_BUF		(2)
> +#define NUM_DIS_INTERNAL_BUF		(5)
> +#define NUM_DNR_INTERNAL_BUF		(2)
> +
> +#define FIMC_IS_FW_BASE_MASK		((1<<  26) - 1)
> +
> +#define FIMC_IS_NUM_COMPS		8
> +
> +enum pipeline_state {
> +	PIPELINE_INIT,
> +	PIPELINE_OPEN,
> +	PIPELINE_START,
> +	PIPELINE_RUN,
> +};
> +
> +enum is_components {
> +	IS_ISP,
> +	IS_DRC,
> +	IS_SCC,
> +	IS_ODC,
> +	IS_DIS,
> +	IS_TDNR,
> +	IS_SCP,
> +	IS_FD
> +};
> +
> +enum component_state {
> +	COMP_ENABLE,
> +	COMP_START,
> +	COMP_RUN
> +};
> +
> +struct fimc_is_pipeline {
> +	unsigned long		state;
> +	unsigned long		comp_state[FIMC_IS_NUM_COMPS];
> +	bool			force_down;
> +	unsigned int		instance;
> +	spinlock_t		slock_buf;
> +	unsigned long		slock_flags;
> +	wait_queue_head_t	wait_q;
> +	struct mutex		pipe_lock;
> +	struct mutex		pipe_scl_lock;
> +
> +	struct fimc_is_meminfo	*minfo;
> +	struct is_region	*is_region;
> +
> +	void			*is;
> +	struct fimc_is_sensor	*sensor;
> +	struct fimc_is_isp	isp;
> +	struct fimc_is_scaler	scaler[FIMC_IS_NUM_SCALERS];
> +
> +	unsigned int		fcount;
> +	unsigned int		sensor_width;
> +	unsigned int		sensor_height;
> +	unsigned int		isp_width;
> +	unsigned int		isp_height;
> +	unsigned int		scaler_width[FIMC_IS_NUM_SCALERS];
> +	unsigned int		scaler_height[FIMC_IS_NUM_SCALERS];
> +
> +	unsigned int		shot_paddr;
> +	unsigned int		shot_vaddr;
> +};

--
Thanks,
Sylwester

Re: [RFC v3 10/13] [media] exynos5-fimc-is: Add the hardware interface module

[Sylwester Nawrocki]

Hi Arun,

On 08/02/2013 05:02 PM, Arun Kumar K wrote:
> The hardware interface module finally sends the commands to the
> FIMC-IS firmware and runs the interrupt handler for getting the
> responses.
>
> Signed-off-by: Arun Kumar K<arun.kk@samsung.com>
> Signed-off-by: Kilyeon Im<kilyeon.im@samsung.com>
> ---
>   .../media/platform/exynos5-is/fimc-is-interface.c  |  861 ++++++++++++++++++++
>   .../media/platform/exynos5-is/fimc-is-interface.h  |  128 +++
>   2 files changed, 989 insertions(+)
>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-interface.c
>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-interface.h
>
> diff --git a/drivers/media/platform/exynos5-is/fimc-is-interface.c b/drivers/media/platform/exynos5-is/fimc-is-interface.c
> new file mode 100644
> index 0000000..12073be
> --- /dev/null
> +++ b/drivers/media/platform/exynos5-is/fimc-is-interface.c
> @@ -0,0 +1,861 @@
> +/*
> + * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
> +*
> + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
> + * Kil-yeon Lim<kilyeon.im@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include<linux/debugfs.h>
> +#include<linux/seq_file.h>
> +#include "fimc-is.h"
> +#include "fimc-is-cmd.h"
> +#include "fimc-is-regs.h"
> +
> +#define init_request_barrier(itf) mutex_init(&itf->request_barrier)
> +#define enter_request_barrier(itf) mutex_lock(&itf->request_barrier)
> +#define exit_request_barrier(itf) mutex_unlock(&itf->request_barrier)
> +
> +static inline void itf_get_cmd(struct fimc_is_interface *itf,
> +	struct fimc_is_msg *msg, unsigned int index)
> +{
> +	struct is_common_reg __iomem *com_regs = itf->com_regs;
> +
> +	memset(msg, 0, sizeof(*msg));
> +
> +	switch (index) {
> +	case INTR_GENERAL:
> +		msg->command = com_regs->ihcmd;
> +		msg->instance = com_regs->ihc_sensorid;

nit: How about doing something like:

		memcpy(msg->param, com_regs->ihc_param,
				4 * sizeof(mgs->iparam[0]);

for such repeated assignments ?

> +		msg->param[0] = com_regs->ihc_param[0];
> +		msg->param[1] = com_regs->ihc_param[1];
> +		msg->param[2] = com_regs->ihc_param[2];
> +		msg->param[3] = com_regs->ihc_param[3];
> +		break;
> +	case INTR_SCC_FDONE:
> +		msg->command = IHC_FRAME_DONE;
> +		msg->instance = com_regs->scc_sensor_id;
> +		msg->param[0] = com_regs->scc_param[0];
> +		msg->param[1] = com_regs->scc_param[1];
> +		msg->param[2] = com_regs->scc_param[2];
> +		break;
> +	case INTR_SCP_FDONE:
> +		msg->command = IHC_FRAME_DONE;
> +		msg->instance = com_regs->scp_sensor_id;
> +		msg->param[0] = com_regs->scp_param[0];
> +		msg->param[1] = com_regs->scp_param[1];
> +		msg->param[2] = com_regs->scp_param[2];
> +		break;
> +	case INTR_META_DONE:
> +		msg->command = IHC_FRAME_DONE;
> +		msg->instance = com_regs->meta_sensor_id;
> +		msg->param[0] = com_regs->meta_param1;
> +		break;
> +	case INTR_SHOT_DONE:
> +		msg->command = IHC_FRAME_DONE;
> +		msg->instance = com_regs->shot_sensor_id;
> +		msg->param[0] = com_regs->shot_param[0];
> +		msg->param[1] = com_regs->shot_param[1];
> +		break;
> +	default:
> +		pr_err("unknown command getting\n");

Would be nice to have at least function name in that log message.

> +		break;
> +	}
> +}
> +
> +static inline unsigned int itf_get_intr(struct fimc_is_interface *itf)
> +{
> +	unsigned int status;
> +	struct is_common_reg __iomem *com_regs = itf->com_regs;
> +
> +	status = readl(itf->regs + INTMSR1) | com_regs->ihcmd_iflag |
> +		com_regs->scc_iflag |
> +		com_regs->scp_iflag |
> +		com_regs->meta_iflag |
> +		com_regs->shot_iflag;
> +
> +	return status;
> +}
> +
> +static void itf_set_state(struct fimc_is_interface *itf,
> +		unsigned long state)
> +{
> +	unsigned long flags;
> +	spin_lock_irqsave(&itf->slock_state, flags);
> +	__set_bit(state,&itf->state);
> +	spin_unlock_irqrestore(&itf->slock_state, flags);
> +}
> +
> +static void itf_clr_state(struct fimc_is_interface *itf,
> +		unsigned long state)
> +{
> +	unsigned long flags;
> +	spin_lock_irqsave(&itf->slock_state, flags);
> +	__clear_bit(state,&itf->state);
> +	spin_unlock_irqrestore(&itf->slock_state, flags);
> +}
> +
> +static int itf_get_state(struct fimc_is_interface *itf,
> +		unsigned long state)
> +{
> +	int ret = 0;
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&itf->slock_state, flags);
> +	ret = test_bit(state,&itf->state);

Shouldn't it be __test_bit() ?

> +	spin_unlock_irqrestore(&itf->slock_state, flags);
> +	return ret;
> +}
> +
> +static void itf_init_wakeup(struct fimc_is_interface *itf)
> +{
> +	itf_set_state(itf, IS_IF_STATE_INIT);
> +	wake_up(&itf->irq_queue);
> +}
> +
> +void itf_busy_wakeup(struct fimc_is_interface *itf)
> +{
> +	itf_clr_state(itf, IS_IF_STATE_BUSY);
> +	wake_up(&itf->irq_queue);
> +}
> +
> +static int itf_wait_hw_ready(struct fimc_is_interface *itf)
> +{
> +	int t;
> +	for (t = TRY_RECV_AWARE_COUNT; t>= 0; t--) {
> +		unsigned int cfg = readl(itf->regs + INTMSR0);

> +		unsigned int status = INTMSR0_GET_INTMSD(0, cfg);
> +		if (!status)
> +			return 0;

You could simplify this to:

		if (INTMSR0_GET_INTMSD(0, cfg) == 0)
			return 0;

> +	}
> +	pr_err("INTMSR0's 0 bit is not cleared.\n");
> +	return -EINVAL;
> +}
> +
> +static int itf_wait_idlestate(struct fimc_is_interface *itf)
> +{
> +	int ret;
> +
> +	ret = wait_event_timeout(itf->irq_queue,
> +			!itf_get_state(itf, IS_IF_STATE_BUSY),
> +			FIMC_IS_COMMAND_TIMEOUT);
> +	if (!ret) {
> +		pr_err("timeout");

Sorry, this is a pretty useless log. It has neither function nor device
name appended. Just imagine other subsystems spitting such single "timeout"
messages. You can't even use grep reasonably with such messages.

> +		return -ETIME;
> +	}
> +	return 0;
> +}
> +
> +int fimc_is_itf_wait_init_state(struct fimc_is_interface *itf)
> +{
> +	int ret = 0;

Unneeded initialization.

> +	ret = wait_event_timeout(itf->irq_queue,
> +		itf_get_state(itf, IS_IF_STATE_INIT),
> +		FIMC_IS_STARTUP_TIMEOUT);
> +
> +	if (!ret) {
> +		pr_err("timeout\n");

Again, single word contextless log message.

> +		return -ETIME;
> +	}
> +	return 0;
> +}
> +
> +/* Send Host to IS command interrupt */
> +static void itf_hic_interrupt(struct fimc_is_interface *itf)
> +{
> +	writel(INTGR0_INTGD(0), itf->regs + INTGR0);
> +}
> +
> +static int itf_send_sensor_number(struct fimc_is_interface *itf)
> +{
> +	struct fimc_is_msg msg = {
> +		.command = ISR_DONE,
> +		.param[0] = IHC_GET_SENSOR_NUMBER,
> +		.param[1] = 1

.param = { IHC_GET_SENSOR_NUMBER, 1 },

?

> +	};
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&itf->slock, flags);
> +	itf->com_regs->hicmd = msg.command;
> +	itf->com_regs->hic_sensorid = msg.instance;
> +	itf->com_regs->hic_param[0] = msg.param[0];
> +	itf->com_regs->hic_param[1] = msg.param[1];
> +	itf->com_regs->hic_param[2] = msg.param[2];
> +	itf->com_regs->hic_param[3] = msg.param[3];

	memcpy(itf->com_regs->hic_param, msg.param,
			4 * sizeof(msg.param[0]));

?
> +	itf_hic_interrupt(itf);
> +	spin_unlock_irqrestore(&itf->slock, flags);
> +
> +	return 0;
> +}
> +
> +static int fimc_is_itf_set_cmd(struct fimc_is_interface *itf,
> +	struct fimc_is_msg *msg)
> +{
> +	int ret = 0;
> +	bool block_io;

To simplify the below switch statement you could initialize block_io
here:

	bool block_io = true;

> +	unsigned long flags;
> +
> +	enter_request_barrier(itf);
> +
> +	switch (msg->command) {
> +	case HIC_STREAM_ON:
> +		if (itf->streaming == IS_IF_STREAMING_ON)
> +			goto exit;
> +		else
> +			block_io = true;

And remove all those else\nblock_io = true; statements.

> +		break;
> +	case HIC_STREAM_OFF:
> +		if (itf->streaming == IS_IF_STREAMING_OFF)
> +			goto exit;
> +		else
> +			block_io = true;
> +		break;
> +	case HIC_PROCESS_START:
> +		if (itf->processing == IS_IF_PROCESSING_ON)
> +			goto exit;
> +		else
> +			block_io = true;
> +		break;
> +	case HIC_PROCESS_STOP:
> +		if (itf->processing == IS_IF_PROCESSING_OFF)
> +			goto exit;
> +		else
> +			block_io = true;
> +		break;
> +	case HIC_POWER_DOWN:
> +		if (itf->pdown_ready == IS_IF_POWER_DOWN_READY)
> +			goto exit;
> +		else
> +			block_io = true;
> +		break;
> +	case HIC_OPEN_SENSOR:
> +	case HIC_GET_SET_FILE_ADDR:
> +	case HIC_SET_PARAMETER:
> +	case HIC_PREVIEW_STILL:
> +	case HIC_GET_STATIC_METADATA:
> +	case HIC_SET_A5_MEM_ACCESS:
> +	case HIC_SET_CAM_CONTROL:
> +		block_io = true;
> +		break;
> +	case HIC_SHOT:
> +	case ISR_DONE:
> +		block_io = false;
> +		break;
> +	default:
> +		block_io = true;
> +		break;
> +	}
> +
> +	ret = itf_wait_hw_ready(itf);
> +	if (ret) {
> +		pr_err("waiting for ready is fail");

This message seems grammatically incorrect, perhaps:

	pr_err("%s: itf_wait_hw_ready() failed", __func__);

?
> +		ret = -EBUSY;
> +		goto exit;
> +	}
> +
> +	spin_lock_irqsave(&itf->slock, flags);
> +	itf_set_state(itf, IS_IF_STATE_BUSY);
> +	itf->com_regs->hicmd = msg->command;
> +	itf->com_regs->hic_sensorid = msg->instance;
> +	itf->com_regs->hic_param[0] = msg->param[0];
> +	itf->com_regs->hic_param[1] = msg->param[1];
> +	itf->com_regs->hic_param[2] = msg->param[2];
> +	itf->com_regs->hic_param[3] = msg->param[3];

	memcpy(itf->com_regs->hic_param, msg->param,
				4 * sizeof(msg->param[0]));
?
> +	itf_hic_interrupt(itf);
> +	spin_unlock_irqrestore(&itf->slock, flags);
> +
> +	if (!block_io)
> +		goto exit;
> +
> +	ret = itf_wait_idlestate(itf);
> +	if (ret) {
> +		pr_err("%d command is timeout\n", msg->command);
> +		itf_clr_state(itf, IS_IF_STATE_BUSY);
> +		ret = -ETIME;
> +		goto exit;
> +	}
> +
> +	if (itf->reply.command == ISR_DONE) {
> +		switch (msg->command) {
> +		case HIC_STREAM_ON:
> +			itf->streaming = IS_IF_STREAMING_ON;
> +			break;
> +		case HIC_STREAM_OFF:
> +			itf->streaming = IS_IF_STREAMING_OFF;
> +			break;
> +		case HIC_PROCESS_START:
> +			itf->processing = IS_IF_PROCESSING_ON;
> +			break;
> +		case HIC_PROCESS_STOP:
> +			itf->processing = IS_IF_PROCESSING_OFF;
> +			break;
> +		case HIC_POWER_DOWN:
> +			itf->pdown_ready = IS_IF_POWER_DOWN_READY;
> +			break;
> +		case HIC_OPEN_SENSOR:
> +			if (itf->reply.param[0] == HIC_POWER_DOWN) {
> +				pr_err("firmware power down");

Add function name prefix.

> +				itf->pdown_ready = IS_IF_POWER_DOWN_READY;
> +				ret = -ECANCELED;
> +				goto exit;
> +			} else
> +				itf->pdown_ready = IS_IF_POWER_DOWN_NREADY;
> +			break;
> +		default:
> +			break;
> +		}
> +	} else {
> +		pr_err("ISR_NDONE is occured");

s/is occured/occured.

> +		ret = -EINVAL;
> +	}
> +exit:
> +	exit_request_barrier(itf);
> +
> +	if (ret)
> +		pr_err("Error returned from FW. See debugfs for error log\n");
> +
> +

nit: Superfluous empty line.

> +	return ret;
> +}
> +
> +static int fimc_is_itf_set_cmd_shot(struct fimc_is_interface *itf,
> +		struct fimc_is_msg *msg)
> +{
> +	int ret = 0;

You could remove this variable and just return 0 below. Or perhaps
this function should be returning void.

> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&itf->slock, flags);
> +	itf->com_regs->hicmd = msg->command;
> +	itf->com_regs->hic_sensorid = msg->instance;

> +	itf->com_regs->hic_param[0] = msg->param[0];
> +	itf->com_regs->hic_param[1] = msg->param[1];
> +	itf->com_regs->hic_param[2] = msg->param[2];
> +	itf->com_regs->hic_param[3] = msg->param[3];

	memcpy(itf->com_regs->hic_param, msg->param,
				4 * sizeof(msg->param[0]));
?
> +	itf->com_regs->fcount = msg->param[2];
> +	itf_hic_interrupt(itf);
> +	spin_unlock_irqrestore(&itf->slock, flags);
> +
> +	return ret;
> +}
> +
> +static void itf_handle_general(struct fimc_is_interface *itf,
> +		struct fimc_is_msg *msg)
> +{
> +	bool is_blocking = true;
> +
> +	switch (msg->command) {
> +
> +	case IHC_GET_SENSOR_NUMBER:
> +		pr_debug("IS version : %d.%d\n",
> +			ISDRV_VERSION, msg->param[0]);
> +		/* Respond with sensor number */
> +		itf_send_sensor_number(itf);
> +		itf_init_wakeup(itf);
> +		break;
> +	case ISR_DONE:
> +		switch (msg->param[0]) {
> +		case HIC_OPEN_SENSOR:
> +			pr_debug("open done\n");
> +			break;
> +		case HIC_GET_SET_FILE_ADDR:
> +			pr_debug("saddr(%p) done\n",
> +				(void *)msg->param[1]);
> +			break;
> +		case HIC_LOAD_SET_FILE:
> +			pr_debug("setfile done\n");
> +			break;
> +		case HIC_SET_A5_MEM_ACCESS:
> +			pr_debug("cfgmem done\n");
> +			break;
> +		case HIC_PROCESS_START:
> +			pr_debug("process_on done\n");
> +			break;
> +		case HIC_PROCESS_STOP:
> +			pr_debug("process_off done\n");
> +			break;
> +		case HIC_STREAM_ON:
> +			pr_debug("stream_on done\n");
> +			break;
> +		case HIC_STREAM_OFF:
> +			pr_debug("stream_off done\n");
> +			break;
> +		case HIC_SET_PARAMETER:
> +			pr_debug("s_param done\n");
> +			break;
> +		case HIC_GET_STATIC_METADATA:
> +			pr_debug("g_capability done\n");
> +			break;
> +		case HIC_PREVIEW_STILL:
> +			pr_debug("a_param(%dx%d) done\n",
> +				msg->param[1],
> +				msg->param[2]);

nit: Couldn't that msg->param* be in one line instead ?

> +			break;
> +		case HIC_POWER_DOWN:
> +			pr_debug("powerdown done\n");
> +			break;
> +		/*non-blocking command*/

nit: Add space after /* and before */.

> +		case HIC_SHOT:
> +			is_blocking = false;
> +			pr_err("shot done is not acceptable\n");
> +			break;
> +		case HIC_SET_CAM_CONTROL:
> +			is_blocking = false;
> +			pr_err("camctrl is not acceptable\n");
> +			break;
> +		default:
> +			is_blocking = false;
> +			pr_err("unknown done is invokded\n");
> +			break;
> +		}
> +		break;
> +	case ISR_NDONE:
> +		switch (msg->param[0]) {
> +		case HIC_SHOT:
> +			is_blocking = false;
> +			pr_err("shot NOT done is not acceptable\n");
> +			break;
> +		case HIC_SET_CAM_CONTROL:
> +			is_blocking = false;
> +			pr_debug("camctrl NOT done\n");
> +			break;
> +		case HIC_SET_PARAMETER:
> +			pr_err("s_param NOT done\n");
> +			pr_err("param2 : 0x%08X\n", msg->param[1]);
> +			pr_err("param3 : 0x%08X\n", msg->param[2]);
> +			pr_err("param4 : 0x%08X\n", msg->param[3]);
> +			break;
> +		default:
> +			pr_err("a command(%d) not done", msg->param[0]);
> +			break;
> +		}
> +		break;
> +	case IHC_SET_FACE_MARK:
> +		is_blocking = false;
> +		pr_err("FACE_MARK(%d,%d,%d) is not acceptable\n",
> +			msg->param[0],
> +			msg->param[1],
> +			msg->param[2]);

Ditto.

> +		break;
> +	case IHC_AA_DONE:
> +		is_blocking = false;
> +		pr_err("AA_DONE(%d,%d,%d) is not acceptable\n",
> +			msg->param[0],
> +			msg->param[1],
> +			msg->param[2]);

Ditto.

> +		break;
> +	case IHC_FLASH_READY:
> +		is_blocking = false;
> +		pr_err("IHC_FLASH_READY is not acceptable");
> +		break;
> +	case IHC_NOT_READY:
> +		is_blocking = false;
> +		pr_err("IHC_NOT_READY is occured, need reset");
> +		break;
> +	default:
> +		is_blocking = false;
> +		pr_err("func_general unknown(0x%08X) end\n", msg->command);

This message is a bit weird, maybe:

		pr_err("%s: unknown (#%08X) command\n", __func__, msg->command);

?
> +		break;
> +	}
> +
> +	if (is_blocking) {
> +		memcpy(&itf->reply, msg,
> +			sizeof(struct fimc_is_msg));

Unnecessarily broken into two lines ?

> +		itf_busy_wakeup(itf);
> +	}
> +}
> +
> +static void itf_handle_scaler_done(struct fimc_is_interface *itf,
> +		struct fimc_is_msg *msg)
> +{
> +	struct fimc_is *is = fimc_interface_to_is(itf);
> +	struct fimc_is_pipeline *pipeline =&is->pipeline[msg->instance];
> +	struct fimc_is_buf *buf;
> +	struct fimc_is_scaler *scl;
> +	const struct fimc_is_fmt *fmt;
> +	struct timeval *tv;
> +	struct timespec ts;
> +	unsigned int wh, i;
> +	unsigned int fcount = msg->param[0];
> +	unsigned long *comp_state;
> +
> +	if (msg->param[3] == SCALER_SCC) {
> +		scl =&pipeline->scaler[SCALER_SCC];
> +		comp_state =&pipeline->comp_state[IS_SCC];
> +	} else {
> +		scl =&pipeline->scaler[SCALER_SCP];
> +		comp_state =&pipeline->comp_state[IS_SCP];
> +	}
> +
> +	fmt = scl->fmt;
> +
> +	fimc_is_pipeline_buf_lock(pipeline);
> +	if (!list_empty(&scl->run_queue)) {
> +
> +		wh = scl->width * scl->height;
> +		buf = fimc_is_scaler_run_queue_get(scl);
> +		for (i = 0; i<  fmt->num_planes; i++) {
> +			vb2_set_plane_payload(buf->vb, i,
> +					(wh * fmt->depth[i]) / 8);
> +		}

CodingStyle: Superfluous braces.

> +		/* Set timestamp */
> +		ktime_get_ts(&ts);
> +		tv =&buf->vb->v4l2_buf.timestamp;
> +		tv->tv_sec = ts.tv_sec;
> +		tv->tv_usec = ts.tv_nsec / NSEC_PER_USEC;
> +		buf->vb->v4l2_buf.sequence = fcount;
> +
> +		pr_debug("SCP buffer done %d/%d\n",
> +				msg->param[0], msg->param[2]);
> +		vb2_buffer_done(buf->vb, VB2_BUF_STATE_DONE);
> +	}
> +	fimc_is_pipeline_buf_unlock(pipeline);
> +	clear_bit(COMP_RUN, comp_state);
> +	wake_up(&scl->event_q);
> +}
> +
> +static void itf_handle_shot_done(struct fimc_is_interface *itf,
> +		struct fimc_is_msg *msg)
> +{
> +	struct fimc_is *is = fimc_interface_to_is(itf);
> +	struct fimc_is_pipeline *pipeline =&is->pipeline[msg->instance];
> +	unsigned int status = msg->param[1];
> +	struct fimc_is_buf *bayer_buf;
> +	int ret;
> +
> +	if (status != ISR_DONE)
> +		pr_err("Shot done is invalid(0x%08X)\n", status);
> +
> +	/* DQ the bayer input buffer */
> +	fimc_is_pipeline_buf_lock(pipeline);
> +	bayer_buf = fimc_is_isp_run_queue_get(&pipeline->isp);
> +	if (bayer_buf) {
> +		vb2_buffer_done(bayer_buf->vb, VB2_BUF_STATE_DONE);
> +		pr_debug("Bayer buffer done.\n");
> +	}
> +	fimc_is_pipeline_buf_unlock(pipeline);
> +
> +	/* Clear state&  call shot again */
> +	clear_bit(PIPELINE_RUN,&pipeline->state);
> +
> +	ret = fimc_is_pipeline_shot(pipeline);
> +	if (ret)
> +		pr_err("Shot failed\n");
> +}
> +
> +/* Main FIMC-IS interrupt handler */
> +static irqreturn_t itf_irq_handler(int irq, void *data)
> +{
> +	struct fimc_is_interface *itf;
> +	struct fimc_is_msg msg;
> +	unsigned int status, intr;
> +	struct is_common_reg __iomem *com_regs;
> +
> +	itf = (struct fimc_is_interface *)data;

Unnecessary casting from void *. You could well make this assignment
at the declaration time above.

> +	com_regs = itf->com_regs;
> +	status = itf_get_intr(itf);
> +
> +	for (intr = INTR_GENERAL; intr<  INTR_MAX_MAP; intr++) {
> +
> +		if (status&  (1<<  intr)) {

nit: you could also use BIT() macro (from <linux/bitops.h>):

		if (status & BIT(intr))

> +			itf_get_cmd(itf,&msg, intr);
> +
> +			switch (intr) {
> +			case INTR_GENERAL:
> +				itf_handle_general(itf,&msg);
> +				com_regs->ihcmd_iflag = 0;
> +				break;
> +			case INTR_SHOT_DONE:
> +				itf_handle_shot_done(itf,&msg);
> +				com_regs->shot_iflag = 0;
> +				break;
> +			case INTR_SCC_FDONE:
> +				msg.param[3] = SCALER_SCC;
> +				itf_handle_scaler_done(itf,&msg);
> +				com_regs->scc_iflag = 0;
> +				break;
> +			case INTR_SCP_FDONE:
> +				msg.param[3] = SCALER_SCP;
> +				itf_handle_scaler_done(itf,&msg);
> +				com_regs->scp_iflag = 0;
> +				break;
> +			case INTR_META_DONE:
> +				com_regs->meta_iflag = 0;
> +				break;
> +			}
> +			status&= ~(1<<  intr);
> +			writel((1<<  intr), itf->regs + INTCR1);

Ditto, s/(1 << intr)/BIT(intr).

> +		}
> +	}
> +
> +	if (status != 0)
> +		pr_err("status is NOT all clear(0x%08X)", status);
> +
> +	return IRQ_HANDLED;
> +}
> +
> +int fimc_is_itf_open_sensor(struct fimc_is_interface *itf,
> +		unsigned int instance,
> +		unsigned int sensor_id,
> +		unsigned int i2c_channel,
> +		unsigned int sensor_ext)
> +{
> +	struct fimc_is_msg msg = {0,};

nit: a colon is not really needed here and in other functions below.

> +	msg.command = HIC_OPEN_SENSOR;
> +	msg.instance = instance;
> +	msg.param[0] = sensor_id;
> +	msg.param[1] = i2c_channel;
> +	msg.param[2] = sensor_ext;
> +
> +	return fimc_is_itf_set_cmd(itf,&msg);
> +}
> +
> +int fimc_is_itf_get_setfile_addr(struct fimc_is_interface *itf,
> +		unsigned int instance, unsigned int *setfile_addr)
> +{
> +	int ret;

> +	struct fimc_is_msg msg = {0,};
> +
> +	msg.command = HIC_GET_SET_FILE_ADDR;
> +	msg.instance = instance;

This could also written as:

	struct fimc_is_msg msg = {
		.command = HIC_GET_SET_FILE_ADDR,
		.instance = instance,
	};

> +	ret = fimc_is_itf_set_cmd(itf,&msg);
> +	*setfile_addr = itf->reply.param[1];
> +
> +	return ret;
> +}
> +
> +int fimc_is_itf_load_setfile(struct fimc_is_interface *itf,
> +		unsigned int instance)
> +{
> +	struct fimc_is_msg msg = {0,};
> +
> +	msg.command = HIC_LOAD_SET_FILE;
> +	msg.instance = instance;
> +
> +	return fimc_is_itf_set_cmd(itf,&msg);
> +}
> +
> +int fimc_is_itf_stream_on(struct fimc_is_interface *itf,
> +		unsigned int instance)
> +{
> +	struct fimc_is_msg msg = {0,};
> +
> +	msg.command = HIC_STREAM_ON;
> +	msg.instance = instance;
> +
> +	return fimc_is_itf_set_cmd(itf,&msg);
> +}
> +
> +int fimc_is_itf_stream_off(struct fimc_is_interface *itf,
> +		unsigned int instance)
> +{
> +	struct fimc_is_msg msg = {0,};
> +
> +	msg.command = HIC_STREAM_OFF;
> +	msg.instance = instance;
> +
> +	return fimc_is_itf_set_cmd(itf,&msg);
> +}
> +
> +int fimc_is_itf_process_on(struct fimc_is_interface *itf,
> +		unsigned int instance)
> +{
> +	struct fimc_is_msg msg = {0,};
> +
> +	msg.command = HIC_PROCESS_START;
> +	msg.instance = instance;
> +
> +	return fimc_is_itf_set_cmd(itf,&msg);
> +}
> +
> +int fimc_is_itf_process_off(struct fimc_is_interface *itf,
> +		unsigned int instance)
> +{
> +	struct fimc_is_msg msg = {0,};
> +
> +	msg.command = HIC_PROCESS_STOP;
> +	msg.instance = instance;
> +
> +	return fimc_is_itf_set_cmd(itf,&msg);
> +}
> +
> +int fimc_is_itf_set_param(struct fimc_is_interface *itf,
> +		unsigned int instance,
> +		unsigned int indexes,
> +		unsigned int lindex,
> +		unsigned int hindex)
> +{
> +	struct fimc_is_msg msg = {0,};
> +
> +	msg.command = HIC_SET_PARAMETER;
> +	msg.instance = instance;
> +	msg.param[0] = ISS_PREVIEW_STILL;
> +	msg.param[1] = indexes;
> +	msg.param[2] = lindex;
> +	msg.param[3] = hindex;
> +
> +	return fimc_is_itf_set_cmd(itf,&msg);
> +}
> +
> +int fimc_is_itf_preview_still(struct fimc_is_interface *itf,
> +		unsigned int instance)
> +{
> +	struct fimc_is_msg msg = {0,};
> +
> +	msg.command = HIC_PREVIEW_STILL;
> +	msg.instance = instance;
> +
> +	return fimc_is_itf_set_cmd(itf,&msg);
> +}
> +
> +int fimc_is_itf_get_capability(struct fimc_is_interface *itf,
> +	unsigned int instance, unsigned int address)
> +{
> +	struct fimc_is_msg msg = {0,};
> +
> +	msg.command = HIC_GET_STATIC_METADATA;
> +	msg.instance = instance;
> +	msg.param[0] = address;
> +
> +	return fimc_is_itf_set_cmd(itf,&msg);
> +}
> +
> +int fimc_is_itf_cfg_mem(struct fimc_is_interface *itf,
> +		unsigned int instance, unsigned int address,
> +		unsigned int size)
> +{
> +	struct fimc_is_msg msg = {0,};
> +
> +	msg.command = HIC_SET_A5_MEM_ACCESS;
> +	msg.instance = instance;
> +	msg.param[0] = address;
> +	msg.param[1] = size;
> +
> +	return fimc_is_itf_set_cmd(itf,&msg);
> +}
> +
> +int fimc_is_itf_shot_nblk(struct fimc_is_interface *itf,
> +		unsigned int instance, unsigned int bayer,
> +		unsigned int shot, unsigned int fcount, unsigned int rcount)
> +{
> +	struct fimc_is_msg msg = {0,};
> +
> +	msg.command = HIC_SHOT;
> +	msg.instance = instance;
> +	msg.param[0] = bayer;
> +	msg.param[1] = shot;
> +	msg.param[2] = fcount;
> +	msg.param[3] = rcount;

nit: And this:

	struct fimc_is_msg msg = {
		.command = HIC_SHOT,
		.instance = instance,
		.param = { bayer, shot, fcount, rcount },
	};

It's more compact this way and still has a good readability IMHO.

> +	return fimc_is_itf_set_cmd_shot(itf,&msg);
> +}
> +
> +int fimc_is_itf_power_down(struct fimc_is_interface *itf,
> +		unsigned int instance)
> +{
> +	struct fimc_is_msg msg = {0,};
> +	int ret;
> +
> +	msg.command = HIC_POWER_DOWN;
> +	msg.instance = instance;
> +
> +	ret = fimc_is_itf_set_cmd(itf,&msg);
> +	itf_clr_state(itf, IS_IF_STATE_INIT);
> +
> +	return ret;
> +}
> +
> +/* Debugfs for showing FW debug messages */
> +static int fimc_is_log_show(struct seq_file *s, void *data)
> +{
> +	struct fimc_is_interface *itf = s->private;
> +	struct fimc_is *is = fimc_interface_to_is(itf);
> +
> +	const u8 *buf = (u8 *) (is->minfo.fw_vaddr + DEBUG_OFFSET);
> +
> +	if (is->minfo.fw_vaddr == 0) {
> +		pr_err("Firmware memory is not initialized\n");

dev_err() !

> +		return -EIO;
> +	}
> +
> +	seq_printf(s, "%s\n", buf);
> +	return 0;
> +}
> +
> +static int fimc_is_debugfs_open(struct inode *inode, struct file *file)
> +{
> +	return single_open(file, fimc_is_log_show, inode->i_private);
> +}
> +
> +static const struct file_operations fimc_is_debugfs_fops = {
> +	.open		= fimc_is_debugfs_open,
> +	.read		= seq_read,
> +	.llseek		= seq_lseek,
> +	.release	= single_release,
> +};
> +
> +static void fimc_is_debugfs_remove(struct fimc_is_interface *itf)
> +{
> +	debugfs_remove(itf->debugfs_entry);
> +	itf->debugfs_entry = NULL;
> +}
> +
> +static int fimc_is_debugfs_create(struct fimc_is_interface *itf)
> +{
> +	struct dentry *dentry;
> +
> +	itf->debugfs_entry = debugfs_create_dir("fimc_is", NULL);
> +
> +	dentry = debugfs_create_file("fw_log", S_IRUGO, itf->debugfs_entry,
> +					itf,&fimc_is_debugfs_fops);
> +	if (!dentry)
> +		fimc_is_debugfs_remove(itf);
> +
> +	return itf->debugfs_entry == NULL ? -EIO : 0;
> +}
> +
> +int fimc_is_interface_init(struct fimc_is_interface *itf,
> +		void __iomem *regs, int irq)
> +{
> +	struct fimc_is *is = fimc_interface_to_is(itf);
> +	struct device *dev =&is->pdev->dev;
> +	int ret;
> +
> +	if (!regs || !irq) {
> +		pr_err("Invalid args\n");

dev_err()

> +		return -EINVAL;
> +	}
> +
> +	itf->regs = regs;
> +	itf->com_regs = (struct is_common_reg *)(regs + ISSR(0));
> +
> +	init_waitqueue_head(&itf->irq_queue);
> +	spin_lock_init(&itf->slock_state);
> +	spin_lock_init(&itf->slock);
> +
> +	/* Register interrupt handler */
> +	ret = devm_request_irq(dev, irq, itf_irq_handler,
> +			       0, dev_name(dev), itf);
> +	if (ret) {
> +		dev_err(dev, "Failed to install irq (%d)\n", ret);
> +		return -EINVAL;
> +	}
> +
> +	/* Initialize context vars */
> +	itf->streaming = IS_IF_STREAMING_INIT;
> +	itf->processing = IS_IF_PROCESSING_INIT;
> +	itf->pdown_ready = IS_IF_POWER_DOWN_READY;
> +	itf->debug_cnt = 0;
> +	init_request_barrier(itf);
> +
> +	/* Debugfs for FW debug log */
> +	fimc_is_debugfs_create(itf);
> +
> +	return 0;
> +}
> diff --git a/drivers/media/platform/exynos5-is/fimc-is-interface.h b/drivers/media/platform/exynos5-is/fimc-is-interface.h
> new file mode 100644
> index 0000000..faf86d8
> --- /dev/null
> +++ b/drivers/media/platform/exynos5-is/fimc-is-interface.h
> @@ -0,0 +1,128 @@
> +/*
> + * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
> + *
> + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
> + *  Arun Kumar K<arun.kk@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +#ifndef FIMC_IS_INTERFACE_H_
> +#define FIMC_IS_INTERFACE_H_
> +
> +#include "fimc-is-core.h"
> +
> +#define TRY_RECV_AWARE_COUNT    100
> +
> +#define ISDRV_VERSION		111
> +
> +#define LOWBIT_OF(num)  (num>= 32 ? 0 : (unsigned int)1<<num)
> +#define HIGHBIT_OF(num) (num>= 32 ? (unsigned int)1<<(num-32) : 0)

These macros should not be needed. Please see my comments to patch 09/13.

> +enum interrupt_map {
> +	INTR_GENERAL            = 0,
> +	INTR_ISP_FDONE          = 1,
> +	INTR_SCC_FDONE          = 2,
> +	INTR_DNR_FDONE          = 3,
> +	INTR_SCP_FDONE          = 4,
> +	INTR_ISP_YUV_DONE	= 5,
> +	INTR_META_DONE          = 6,
> +	INTR_SHOT_DONE          = 7,
> +	INTR_MAX_MAP
> +};
> +
> +enum fimc_is_interface_state {
> +	IS_IF_STATE_INIT,
> +	IS_IF_STATE_OPEN,
> +	IS_IF_STATE_START,
> +	IS_IF_STATE_BUSY
> +};
> +
> +enum streaming_state {
> +	IS_IF_STREAMING_INIT,
> +	IS_IF_STREAMING_OFF,
> +	IS_IF_STREAMING_ON
> +};
> +
> +enum processing_state {
> +	IS_IF_PROCESSING_INIT,
> +	IS_IF_PROCESSING_OFF,
> +	IS_IF_PROCESSING_ON
> +};
> +
> +enum pdown_ready_state {
> +	IS_IF_POWER_DOWN_READY,
> +	IS_IF_POWER_DOWN_NREADY
> +};
> +
> +struct fimc_is_msg {
> +	unsigned int	id;
> +	unsigned int	command;
> +	unsigned int	instance;
> +	unsigned int	param[4];

Shouldn't all these fields be of u32 type instead ?

> +};
> +
> +struct fimc_is_interface {
> +

Superfluous empty line.

> +	unsigned long			state;
> +
> +	void __iomem			*regs;
> +	struct is_common_reg __iomem    *com_regs;
> +	spinlock_t			slock;
> +	spinlock_t			slock_state;

Locking needs to be documented. A short comment on how these
spinlocks are used would do.

> +	wait_queue_head_t		irq_queue;
> +
> +	spinlock_t			process_barrier;
> +	struct mutex			request_barrier;

Ditto.

> +	enum streaming_state		streaming;
> +	enum processing_state		processing;
> +	enum pdown_ready_state		pdown_ready;
> +
> +	struct fimc_is_msg		reply;
> +
> +	int				debug_cnt;
> +	struct dentry                   *debugfs_entry;
> +
> +};

--
Thanks,
Sylwester

Re: [RFC v3 00/13] Exynos5 IS driver

[Arun Kumar K]

Hi Sylwester,

On Sun, Aug 4, 2013 at 3:10 AM, Sylwester Nawrocki
<sylvester.nawrocki@gmail.com> wrote:
> Hi Arun,
>
>
> On 08/02/2013 05:02 PM, Arun Kumar K wrote:
>>
>> The patch series add support for Exynos5 camera subsystem. It
>> re-uses mipi-csis and fimc-lite from exynos4-is and adds a new
>> media device and fimc-is device drivers for exynos5.
>> The media device supports asynchronos subdev registration for the
>> fimc-is sensors and is based on the patch series from Sylwester
>> for exynos4-is [1].
>>
>> [1]http://www.mail-archive.com/linux-media@vger.kernel.org/msg64653.html
>>
>> Changes from v2
>> ---------------
>> - Added exynos5 media device driver from Shaik to this series
>> - Added ISP pipeline support in media device driver
>> - Based on Sylwester's latest exynos4-is development
>> - Asynchronos registration of sensor subdevs
>> - Made independent IS-sensor support
>> - Add s5k4e5 sensor driver
>> - Addressed review comments from Sylwester, Hans, Andrzej, Sachin
>
>
> This is starting to look pretty good to me, I hope we can merge this
> patch set for v3.12. Let use coming two weeks for one or two review/
> corrections round.

Sure. I will address the review comments quickly and send v4 version.

> In the meantime I've done numerous fixes to the patch series [1],
> especially the clock provider code was pretty buggy on the clean up
> paths. Let's go through the patches and see what can be improved yet.
>

Ok. Is the updated version available in your git repository
git://linuxtv.org/snawrocki/samsung.git?

Regards
Arun

Re: [RFC v3 01/13] [media] exynos5-is: Adding media device driver for exynos5

[Sachin Kamat]

On 2 August 2013 20:32, Arun Kumar K <arun.kk@samsung.com> wrote:
> From: Shaik Ameer Basha <shaik.ameer@samsung.com>
>
> This patch adds support for media device for EXYNOS5 SoCs.
> The current media device supports the following ips to connect
> through the media controller framework.
>
> * MIPI-CSIS
>   Support interconnection(subdev interface) between devices
>
> * FIMC-LITE
>   Support capture interface from device(Sensor, MIPI-CSIS) to memory
>   Support interconnection(subdev interface) between devices
>
> * FIMC-IS
>   Camera post-processing IP having multiple sub-nodes.
>
> G-Scaler will be added later to the current media device.
>
> The media device creates two kinds of pipelines for connecting
> the above mentioned IPs.
> The pipeline0 is uses Sensor, MIPI-CSIS and FIMC-LITE which captures
> image data and dumps to memory.
> Pipeline1 uses FIMC-IS components for doing post-processing
> operations on the captured image and give scaled YUV output.
>
> Pipeline0
>   +--------+     +-----------+     +-----------+     +--------+
>   | Sensor | --> | MIPI-CSIS | --> | FIMC-LITE | --> | Memory |
>   +--------+     +-----------+     +-----------+     +--------+
>
> Pipeline1
>  +--------+      +--------+     +-----------+     +-----------+
>  | Memory | -->  |  ISP   | --> |    SCC    | --> |    SCP    |
>  +--------+      +--------+     +-----------+     +-----------+
>
> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
> Signed-off-by: Arun Kumar K <arun.kk@samsung.com>

[snip]

> +
> +Common 'camera' node
> +--------------------
> +
> +Required properties:
> +
> +- compatible   : must be "samsung,exynos5-fimc", "simple-bus"

I am not sure if this point was discusssed during the previous
versions. "samsung,exynos5-fimc" seems a bit generic.
The compatible string should generally point to a specific SoC (the
first one to have this IP), something like "samsung,exynos5250-fimc".

> +- clocks       : list of clock specifiers, corresponding to entries in
> +                 the clock-names property;
> +- clock-names  : must contain "sclk_cam0", "sclk_cam1" entries,
> +                 matching entries in the clocks property.
> +

[snip]

> +Example:
> +
> +       aliases {
> +               fimc-lite0 = &fimc_lite_0
> +       };
> +
> +       /* Parallel bus IF sensor */
> +       i2c_0: i2c@13860000 {
> +               s5k6aa: sensor@3c {
> +                       compatible = "samsung,s5k6aafx";
> +                       reg = <0x3c>;
> +                       vddio-supply = <...>;
> +
> +                       clock-frequency = <24000000>;
> +                       clocks = <...>;
> +                       clock-names = "mclk";
> +
> +                       port {
> +                               s5k6aa_ep: endpoint {
> +                                       remote-endpoint = <&fimc0_ep>;
> +                                       bus-width = <8>;
> +                                       hsync-active = <0>;
> +                                       vsync-active = <1>;
> +                                       pclk-sample = <1>;
> +                               };
> +                       };
> +               };
> +       };
> +
> +       /* MIPI CSI-2 bus IF sensor */
> +       s5c73m3: sensor@0x1a {

0x not needed.

-- 
With warm regards,
Sachin

Re: [RFC v3 01/13] [media] exynos5-is: Adding media device driver for exynos5

[Arun Kumar K]

Hi Sylwester,

Thank you for the review.
Will address all your review comments.
Some responses below:

[snip]
>> +
>> +static int fimc_md_register_sensor_entities(struct fimc_md *fmd)
>> +{
>> +       struct device_node *of_node = fmd->pdev->dev.of_node;
>> +       int ret;
>> +
>> +       /*
>> +        * Runtime resume one of the FIMC entities to make sure
>> +        * the sclk_cam clocks are not globally disabled.
>
>
> It's a bit mysterious to me, is this requirement still valid on Exynos5 ?
> I glanced over the Exynos5250 datasheet and there seem to be no sclk_cam?
> clocks dependency on any of GScaler clocks. Maybe you don't need a clock
> provider in this driver, perhaps sensor drivers could use sclk_cam clocks
> directly, assigned through dts ?
>

Yes these clocks can be directly exposed via dt.
I will drop clock provider from this driver.

[snip]

>> +/*
>> + * The peripheral sensor clock management.
>> + */
>> +static void fimc_md_put_clocks(struct fimc_md *fmd)
>> +{
>> +       int i = FIMC_MAX_CAMCLKS;
>> +
>> +       while (--i>= 0) {
>> +               if (IS_ERR(fmd->camclk[i].clock))
>> +                       continue;
>> +               clk_put(fmd->camclk[i].clock);
>> +               fmd->camclk[i].clock = ERR_PTR(-EINVAL);
>> +       }
>
>
> Please double check if you need this sclk_cam clocks handling. We could
> simply add a requirement that this driver supports only sensor subdevs
> through the v4l2-async API and which controls their clock themselves.
>

sclk_cam* handling can be removed and be done from respective
sensors. But I think the sclk_bayer handling needs to be retained in the
media driver.

>> +}
>> +
>> +static int fimc_md_get_clocks(struct fimc_md *fmd)
>> +{
>> +       struct device *dev = NULL;
>> +       char clk_name[32];
>> +       struct clk *clock;
>> +       int i, ret = 0;
>> +
>> +       for (i = 0; i<  FIMC_MAX_CAMCLKS; i++)
>> +               fmd->camclk[i].clock = ERR_PTR(-EINVAL);
>> +
>> +       if (fmd->pdev->dev.of_node)
>> +               dev =&fmd->pdev->dev;
>> +
>> +       for (i = 0; i<  SCLK_BAYER; i++) {
>> +               snprintf(clk_name, sizeof(clk_name), "sclk_cam%u", i);
>> +               clock = clk_get(dev, clk_name);
>> +
>> +               if (IS_ERR(clock)) {
>> +                       dev_err(&fmd->pdev->dev, "Failed to get clock:
>> %s\n",
>> +                                                               clk_name);
>> +                       ret = PTR_ERR(clock);
>> +                       break;
>> +               }
>> +               fmd->camclk[i].clock = clock;
>> +       }
>> +       if (ret)
>> +               fimc_md_put_clocks(fmd);
>> +
>> +       /* Prepare bayer clk */
>> +       clock = clk_get(dev, "sclk_bayer");
>> +
>> +       if (IS_ERR(clock)) {
>> +               dev_err(&fmd->pdev->dev, "Failed to get clock: %s\n",
>> +                                                       clk_name);
>
>
> Wrong error message.
>
>> +               ret = PTR_ERR(clock);
>> +               goto err_exit;
>> +       }
>> +       ret = clk_prepare(clock);
>> +       if (ret<  0) {
>> +               clk_put(clock);
>> +               fmd->camclk[SCLK_BAYER].clock = ERR_PTR(-EINVAL);
>> +               goto err_exit;
>> +       }
>> +       fmd->camclk[SCLK_BAYER].clock = clock;
>
>
> Could you explain a bit how is this SCLK_BAYER clock used ? Is it routed
> to external image sensor, or is it used only inside an SoC ?
>

It is not defined properly in the manual, but I suppose its the bus clock
for the bayer rgb data bus. So for proper sensor functionality, we need this
sclk_bayer in addition to the external sensor clks (sclk_cam*). Isn't
exynos5 media driver is the best place to handle such clocks?

>> +       return 0;
>> +err_exit:
>> +       fimc_md_put_clocks(fmd);
>> +       return ret;
>> +}
>> +

Regards
Arun

Re: [RFC v3 01/13] [media] exynos5-is: Adding media device driver for exynos5

[Arun Kumar K]

Hi Sachin,

Thank you for the review.

On Mon, Aug 5, 2013 at 10:51 AM, Sachin Kamat <sachin.kamat@linaro.org> wrote:
> On 2 August 2013 20:32, Arun Kumar K <arun.kk@samsung.com> wrote:
>> From: Shaik Ameer Basha <shaik.ameer@samsung.com>
>>
>> This patch adds support for media device for EXYNOS5 SoCs.
>> The current media device supports the following ips to connect
>> through the media controller framework.
>>
>> * MIPI-CSIS
>>   Support interconnection(subdev interface) between devices
>>
>> * FIMC-LITE
>>   Support capture interface from device(Sensor, MIPI-CSIS) to memory
>>   Support interconnection(subdev interface) between devices
>>
>> * FIMC-IS
>>   Camera post-processing IP having multiple sub-nodes.
>>
>> G-Scaler will be added later to the current media device.
>>
>> The media device creates two kinds of pipelines for connecting
>> the above mentioned IPs.
>> The pipeline0 is uses Sensor, MIPI-CSIS and FIMC-LITE which captures
>> image data and dumps to memory.
>> Pipeline1 uses FIMC-IS components for doing post-processing
>> operations on the captured image and give scaled YUV output.
>>
>> Pipeline0
>>   +--------+     +-----------+     +-----------+     +--------+
>>   | Sensor | --> | MIPI-CSIS | --> | FIMC-LITE | --> | Memory |
>>   +--------+     +-----------+     +-----------+     +--------+
>>
>> Pipeline1
>>  +--------+      +--------+     +-----------+     +-----------+
>>  | Memory | -->  |  ISP   | --> |    SCC    | --> |    SCP    |
>>  +--------+      +--------+     +-----------+     +-----------+
>>
>> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
>> Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
>
> [snip]
>
>> +
>> +Common 'camera' node
>> +--------------------
>> +
>> +Required properties:
>> +
>> +- compatible   : must be "samsung,exynos5-fimc", "simple-bus"
>
> I am not sure if this point was discusssed during the previous
> versions. "samsung,exynos5-fimc" seems a bit generic.
> The compatible string should generally point to a specific SoC (the
> first one to have this IP), something like "samsung,exynos5250-fimc".
>

Yes will make it samsung,exynos5250-fimc

>> +- clocks       : list of clock specifiers, corresponding to entries in
>> +                 the clock-names property;
>> +- clock-names  : must contain "sclk_cam0", "sclk_cam1" entries,
>> +                 matching entries in the clocks property.
>> +
>
> [snip]
>
>> +Example:
>> +
>> +       aliases {
>> +               fimc-lite0 = &fimc_lite_0
>> +       };
>> +
>> +       /* Parallel bus IF sensor */
>> +       i2c_0: i2c@13860000 {
>> +               s5k6aa: sensor@3c {
>> +                       compatible = "samsung,s5k6aafx";
>> +                       reg = <0x3c>;
>> +                       vddio-supply = <...>;
>> +
>> +                       clock-frequency = <24000000>;
>> +                       clocks = <...>;
>> +                       clock-names = "mclk";
>> +
>> +                       port {
>> +                               s5k6aa_ep: endpoint {
>> +                                       remote-endpoint = <&fimc0_ep>;
>> +                                       bus-width = <8>;
>> +                                       hsync-active = <0>;
>> +                                       vsync-active = <1>;
>> +                                       pclk-sample = <1>;
>> +                               };
>> +                       };
>> +               };
>> +       };
>> +
>> +       /* MIPI CSI-2 bus IF sensor */
>> +       s5c73m3: sensor@0x1a {
>
> 0x not needed.
>

Ok.

Regards
Arun

Re: [RFC v3 01/13] [media] exynos5-is: Adding media device driver for exynos5

[Sylwester Nawrocki]

Hi Arun,

On 08/05/2013 12:06 PM, Arun Kumar K wrote:
> Hi Sylwester,
> 
> Thank you for the review.
> Will address all your review comments.
> Some responses below:

Thanks, it took me a while to review this nearly 10k of code.
But fortunately I could spent some more time at the computer
this weekend ;)

> [snip]
>>> +
>>> +static int fimc_md_register_sensor_entities(struct fimc_md *fmd)
>>> +{
>>> +       struct device_node *of_node = fmd->pdev->dev.of_node;
>>> +       int ret;
>>> +
>>> +       /*
>>> +        * Runtime resume one of the FIMC entities to make sure
>>> +        * the sclk_cam clocks are not globally disabled.
>>
>>
>> It's a bit mysterious to me, is this requirement still valid on Exynos5 ?
>> I glanced over the Exynos5250 datasheet and there seem to be no sclk_cam?
>> clocks dependency on any of GScaler clocks. Maybe you don't need a clock
>> provider in this driver, perhaps sensor drivers could use sclk_cam clocks
>> directly, assigned through dts ?
> 
> Yes these clocks can be directly exposed via dt.
> I will drop clock provider from this driver.

That's great, this patch set won't depend then on the proper clock
deregistration support in the common clock framework.

>>> +/*
>>> + * The peripheral sensor clock management.
>>> + */
>>> +static void fimc_md_put_clocks(struct fimc_md *fmd)
>>> +{
>>> +       int i = FIMC_MAX_CAMCLKS;
>>> +
>>> +       while (--i>= 0) {
>>> +               if (IS_ERR(fmd->camclk[i].clock))
>>> +                       continue;
>>> +               clk_put(fmd->camclk[i].clock);
>>> +               fmd->camclk[i].clock = ERR_PTR(-EINVAL);
>>> +       }
>>
>>
>> Please double check if you need this sclk_cam clocks handling. We could
>> simply add a requirement that this driver supports only sensor subdevs
>> through the v4l2-async API and which controls their clock themselves.
>>
> 
> sclk_cam* handling can be removed and be done from respective
> sensors. But I think the sclk_bayer handling needs to be retained in the
> media driver.

Yes, that was my understanding as well.

>>> +}
>>> +
>>> +static int fimc_md_get_clocks(struct fimc_md *fmd)
>>> +{
>>> +       struct device *dev = NULL;
>>> +       char clk_name[32];
>>> +       struct clk *clock;
>>> +       int i, ret = 0;
>>> +
>>> +       for (i = 0; i<  FIMC_MAX_CAMCLKS; i++)
>>> +               fmd->camclk[i].clock = ERR_PTR(-EINVAL);
>>> +
>>> +       if (fmd->pdev->dev.of_node)
>>> +               dev =&fmd->pdev->dev;
>>> +
>>> +       for (i = 0; i<  SCLK_BAYER; i++) {
>>> +               snprintf(clk_name, sizeof(clk_name), "sclk_cam%u", i);
>>> +               clock = clk_get(dev, clk_name);
>>> +
>>> +               if (IS_ERR(clock)) {
>>> +                       dev_err(&fmd->pdev->dev, "Failed to get clock:
>>> %s\n",
>>> +                                                               clk_name);
>>> +                       ret = PTR_ERR(clock);
>>> +                       break;
>>> +               }
>>> +               fmd->camclk[i].clock = clock;
>>> +       }
>>> +       if (ret)
>>> +               fimc_md_put_clocks(fmd);
>>> +
>>> +       /* Prepare bayer clk */
>>> +       clock = clk_get(dev, "sclk_bayer");
>>> +
>>> +       if (IS_ERR(clock)) {
>>> +               dev_err(&fmd->pdev->dev, "Failed to get clock: %s\n",
>>> +                                                       clk_name);
>>
>>
>> Wrong error message.
>>
>>> +               ret = PTR_ERR(clock);
>>> +               goto err_exit;
>>> +       }
>>> +       ret = clk_prepare(clock);
>>> +       if (ret<  0) {
>>> +               clk_put(clock);
>>> +               fmd->camclk[SCLK_BAYER].clock = ERR_PTR(-EINVAL);
>>> +               goto err_exit;
>>> +       }
>>> +       fmd->camclk[SCLK_BAYER].clock = clock;
>>
>>
>> Could you explain a bit how is this SCLK_BAYER clock used ? Is it routed
>> to external image sensor, or is it used only inside an SoC ?
>>
> 
> It is not defined properly in the manual, but I suppose its the bus clock
> for the bayer rgb data bus. So for proper sensor functionality, we need this
> sclk_bayer in addition to the external sensor clks (sclk_cam*). Isn't
> exynos5 media driver is the best place to handle such clocks?

I see, I think it's the right place. I was just curious what this clock
was exactly. It an SoC requires it internally then it is correct to handle
it as you do now. And if it happens that it controls the CAM_BAY_MCLK
output clock of the camera bay, then it could be exposed as the master
clock for the device attached to that physical camera port. In that case
the SCLK_CAM bayer clock could be gated conditionally in the media device
driver, depending on the data bus interface used by a remote image data
source device. But that's mostly speculations. I'm fine with associating
this clock with the media device, especially as far as the DT binding is
concerned.

--
Thanks,
Sylwester

Re: [RFC v3 03/13] [media] exynos5-fimc-is: Add driver core files

[Arun Kumar K]

Hi Sylwester,

On Sun, Aug 4, 2013 at 3:12 AM, Sylwester Nawrocki
<sylvester.nawrocki@gmail.com> wrote:
> On 08/02/2013 05:02 PM, Arun Kumar K wrote:
>>
>> This driver is for the FIMC-IS IP available in Samsung Exynos5
>> SoC onwards. This patch adds the core files for the new driver.
>>
>> Signed-off-by: Arun Kumar K<arun.kk@samsung.com>
>> Signed-off-by: Kilyeon Im<kilyeon.im@samsung.com>
>> ---
>>   drivers/media/platform/exynos5-is/fimc-is-core.c |  394
>> ++++++++++++++++++++++
>>   drivers/media/platform/exynos5-is/fimc-is-core.h |  122 +++++++
>>   2 files changed, 516 insertions(+)
>>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.c
>>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.h
>>
>> diff --git a/drivers/media/platform/exynos5-is/fimc-is-core.c
>> b/drivers/media/platform/exynos5-is/fimc-is-core.c
>> new file mode 100644
>> index 0000000..7b7762b
>> --- /dev/null
>> +++ b/drivers/media/platform/exynos5-is/fimc-is-core.c
>> @@ -0,0 +1,394 @@
>> +/*
>> + * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
>> +*
>> + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
>> + * Arun Kumar K<arun.kk@samsung.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include<linux/bug.h>
>> +#include<linux/ctype.h>
>> +#include<linux/device.h>
>> +#include<linux/debugfs.h>
>> +#include<linux/delay.h>
>> +#include<linux/errno.h>
>> +#include<linux/err.h>
>> +#include<linux/firmware.h>
>> +#include<linux/fs.h>
>> +#include<linux/gpio.h>
>> +#include<linux/interrupt.h>
>> +#include<linux/kernel.h>
>> +#include<linux/list.h>
>> +#include<linux/module.h>
>> +#include<linux/types.h>
>> +#include<linux/platform_device.h>
>> +#include<linux/pm_runtime.h>
>> +#include<linux/slab.h>
>> +#include<linux/videodev2.h>
>> +#include<linux/of.h>
>> +#include<linux/of_gpio.h>
>> +#include<linux/of_address.h>
>> +#include<linux/of_platform.h>
>> +#include<linux/of_irq.h>
>> +#include<linux/pinctrl/consumer.h>
>> +
>> +#include<media/v4l2-device.h>
>> +#include<media/v4l2-ioctl.h>
>> +#include<media/v4l2-mem2mem.h>
>> +#include<media/v4l2-of.h>
>> +#include<media/videobuf2-core.h>
>> +#include<media/videobuf2-dma-contig.h>
>> +
>> +#include "fimc-is.h"
>> +#include "fimc-is-i2c.h"
>> +
>> +#define CLK_MCU_ISP_DIV0_FREQ  (200 * 1000000)
>> +#define CLK_MCU_ISP_DIV1_FREQ  (100 * 1000000)
>> +#define CLK_ISP_DIV0_FREQ      (134 * 1000000)
>> +#define CLK_ISP_DIV1_FREQ      (68 * 1000000)
>> +#define CLK_ISP_DIVMPWM_FREQ   (34 * 1000000)
>> +
>> +static char *fimc_is_clock_name[] = {
>> +       [IS_CLK_ISP]            = "isp",
>> +       [IS_CLK_MCU_ISP]        = "mcu_isp",
>> +       [IS_CLK_ISP_DIV0]       = "isp_div0",
>> +       [IS_CLK_ISP_DIV1]       = "isp_div1",
>> +       [IS_CLK_ISP_DIVMPWM]    = "isp_divmpwm",
>> +       [IS_CLK_MCU_ISP_DIV0]   = "mcu_isp_div0",
>> +       [IS_CLK_MCU_ISP_DIV1]   = "mcu_isp_div1",
>> +};
>> +
>> +static void fimc_is_put_clocks(struct fimc_is *is)
>> +{
>> +       int i;
>> +
>> +       for (i = 0; i<  IS_CLK_MAX_NUM; i++) {
>> +               if (IS_ERR(is->clock[i]))
>> +                       continue;
>> +               clk_unprepare(is->clock[i]);
>> +               clk_put(is->clock[i]);
>> +               is->clock[i] = NULL;
>> +       }
>> +}
>> +
>> +static int fimc_is_get_clocks(struct fimc_is *is)
>> +{
>> +       struct device *dev =&is->pdev->dev;
>>
>> +       int i, ret;
>> +
>> +       for (i = 0; i<  IS_CLK_MAX_NUM; i++) {
>> +               is->clock[i] = clk_get(dev, fimc_is_clock_name[i]);
>> +               if (IS_ERR(is->clock[i]))
>> +                       goto err;
>> +               ret = clk_prepare(is->clock[i]);
>> +               if (ret<  0) {
>> +                       clk_put(is->clock[i]);
>> +                       is->clock[i] = ERR_PTR(-EINVAL);
>> +                       goto err;
>> +               }
>> +       }
>> +       return 0;
>> +err:
>> +       fimc_is_put_clocks(is);
>> +       pr_err("Failed to get clock: %s\n", fimc_is_clock_name[i]);
>> +       return -ENXIO;
>> +}
>> +
>> +static int fimc_is_configure_clocks(struct fimc_is *is)
>> +{
>> +       int i, ret;
>> +
>> +       for (i = 0; i<  IS_CLK_MAX_NUM; i++)
>> +               is->clock[i] = ERR_PTR(-EINVAL);
>> +
>> +       ret = fimc_is_get_clocks(is);
>> +       if (ret)
>> +               return ret;
>> +
>> +       /* Set rates */
>> +       ret = clk_set_rate(is->clock[IS_CLK_MCU_ISP_DIV0],
>> +                       CLK_MCU_ISP_DIV0_FREQ);
>> +       if (ret)
>> +               return ret;
>> +       ret = clk_set_rate(is->clock[IS_CLK_MCU_ISP_DIV1],
>> +                       CLK_MCU_ISP_DIV1_FREQ);
>> +       if (ret)
>> +               return ret;
>> +       ret = clk_set_rate(is->clock[IS_CLK_ISP_DIV0], CLK_ISP_DIV0_FREQ);
>> +       if (ret)
>> +               return ret;
>> +       ret = clk_set_rate(is->clock[IS_CLK_ISP_DIV1], CLK_ISP_DIV1_FREQ);
>> +       if (ret)
>> +               return ret;
>> +       ret = clk_set_rate(is->clock[IS_CLK_ISP_DIVMPWM],
>> +                       CLK_ISP_DIVMPWM_FREQ);
>> +       return ret;
>> +}
>> +
>> +static void fimc_is_pipelines_destroy(struct fimc_is *is)
>> +{
>> +       int i;
>> +
>> +       for (i = 0; i<  is->num_instance; i++)
>> +               fimc_is_pipeline_destroy(&is->pipeline[i]);
>> +}
>> +
>> +static int fimc_is_parse_sensor_config(struct fimc_is *is, unsigned int
>> index,
>> +                                               struct device_node *node)
>> +{
>> +       struct fimc_is_sensor *sensor =&is->sensor[index];
>>
>> +       u32 tmp = 0;
>> +       int ret;
>> +
>> +       sensor->drvdata = exynos5_is_sensor_get_drvdata(node);
>> +       if (!sensor->drvdata) {
>> +               dev_err(&is->pdev->dev, "no driver data found for: %s\n",
>> +                                                        node->full_name);
>> +               return -EINVAL;
>> +       }
>> +
>> +       node = v4l2_of_get_next_endpoint(node, NULL);
>> +       if (!node)
>> +               return -ENXIO;
>> +
>> +       node = v4l2_of_get_remote_port(node);
>> +       if (!node)
>> +               return -ENXIO;
>> +
>> +       /* Use MIPI-CSIS channel id to determine the ISP I2C bus index. */
>> +       ret = of_property_read_u32(node, "reg",&tmp);
>> +       if (ret<  0) {
>> +               dev_err(&is->pdev->dev, "reg property not found at: %s\n",
>> +                                                        node->full_name);
>> +               return ret;
>> +       }
>> +
>> +       sensor->i2c_bus = tmp - FIMC_INPUT_MIPI_CSI2_0;
>> +       return 0;
>> +}
>> +
>> +static int fimc_is_parse_sensor(struct fimc_is *is)
>> +{
>> +       struct device_node *i2c_bus, *child;
>> +       int ret, index = 0;
>> +
>> +       for_each_compatible_node(i2c_bus, NULL, FIMC_IS_I2C_COMPATIBLE) {
>> +               for_each_available_child_of_node(i2c_bus, child) {
>> +                       ret = fimc_is_parse_sensor_config(is, index,
>> child);
>> +
>> +                       if (ret<  0 || index>= FIMC_IS_NUM_SENSORS) {
>> +                               of_node_put(child);
>> +                               return ret;
>> +                       }
>> +                       index++;
>> +               }
>> +       }
>> +       return 0;
>> +}
>> +
>> +static int fimc_is_probe(struct platform_device *pdev)
>> +{
>> +       struct device *dev =&pdev->dev;
>>
>> +       struct resource *res;
>> +       struct fimc_is *is;
>> +       void __iomem *regs;
>> +       struct device_node *node;
>> +       int irq, ret;
>> +       int i;
>> +
>> +       pr_debug("FIMC-IS Probe Enter\n");
>
>
> dev_dbg() ?
>
>> +       if (!pdev->dev.of_node)
>> +               return -ENODEV;
>> +
>> +       is = devm_kzalloc(&pdev->dev, sizeof(*is), GFP_KERNEL);
>> +       if (!is)
>> +               return -ENOMEM;
>> +
>> +       is->pdev = pdev;
>> +
>> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +       regs = devm_ioremap_resource(dev, res);
>> +       if (IS_ERR(regs))
>> +               return PTR_ERR(regs);
>> +
>> +       /* Get the PMU base */
>> +       node = of_get_child_by_name(dev->of_node, "pmu");
>> +       if (!node)
>> +               return -ENODEV;
>> +       is->pmu_regs = of_iomap(node, 0);
>> +       if (!is->pmu_regs)
>> +               return -ENOMEM;
>> +
>> +       irq = irq_of_parse_and_map(dev->of_node, 0);
>> +       if (irq<  0) {
>> +               dev_err(dev, "Failed to get IRQ\n");
>> +               return irq;
>> +       }
>> +
>> +       ret = of_property_read_u32(pdev->dev.of_node, "num-instance",
>> +                       &is->num_instance);
>> +       if (ret&&  !is->num_instance) {
>>
>> +               dev_err(dev, "Error num instances\n");
>
>
> Hmm, what is this property ? I can't see it listed in the binding document.
>

It is the number of parallel instances that the IS-firmware can handle.
For 5250, its only 1, but in future SoCs, it can handle multiple
parallel pipelines
for supporting multiple sensors simultaneously. I have now moved it to
driver data instead of DT as its a firmware property.

>
>> +               return -EINVAL;
>> +       }
>> +
>> +       ret = fimc_is_configure_clocks(is);
>> +       if (ret<  0) {
>> +               dev_err(dev, "Clock config failed\n");
>
>
> s/Clock config/clocks configration ?
>
>
>> +               goto err_clk;
>> +       }
>> +
>> +       platform_set_drvdata(pdev, is);
>> +       pm_runtime_enable(dev);
>> +
>> +       ret = pm_runtime_get_sync(dev);
>> +       if (ret<  0)
>> +               goto err_pm;
>> +
>> +       is->alloc_ctx = vb2_dma_contig_init_ctx(dev);
>> +       if (IS_ERR(is->alloc_ctx)) {
>> +               ret = PTR_ERR(is->alloc_ctx);
>> +               goto err_vb;
>> +       }
>> +
>> +       /* Get IS-sensor contexts */
>> +       ret = fimc_is_parse_sensor(is);
>> +       if (ret<  0)
>> +               goto err_vb;
>> +
>> +       /* Initialize FIMC Pipeline */
>> +       for (i = 0; i<  is->num_instance; i++) {
>> +               ret = fimc_is_pipeline_init(&is->pipeline[i], i, is);
>> +               if (ret<  0)
>> +                       goto err_sd;
>> +       }
>> +
>> +       /* Initialize FIMC Interface */
>> +       ret = fimc_is_interface_init(&is->interface, regs, irq);
>> +       if (ret<  0)
>> +               goto err_sd;
>> +
>> +       pm_runtime_put(dev);
>> +
>> +       dev_dbg(dev, "FIMC-IS registered successfully\n");
>> +
>> +       return 0;
>> +
>> +err_sd:
>> +       fimc_is_pipelines_destroy(is);
>> +err_vb:
>> +       vb2_dma_contig_cleanup_ctx(is->alloc_ctx);
>> +err_pm:
>> +       pm_runtime_put(dev);
>> +err_clk:
>> +       fimc_is_put_clocks(is);
>> +
>> +       return ret;
>> +}
>> +
>> +int fimc_is_clk_enable(struct fimc_is *is)
>> +{
>> +       int ret;
>> +
>> +       ret = clk_enable(is->clock[IS_CLK_ISP]);
>> +       if (ret)
>> +               return ret;
>> +       ret = clk_enable(is->clock[IS_CLK_MCU_ISP]);
>> +       return ret;
>> +}
>> +
>> +void fimc_is_clk_disable(struct fimc_is *is)
>> +{
>> +       clk_disable(is->clock[IS_CLK_ISP]);
>> +       clk_disable(is->clock[IS_CLK_MCU_ISP]);
>> +}
>> +
>> +static int fimc_is_pm_resume(struct device *dev)
>> +{
>> +       struct fimc_is *is = dev_get_drvdata(dev);
>> +       int ret;
>> +
>> +       ret = fimc_is_clk_enable(is);
>> +       if (ret<  0) {
>> +               dev_err(dev, "Could not enable clocks\n");
>> +               return ret;
>> +       }
>> +       return 0;
>> +}
>> +
>> +static int fimc_is_pm_suspend(struct device *dev)
>> +{
>> +       struct fimc_is *is = dev_get_drvdata(dev);
>> +
>> +       fimc_is_clk_disable(is);
>> +       return 0;
>> +}
>> +
>> +static int fimc_is_runtime_resume(struct device *dev)
>> +{
>> +       return fimc_is_pm_resume(dev);
>> +}
>> +
>> +static int fimc_is_runtime_suspend(struct device *dev)
>> +{
>> +       return fimc_is_pm_suspend(dev);
>> +}
>> +
>> +#ifdef CONFIG_PM_SLEEP
>> +static int fimc_is_resume(struct device *dev)
>> +{
>> +       return fimc_is_pm_resume(dev);
>
>
> You're using same function for system sleep and runtime PM, fimc_is_resume()
> should not attempt to disable the clocks if they are already disabled, i.e.
> the device is not active.
>

Ok I havent implemented system sleep functionality yet. I will keep
it as a TODO for now. Hope its ok.

>> +}
>> +

Regards
Arun

Re: [RFC v3 02/13] [media] exynos5-fimc-is: Add Exynos5 FIMC-IS device tree bindings documentation

[Stephen Warren]

On 08/03/2013 03:41 PM, Sylwester Nawrocki wrote:
> On 08/02/2013 05:02 PM, Arun Kumar K wrote:
>> The patch adds the DT binding documentation for Samsung
>> Exynos5 SoC series imaging subsystem (FIMC-IS).

>> diff --git
>> a/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
>> b/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
>> new file mode 100644
>> index 0000000..49a373a
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
>> @@ -0,0 +1,52 @@
>> +Samsung EXYNOS5 SoC series Imaging Subsystem (FIMC-IS)
>> +------------------------------------------------------
>> +
>> +The camera subsystem on Samsung Exynos5 SoC has some changes relative
>> +to previous SoC versions. Exynos5 has almost similar MIPI-CSIS and
>> +FIMC-LITE IPs but has a much improved version of FIMC-IS which can
>> +handle sensor controls and camera post-processing operations. The
>> +Exynos5 FIMC-IS has a dedicated ARM Cortex A5 processor, many
>> +post-processing blocks (ISP, DRC, FD, ODC, DIS, 3DNR) and two
>> +dedicated scalers (SCC and SCP).

So there are a lot of blocks mentioned there, yet the binding doesn't
seem to describe most of it. Is the binding complete?

>> +pmu subnode
>> +-----------
>> +
>> +Required properties:
>> + - reg : should contain PMU physical base address and size of the memory
>> +         mapped registers.

I think you need a compatible value for this. How else is the node
identified? The node name probably should not be used for identification.

>> +
>> +i2c-isp (ISP I2C bus controller) nodes
>> +------------------------------------------
>> +
>> +Required properties:
>> +
>> +- compatible    : should be "samsung,exynos4212-i2c-isp" for Exynos4212,
>> +          Exynos4412 and Exynos5250 SoCs;
>> +- reg        : physical base address and length of the registers set;
>> +- clocks    : must contain gate clock specifier for this controller;
>> +- clock-names    : must contain "i2c_isp" entry.
>> +
>> +For the above nodes it is required to specify a pinctrl state named "default",

Is "above nodes" both pmu, i2c-isp? It might make sense to be more
explicit re: which nodes this comment applies to.

>> +according to the pinctrl bindings defined in ../pinctrl/pinctrl-bindings.txt.
>> +
>> +Device tree nodes of the image sensors' controlled directly by the FIMC-IS

s/'// ?

>> +firmware must be child nodes of their corresponding ISP I2C bus controller node.
>> +The data link of these image sensors must be specified using the common video
>> +interfaces bindings, defined in video-interfaces.txt.

Re: [RFC v3 02/13] [media] exynos5-fimc-is: Add Exynos5 FIMC-IS device tree bindings documentation

[Sylwester Nawrocki]

On 08/05/2013 06:53 PM, Stephen Warren wrote:
> On 08/03/2013 03:41 PM, Sylwester Nawrocki wrote:
>> On 08/02/2013 05:02 PM, Arun Kumar K wrote:
>>> The patch adds the DT binding documentation for Samsung
>>> Exynos5 SoC series imaging subsystem (FIMC-IS).
>
>>> diff --git
>>> a/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
>>> b/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
>>> new file mode 100644
>>> index 0000000..49a373a
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
>>> @@ -0,0 +1,52 @@
>>> +Samsung EXYNOS5 SoC series Imaging Subsystem (FIMC-IS)
>>> +------------------------------------------------------
>>> +
>>> +The camera subsystem on Samsung Exynos5 SoC has some changes relative
>>> +to previous SoC versions. Exynos5 has almost similar MIPI-CSIS and
>>> +FIMC-LITE IPs but has a much improved version of FIMC-IS which can
>>> +handle sensor controls and camera post-processing operations. The
>>> +Exynos5 FIMC-IS has a dedicated ARM Cortex A5 processor, many
>>> +post-processing blocks (ISP, DRC, FD, ODC, DIS, 3DNR) and two
>>> +dedicated scalers (SCC and SCP).
>
> So there are a lot of blocks mentioned there, yet the binding doesn't
> seem to describe most of it. Is the binding complete?

Thanks for the review Stephen.

No, the binding certainly isn't complete, it doesn't describe the all
available IP blocks. There are separate MMIO address regions for each
block for the main CPUs and for the Cortex-A5 which is supposed to run
firmware that controls the whole subsystem. So in theory all those IP
blocks should be listed as device tree nodes, with at least their
compatible, reg and interrupts properties. However due to most of the
sub-devices being controlled by the firmware the current Linux driver
for this whole FIMC-IS subsystem doesn't need to now exact details
of each internal data processing block. The is a mailbox interface
used for communication between host CPU and the FIMC-IS CPU.

So while we could list all the devices, we decided not to do so.
Because it is not needed by the current software and we may miss some
details for case where the whole subsystem is controlled by the host
CPU (however such scenario is extremely unlikely AFAICT) which then
would be impossible or hard to change.

I guess we should list all available devices, similarly as it's done
in Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt.

And then should they just be disabled through the status property
if they are not needed in the Linux driver ? I guess it is more
sensible than marking them as optional and then not listing them
in dts at all ?

>>> +pmu subnode
>>> +-----------
>>> +
>>> +Required properties:
>>> + - reg : should contain PMU physical base address and size of the memory
>>> +         mapped registers.
>
> I think you need a compatible value for this. How else is the node
> identified? The node name probably should not be used for identification.

Of course the node name is currently used for identification. There is no
compatible property because this pmu node is used to get hold of only part
of the Power Management Unit registers, specific to the FIMC-IS.
The PMU has more registers that also other drivers would be interested in,
e.g. clocks or USB.

I have been considering exposing the PMU registers through a syscon-like
interface and having a phandle pointing to it in the relevant device nodes.

Adding compatible property might not be a good approach. It would have
been hard to map this to a separate device described in the SoC's
datasheet. Registers specific to the FIMC-IS are not contiguous in the
PMU MMIO region.

>>> +
>>> +i2c-isp (ISP I2C bus controller) nodes
>>> +------------------------------------------
>>> +
>>> +Required properties:
>>> +
>>> +- compatible    : should be "samsung,exynos4212-i2c-isp" for Exynos4212,
>>> +          Exynos4412 and Exynos5250 SoCs;
>>> +- reg        : physical base address and length of the registers set;
>>> +- clocks    : must contain gate clock specifier for this controller;
>>> +- clock-names    : must contain "i2c_isp" entry.
>>> +
>>> +For the above nodes it is required to specify a pinctrl state named "default",
>
> Is "above nodes" both pmu, i2c-isp? It might make sense to be more
> explicit re: which nodes this comment applies to.

Yeah, certainly there is room for improvement here. "above nodes" was 
supposed
to refer to the i2c-isp nodes only, it should be said more precisely.

>>> +according to the pinctrl bindings defined in ../pinctrl/pinctrl-bindings.txt.

Re: [RFC v3 04/13] [media] exynos5-fimc-is: Add common driver header files

[Arun Kumar K]

Hi Sylwester,

On Sun, Aug 4, 2013 at 3:13 AM, Sylwester Nawrocki
<sylvester.nawrocki@gmail.com> wrote:
> On 08/02/2013 05:02 PM, Arun Kumar K wrote:
>>
>> This patch adds all the common header files used by the fimc-is
>> driver. It includes the commands for interfacing with the firmware
>> and error codes from IS firmware, metadata and command parameter
>> definitions.
>>
>> Signed-off-by: Arun Kumar K<arun.kk@samsung.com>
>> Signed-off-by: Kilyeon Im<kilyeon.im@samsung.com>
>> ---
>>   drivers/media/platform/exynos5-is/fimc-is-cmd.h    |  187 +++
>>   drivers/media/platform/exynos5-is/fimc-is-err.h    |  257 +++++
>>   .../media/platform/exynos5-is/fimc-is-metadata.h   |  767 +++++++++++++
>>   drivers/media/platform/exynos5-is/fimc-is-param.h  | 1212
>> ++++++++++++++++++++
>>   4 files changed, 2423 insertions(+)
>>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-cmd.h
>>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-err.h
>>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-metadata.h
>>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-param.h
>>

[snip]

>> +
>> +struct camera2_tonemap_dm {
>> +       enum tonemap_mode               mode;
>> +       /* assuming maxCurvePoints = 64 */
>> +       float                           curve_red[64];
>> +       float                           curve_green[64];
>> +       float                           curve_blue[64];
>
>
> So all those floating point numbers are now not really used in
> the driver but we need them for proper data structures/offsets
> declarations of the firmware interface ?
>

Yes. Same floats are used in firmware internal data structures
also and the driver should assign these values when these parameters
are to be changed.

>> +};
>> +

[snip]

>> +/* --------------------------  Effect
>> ----------------------------------- */
>> +enum isp_imageeffect_command {
>> +       ISP_IMAGE_EFFECT_DISABLE                = 0,
>> +       ISP_IMAGE_EFFECT_MONOCHROME             = 1,
>> +       ISP_IMAGE_EFFECT_NEGATIVE_MONO          = 2,
>> +       ISP_IMAGE_EFFECT_NEGATIVE_COLOR         = 3,
>> +       ISP_IMAGE_EFFECT_SEPIA                  = 4,
>> +       ISP_IMAGE_EFFECT_AQUA                   = 5,
>> +       ISP_IMAGE_EFFECT_EMBOSS                 = 6,
>> +       ISP_IMAGE_EFFECT_EMBOSS_MONO            = 7,
>> +       ISP_IMAGE_EFFECT_SKETCH                 = 8,
>> +       ISP_IMAGE_EFFECT_RED_YELLOW_POINT       = 9,
>> +       ISP_IMAGE_EFFECT_GREEN_POINT            = 10,
>> +       ISP_IMAGE_EFFECT_BLUE_POINT             = 11,
>> +       ISP_IMAGE_EFFECT_MAGENTA_POINT          = 12,
>> +       ISP_IMAGE_EFFECT_WARM_VINTAGE           = 13,
>> +       ISP_IMAGE_EFFECT_COLD_VINTAGE           = 14,
>> +       ISP_IMAGE_EFFECT_POSTERIZE              = 15,
>> +       ISP_IMAGE_EFFECT_SOLARIZE               = 16,
>> +       ISP_IMAGE_EFFECT_WASHED                 = 17,
>> +       ISP_IMAGE_EFFECT_CCM                    = 18,
>> +};
>
>
> Hmm, I guess we will need a private v4l2 control for those.
>

Yes. I am planning to add the controls after the basic support
gets merged.

Regards
Arun

Re: [RFC v3 09/13] [media] exynos5-fimc-is: Add the hardware pipeline control

[Arun Kumar K]

Hi Sylwester,

On Sun, Aug 4, 2013 at 8:30 PM, Sylwester Nawrocki
<sylvester.nawrocki@gmail.com> wrote:
> Hi Arun,
>
> On 08/02/2013 05:02 PM, Arun Kumar K wrote:
>>
>> This patch adds the crucial hardware pipeline control for the
>> fimc-is driver. All the subdev nodes will call this pipeline
>> interfaces to reach the hardware. Responsibilities of this module
>> involves configuring and maintaining the hardware pipeline involving
>> multiple sub-ips like ISP, DRC, Scalers, ODC, 3DNR, FD etc.
>>
>> Signed-off-by: Arun Kumar K<arun.kk@samsung.com>
>> Signed-off-by: Kilyeon Im<kilyeon.im@samsung.com>
>> ---

[snip]


>> +static int fimc_is_pipeline_isp_setparams(struct fimc_is_pipeline
>> *pipeline,
>> +               unsigned int enable)
>> +{
>> +       struct isp_param *isp_param =&pipeline->is_region->parameter.isp;
>> +       struct fimc_is *is = pipeline->is;
>> +       unsigned int indexes, lindex, hindex;
>> +       unsigned int sensor_width, sensor_height, scc_width, scc_height;
>> +       unsigned int crop_x, crop_y, isp_width, isp_height;
>> +       unsigned int sensor_ratio, output_ratio;
>> +       int ret;
>> +
>> +       /* Crop calculation */
>> +       sensor_width = pipeline->sensor_width;
>> +       sensor_height = pipeline->sensor_height;
>> +       scc_width = pipeline->scaler_width[SCALER_SCC];
>> +       scc_height = pipeline->scaler_height[SCALER_SCC];
>> +       isp_width = sensor_width;
>> +       isp_height = sensor_height;
>> +       crop_x = crop_y = 0;
>> +
>> +       sensor_ratio = sensor_width * 1000 / sensor_height;
>> +       output_ratio = scc_width * 1000 / scc_height;
>> +
>> +       if (sensor_ratio == output_ratio) {
>> +               isp_width = sensor_width;
>> +               isp_height = sensor_height;
>> +       } else if (sensor_ratio<  output_ratio) {
>> +               isp_height = (sensor_width * scc_height) / scc_width;
>> +               isp_height = ALIGN(isp_height, 2);
>> +               crop_y = ((sensor_height - isp_height)>>  1)&  0xFFFFFFFE;
>
>
> nit: Use ~1U instead of 0xFFFFFFFE.
>
>
>> +       } else {
>> +               isp_width = (sensor_height * scc_width) / scc_height;
>> +               isp_width = ALIGN(isp_width, 4);
>> +               crop_x =  ((sensor_width - isp_width)>>  1)&  0xFFFFFFFE;
>
>
> Ditto.
>
>> +       }
>> +       pipeline->isp_width = isp_width;
>> +       pipeline->isp_height = isp_height;
>> +
>> +       indexes = hindex = lindex = 0;
>> +
>> +       isp_param->otf_output.cmd = OTF_OUTPUT_COMMAND_ENABLE;
>> +       isp_param->otf_output.width = pipeline->sensor_width;
>> +       isp_param->otf_output.height = pipeline->sensor_height;
>> +       isp_param->otf_output.format = OTF_OUTPUT_FORMAT_YUV444;
>> +       isp_param->otf_output.bitwidth = OTF_OUTPUT_BIT_WIDTH_12BIT;
>> +       isp_param->otf_output.order = OTF_INPUT_ORDER_BAYER_GR_BG;
>> +       lindex |= LOWBIT_OF(PARAM_ISP_OTF_OUTPUT);
>> +       hindex |= HIGHBIT_OF(PARAM_ISP_OTF_OUTPUT);
>> +       indexes++;
>
>
> All right, let's stop this hindex/lindex/indexes madness. I've already
> commented on that IIRC. Nevertheless, this should be replaced with proper
> bitmap operations. A similar issue has been fixed in commit
>
>
>> +       isp_param->dma1_output.cmd = DMA_OUTPUT_COMMAND_DISABLE;
>> +       lindex |= LOWBIT_OF(PARAM_ISP_DMA1_OUTPUT);
>> +       hindex |= HIGHBIT_OF(PARAM_ISP_DMA1_OUTPUT);
>> +       indexes++;
>> +
>> +       isp_param->dma2_output.cmd = DMA_OUTPUT_COMMAND_DISABLE;
>> +       lindex |= LOWBIT_OF(PARAM_ISP_DMA2_OUTPUT);
>> +       hindex |= HIGHBIT_OF(PARAM_ISP_DMA2_OUTPUT);
>> +       indexes++;
>> +
>> +       if (enable)
>> +               isp_param->control.bypass = CONTROL_BYPASS_DISABLE;
>> +       else
>> +               isp_param->control.bypass = CONTROL_BYPASS_ENABLE;
>> +       isp_param->control.cmd = CONTROL_COMMAND_START;
>> +       isp_param->control.run_mode = 1;
>> +       lindex |= LOWBIT_OF(PARAM_ISP_CONTROL);
>> +       hindex |= HIGHBIT_OF(PARAM_ISP_CONTROL);
>> +       indexes++;
>> +
>> +       isp_param->dma1_input.cmd = DMA_INPUT_COMMAND_BUF_MNGR;
>> +       isp_param->dma1_input.width = sensor_width;
>> +       isp_param->dma1_input.height = sensor_height;
>> +       isp_param->dma1_input.dma_crop_offset_x = crop_x;
>> +       isp_param->dma1_input.dma_crop_offset_y = crop_y;
>> +       isp_param->dma1_input.dma_crop_width = isp_width;
>> +       isp_param->dma1_input.dma_crop_height = isp_height;
>> +       isp_param->dma1_input.bayer_crop_offset_x = 0;
>> +       isp_param->dma1_input.bayer_crop_offset_y = 0;
>> +       isp_param->dma1_input.bayer_crop_width = 0;
>> +       isp_param->dma1_input.bayer_crop_height = 0;
>> +       isp_param->dma1_input.user_min_frametime = 0;
>> +       isp_param->dma1_input.user_max_frametime = 66666;
>> +       isp_param->dma1_input.wide_frame_gap = 1;
>> +       isp_param->dma1_input.frame_gap = 4096;
>> +       isp_param->dma1_input.line_gap = 45;
>> +       isp_param->dma1_input.order = DMA_INPUT_ORDER_GR_BG;
>> +       isp_param->dma1_input.plane = 1;
>> +       isp_param->dma1_input.buffer_number = 1;
>> +       isp_param->dma1_input.buffer_address = 0;
>> +       isp_param->dma1_input.reserved[1] = 0;
>> +       isp_param->dma1_input.reserved[2] = 0;
>> +       if (pipeline->isp.fmt->fourcc == V4L2_PIX_FMT_SGRBG8)
>> +               isp_param->dma1_input.bitwidth = DMA_INPUT_BIT_WIDTH_8BIT;
>> +       else if (pipeline->isp.fmt->fourcc == V4L2_PIX_FMT_SGRBG10)
>> +               isp_param->dma1_input.bitwidth =
>> DMA_INPUT_BIT_WIDTH_10BIT;
>> +       else
>> +               isp_param->dma1_input.bitwidth =
>> DMA_INPUT_BIT_WIDTH_12BIT;
>> +       lindex |= LOWBIT_OF(PARAM_ISP_DMA1_INPUT);
>> +       hindex |= HIGHBIT_OF(PARAM_ISP_DMA1_INPUT);
>> +       indexes++;
>> +
>> +       lindex = 0xFFFFFFFF;
>> +       hindex = 0xFFFFFFFF;
>
>
> Hmm, is this a workaround for some firmware bug ? You're setting individual
> bits of lindex, hindex only to set them all to 1 just before using those
> variables ? WTH ? :)
>

We set this 0xffffff so that all the init params which are copied
earlier during pipeline_open
are set to the firmware. FW set_param cannot be done after copying of
init params since
FW expects isp params to be set correctly before accepting any other params.
So this is a workaround to force all init values to go along with the
ISP params.

>
> Anyway, instead of doing this:
>
>         lindex |= LOWBIT_OF(A);
>         hindex |= HIGHBIT_OF(A);
>         indexes++;
>
>         lindex |= LOWBIT_OF(B);
>         hindex |= HIGHBIT_OF(B);
>         indexes++;
>
>         ...
>
>         fimc_is_itf_set_param(..., indexes, lindex, hindex);
>
>
> You could do:
>
>         u32 index[2];
>
>         __set_bit(A, index);
>
>         __set_bit(B, index);
>
>         ...
>
>         indexes = hweight32(index[0]);
>         indexes += hweight32(index[1]);
>
>         fimc_is_itf_set_param(..., indexes, index[0], index[1]);
>
> I.e. the bit operations work well with arbitrary length bitmaps.
>

Ok I will use this method.

> BTW, the firmware interface seems pretty odd with it's requirement to
> pass bitmask and number of bits set in this bitmaks separately. Does
> it ever allow 'indexes' to be different than number of bits set in
> lindex, hindex ? What happens in such case ?

Yes. It is working even when indexes is set as 0 !
I will remove that indexes field and use only bitmask.

Regards
Arun

Re: [RFC v3 10/13] [media] exynos5-fimc-is: Add the hardware interface module

[Arun Kumar K]

Hi Sylwester,

On Sun, Aug 4, 2013 at 8:33 PM, Sylwester Nawrocki
<sylvester.nawrocki@gmail.com> wrote:
> Hi Arun,
>
>
> On 08/02/2013 05:02 PM, Arun Kumar K wrote:
>>
>> The hardware interface module finally sends the commands to the
>> FIMC-IS firmware and runs the interrupt handler for getting the
>> responses.
>>
>> Signed-off-by: Arun Kumar K<arun.kk@samsung.com>
>> Signed-off-by: Kilyeon Im<kilyeon.im@samsung.com>
>> ---

[snip]

>> +static int itf_get_state(struct fimc_is_interface *itf,
>> +               unsigned long state)
>> +{
>> +       int ret = 0;
>> +       unsigned long flags;
>> +
>> +       spin_lock_irqsave(&itf->slock_state, flags);
>> +       ret = test_bit(state,&itf->state);
>
>
> Shouldn't it be __test_bit() ?
>

__test_bit() is not availble !
In file include/asm-generic/bitops/non-atomic.h, all other ops
are prefixed with __xxx(), but its just test_bit().

Regards
Arun

Re: [RFC v3 09/13] [media] exynos5-fimc-is: Add the hardware pipeline control

[Sachin Kamat]

Hi Arun,

On 4 August 2013 20:30, Sylwester Nawrocki <sylvester.nawrocki@gmail.com> wrote:
> Hi Arun,
>
> On 08/02/2013 05:02 PM, Arun Kumar K wrote:
>>
>> This patch adds the crucial hardware pipeline control for the
>> fimc-is driver. All the subdev nodes will call this pipeline
>> interfaces to reach the hardware. Responsibilities of this module
>> involves configuring and maintaining the hardware pipeline involving
>> multiple sub-ips like ISP, DRC, Scalers, ODC, 3DNR, FD etc.
>>
>> Signed-off-by: Arun Kumar K<arun.kk@samsung.com>
>> Signed-off-by: Kilyeon Im<kilyeon.im@samsung.com>
>> ---
>>   .../media/platform/exynos5-is/fimc-is-pipeline.c   | 1961
>> ++++++++++++++++++++
>>   .../media/platform/exynos5-is/fimc-is-pipeline.h   |  129 ++
>>   2 files changed, 2090 insertions(+)
>>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-pipeline.c
>>   create mode 100644 drivers/media/platform/exynos5-is/fimc-is-pipeline.h

[snip]

>> +                       setfile_name,&is->pdev->dev);
>> +       if (ret != 0) {
>> +               pr_err("Setfile %s not found\n", setfile_name);
>
>
> dev_err(), please. I'm a bit tired of commenting on this excessive pr_*
> usage. Please really make sure dev_err()/v4l2_err() is used where possible.

pr_* should be used only when device pointer is not available. In all
other cases dev_* takes priority.

-- 
With warm regards,
Sachin

Re: [RFC v3 02/13] [media] exynos5-fimc-is: Add Exynos5 FIMC-IS device tree bindings documentation

[Stephen Warren]

On 08/05/2013 04:37 PM, Sylwester Nawrocki wrote:
> On 08/05/2013 06:53 PM, Stephen Warren wrote:
>> On 08/03/2013 03:41 PM, Sylwester Nawrocki wrote:
>>> On 08/02/2013 05:02 PM, Arun Kumar K wrote:
>>>> The patch adds the DT binding documentation for Samsung
>>>> Exynos5 SoC series imaging subsystem (FIMC-IS).
>>
>>>> diff --git
>>>> a/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
>>>> b/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
>>>> new file mode 100644
>>>> index 0000000..49a373a
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
>>>> @@ -0,0 +1,52 @@
>>>> +Samsung EXYNOS5 SoC series Imaging Subsystem (FIMC-IS)
>>>> +------------------------------------------------------
>>>> +
>>>> +The camera subsystem on Samsung Exynos5 SoC has some changes relative
>>>> +to previous SoC versions. Exynos5 has almost similar MIPI-CSIS and
>>>> +FIMC-LITE IPs but has a much improved version of FIMC-IS which can
>>>> +handle sensor controls and camera post-processing operations. The
>>>> +Exynos5 FIMC-IS has a dedicated ARM Cortex A5 processor, many
>>>> +post-processing blocks (ISP, DRC, FD, ODC, DIS, 3DNR) and two
>>>> +dedicated scalers (SCC and SCP).
>>
>> So there are a lot of blocks mentioned there, yet the binding doesn't
>> seem to describe most of it. Is the binding complete?
> 
> Thanks for the review Stephen.
> 
> No, the binding certainly isn't complete, it doesn't describe the all
> available IP blocks. There are separate MMIO address regions for each
...
> So while we could list all the devices, we decided not to do so.
> Because it is not needed by the current software and we may miss some
> details for case where the whole subsystem is controlled by the host
> CPU (however such scenario is extremely unlikely AFAICT) which then
> would be impossible or hard to change.

Yes, that's probably a good approach.

> I guess we should list all available devices, similarly as it's done
> in Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt.
> 
> And then should they just be disabled through the status property
> if they are not needed in the Linux driver ? I guess it is more
> sensible than marking them as optional and then not listing them
> in dts at all ?

If you can define complete bindings for those nodes, it might make sense
to do that. If the devices are perhaps complex to represent and hence
you might not be able to come up with complete bindings for them right
now, it may indeed be better to simply not mention the devices you don't
care about for now.

>>>> +pmu subnode
>>>> +-----------
>>>> +
>>>> +Required properties:
>>>> + - reg : should contain PMU physical base address and size of the
>>>> memory
>>>> +         mapped registers.
>>
>> I think you need a compatible value for this. How else is the node
>> identified? The node name probably should not be used for identification.
> 
> Of course the node name is currently used for identification. There is no
> compatible property because this pmu node is used to get hold of only part
> of the Power Management Unit registers, specific to the FIMC-IS.
> The PMU has more registers that also other drivers would be interested in,
> e.g. clocks or USB.

I believe the correct way to solve this is for there to be a standalone
PMU node at the appropriate location in DT, and for the FIMC bindings to
reference that other node by phandle.

Right now, the FIMC driver SW can manually follow the phandle, look at
the reg property, and map that itself. Later down the road, you could
instantiate a true PMU driver, and have the FIMC driver look up that
driver, and call APIs on it. This change can be made without requiring
any changes to the DT binding. That way, you aren't introducing a fake
PMU node into the FIMC bindings just to satisfy internal Linux driver
details.

Re: [RFC v3 02/13] [media] exynos5-fimc-is: Add Exynos5 FIMC-IS device tree bindings documentation

[Sylwester Nawrocki]

W dniu 2013-08-08 22:34, Stephen Warren pisze:
> On 08/05/2013 04:37 PM, Sylwester Nawrocki wrote:
>> On 08/05/2013 06:53 PM, Stephen Warren wrote:
>>> On 08/03/2013 03:41 PM, Sylwester Nawrocki wrote:
>>>> On 08/02/2013 05:02 PM, Arun Kumar K wrote:
>>>>> The patch adds the DT binding documentation for Samsung
>>>>> Exynos5 SoC series imaging subsystem (FIMC-IS).
>>>
>>>>> diff --git
>>>>> a/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
>>>>> b/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
>>>>> new file mode 100644
>>>>> index 0000000..49a373a
>>>>> --- /dev/null
>>>>> +++ b/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt
>>>>> @@ -0,0 +1,52 @@
>>>>> +Samsung EXYNOS5 SoC series Imaging Subsystem (FIMC-IS)
>>>>> +------------------------------------------------------
>>>>> +
>>>>> +The camera subsystem on Samsung Exynos5 SoC has some changes relative
>>>>> +to previous SoC versions. Exynos5 has almost similar MIPI-CSIS and
>>>>> +FIMC-LITE IPs but has a much improved version of FIMC-IS which can
>>>>> +handle sensor controls and camera post-processing operations. The
>>>>> +Exynos5 FIMC-IS has a dedicated ARM Cortex A5 processor, many
>>>>> +post-processing blocks (ISP, DRC, FD, ODC, DIS, 3DNR) and two
>>>>> +dedicated scalers (SCC and SCP).
>>>
>>> So there are a lot of blocks mentioned there, yet the binding doesn't
>>> seem to describe most of it. Is the binding complete?
>>
>> Thanks for the review Stephen.
>>
>> No, the binding certainly isn't complete, it doesn't describe the all
>> available IP blocks. There are separate MMIO address regions for each
> ...
>> So while we could list all the devices, we decided not to do so.
>> Because it is not needed by the current software and we may miss some
>> details for case where the whole subsystem is controlled by the host
>> CPU (however such scenario is extremely unlikely AFAICT) which then
>> would be impossible or hard to change.
>
> Yes, that's probably a good approach.
>
>> I guess we should list all available devices, similarly as it's done
>> in Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt.
>>
>> And then should they just be disabled through the status property
>> if they are not needed in the Linux driver ? I guess it is more
>> sensible than marking them as optional and then not listing them
>> in dts at all ?
>
> If you can define complete bindings for those nodes, it might make sense
> to do that. If the devices are perhaps complex to represent and hence
> you might not be able to come up with complete bindings for them right
> now, it may indeed be better to simply not mention the devices you don't
> care about for now.

We would prefer to start with a minimal binding, this would minimize
possible issues in future IMHO, as the subsystem is pretty complex.
Then, if detailed H/W description is required the firmware would need
to be updated, which would have been backward compatible.
We could probably come up with a complete binding, but there is a good
chance something could be done wrong, as that couldn't be actually
tested. It's not trivial to make this all work on the host CPU while
most of the detailed H/W knowledge stays on the firmware teams side.

>>>>> +pmu subnode
>>>>> +-----------
>>>>> +
>>>>> +Required properties:
>>>>> + - reg : should contain PMU physical base address and size of the
>>>>> memory
>>>>> +         mapped registers.
>>>
>>> I think you need a compatible value for this. How else is the node
>>> identified? The node name probably should not be used for identification.
>>
>> Of course the node name is currently used for identification. There is no
>> compatible property because this pmu node is used to get hold of only part
>> of the Power Management Unit registers, specific to the FIMC-IS.
>> The PMU has more registers that also other drivers would be interested in,
>> e.g. clocks or USB.
>
> I believe the correct way to solve this is for there to be a standalone
> PMU node at the appropriate location in DT, and for the FIMC bindings to
> reference that other node by phandle.
>
> Right now, the FIMC driver SW can manually follow the phandle, look at
> the reg property, and map that itself. Later down the road, you could
> instantiate a true PMU driver, and have the FIMC driver look up that
> driver, and call APIs on it. This change can be made without requiring
> any changes to the DT binding. That way, you aren't introducing a fake
> PMU node into the FIMC bindings just to satisfy internal Linux driver
> details.

That sounds reasonable. It lets us to keep the DT binding stable and
at the same move forward with the FIMC-IS while the PMU part is being
worked on. Thanks.