From: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
To: Eddie James <eajames@linux.ibm.com>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Joel Stanley <joel@jms.id.au>, Andrew Jeffery <andrew@aj.id.au>
Cc: linux-aspeed@lists.ozlabs.org, linux-media@vger.kernel.org,
openbmc@lists.ozlabs.org,
Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Subject: [PATCH -next 1/2] media: aspeed: refine hsync/vsync polarity setting logic
Date: Tue, 10 Sep 2019 12:07:55 -0700 [thread overview]
Message-ID: <20190910190756.31432-2-jae.hyun.yoo@linux.intel.com> (raw)
In-Reply-To: <20190910190756.31432-1-jae.hyun.yoo@linux.intel.com>
This commit refines hsync/vsync polarity setting logic by making
also clearing register bits possible based on probed sync state
accordingly.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
---
drivers/media/platform/aspeed-video.c | 43 +++++++++++++--------------
1 file changed, 21 insertions(+), 22 deletions(-)
diff --git a/drivers/media/platform/aspeed-video.c b/drivers/media/platform/aspeed-video.c
index eb12f3793062..8f77079da55a 100644
--- a/drivers/media/platform/aspeed-video.c
+++ b/drivers/media/platform/aspeed-video.c
@@ -614,7 +614,7 @@ static void aspeed_video_check_and_set_polarity(struct aspeed_video *video)
int i;
int hsync_counter = 0;
int vsync_counter = 0;
- u32 sts;
+ u32 sts, ctrl;
for (i = 0; i < NUM_POLARITY_CHECKS; ++i) {
sts = aspeed_video_read(video, VE_MODE_DETECT_STATUS);
@@ -629,30 +629,29 @@ static void aspeed_video_check_and_set_polarity(struct aspeed_video *video)
hsync_counter++;
}
- if (hsync_counter < 0 || vsync_counter < 0) {
- u32 ctrl = 0;
+ ctrl = aspeed_video_read(video, VE_CTRL);
- if (hsync_counter < 0) {
- ctrl = VE_CTRL_HSYNC_POL;
- video->detected_timings.polarities &=
- ~V4L2_DV_HSYNC_POS_POL;
- } else {
- video->detected_timings.polarities |=
- V4L2_DV_HSYNC_POS_POL;
- }
-
- if (vsync_counter < 0) {
- ctrl = VE_CTRL_VSYNC_POL;
- video->detected_timings.polarities &=
- ~V4L2_DV_VSYNC_POS_POL;
- } else {
- video->detected_timings.polarities |=
- V4L2_DV_VSYNC_POS_POL;
- }
+ if (hsync_counter < 0) {
+ ctrl |= VE_CTRL_HSYNC_POL;
+ video->detected_timings.polarities &=
+ ~V4L2_DV_HSYNC_POS_POL;
+ } else {
+ ctrl &= ~VE_CTRL_HSYNC_POL;
+ video->detected_timings.polarities |=
+ V4L2_DV_HSYNC_POS_POL;
+ }
- if (ctrl)
- aspeed_video_update(video, VE_CTRL, 0, ctrl);
+ if (vsync_counter < 0) {
+ ctrl |= VE_CTRL_VSYNC_POL;
+ video->detected_timings.polarities &=
+ ~V4L2_DV_VSYNC_POS_POL;
+ } else {
+ ctrl &= ~VE_CTRL_VSYNC_POL;
+ video->detected_timings.polarities |=
+ V4L2_DV_VSYNC_POS_POL;
}
+
+ aspeed_video_write(video, VE_CTRL, ctrl);
}
static bool aspeed_video_alloc_buf(struct aspeed_video *video,
--
2.23.0
next prev parent reply other threads:[~2019-09-10 19:08 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-10 19:07 [PATCH -next 0/2] media: aspeed: refine mode detection flow Jae Hyun Yoo
2019-09-10 19:07 ` Jae Hyun Yoo [this message]
2019-09-12 5:33 ` [PATCH -next 1/2] media: aspeed: refine hsync/vsync polarity setting logic Andrew Jeffery
2019-09-12 17:04 ` Jae Hyun Yoo
2019-09-10 19:07 ` [PATCH -next 2/2] media: aspeed: set hsync and vsync polarities to normal before starting mode detection Jae Hyun Yoo
2019-09-12 5:39 ` Andrew Jeffery
2019-09-12 17:06 ` Jae Hyun Yoo
2019-09-13 0:18 ` Andrew Jeffery
2019-09-13 16:14 ` Jae Hyun Yoo
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