From: "Andrew Jeffery" <andrew@aj.id.au>
To: "Jae Hyun Yoo" <jae.hyun.yoo@linux.intel.com>,
"Eddie James" <eajames@linux.ibm.com>,
"Mauro Carvalho Chehab" <mchehab@kernel.org>,
"Joel Stanley" <joel@jms.id.au>
Cc: linux-aspeed@lists.ozlabs.org, linux-media@vger.kernel.org,
openbmc@lists.ozlabs.org
Subject: Re: [PATCH -next 1/2] media: aspeed: refine hsync/vsync polarity setting logic
Date: Thu, 12 Sep 2019 15:03:00 +0930 [thread overview]
Message-ID: <a11026fa-f2bb-47a2-b792-6009c2bbe63d@www.fastmail.com> (raw)
In-Reply-To: <20190910190756.31432-2-jae.hyun.yoo@linux.intel.com>
On Wed, 11 Sep 2019, at 04:37, Jae Hyun Yoo wrote:
> This commit refines hsync/vsync polarity setting logic by making
> also clearing register bits possible based on probed sync state
> accordingly.
That was tough to parse, but I think I understand. Trying to rephrase:
Enable clearing of hsync/vsync plarity bits based on probed sync state.
What was the issue that drove the change? Do you know why it was done
the way it was prior to this patch?
Andrew
next prev parent reply other threads:[~2019-09-12 5:32 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-10 19:07 [PATCH -next 0/2] media: aspeed: refine mode detection flow Jae Hyun Yoo
2019-09-10 19:07 ` [PATCH -next 1/2] media: aspeed: refine hsync/vsync polarity setting logic Jae Hyun Yoo
2019-09-12 5:33 ` Andrew Jeffery [this message]
2019-09-12 17:04 ` Jae Hyun Yoo
2019-09-10 19:07 ` [PATCH -next 2/2] media: aspeed: set hsync and vsync polarities to normal before starting mode detection Jae Hyun Yoo
2019-09-12 5:39 ` Andrew Jeffery
2019-09-12 17:06 ` Jae Hyun Yoo
2019-09-13 0:18 ` Andrew Jeffery
2019-09-13 16:14 ` Jae Hyun Yoo
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