[RFC PATCH 00/11] rkisp1 support for px30 - including uapi questions for 5.11

[RFC PATCH 00/11] rkisp1 support for px30 - including uapi questions for 5.11

[Heiko Stuebner]

As discussed on IRC, here is a series that makes the ISP produce images
on the px30/rk3326.

There is probably a lot of stuff that can be done more cleanly in future
revisions, but the main issues right now is the uapi change in patch 5.

Extending these constants causes the uapi arrays to increase as well.

So this is more base for discussions, especially as we only have the 5.11
rc cycle to decide.

The users of these changes can be found in
  patch 10: add support for v12 isp variants


Heiko Stuebner (11):
  arm64: dts: rockchip: add csi-dphy to px30
  arm64: dts: rockchip: add isp node for px30
  arm64: dts: rockchip: hook up camera on px30-evb
  phy/rockchip: add Innosilicon-based CSI dphy
  media: rockchip: rkisp1: extend uapi array sizes
  media: rockchip: rkisp1: allow separate interrupts
  media: rockchip: rkisp1: carry ip version information
  media: rockchip: rkisp1: make some isp-param functions variable
  media: rockchip: rkisp1: make some isp-stats functions variable
  media: rockchip: rkisp1: add support for v12 isp variants
  media: rockchip: rkisp1: add support for px30 isp version

 arch/arm64/boot/dts/rockchip/px30-evb.dts     |  52 ++
 arch/arm64/boot/dts/rockchip/px30.dtsi        |  56 ++
 .../platform/rockchip/rkisp1/rkisp1-capture.c |   9 +-
 .../platform/rockchip/rkisp1/rkisp1-common.h  |  60 +-
 .../platform/rockchip/rkisp1/rkisp1-dev.c     |  82 ++-
 .../platform/rockchip/rkisp1/rkisp1-isp.c     |  29 +-
 .../platform/rockchip/rkisp1/rkisp1-params.c  | 581 ++++++++++++++----
 .../platform/rockchip/rkisp1/rkisp1-regs.h    | 404 ++++++++----
 .../platform/rockchip/rkisp1/rkisp1-stats.c   | 122 +++-
 drivers/phy/rockchip/Kconfig                  |   9 +
 drivers/phy/rockchip/Makefile                 |   1 +
 .../phy/rockchip/phy-rockchip-inno-csidphy.c  | 580 +++++++++++++++++
 include/uapi/linux/rkisp1-config.h            |   8 +-
 13 files changed, 1713 insertions(+), 280 deletions(-)
 create mode 100644 drivers/phy/rockchip/phy-rockchip-inno-csidphy.c

-- 
2.29.2

[PATCH RFC 01/11] arm64: dts: rockchip: add csi-dphy to px30

[Heiko Stuebner]

From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
---
 arch/arm64/boot/dts/rockchip/px30.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
index f4dfcb01e3d9..52bc54416657 100644
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -863,6 +863,19 @@ dsi_dphy: phy@ff2e0000 {
 		status = "disabled";
 	};
 
+	csi_dphy: phy@ff2f0000 {
+		compatible = "rockchip,px30-mipi-dphy";
+		reg = <0x0 0xff2f0000 0x0 0x4000>;
+		clocks = <&cru PCLK_MIPICSIPHY>;
+		clock-names = "pclk";
+		#phy-cells = <0>;
+		power-domains = <&power PX30_PD_VI>;
+		resets = <&cru SRST_MIPICSIPHY_P>;
+		reset-names = "apb";
+		rockchip,grf = <&grf>;
+		status = "disabled";
+	};
+
 	usb20_otg: usb@ff300000 {
 		compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
 			     "snps,dwc2";
-- 
2.29.2

[PATCH RFC 02/11] arm64: dts: rockchip: add isp node for px30

[Heiko Stuebner]

From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>

Add the rkisp1 node and iommu for the px30 soc.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
---
 arch/arm64/boot/dts/rockchip/px30.dtsi | 43 ++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
index 52bc54416657..4f762968f75f 100644
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -1131,6 +1131,49 @@ vip: vip@ff490000 {
 		status = "disabled";
 	};
 
+	isp: isp@ff4a0000 {
+		compatible = "rockchip,px30-cif-isp"; /*rk3326-rkisp1*/
+		reg = <0x0 0xff4a0000 0x0 0x8000>;
+		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "isp", "mi", "mipi";
+		clocks = <&cru SCLK_ISP>,
+			 <&cru ACLK_ISP>,
+			 <&cru HCLK_ISP>,
+			 <&cru PCLK_ISP>;
+		clock-names = "isp", "aclk", "hclk", "pclk";
+		iommus = <&isp_mmu>;
+		phys = <&csi_dphy>;
+		phy-names = "dphy";
+		power-domains = <&power PX30_PD_VI>;
+		status = "disabled";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+	};
+
+	isp_mmu: iommu@ff4a8000 {
+		compatible = "rockchip,iommu";
+		reg = <0x0 0xff4a8000 0x0 0x100>;
+		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "isp_mmu";
+		clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
+		clock-names = "aclk", "iface";
+		power-domains = <&power PX30_PD_VI>;
+		rk_iommu,disable_reset_quirk;
+		#iommu-cells = <0>;
+		status = "disabled";
+	};
+
 	qos_gmac: qos@ff518000 {
 		compatible = "syscon";
 		reg = <0x0 0xff518000 0x0 0x20>;
-- 
2.29.2

[PATCH RFC 03/11] arm64: dts: rockchip: hook up camera on px30-evb

[Heiko Stuebner]

From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
---
 arch/arm64/boot/dts/rockchip/px30-evb.dts | 52 +++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/px30-evb.dts b/arch/arm64/boot/dts/rockchip/px30-evb.dts
index 5fe905fae9a8..52e788e983af 100644
--- a/arch/arm64/boot/dts/rockchip/px30-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/px30-evb.dts
@@ -422,6 +422,58 @@ sensor@4c {
 	};
 };
 
+&i2c2 {
+	status = "okay";
+
+	clock-frequency = <100000>;
+
+	/* These are relatively safe rise/fall times; TODO: measure */
+	i2c-scl-falling-time-ns = <50>;
+	i2c-scl-rising-time-ns = <300>;
+
+	ov5695: ov5695@36 {
+		compatible = "ovti,ov5695";
+		reg = <0x36>;
+		avdd-supply = <&vcc2v8_dvp>;
+		dvdd-supply = <&vcc1v5_dvp>;
+		dovdd-supply = <&vcc1v8_dvp>;
+		clocks = <&cru SCLK_CIF_OUT>;
+		clock-names = "xvclk";
+		pinctrl-names = "default";
+		pinctrl-0 = <&cif_clkout_m0>;
+		reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
+
+		port {
+			ucam_out: endpoint {
+				remote-endpoint = <&mipi_in_ucam>;
+				data-lanes = <1 2>;
+			};
+		};
+	};
+};
+
+&csi_dphy {
+	status = "okay";
+};
+
+&isp {
+	status = "okay";
+
+	ports {
+		port@0 {
+			mipi_in_ucam: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&ucam_out>;
+				data-lanes = <1 2>;
+			};
+		};
+	};
+};
+
+&isp_mmu {
+	status = "okay";
+};
+
 &i2s1_2ch {
 	status = "okay";
 };
-- 
2.29.2

[PATCH RFC 04/11] phy/rockchip: add Innosilicon-based CSI dphy

[Heiko Stuebner]

From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>

The CSI dphy found for example on the rk3326/px30 and rk3368 is based
on an IP design from Innosilicon. Add a driver for it.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
---
 drivers/phy/rockchip/Kconfig                  |   9 +
 drivers/phy/rockchip/Makefile                 |   1 +
 .../phy/rockchip/phy-rockchip-inno-csidphy.c  | 580 ++++++++++++++++++
 3 files changed, 590 insertions(+)
 create mode 100644 drivers/phy/rockchip/phy-rockchip-inno-csidphy.c

diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
index 159285f42e5c..e812adad7242 100644
--- a/drivers/phy/rockchip/Kconfig
+++ b/drivers/phy/rockchip/Kconfig
@@ -48,6 +48,15 @@ config PHY_ROCKCHIP_INNO_USB2
 	help
 	  Support for Rockchip USB2.0 PHY with Innosilicon IP block.
 
+config PHY_ROCKCHIP_INNO_CSIDPHY
+	tristate "Rockchip Innosilicon MIPI CSI PHY driver"
+	depends on (ARCH_ROCKCHIP || COMPILE_TEST) && OF
+	select GENERIC_PHY
+	select GENERIC_PHY_MIPI_DPHY
+	help
+	  Enable this to support the Rockchip MIPI CSI PHY with
+	  Innosilicon IP block.
+
 config PHY_ROCKCHIP_INNO_DSIDPHY
 	tristate "Rockchip Innosilicon MIPI/LVDS/TTL PHY driver"
 	depends on (ARCH_ROCKCHIP || COMPILE_TEST) && OF
diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
index c3cfc7f0af5c..f0eec212b2aa 100644
--- a/drivers/phy/rockchip/Makefile
+++ b/drivers/phy/rockchip/Makefile
@@ -2,6 +2,7 @@
 obj-$(CONFIG_PHY_ROCKCHIP_DP)		+= phy-rockchip-dp.o
 obj-$(CONFIG_PHY_ROCKCHIP_DPHY_RX0)     += phy-rockchip-dphy-rx0.o
 obj-$(CONFIG_PHY_ROCKCHIP_EMMC)		+= phy-rockchip-emmc.o
+obj-$(CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY)	+= phy-rockchip-inno-csidphy.o
 obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY)	+= phy-rockchip-inno-dsidphy.o
 obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI)	+= phy-rockchip-inno-hdmi.o
 obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)	+= phy-rockchip-inno-usb2.o
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
new file mode 100644
index 000000000000..96a7fe137bb9
--- /dev/null
+++ b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
@@ -0,0 +1,580 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Rockchip MIPI RX Innosilicon DPHY driver
+ *
+ * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/phy/phy.h>
+#include <linux/phy/phy-mipi-dphy.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+
+/* GRF */
+#define RK1808_GRF_PD_VI_CON_OFFSET	0x0430
+
+#define RK3326_GRF_IO_VSEL_OFFSET	0x0180
+#define RK3326_GRF_PD_VI_CON_OFFSET	0x0430
+
+#define RK3368_GRF_SOC_CON6_OFFSET	0x0418
+#define RK3368_GRF_IO_VSEL_OFFSET	0x0900
+
+/* PHY */
+#define CLOCK_LANE_HS_RX_CONTROL		0x34
+#define LANE0_HS_RX_CONTROL			0x44
+#define LANE1_HS_RX_CONTROL			0x54
+#define LANE2_HS_RX_CONTROL			0x84
+#define LANE3_HS_RX_CONTROL			0x94
+#define HS_RX_DATA_LANES_THS_SETTLE_CONTROL	0x75
+
+#define CSIDPHY_CTRL_LANE_ENABLE		0x00
+#define CSIDPHY_CTRL_LANE_ENABLE_CK		BIT(6)
+#define CSIDPHY_CTRL_LANE_ENABLE_LANE3		BIT(5)
+#define CSIDPHY_CTRL_LANE_ENABLE_LANE2		BIT(4)
+#define CSIDPHY_CTRL_LANE_ENABLE_LANE1		BIT(3)
+#define CSIDPHY_CTRL_LANE_ENABLE_LANE0		BIT(2)
+#define CSIDPHY_CTRL_LANE_ENABLE_UNDEFINED	BIT(0)
+
+#define CSIDPHY_CTRL_LANE_ENABLE_SHIFT		2
+
+/* not present on all variants */
+#define CSIDPHY_CTRL_PWRCTL		0x04
+#define CSIDPHY_CTRL_PWRCTL_UNDEFINED	GENMASK(7, 5)
+#define CSIDPHY_CTRL_PWRCTL_SYNCRST	BIT(2)
+#define CSIDPHY_CTRL_PWRCTL_LDO_PD	BIT(1)
+#define CSIDPHY_CTRL_PWRCTL_PLL_PD	BIT(0)
+
+#define CSIDPHY_CTRL_DIG_RST			0x80
+#define CSIDPHY_CTRL_DIG_RST_UNDEFINED		0x1e
+#define CSIDPHY_CTRL_DIG_RST_RESET		BIT(0)
+
+
+
+
+/* offset after CLK_THS_SETTLE */
+#define CSIDPHY_CLK_THS_SETTLE			0
+#define CSIDPHY_LANE_THS_SETTLE(n)		((n + 1) * 0x80)
+#define CSIDPHY_THS_SETTLE_MASK			0x7f
+
+/* Configure the count time of the THS-SETTLE by protocol. */
+#define RK1808_CSIDPHY_CLK_WR_THS_SETTLE	0x160
+#define RK3326_CSIDPHY_CLK_WR_THS_SETTLE	0x100
+#define RK3368_CSIDPHY_CLK_WR_THS_SETTLE	0x100
+
+
+#define RK1808_CSI_DPHY_LANE0_WR_THS_SETTLE	\
+		(RK1808_CSI_DPHY_CLK_WR_THS_SETTLE + 0x80)
+#define RK1808_CSI_DPHY_LANE1_WR_THS_SETTLE	\
+		(RK1808_CSI_DPHY_LANE0_WR_THS_SETTLE + 0x80)
+#define RK1808_CSI_DPHY_LANE2_WR_THS_SETTLE	\
+		(RK1808_CSI_DPHY_LANE1_WR_THS_SETTLE + 0x80)
+#define RK1808_CSI_DPHY_LANE3_WR_THS_SETTLE	\
+		(RK1808_CSI_DPHY_LANE2_WR_THS_SETTLE + 0x80)
+
+#define RK3326_CSI_DPHY_LANE0_WR_THS_SETTLE	\
+		(RK3326_CSI_DPHY_CLK_WR_THS_SETTLE + 0x80)
+#define RK3326_CSI_DPHY_LANE1_WR_THS_SETTLE	\
+		(RK3326_CSI_DPHY_LANE0_WR_THS_SETTLE + 0x80)
+#define RK3326_CSI_DPHY_LANE2_WR_THS_SETTLE	\
+		(RK3326_CSI_DPHY_LANE1_WR_THS_SETTLE + 0x80)
+#define RK3326_CSI_DPHY_LANE3_WR_THS_SETTLE	\
+		(RK3326_CSI_DPHY_LANE2_WR_THS_SETTLE + 0x80)
+
+#define RK3368_CSI_DPHY_LANE0_WR_THS_SETTLE	\
+		(RK3368_CSI_DPHY_CLK_WR_THS_SETTLE + 0x80)
+#define RK3368_CSI_DPHY_LANE1_WR_THS_SETTLE	\
+		(RK3368_CSI_DPHY_LANE0_WR_THS_SETTLE + 0x80)
+#define RK3368_CSI_DPHY_LANE2_WR_THS_SETTLE	\
+		(RK3368_CSI_DPHY_LANE1_WR_THS_SETTLE + 0x80)
+#define RK3368_CSI_DPHY_LANE3_WR_THS_SETTLE	\
+		(RK3368_CSI_DPHY_LANE2_WR_THS_SETTLE + 0x80)
+
+/* Calibration reception enable */
+#define RK1808_CSIDPHY_CLK_CALIB_EN		0x168
+
+#define RK1808_CSI_DPHY_LANE0_CALIB_EN		0x1e8
+#define RK1808_CSI_DPHY_LANE1_CALIB_EN		0x268
+#define RK1808_CSI_DPHY_LANE2_CALIB_EN		0x2e8
+#define RK1808_CSI_DPHY_LANE3_CALIB_EN		0x368
+
+#define RK3326_CSI_DPHY_CLK_CALIB_EN		\
+		MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
+#define RK3326_CSI_DPHY_LANE0_CALIB_EN		\
+		MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
+#define RK3326_CSI_DPHY_LANE1_CALIB_EN		\
+		MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
+#define RK3326_CSI_DPHY_LANE2_CALIB_EN		\
+		MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
+#define RK3326_CSI_DPHY_LANE3_CALIB_EN		\
+		MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
+
+#define RK3368_CSI_DPHY_CLK_CALIB_EN		\
+		MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
+#define RK3368_CSI_DPHY_LANE0_CALIB_EN		\
+		MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
+#define RK3368_CSI_DPHY_LANE1_CALIB_EN		\
+		MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
+#define RK3368_CSI_DPHY_LANE2_CALIB_EN		\
+		MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
+#define RK3368_CSI_DPHY_LANE3_CALIB_EN		\
+		MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
+
+#define HIWORD_UPDATE(val, mask, shift) \
+	((val) << (shift) | (mask) << ((shift) + 16))
+
+enum dphy_reg_id {
+	GRF_DPHY_RX0_TURNDISABLE = 0,
+	GRF_DPHY_RX0_FORCERXMODE,
+	GRF_DPHY_RX0_FORCETXSTOPMODE,
+	GRF_DPHY_RX0_ENABLE,
+	GRF_DPHY_RX0_TURNREQUEST,
+	GRF_DPHY_TX0_TURNDISABLE,
+	GRF_DPHY_TX0_FORCERXMODE,
+	GRF_DPHY_TX0_FORCETXSTOPMODE,
+	GRF_DPHY_TX0_TURNREQUEST,
+	GRF_DPHY_RX1_SRC_SEL,
+//	GRF_DVP_V18SEL,
+	/* rk1808 & rk3326 */
+	GRF_DPHY_CSIPHY_FORCERXMODE,
+	GRF_DPHY_CSIPHY_CLKLANE_EN,
+	GRF_DPHY_CSIPHY_DATALANE_EN,
+	/* rk3368 only */
+	GRF_ISP_MIPI_CSI_HOST_SEL,
+};
+
+struct dphy_reg {
+	u32 offset;
+	u32 mask;
+	u32 shift;
+};
+
+#define PHY_REG(_offset, _width, _shift) \
+	{ .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
+
+static const struct dphy_reg rk1808_grf_dphy_regs[] = {
+	[GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4, 0),
+	[GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 1, 8),
+	[GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4, 4),
+};
+
+static const struct dphy_reg rk3326_grf_dphy_regs[] = {
+//	[GRF_DVP_V18SEL] = PHY_REG(RK3326_GRF_IO_VSEL_OFFSET, 1, 4),
+	[GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 4, 0),
+	[GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 1, 8),
+	[GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 4, 4),
+};
+
+static const struct dphy_reg rk3368_grf_dphy_regs[] = {
+//	[GRF_DVP_V18SEL] = PHY_REG(RK3368_GRF_IO_VSEL_OFFSET, 1, 1),
+	[GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3368_GRF_SOC_CON6_OFFSET, 4, 8),
+	[GRF_ISP_MIPI_CSI_HOST_SEL] = PHY_REG(RK3368_GRF_SOC_CON6_OFFSET, 1, 1),
+//	[GRF_CON_DISABLE_ISP] = PHY_REG(RK3368_GRF_SOC_CON6_OFFSET, 1, 0),
+};
+
+struct hsfreq_range {
+	u32 range_h;
+	u8 cfg_bit;
+};
+
+struct rockchip_inno_csidphy;
+
+struct dphy_drv_data {
+	int pwrctl_offset;
+	int ths_settle_offset;
+	int calib_offset;
+	const struct hsfreq_range *hsfreq_ranges;
+	int num_hsfreq_ranges;
+	const struct dphy_reg *grf_regs;
+	void (*individual_init)(struct rockchip_inno_csidphy *priv);
+};
+
+struct rockchip_inno_csidphy {
+	struct device *dev;
+	void __iomem *phy_base;
+	struct clk *pclk;
+	struct regmap *grf;
+	struct reset_control *rst;
+	const struct dphy_drv_data *drv_data;
+	struct phy_configure_opts_mipi_dphy config;
+	u8 hsfreq;
+};
+
+static inline void write_grf_reg(struct rockchip_inno_csidphy *priv,
+				 int index, u8 value)
+{
+	struct dphy_drv_data *drv_data = priv->drv_data;
+	const struct dphy_reg *reg = &drv_data->grf_regs[index];
+	unsigned int val = HIWORD_UPDATE(value, reg->mask, reg->shift);
+
+	if (reg->offset)
+		regmap_write(priv->grf, reg->offset, val);
+}
+
+static inline u32 read_grf_reg(struct rockchip_inno_csidphy *priv, int index)
+{
+	struct dphy_drv_data *drv_data = priv->drv_data;
+	const struct dphy_reg *reg = &drv_data->grf_regs[index];
+	unsigned int val = 0;
+
+	if (reg->offset) {
+		regmap_read(priv->grf, reg->offset, &val);
+		val = (val >> reg->shift) & reg->mask;
+	}
+	return val;
+}
+
+/* These tables must be sorted by .range_h ascending. */
+static const struct hsfreq_range rk1808_mipidphy_hsfreq_ranges[] = {
+	{ 109, 0x02}, { 149, 0x03}, { 199, 0x06}, { 249, 0x06},
+	{ 299, 0x06}, { 399, 0x08}, { 499, 0x0b}, { 599, 0x0e},
+	{ 699, 0x10}, { 799, 0x12}, { 999, 0x16}, {1199, 0x1e},
+	{1399, 0x23}, {1599, 0x2d}, {1799, 0x32}, {1999, 0x37},
+	{2199, 0x3c}, {2399, 0x41}, {2499, 0x46}
+};
+
+static const struct hsfreq_range rk3326_mipidphy_hsfreq_ranges[] = {
+	{ 109, 0x00}, { 149, 0x01}, { 199, 0x02}, { 249, 0x03},
+	{ 299, 0x04}, { 399, 0x05}, { 499, 0x06}, { 599, 0x07},
+	{ 699, 0x08}, { 799, 0x09}, { 899, 0x0a}, {1099, 0x0b},
+	{1249, 0x0c}, {1349, 0x0d}, {1500, 0x0e}
+};
+
+static const struct hsfreq_range rk3368_mipidphy_hsfreq_ranges[] = {
+	{ 109, 0x00}, { 149, 0x01}, { 199, 0x02}, { 249, 0x03},
+	{ 299, 0x04}, { 399, 0x05}, { 499, 0x06}, { 599, 0x07},
+	{ 699, 0x08}, { 799, 0x09}, { 899, 0x0a}, {1099, 0x0b},
+	{1249, 0x0c}, {1349, 0x0d}, {1500, 0x0e}
+};
+
+static void default_mipidphy_individual_init(struct rockchip_inno_csidphy *priv)
+{
+}
+
+static void rk3368_mipidphy_individual_init(struct rockchip_inno_csidphy *priv)
+{
+	/* isp select */
+	write_grf_reg(priv, GRF_ISP_MIPI_CSI_HOST_SEL, 1);
+}
+
+static void rockchip_inno_csidphy_ths_settle(struct rockchip_inno_csidphy *priv,
+					     int hsfreq, int offset)
+{
+	struct dphy_drv_data *drv_data = priv->drv_data;
+	u32 val;
+
+	val = readl(priv->phy_base + drv_data->ths_settle_offset + offset);
+	val &= ~CSIDPHY_THS_SETTLE_MASK;
+	val |= hsfreq;
+	writel(val, priv->phy_base + drv_data->ths_settle_offset + offset);
+}
+
+static int rockchip_inno_csidphy_configure(struct phy *phy,
+					   union phy_configure_opts *opts)
+{
+	struct rockchip_inno_csidphy *priv = phy_get_drvdata(phy);
+	struct dphy_drv_data *drv_data = priv->drv_data;
+	struct phy_configure_opts_mipi_dphy *config = &opts->mipi_dphy;
+	unsigned int hsfreq = 0;
+	unsigned int i;
+	u64 data_rate_mbps;
+	int ret;
+
+	/* pass with phy_mipi_dphy_get_default_config (with pixel rate?) */
+	ret = phy_mipi_dphy_config_validate(config);
+	if (ret)
+		return ret;
+
+	data_rate_mbps = div_u64(config->hs_clk_rate, 1000 * 1000);
+
+	dev_dbg(priv->dev, "lanes %d - data_rate_mbps %llu\n",
+		config->lanes, data_rate_mbps);
+	for (i = 0; i < drv_data->num_hsfreq_ranges; i++) {
+		if (drv_data->hsfreq_ranges[i].range_h >= data_rate_mbps) {
+			hsfreq = drv_data->hsfreq_ranges[i].cfg_bit;
+			break;
+		}
+	}
+	if (!hsfreq)
+		return -EINVAL;
+
+	priv->hsfreq = hsfreq;
+	priv->config = *config;
+	return 0;
+}
+
+static int rockchip_inno_csidphy_power_on(struct phy *phy)
+{
+	struct rockchip_inno_csidphy *priv = phy_get_drvdata(phy);
+	struct dphy_drv_data *drv_data = priv->drv_data;
+	u32 val = 0;
+	int ret, i;
+
+	u64 data_rate_mbps;
+
+	data_rate_mbps = div_u64(priv->config.hs_clk_rate, 1000 * 1000);
+
+	ret = clk_enable(priv->pclk);
+	if (ret < 0)
+		return ret;
+
+//	write_grf_reg(priv, GRF_DVP_V18SEL, 0x1);
+
+	/* phy start */
+	if (drv_data->pwrctl_offset >= 0)
+		writel(CSIDPHY_CTRL_PWRCTL_UNDEFINED |
+		       CSIDPHY_CTRL_PWRCTL_SYNCRST,
+		       priv->phy_base + drv_data->pwrctl_offset);
+
+	/* set data lane num and enable clock lane */
+	val = GENMASK(priv->config.lanes - 1, 0) << CSIDPHY_CTRL_LANE_ENABLE_SHIFT;
+	writel(val | CSIDPHY_CTRL_LANE_ENABLE_CK |
+	       CSIDPHY_CTRL_LANE_ENABLE_UNDEFINED,
+	       priv->phy_base + CSIDPHY_CTRL_LANE_ENABLE);
+
+	/* Reset dphy analog part */
+	if (drv_data->pwrctl_offset >= 0)
+		writel(CSIDPHY_CTRL_PWRCTL_UNDEFINED,
+		       priv->phy_base + drv_data->pwrctl_offset);
+	usleep_range(500, 1000);
+
+
+	/* Reset dphy digital part */
+	writel(CSIDPHY_CTRL_DIG_RST_UNDEFINED,
+	       priv->phy_base + CSIDPHY_CTRL_DIG_RST);
+	writel(CSIDPHY_CTRL_DIG_RST_UNDEFINED + CSIDPHY_CTRL_DIG_RST_RESET,
+	       priv->phy_base + CSIDPHY_CTRL_DIG_RST);
+
+	/* not into receive mode/wait stopstate */
+	write_grf_reg(priv, GRF_DPHY_CSIPHY_FORCERXMODE, 0x0);
+
+	/* enable calibration */
+/* FIXME: reenable
+	if (data_rate_mbps > 1500) {
+		write_csiphy_reg(priv, CSIPHY_CLK_CALIB_ENABLE, 0x80);
+		if (priv->config.lanes > 0)
+			write_csiphy_reg(priv, CSIPHY_LANE0_CALIB_ENABLE, 0x80);
+		if (priv->config.lanes > 1)
+			write_csiphy_reg(priv, CSIPHY_LANE1_CALIB_ENABLE, 0x80);
+		if (priv->config.lanes > 2)
+			write_csiphy_reg(priv, CSIPHY_LANE2_CALIB_ENABLE, 0x80);
+		if (priv->config.lanes > 3)
+			write_csiphy_reg(priv, CSIPHY_LANE3_CALIB_ENABLE, 0x80);
+	} */
+
+	rockchip_inno_csidphy_ths_settle(priv, priv->hsfreq,
+					 CSIDPHY_CLK_THS_SETTLE);
+	for (i = 0; i < priv->config.lanes; i++)
+		rockchip_inno_csidphy_ths_settle(priv, priv->hsfreq,
+						 CSIDPHY_LANE_THS_SETTLE(i));
+
+//	write_grf_reg(priv, GRF_DPHY_CLK_INV_SEL, 0x1);
+	write_grf_reg(priv, GRF_DPHY_CSIPHY_CLKLANE_EN, 0x1);
+	write_grf_reg(priv, GRF_DPHY_CSIPHY_DATALANE_EN,
+		      GENMASK(priv->config.lanes - 1, 0));
+
+	return 0;
+}
+
+static int rockchip_inno_csidphy_power_off(struct phy *phy)
+{
+	struct rockchip_inno_csidphy *priv = phy_get_drvdata(phy);
+	struct dphy_drv_data *drv_data = priv->drv_data;
+
+	/* disable all lanes */
+	writel(CSIDPHY_CTRL_LANE_ENABLE_UNDEFINED,
+	       priv->phy_base + CSIDPHY_CTRL_LANE_ENABLE);
+
+	/* disable pll and ldo */
+	if (drv_data->pwrctl_offset >= 0)
+		writel(CSIDPHY_CTRL_PWRCTL_UNDEFINED |
+		       CSIDPHY_CTRL_PWRCTL_LDO_PD |
+		       CSIDPHY_CTRL_PWRCTL_PLL_PD,
+		       priv->phy_base + drv_data->pwrctl_offset);
+	usleep_range(500, 1000);
+
+	clk_disable(priv->pclk);
+
+	return 0;
+}
+
+static int rockchip_inno_csidphy_init(struct phy *phy)
+{
+	struct rockchip_inno_csidphy *priv = phy_get_drvdata(phy);
+
+	return clk_prepare(priv->pclk);
+}
+
+static int rockchip_inno_csidphy_exit(struct phy *phy)
+{
+	struct rockchip_inno_csidphy *priv = phy_get_drvdata(phy);
+
+	clk_unprepare(priv->pclk);
+
+	return 0;
+}
+
+static const struct phy_ops rockchip_inno_csidphy_ops = {
+	.power_on	= rockchip_inno_csidphy_power_on,
+	.power_off	= rockchip_inno_csidphy_power_off,
+	.init		= rockchip_inno_csidphy_init,
+	.exit		= rockchip_inno_csidphy_exit,
+	.configure	= rockchip_inno_csidphy_configure,
+	.owner		= THIS_MODULE,
+};
+
+
+static const struct dphy_drv_data rk1808_mipidphy_drv_data = {
+	.pwrctl_offset = -1,
+	.ths_settle_offset = RK1808_CSIDPHY_CLK_WR_THS_SETTLE,
+	.calib_offset = RK1808_CSIDPHY_CLK_CALIB_EN,
+	.hsfreq_ranges = rk1808_mipidphy_hsfreq_ranges,
+	.num_hsfreq_ranges = ARRAY_SIZE(rk1808_mipidphy_hsfreq_ranges),
+	.grf_regs = rk1808_grf_dphy_regs,
+
+	.individual_init = default_mipidphy_individual_init,
+};
+
+static const struct dphy_drv_data rk3326_mipidphy_drv_data = {
+	.pwrctl_offset = CSIDPHY_CTRL_PWRCTL,
+	.ths_settle_offset = RK3326_CSIDPHY_CLK_WR_THS_SETTLE,
+	.calib_offset = -1,
+	.hsfreq_ranges = rk3326_mipidphy_hsfreq_ranges,
+	.num_hsfreq_ranges = ARRAY_SIZE(rk3326_mipidphy_hsfreq_ranges),
+	.grf_regs = rk3326_grf_dphy_regs,
+
+	.individual_init = default_mipidphy_individual_init,
+};
+
+static const struct dphy_drv_data rk3368_mipidphy_drv_data = {
+	.pwrctl_offset = CSIDPHY_CTRL_PWRCTL,
+	.ths_settle_offset = RK3368_CSIDPHY_CLK_WR_THS_SETTLE,
+	.calib_offset = -1,
+	.hsfreq_ranges = rk3368_mipidphy_hsfreq_ranges,
+	.num_hsfreq_ranges = ARRAY_SIZE(rk3368_mipidphy_hsfreq_ranges),
+	.grf_regs = rk3368_grf_dphy_regs,
+
+	.individual_init = rk3368_mipidphy_individual_init,
+};
+
+static const struct of_device_id rockchip_inno_csidphy_match_id[] = {
+	{
+		.compatible = "rockchip,px30-mipi-dphy",
+		.data = &rk3326_mipidphy_drv_data,
+	},
+	{
+		.compatible = "rockchip,rk1808-mipi-dphy-rx",
+		.data = &rk1808_mipidphy_drv_data,
+	},
+	{
+		.compatible = "rockchip,rk3326-mipi-dphy",
+		.data = &rk3326_mipidphy_drv_data,
+	},
+	{
+		.compatible = "rockchip,rk3368-mipi-dphy",
+		.data = &rk3368_mipidphy_drv_data,
+	},
+	{}
+};
+MODULE_DEVICE_TABLE(of, rockchip_inno_csidphy_match_id);
+
+
+static int rockchip_inno_csidphy_probe(struct platform_device *pdev)
+{
+	struct rockchip_inno_csidphy *priv;
+	struct device *dev = &pdev->dev;
+	struct regmap *grf;
+	struct phy_provider *phy_provider;
+	struct phy *phy;
+	int i, ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->dev = dev;
+	platform_set_drvdata(pdev, priv);
+
+	priv->phy_base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(priv->phy_base))
+		return PTR_ERR(priv->phy_base);
+
+	priv->pclk = devm_clk_get(dev, "pclk");
+	if (IS_ERR(priv->pclk)) {
+		ret = PTR_ERR(priv->pclk);
+		dev_err(dev, "failed to get pclk: %d\n", ret);
+		return ret;
+	}
+
+	priv->rst = devm_reset_control_get(dev, "apb");
+	if (IS_ERR(priv->rst)) {
+		ret = PTR_ERR(priv->rst);
+		dev_err(dev, "failed to get system reset control: %d\n", ret);
+		return ret;
+	}
+
+	priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
+						    "rockchip,grf");
+	if (IS_ERR(priv->grf)) {
+		dev_err(dev, "Can't find GRF syscon\n");
+		return PTR_ERR(priv->grf);
+	}
+
+	priv->drv_data = of_device_get_match_data(dev);
+	if (!priv->drv_data) {
+		dev_err(dev, "Can't find device data\n");
+		return -ENODEV;
+	}
+
+	phy = devm_phy_create(dev, NULL, &rockchip_inno_csidphy_ops);
+	if (IS_ERR(phy)) {
+		ret = PTR_ERR(phy);
+		dev_err(dev, "failed to create phy: %d\n", ret);
+		return ret;
+	}
+
+	phy_set_drvdata(phy, priv);
+
+	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+	if (IS_ERR(phy_provider)) {
+		ret = PTR_ERR(phy_provider);
+		dev_err(dev, "failed to register phy provider: %d\n", ret);
+		return ret;
+	}
+
+	pm_runtime_enable(dev);
+
+	priv->drv_data->individual_init(priv);
+	return 0;
+}
+
+static int rockchip_inno_csidphy_remove(struct platform_device *pdev)
+{
+	struct rockchip_inno_csidphy *priv = platform_get_drvdata(pdev);
+
+	pm_runtime_disable(priv->dev);
+
+	return 0;
+}
+
+static struct platform_driver rockchip_inno_csidphy_driver = {
+	.driver = {
+			.name = "rockchip-inno-csidphy",
+			.of_match_table = rockchip_inno_csidphy_match_id,
+	},
+	.probe = rockchip_inno_csidphy_probe,
+	.remove = rockchip_inno_csidphy_remove,
+};
+
+module_platform_driver(rockchip_inno_csidphy_driver);
+MODULE_AUTHOR("Rockchip Camera/ISP team");
+MODULE_DESCRIPTION("Rockchip MIPI RX DPHY driver");
+MODULE_LICENSE("Dual BSD/GPL");
-- 
2.29.2

[PATCH RFC 05/11] media: rockchip: rkisp1: extend uapi array sizes

[Heiko Stuebner]

From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>

Later variants of the rkisp1 block use more entries in some arrays:

RKISP1_CIF_ISP_AE_MEAN_MAX                 25 -> 81
RKISP1_CIF_ISP_HIST_BIN_N_MAX              16 -> 32
RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES       17 -> 34
RKISP1_CIF_ISP_HISTOGRAM_WEIGHT_GRIDS_SIZE 28 -> 81

and we can still extend the uapi during the 5.11-rc cycle, so do that
now to be on the safe side.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
---
 include/uapi/linux/rkisp1-config.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/uapi/linux/rkisp1-config.h b/include/uapi/linux/rkisp1-config.h
index 6e449e784260..31a88bb65e03 100644
--- a/include/uapi/linux/rkisp1-config.h
+++ b/include/uapi/linux/rkisp1-config.h
@@ -49,8 +49,8 @@
 #define RKISP1_CIF_ISP_CTK_COEFF_MAX            0x100
 #define RKISP1_CIF_ISP_CTK_OFFSET_MAX           0x800
 
-#define RKISP1_CIF_ISP_AE_MEAN_MAX              25
-#define RKISP1_CIF_ISP_HIST_BIN_N_MAX           16
+#define RKISP1_CIF_ISP_AE_MEAN_MAX              81
+#define RKISP1_CIF_ISP_HIST_BIN_N_MAX           32
 #define RKISP1_CIF_ISP_AFM_MAX_WINDOWS          3
 #define RKISP1_CIF_ISP_DEGAMMA_CURVE_SIZE       17
 
@@ -86,7 +86,7 @@
  * Gamma out
  */
 /* Maximum number of color samples supported */
-#define RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES       17
+#define RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES       34
 
 /*
  * Lens shade correction
@@ -103,7 +103,7 @@
  * Histogram calculation
  */
 /* Last 3 values unused. */
-#define RKISP1_CIF_ISP_HISTOGRAM_WEIGHT_GRIDS_SIZE 28
+#define RKISP1_CIF_ISP_HISTOGRAM_WEIGHT_GRIDS_SIZE 81
 
 /*
  * Defect Pixel Cluster Correction
-- 
2.29.2

[PATCH RFC 06/11] media: rockchip: rkisp1: allow separate interrupts

[Heiko Stuebner]

From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>

Depending on the per-soc implementation there can be one interrupt
for isp, mipi and capture events or separate per-event interrupts.

So simply check for the presence of a named "mi" interrupt
to differentiate between the two cases.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
---
 .../platform/rockchip/rkisp1/rkisp1-capture.c |  9 ++-
 .../platform/rockchip/rkisp1/rkisp1-common.h  |  7 ++-
 .../platform/rockchip/rkisp1/rkisp1-dev.c     | 58 ++++++++++++++-----
 .../platform/rockchip/rkisp1/rkisp1-isp.c     | 16 +++--
 4 files changed, 69 insertions(+), 21 deletions(-)

diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
index 5f6c9d1623e4..f70c66c2a1d7 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
@@ -685,12 +685,17 @@ static void rkisp1_handle_buffer(struct rkisp1_capture *cap)
 	spin_unlock(&cap->buf.lock);
 }
 
-void rkisp1_capture_isr(struct rkisp1_device *rkisp1)
+irqreturn_t rkisp1_capture_isr(int irq, void *ctx)
 {
+	struct device *dev = ctx;
+	struct rkisp1_device *rkisp1 = dev_get_drvdata(dev);
 	unsigned int i;
 	u32 status;
 
 	status = rkisp1_read(rkisp1, RKISP1_CIF_MI_MIS);
+	if (!status)
+		return IRQ_NONE;
+
 	rkisp1_write(rkisp1, status, RKISP1_CIF_MI_ICR);
 
 	for (i = 0; i < ARRAY_SIZE(rkisp1->capture_devs); ++i) {
@@ -718,6 +723,8 @@ void rkisp1_capture_isr(struct rkisp1_device *rkisp1)
 		cap->is_streaming = false;
 		wake_up(&cap->done);
 	}
+
+	return IRQ_HANDLED;
 }
 
 /* ----------------------------------------------------------------------------
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
index 038c303a8aed..44f333bf5d6a 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
@@ -12,6 +12,7 @@
 #define _RKISP1_COMMON_H
 
 #include <linux/clk.h>
+#include <linux/interrupt.h>
 #include <linux/mutex.h>
 #include <linux/rkisp1-config.h>
 #include <media/media-device.h>
@@ -460,9 +461,9 @@ void rkisp1_params_configure(struct rkisp1_params *params,
 void rkisp1_params_disable(struct rkisp1_params *params);
 
 /* irq handlers */
-void rkisp1_isp_isr(struct rkisp1_device *rkisp1);
-void rkisp1_mipi_isr(struct rkisp1_device *rkisp1);
-void rkisp1_capture_isr(struct rkisp1_device *rkisp1);
+irqreturn_t rkisp1_isp_isr(int irq, void *ctx);
+irqreturn_t rkisp1_mipi_isr(int irq, void *ctx);
+irqreturn_t rkisp1_capture_isr(int irq, void *ctx);
 void rkisp1_stats_isr(struct rkisp1_stats *stats, u32 isp_ris);
 void rkisp1_params_isr(struct rkisp1_device *rkisp1);
 
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
index 68da1eed753d..96afc1d1a914 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
@@ -389,18 +389,15 @@ static int rkisp1_entities_register(struct rkisp1_device *rkisp1)
 
 static irqreturn_t rkisp1_isr(int irq, void *ctx)
 {
-	struct device *dev = ctx;
-	struct rkisp1_device *rkisp1 = dev_get_drvdata(dev);
-
 	/*
 	 * Call rkisp1_capture_isr() first to handle the frame that
 	 * potentially completed using the current frame_sequence number before
 	 * it is potentially incremented by rkisp1_isp_isr() in the vertical
 	 * sync.
 	 */
-	rkisp1_capture_isr(rkisp1);
-	rkisp1_isp_isr(rkisp1);
-	rkisp1_mipi_isr(rkisp1);
+	rkisp1_capture_isr(irq, ctx);
+	rkisp1_isp_isr(irq, ctx);
+	rkisp1_mipi_isr(irq, ctx);
 
 	return IRQ_HANDLED;
 }
@@ -481,15 +478,50 @@ static int rkisp1_probe(struct platform_device *pdev)
 	if (IS_ERR(rkisp1->base_addr))
 		return PTR_ERR(rkisp1->base_addr);
 
-	irq = platform_get_irq(pdev, 0);
-	if (irq < 0)
+	irq = platform_get_irq_byname_optional(pdev, "mi");
+	if (irq == -EPROBE_DEFER) {
 		return irq;
+	} else if (irq < 0) {
+		irq = platform_get_irq(pdev, 0);
+		if (irq < 0)
+			return irq;
+
+		ret = devm_request_irq(dev, irq, rkisp1_isr, IRQF_SHARED,
+				       dev_driver_string(dev), dev);
+		if (ret) {
+			dev_err(dev, "request irq failed: %d\n", ret);
+			return ret;
+		}
+	} else {
+		/* we test-got the MI (capture) interrupt */
+		ret = devm_request_irq(dev, irq, rkisp1_capture_isr, IRQF_SHARED,
+				       dev_driver_string(dev), dev);
+		if (ret) {
+			dev_err(dev, "request mi irq failed: %d\n", ret);
+			return ret;
+		}
 
-	ret = devm_request_irq(dev, irq, rkisp1_isr, IRQF_SHARED,
-			       dev_driver_string(dev), dev);
-	if (ret) {
-		dev_err(dev, "request irq failed: %d\n", ret);
-		return ret;
+		irq = platform_get_irq_byname_optional(pdev, "mipi");
+		if (irq < 0)
+			return irq;
+
+		ret = devm_request_irq(dev, irq, rkisp1_mipi_isr, IRQF_SHARED,
+				       dev_driver_string(dev), dev);
+		if (ret) {
+			dev_err(dev, "request mipi irq failed: %d\n", ret);
+			return ret;
+		}
+
+		irq = platform_get_irq_byname_optional(pdev, "isp");
+		if (irq < 0)
+			return irq;
+
+		ret = devm_request_irq(dev, irq, rkisp1_isp_isr, IRQF_SHARED,
+				       dev_driver_string(dev), dev);
+		if (ret) {
+			dev_err(dev, "request isp irq failed: %d\n", ret);
+			return ret;
+		}
 	}
 
 	rkisp1->irq = irq;
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
index 889982d8ca41..84440aa71210 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
@@ -1056,13 +1056,15 @@ void rkisp1_isp_unregister(struct rkisp1_device *rkisp1)
  * Interrupt handlers
  */
 
-void rkisp1_mipi_isr(struct rkisp1_device *rkisp1)
+irqreturn_t rkisp1_mipi_isr(int irq, void *ctx)
 {
+	struct device *dev = ctx;
+	struct rkisp1_device *rkisp1 = dev_get_drvdata(dev);
 	u32 val, status;
 
 	status = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_MIS);
 	if (!status)
-		return;
+		return IRQ_NONE;
 
 	rkisp1_write(rkisp1, status, RKISP1_CIF_MIPI_ICR);
 
@@ -1097,6 +1099,8 @@ void rkisp1_mipi_isr(struct rkisp1_device *rkisp1)
 	} else {
 		rkisp1->debug.mipi_error++;
 	}
+
+	return IRQ_HANDLED;
 }
 
 static void rkisp1_isp_queue_event_sof(struct rkisp1_isp *isp)
@@ -1109,13 +1113,15 @@ static void rkisp1_isp_queue_event_sof(struct rkisp1_isp *isp)
 	v4l2_event_queue(isp->sd.devnode, &event);
 }
 
-void rkisp1_isp_isr(struct rkisp1_device *rkisp1)
+irqreturn_t rkisp1_isp_isr(int irq, void *ctx)
 {
+	struct device *dev = ctx;
+	struct rkisp1_device *rkisp1 = dev_get_drvdata(dev);
 	u32 status, isp_err;
 
 	status = rkisp1_read(rkisp1, RKISP1_CIF_ISP_MIS);
 	if (!status)
-		return;
+		return IRQ_NONE;
 
 	rkisp1_write(rkisp1, status, RKISP1_CIF_ISP_ICR);
 
@@ -1157,4 +1163,6 @@ void rkisp1_isp_isr(struct rkisp1_device *rkisp1)
 		 */
 		rkisp1_params_isr(rkisp1);
 	}
+
+	return IRQ_HANDLED;
 }
-- 
2.29.2

[PATCH RFC 07/11] media: rockchip: rkisp1: carry ip version information

[Heiko Stuebner]

From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>

The IP block evolved from its rk3288/rk3399 base and the vendor
designates them with a numerical version. rk3399 for example
is designated V10 probably meaning V1.0.

There doesn't seem to be an actual version register we could read that
information from, so allow the match_data to carry that information
for future differentiation.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
---
 drivers/media/platform/rockchip/rkisp1/rkisp1-common.h | 5 +++++
 drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c    | 7 +++++--
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
index 44f333bf5d6a..7678eabc9ffc 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
@@ -59,6 +59,10 @@
 					 RKISP1_CIF_ISP_EXP_END |	\
 					 RKISP1_CIF_ISP_HIST_MEASURE_RDY)
 
+enum rkisp1_isp_ver {
+	RKISP1_V10 = 0,
+};
+
 /* enum for the resizer pads */
 enum rkisp1_rsz_pad {
 	RKISP1_RSZ_PAD_SINK,
@@ -355,6 +359,7 @@ struct rkisp1_device {
 	void __iomem *base_addr;
 	int irq;
 	struct device *dev;
+	enum rkisp1_isp_ver isp_ver;
 	unsigned int clk_size;
 	struct clk_bulk_data clks[RKISP1_MAX_BUS_CLK];
 	struct v4l2_device v4l2_dev;
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
index 96afc1d1a914..0a01ffbc2cae 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
@@ -104,6 +104,7 @@
 struct rkisp1_match_data {
 	const char * const *clks;
 	unsigned int size;
+	enum rkisp1_isp_ver isp_ver;
 };
 
 /* ----------------------------------------------------------------------------
@@ -408,15 +409,16 @@ static const char * const rk3399_isp_clks[] = {
 	"hclk",
 };
 
-static const struct rkisp1_match_data rk3399_isp_clk_data = {
+static const struct rkisp1_match_data rk3399_isp_match_data = {
 	.clks = rk3399_isp_clks,
 	.size = ARRAY_SIZE(rk3399_isp_clks),
+	.isp_ver = RKISP1_V10,
 };
 
 static const struct of_device_id rkisp1_of_match[] = {
 	{
 		.compatible = "rockchip,rk3399-cif-isp",
-		.data = &rk3399_isp_clk_data,
+		.data = &rk3399_isp_match_data,
 	},
 	{},
 };
@@ -532,6 +534,7 @@ static int rkisp1_probe(struct platform_device *pdev)
 	if (ret)
 		return ret;
 	rkisp1->clk_size = clk_data->size;
+	rkisp1->isp_ver = clk_data->isp_ver;
 
 	pm_runtime_enable(&pdev->dev);
 
-- 
2.29.2

[PATCH RFC 08/11] media: rockchip: rkisp1: make some isp-param functions variable

[Heiko Stuebner]

From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>

The isp block evolved in subsequent socs, so some functions
will behave differently on newer variants.

Therefore make it possible to override the needed params functions.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
---
 .../platform/rockchip/rkisp1/rkisp1-common.h  | 30 ++++++++
 .../platform/rockchip/rkisp1/rkisp1-params.c  | 76 ++++++++++++-------
 2 files changed, 77 insertions(+), 29 deletions(-)

diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
index 7678eabc9ffc..4034a05ef9d2 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
@@ -258,11 +258,39 @@ struct rkisp1_stats {
 	struct v4l2_format vdev_fmt;
 };
 
+struct rkisp1_params;
+struct rkisp1_params_ops {
+	void (*lsc_matrix_config)(struct rkisp1_params *params,
+				  const struct rkisp1_cif_isp_lsc_config *pconfig);
+	void (*goc_config)(struct rkisp1_params *params,
+			   const struct rkisp1_cif_isp_goc_config *arg);
+	void (*awb_meas_config)(struct rkisp1_params *params,
+				const struct rkisp1_cif_isp_awb_meas_config *arg);
+	void (*awb_meas_enable)(struct rkisp1_params *params,
+				const struct rkisp1_cif_isp_awb_meas_config *arg,
+				bool en);
+	void (*awb_gain_config)(struct rkisp1_params *params,
+				const struct rkisp1_cif_isp_awb_gain_config *arg);
+	void (*aec_config)(struct rkisp1_params *params,
+			   const struct rkisp1_cif_isp_aec_config *arg);
+	void (*hst_config)(struct rkisp1_params *params,
+			   const struct rkisp1_cif_isp_hst_config *arg);
+	void (*hst_enable)(struct rkisp1_params *params,
+			   const struct rkisp1_cif_isp_hst_config *arg, bool en);
+	void (*afm_config)(struct rkisp1_params *params,
+			   const struct rkisp1_cif_isp_afc_config *arg);
+};
+
+struct rkisp1_params_config {
+	const int gamma_out_max_samples;
+};
+
 /*
  * struct rkisp1_params - ISP input parameters device
  *
  * @vnode:		video node
  * @rkisp1:		pointer to the rkisp1 device
+ * @ops:		pointer to the variant-specific operations
  * @config_lock:	locks the buffer list 'params'
  * @params:		queue of rkisp1_buffer
  * @vdev_fmt:		v4l2_format of the metadata format
@@ -272,6 +300,8 @@ struct rkisp1_stats {
 struct rkisp1_params {
 	struct rkisp1_vdev_node vnode;
 	struct rkisp1_device *rkisp1;
+	struct rkisp1_params_ops *ops;
+	struct rkisp1_params_config *config;
 
 	spinlock_t config_lock; /* locks the buffers list 'params' */
 	struct list_head params;
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
index 6af4d551ffb5..008584caaad0 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
@@ -185,8 +185,8 @@ static void rkisp1_bls_config(struct rkisp1_params *params,
 
 /* ISP LS correction interface function */
 static void
-rkisp1_lsc_correct_matrix_config(struct rkisp1_params *params,
-				 const struct rkisp1_cif_isp_lsc_config *pconfig)
+rkisp1_lsc_matrix_config(struct rkisp1_params *params,
+			 const struct rkisp1_cif_isp_lsc_config *pconfig)
 {
 	unsigned int isp_lsc_status, sram_addr, isp_lsc_table_sel, i, j, data;
 
@@ -265,7 +265,7 @@ static void rkisp1_lsc_config(struct rkisp1_params *params,
 	lsc_ctrl = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_LSC_CTRL);
 	rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_LSC_CTRL,
 				RKISP1_CIF_ISP_LSC_CTRL_ENA);
-	rkisp1_lsc_correct_matrix_config(params, arg);
+	params->ops->lsc_matrix_config(params, arg);
 
 	for (i = 0; i < RKISP1_CIF_ISP_LSC_SECTORS_TBL_SIZE / 2; i++) {
 		/* program x size tables */
@@ -391,7 +391,7 @@ static void rkisp1_goc_config(struct rkisp1_params *params,
 				RKISP1_CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA);
 	rkisp1_write(params->rkisp1, arg->mode, RKISP1_CIF_ISP_GAMMA_OUT_MODE);
 
-	for (i = 0; i < RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES; i++)
+	for (i = 0; i < params->config->gamma_out_max_samples; i++)
 		rkisp1_write(params->rkisp1, arg->gamma_y[i],
 			     RKISP1_CIF_ISP_GAMMA_OUT_Y_0 + i * 4);
 }
@@ -968,8 +968,8 @@ rkisp1_isp_isr_other_config(struct rkisp1_params *params,
 	    (module_cfg_update & RKISP1_CIF_ISP_MODULE_AWB_GAIN)) {
 		/* update awb gains */
 		if (module_cfg_update & RKISP1_CIF_ISP_MODULE_AWB_GAIN)
-			rkisp1_awb_gain_config(params,
-					       &new_params->others.awb_gain_config);
+			params->ops->awb_gain_config(params,
+						     &new_params->others.awb_gain_config);
 
 		if (module_en_update & RKISP1_CIF_ISP_MODULE_AWB_GAIN) {
 			if (module_ens & RKISP1_CIF_ISP_MODULE_AWB_GAIN)
@@ -1037,8 +1037,8 @@ rkisp1_isp_isr_other_config(struct rkisp1_params *params,
 	    (module_cfg_update & RKISP1_CIF_ISP_MODULE_GOC)) {
 		/* update goc config */
 		if (module_cfg_update & RKISP1_CIF_ISP_MODULE_GOC)
-			rkisp1_goc_config(params,
-					  &new_params->others.goc_config);
+			params->ops->goc_config(params,
+						&new_params->others.goc_config);
 
 		if (module_en_update & RKISP1_CIF_ISP_MODULE_GOC) {
 			if (module_ens & RKISP1_CIF_ISP_MODULE_GOC)
@@ -1124,20 +1124,20 @@ static void rkisp1_isp_isr_meas_config(struct rkisp1_params *params,
 	    (module_cfg_update & RKISP1_CIF_ISP_MODULE_AWB)) {
 		/* update awb config */
 		if (module_cfg_update & RKISP1_CIF_ISP_MODULE_AWB)
-			rkisp1_awb_meas_config(params,
-					       &new_params->meas.awb_meas_config);
+			params->ops->awb_meas_config(params,
+						     &new_params->meas.awb_meas_config);
 
 		if (module_en_update & RKISP1_CIF_ISP_MODULE_AWB)
-			rkisp1_awb_meas_enable(params,
-					       &new_params->meas.awb_meas_config,
-					       !!(module_ens & RKISP1_CIF_ISP_MODULE_AWB));
+			params->ops->awb_meas_enable(params,
+						     &new_params->meas.awb_meas_config,
+						     !!(module_ens & RKISP1_CIF_ISP_MODULE_AWB));
 	}
 
 	if ((module_en_update & RKISP1_CIF_ISP_MODULE_AFC) ||
 	    (module_cfg_update & RKISP1_CIF_ISP_MODULE_AFC)) {
 		/* update afc config */
 		if (module_cfg_update & RKISP1_CIF_ISP_MODULE_AFC)
-			rkisp1_afm_config(params,
+			params->ops->afm_config(params,
 					  &new_params->meas.afc_config);
 
 		if (module_en_update & RKISP1_CIF_ISP_MODULE_AFC) {
@@ -1156,21 +1156,21 @@ static void rkisp1_isp_isr_meas_config(struct rkisp1_params *params,
 	    (module_cfg_update & RKISP1_CIF_ISP_MODULE_HST)) {
 		/* update hst config */
 		if (module_cfg_update & RKISP1_CIF_ISP_MODULE_HST)
-			rkisp1_hst_config(params,
-					  &new_params->meas.hst_config);
+			params->ops->hst_config(params,
+						&new_params->meas.hst_config);
 
 		if (module_en_update & RKISP1_CIF_ISP_MODULE_HST)
-			rkisp1_hst_enable(params,
-					  &new_params->meas.hst_config,
-					  !!(module_ens & RKISP1_CIF_ISP_MODULE_HST));
+			params->ops->hst_enable(params,
+						&new_params->meas.hst_config,
+						!!(module_ens & RKISP1_CIF_ISP_MODULE_HST));
 	}
 
 	if ((module_en_update & RKISP1_CIF_ISP_MODULE_AEC) ||
 	    (module_cfg_update & RKISP1_CIF_ISP_MODULE_AEC)) {
 		/* update aec config */
 		if (module_cfg_update & RKISP1_CIF_ISP_MODULE_AEC)
-			rkisp1_aec_config(params,
-					  &new_params->meas.aec_config);
+			params->ops->aec_config(params,
+						&new_params->meas.aec_config);
 
 		if (module_en_update & RKISP1_CIF_ISP_MODULE_AEC) {
 			if (module_ens & RKISP1_CIF_ISP_MODULE_AEC)
@@ -1272,20 +1272,20 @@ static void rkisp1_params_config_parameter(struct rkisp1_params *params)
 {
 	struct rkisp1_cif_isp_hst_config hst = rkisp1_hst_params_default_config;
 
-	rkisp1_awb_meas_config(params, &rkisp1_awb_params_default_config);
-	rkisp1_awb_meas_enable(params, &rkisp1_awb_params_default_config,
-			       true);
+	params->ops->awb_meas_config(params, &rkisp1_awb_params_default_config);
+	params->ops->awb_meas_enable(params, &rkisp1_awb_params_default_config,
+				     true);
 
-	rkisp1_aec_config(params, &rkisp1_aec_params_default_config);
+	params->ops->aec_config(params, &rkisp1_aec_params_default_config);
 	rkisp1_param_set_bits(params, RKISP1_CIF_ISP_EXP_CTRL,
 			      RKISP1_CIF_ISP_EXP_ENA);
 
-	rkisp1_afm_config(params, &rkisp1_afc_params_default_config);
+	params->ops->afm_config(params, &rkisp1_afc_params_default_config);
 	rkisp1_param_set_bits(params, RKISP1_CIF_ISP_AFM_CTRL,
 			      RKISP1_CIF_ISP_AFM_ENA);
 
 	memset(hst.hist_weight, 0x01, sizeof(hst.hist_weight));
-	rkisp1_hst_config(params, &hst);
+	params->ops->hst_config(params, &hst);
 	rkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_PROP,
 			      ~RKISP1_CIF_ISP_HIST_PROP_MODE_MASK |
 			      rkisp1_hst_params_default_config.mode);
@@ -1330,7 +1330,7 @@ void rkisp1_params_disable(struct rkisp1_params *params)
 				RKISP1_CIF_ISP_DEMOSAIC_BYPASS);
 	rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_FILT_MODE,
 				RKISP1_CIF_ISP_FLT_ENA);
-	rkisp1_awb_meas_enable(params, NULL, false);
+	params->ops->awb_meas_enable(params, NULL, false);
 	rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_CTRL,
 				RKISP1_CIF_ISP_CTRL_ISP_AWB_ENA);
 	rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_EXP_CTRL,
@@ -1338,7 +1338,7 @@ void rkisp1_params_disable(struct rkisp1_params *params)
 	rkisp1_ctk_enable(params, false);
 	rkisp1_param_clear_bits(params, RKISP1_CIF_C_PROC_CTRL,
 				RKISP1_CIF_C_PROC_CTR_ENABLE);
-	rkisp1_hst_enable(params, NULL, false);
+	params->ops->hst_enable(params, NULL, false);
 	rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_AFM_CTRL,
 				RKISP1_CIF_ISP_AFM_ENA);
 	rkisp1_ie_enable(params, false);
@@ -1346,6 +1346,22 @@ void rkisp1_params_disable(struct rkisp1_params *params)
 				RKISP1_CIF_ISP_DPF_MODE_EN);
 }
 
+static struct rkisp1_params_ops rkisp1_params_ops = {
+	.lsc_matrix_config = rkisp1_lsc_matrix_config,
+	.goc_config = rkisp1_goc_config,
+	.awb_meas_config = rkisp1_awb_meas_config,
+	.awb_meas_enable = rkisp1_awb_meas_enable,
+	.awb_gain_config = rkisp1_awb_gain_config,
+	.aec_config = rkisp1_aec_config,
+	.hst_config = rkisp1_hst_config,
+	.hst_enable = rkisp1_hst_enable,
+	.afm_config = rkisp1_afm_config,
+};
+
+static struct rkisp1_params_config rkisp1_params_config = {
+	.gamma_out_max_samples = 17,
+};
+
 static int rkisp1_params_enum_fmt_meta_out(struct file *file, void *priv,
 					   struct v4l2_fmtdesc *f)
 {
@@ -1512,6 +1528,8 @@ static void rkisp1_init_params(struct rkisp1_params *params)
 		V4L2_META_FMT_RK_ISP1_PARAMS;
 	params->vdev_fmt.fmt.meta.buffersize =
 		sizeof(struct rkisp1_params_cfg);
+	params->ops = &rkisp1_params_ops;
+	params->config = &rkisp1_params_config;
 }
 
 int rkisp1_params_register(struct rkisp1_device *rkisp1)
-- 
2.29.2

[PATCH RFC 09/11] media: rockchip: rkisp1: make some isp-stats functions variable

[Heiko Stuebner]

From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>

The isp block evolved in subsequent socs, so some functions
will behave differently on newer variants.

Therefore make it possible to override the needed stats functions.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
---
 .../platform/rockchip/rkisp1/rkisp1-common.h  | 17 +++++++++++++
 .../platform/rockchip/rkisp1/rkisp1-stats.c   | 24 +++++++++++++++----
 2 files changed, 36 insertions(+), 5 deletions(-)

diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
index 4034a05ef9d2..be0ae02165c9 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
@@ -240,6 +240,21 @@ struct rkisp1_capture {
 	} pix;
 };
 
+struct rkisp1_stats;
+struct rkisp1_stats_ops {
+	void (*get_awb_meas)(struct rkisp1_stats *stats,
+			     struct rkisp1_stat_buffer *pbuf);
+	void (*get_aec_meas)(struct rkisp1_stats *stats,
+			     struct rkisp1_stat_buffer *pbuf);
+	void (*get_hst_meas)(struct rkisp1_stats *stats,
+			     struct rkisp1_stat_buffer *pbuf);
+};
+
+struct rkisp1_stats_config {
+	const int ae_mean_max;
+	const int hist_bin_n_max;
+};
+
 /*
  * struct rkisp1_stats - ISP Statistics device
  *
@@ -252,6 +267,8 @@ struct rkisp1_capture {
 struct rkisp1_stats {
 	struct rkisp1_vdev_node vnode;
 	struct rkisp1_device *rkisp1;
+	struct rkisp1_stats_ops *ops;
+	struct rkisp1_stats_config *config;
 
 	spinlock_t lock; /* locks the buffers list 'stats' */
 	struct list_head stat;
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c
index 3ddab8fa8f2d..7136292039f6 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c
@@ -203,7 +203,7 @@ static void rkisp1_stats_get_aec_meas(struct rkisp1_stats *stats,
 	unsigned int i;
 
 	pbuf->meas_type |= RKISP1_CIF_ISP_STAT_AUTOEXP;
-	for (i = 0; i < RKISP1_CIF_ISP_AE_MEAN_MAX; i++)
+	for (i = 0; i < stats->config->ae_mean_max; i++)
 		pbuf->params.ae.exp_mean[i] =
 			(u8)rkisp1_read(rkisp1,
 					RKISP1_CIF_ISP_EXP_MEAN_00 + i * 4);
@@ -233,7 +233,7 @@ static void rkisp1_stats_get_hst_meas(struct rkisp1_stats *stats,
 	unsigned int i;
 
 	pbuf->meas_type |= RKISP1_CIF_ISP_STAT_HIST;
-	for (i = 0; i < RKISP1_CIF_ISP_HIST_BIN_N_MAX; i++)
+	for (i = 0; i < stats->config->hist_bin_n_max; i++)
 		pbuf->params.hist.hist_bins[i] =
 			(u8)rkisp1_read(rkisp1,
 					RKISP1_CIF_ISP_HIST_BIN_0 + i * 4);
@@ -286,6 +286,17 @@ static void rkisp1_stats_get_bls_meas(struct rkisp1_stats *stats,
 	}
 }
 
+static struct rkisp1_stats_ops rkisp1_stats_ops = {
+	.get_awb_meas = rkisp1_stats_get_awb_meas,
+	.get_aec_meas = rkisp1_stats_get_aec_meas,
+	.get_hst_meas = rkisp1_stats_get_hst_meas,
+};
+
+static struct rkisp1_stats_config rkisp1_stats_config = {
+	.ae_mean_max = 25,
+	.hist_bin_n_max = 16,
+};
+
 static void
 rkisp1_stats_send_measurement(struct rkisp1_stats *stats, u32 isp_ris)
 {
@@ -308,18 +319,18 @@ rkisp1_stats_send_measurement(struct rkisp1_stats *stats, u32 isp_ris)
 		(struct rkisp1_stat_buffer *)(cur_buf->vaddr);
 
 	if (isp_ris & RKISP1_CIF_ISP_AWB_DONE)
-		rkisp1_stats_get_awb_meas(stats, cur_stat_buf);
+		stats->ops->get_awb_meas(stats, cur_stat_buf);
 
 	if (isp_ris & RKISP1_CIF_ISP_AFM_FIN)
 		rkisp1_stats_get_afc_meas(stats, cur_stat_buf);
 
 	if (isp_ris & RKISP1_CIF_ISP_EXP_END) {
-		rkisp1_stats_get_aec_meas(stats, cur_stat_buf);
+		stats->ops->get_aec_meas(stats, cur_stat_buf);
 		rkisp1_stats_get_bls_meas(stats, cur_stat_buf);
 	}
 
 	if (isp_ris & RKISP1_CIF_ISP_HIST_MEASURE_RDY)
-		rkisp1_stats_get_hst_meas(stats, cur_stat_buf);
+		stats->ops->get_hst_meas(stats, cur_stat_buf);
 
 	vb2_set_plane_payload(&cur_buf->vb.vb2_buf, 0,
 			      sizeof(struct rkisp1_stat_buffer));
@@ -353,6 +364,9 @@ static void rkisp1_init_stats(struct rkisp1_stats *stats)
 		V4L2_META_FMT_RK_ISP1_STAT_3A;
 	stats->vdev_fmt.fmt.meta.buffersize =
 		sizeof(struct rkisp1_stat_buffer);
+
+	stats->ops = &rkisp1_stats_ops;
+	stats->config = &rkisp1_stats_config;
 }
 
 int rkisp1_stats_register(struct rkisp1_device *rkisp1)
-- 
2.29.2

[PATCH RFC 10/11] media: rockchip: rkisp1: add support for v12 isp variants

[Heiko Stuebner]

From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>

The rkisp1 evolved over soc generations and the rk3326/px30 introduced
the so called v12 - probably meaning v1.2.

Add the changed register definitions.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
---
 .../platform/rockchip/rkisp1/rkisp1-common.h  |   1 +
 .../platform/rockchip/rkisp1/rkisp1-isp.c     |  13 +
 .../platform/rockchip/rkisp1/rkisp1-params.c  | 535 +++++++++++++++---
 .../platform/rockchip/rkisp1/rkisp1-regs.h    | 404 ++++++++-----
 .../platform/rockchip/rkisp1/rkisp1-stats.c   | 112 +++-
 5 files changed, 824 insertions(+), 241 deletions(-)

diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
index be0ae02165c9..9deb1ef1aa8b 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
@@ -61,6 +61,7 @@
 
 enum rkisp1_isp_ver {
 	RKISP1_V10 = 0,
+	RKISP1_V12,
 };
 
 /* enum for the resizer pads */
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
index 84440aa71210..306cc96f8230 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
@@ -408,6 +408,10 @@ static int rkisp1_config_mipi(struct rkisp1_device *rkisp1)
 
 	rkisp1_write(rkisp1, mipi_ctrl, RKISP1_CIF_MIPI_CTRL);
 
+	/* V12 could also use a newer csi2-host, but we don't want that yet */
+	if (rkisp1->isp_ver == RKISP1_V12)
+		rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_CSI0_CTRL0);
+
 	/* Configure Data Type and Virtual Channel */
 	rkisp1_write(rkisp1,
 		     RKISP1_CIF_MIPI_DATA_SEL_DT(sink_fmt->mipi_dt) |
@@ -527,6 +531,15 @@ static void rkisp1_config_clk(struct rkisp1_device *rkisp1)
 		  RKISP1_CIF_ICCL_DCROP_CLK;
 
 	rkisp1_write(rkisp1, val, RKISP1_CIF_ICCL);
+
+	/* ensure sp and mp can run at the same time in V12 */
+	if (rkisp1->isp_ver == RKISP1_V12) {
+		val = RKISP1_CIF_CLK_CTRL_MI_Y12 | RKISP1_CIF_CLK_CTRL_MI_SP |
+		      RKISP1_CIF_CLK_CTRL_MI_RAW0 | RKISP1_CIF_CLK_CTRL_MI_RAW1 |
+		      RKISP1_CIF_CLK_CTRL_MI_READ | RKISP1_CIF_CLK_CTRL_MI_RAWRD |
+		      RKISP1_CIF_CLK_CTRL_CP | RKISP1_CIF_CLK_CTRL_IE;
+		rkisp1_write(rkisp1, val, RKISP1_CIF_VI_ISP_CLK_CTRL_V12);
+	}
 }
 
 static void rkisp1_isp_start(struct rkisp1_device *rkisp1)
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
index 008584caaad0..408fa33bdc30 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
@@ -185,8 +185,8 @@ static void rkisp1_bls_config(struct rkisp1_params *params,
 
 /* ISP LS correction interface function */
 static void
-rkisp1_lsc_matrix_config(struct rkisp1_params *params,
-			 const struct rkisp1_cif_isp_lsc_config *pconfig)
+rkisp1_lsc_matrix_config_v10(struct rkisp1_params *params,
+			     const struct rkisp1_cif_isp_lsc_config *pconfig)
 {
 	unsigned int isp_lsc_status, sram_addr, isp_lsc_table_sel, i, j, data;
 
@@ -212,39 +212,111 @@ rkisp1_lsc_matrix_config(struct rkisp1_params *params,
 		 * DWORDs (2nd value of last DWORD unused)
 		 */
 		for (j = 0; j < RKISP1_CIF_ISP_LSC_SAMPLES_MAX - 1; j += 2) {
-			data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->r_data_tbl[i][j],
-							     pconfig->r_data_tbl[i][j + 1]);
+			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->r_data_tbl[i][j],
+								 pconfig->r_data_tbl[i][j + 1]);
 			rkisp1_write(params->rkisp1, data,
 				     RKISP1_CIF_ISP_LSC_R_TABLE_DATA);
 
-			data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->gr_data_tbl[i][j],
-							     pconfig->gr_data_tbl[i][j + 1]);
+			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->gr_data_tbl[i][j],
+								 pconfig->gr_data_tbl[i][j + 1]);
 			rkisp1_write(params->rkisp1, data,
 				     RKISP1_CIF_ISP_LSC_GR_TABLE_DATA);
 
-			data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->gb_data_tbl[i][j],
-							     pconfig->gb_data_tbl[i][j + 1]);
+			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->gb_data_tbl[i][j],
+								 pconfig->gb_data_tbl[i][j + 1]);
 			rkisp1_write(params->rkisp1, data,
 				     RKISP1_CIF_ISP_LSC_GB_TABLE_DATA);
 
-			data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->b_data_tbl[i][j],
-							     pconfig->b_data_tbl[i][j + 1]);
+			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->b_data_tbl[i][j],
+								 pconfig->b_data_tbl[i][j + 1]);
 			rkisp1_write(params->rkisp1, data,
 				     RKISP1_CIF_ISP_LSC_B_TABLE_DATA);
 		}
-		data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->r_data_tbl[i][j], 0);
+		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->r_data_tbl[i][j], 0);
 		rkisp1_write(params->rkisp1, data,
 			     RKISP1_CIF_ISP_LSC_R_TABLE_DATA);
 
-		data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->gr_data_tbl[i][j], 0);
+		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->gr_data_tbl[i][j], 0);
 		rkisp1_write(params->rkisp1, data,
 			     RKISP1_CIF_ISP_LSC_GR_TABLE_DATA);
 
-		data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->gb_data_tbl[i][j], 0);
+		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->gb_data_tbl[i][j], 0);
 		rkisp1_write(params->rkisp1, data,
 			     RKISP1_CIF_ISP_LSC_GB_TABLE_DATA);
 
-		data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->b_data_tbl[i][j], 0);
+		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->b_data_tbl[i][j], 0);
+		rkisp1_write(params->rkisp1, data,
+			     RKISP1_CIF_ISP_LSC_B_TABLE_DATA);
+	}
+	isp_lsc_table_sel = (isp_lsc_status & RKISP1_CIF_ISP_LSC_ACTIVE_TABLE) ?
+			    RKISP1_CIF_ISP_LSC_TABLE_0 :
+			    RKISP1_CIF_ISP_LSC_TABLE_1;
+	rkisp1_write(params->rkisp1, isp_lsc_table_sel,
+		     RKISP1_CIF_ISP_LSC_TABLE_SEL);
+}
+
+static void
+rkisp1_lsc_matrix_config_v12(struct rkisp1_params *params,
+			     const struct rkisp1_cif_isp_lsc_config *pconfig)
+{
+	unsigned int isp_lsc_status, sram_addr, isp_lsc_table_sel, i, j, data;
+
+	isp_lsc_status = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_LSC_STATUS);
+
+	/* RKISP1_CIF_ISP_LSC_TABLE_ADDRESS_153 = ( 17 * 18 ) >> 1 */
+	sram_addr = (isp_lsc_status & RKISP1_CIF_ISP_LSC_ACTIVE_TABLE) ?
+		     RKISP1_CIF_ISP_LSC_TABLE_ADDRESS_0 :
+		     RKISP1_CIF_ISP_LSC_TABLE_ADDRESS_153;
+	rkisp1_write(params->rkisp1, sram_addr, RKISP1_CIF_ISP_LSC_R_TABLE_ADDR);
+	rkisp1_write(params->rkisp1, sram_addr, RKISP1_CIF_ISP_LSC_GR_TABLE_ADDR);
+	rkisp1_write(params->rkisp1, sram_addr, RKISP1_CIF_ISP_LSC_GB_TABLE_ADDR);
+	rkisp1_write(params->rkisp1, sram_addr, RKISP1_CIF_ISP_LSC_B_TABLE_ADDR);
+
+	/* program data tables (table size is 9 * 17 = 153) */
+	for (i = 0; i < RKISP1_CIF_ISP_LSC_SAMPLES_MAX; i++) {
+		/*
+		 * 17 sectors with 2 values in one DWORD = 9
+		 * DWORDs (2nd value of last DWORD unused)
+		 */
+		for (j = 0; j < RKISP1_CIF_ISP_LSC_SAMPLES_MAX - 1; j += 2) {
+			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(
+					pconfig->r_data_tbl[i][j],
+					pconfig->r_data_tbl[i][j + 1]);
+			rkisp1_write(params->rkisp1, data,
+				     RKISP1_CIF_ISP_LSC_R_TABLE_DATA);
+
+			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(
+					pconfig->gr_data_tbl[i][j],
+					pconfig->gr_data_tbl[i][j + 1]);
+			rkisp1_write(params->rkisp1, data,
+				     RKISP1_CIF_ISP_LSC_GR_TABLE_DATA);
+
+			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(
+					pconfig->gb_data_tbl[i][j],
+					pconfig->gb_data_tbl[i][j + 1]);
+			rkisp1_write(params->rkisp1, data,
+				     RKISP1_CIF_ISP_LSC_GB_TABLE_DATA);
+
+			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(
+					pconfig->b_data_tbl[i][j],
+					pconfig->b_data_tbl[i][j + 1]);
+			rkisp1_write(params->rkisp1, data,
+				     RKISP1_CIF_ISP_LSC_B_TABLE_DATA);
+		}
+
+		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(pconfig->r_data_tbl[i][j], 0);
+		rkisp1_write(params->rkisp1, data,
+			     RKISP1_CIF_ISP_LSC_R_TABLE_DATA);
+
+		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(pconfig->gr_data_tbl[i][j], 0);
+		rkisp1_write(params->rkisp1, data,
+			     RKISP1_CIF_ISP_LSC_GR_TABLE_DATA);
+
+		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(pconfig->gb_data_tbl[i][j], 0);
+		rkisp1_write(params->rkisp1, data,
+			     RKISP1_CIF_ISP_LSC_GB_TABLE_DATA);
+
+		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(pconfig->b_data_tbl[i][j], 0);
 		rkisp1_write(params->rkisp1, data,
 			     RKISP1_CIF_ISP_LSC_B_TABLE_DATA);
 	}
@@ -382,18 +454,37 @@ static void rkisp1_sdg_config(struct rkisp1_params *params,
 }
 
 /* ISP GAMMA correction interface function */
-static void rkisp1_goc_config(struct rkisp1_params *params,
-			      const struct rkisp1_cif_isp_goc_config *arg)
+static void rkisp1_goc_config_v10(struct rkisp1_params *params,
+				  const struct rkisp1_cif_isp_goc_config *arg)
 {
 	unsigned int i;
 
 	rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_CTRL,
 				RKISP1_CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA);
-	rkisp1_write(params->rkisp1, arg->mode, RKISP1_CIF_ISP_GAMMA_OUT_MODE);
+	rkisp1_write(params->rkisp1, arg->mode, RKISP1_CIF_ISP_GAMMA_OUT_MODE_V10);
 
 	for (i = 0; i < params->config->gamma_out_max_samples; i++)
 		rkisp1_write(params->rkisp1, arg->gamma_y[i],
-			     RKISP1_CIF_ISP_GAMMA_OUT_Y_0 + i * 4);
+			     RKISP1_CIF_ISP_GAMMA_OUT_Y_0_V10 + i * 4);
+}
+
+static void rkisp1_goc_config_v12(struct rkisp1_params *params,
+				  const struct rkisp1_cif_isp_goc_config *arg)
+{
+	int i;
+	u32 value;
+
+	rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_CTRL,
+				RKISP1_CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA);
+	rkisp1_write(params->rkisp1, arg->mode, RKISP1_CIF_ISP_GAMMA_OUT_MODE_V12);
+
+	for (i = 0; i < params->config->gamma_out_max_samples / 2; i++) {
+		value = RKISP1_CIF_ISP_GAMMA_VALUE_V12(
+			arg->gamma_y[2 * i + 1],
+			arg->gamma_y[2 * i]);
+		rkisp1_write(params->rkisp1, value,
+			     RKISP1_CIF_ISP_GAMMA_OUT_Y_0_V12 + i * 4);
+	}
 }
 
 /* ISP Cross Talk */
@@ -433,8 +524,8 @@ static void rkisp1_ctk_enable(struct rkisp1_params *params, bool en)
 }
 
 /* ISP White Balance Mode */
-static void rkisp1_awb_meas_config(struct rkisp1_params *params,
-				   const struct rkisp1_cif_isp_awb_meas_config *arg)
+static void rkisp1_awb_meas_config_v10(struct rkisp1_params *params,
+				       const struct rkisp1_cif_isp_awb_meas_config *arg)
 {
 	u32 reg_val = 0;
 	/* based on the mode,configure the awb module */
@@ -442,43 +533,82 @@ static void rkisp1_awb_meas_config(struct rkisp1_params *params,
 		/* Reference Cb and Cr */
 		rkisp1_write(params->rkisp1,
 			     RKISP1_CIF_ISP_AWB_REF_CR_SET(arg->awb_ref_cr) |
-			     arg->awb_ref_cb, RKISP1_CIF_ISP_AWB_REF);
+			     arg->awb_ref_cb, RKISP1_CIF_ISP_AWB_REF_V10);
 		/* Yc Threshold */
 		rkisp1_write(params->rkisp1,
 			     RKISP1_CIF_ISP_AWB_MAX_Y_SET(arg->max_y) |
 			     RKISP1_CIF_ISP_AWB_MIN_Y_SET(arg->min_y) |
 			     RKISP1_CIF_ISP_AWB_MAX_CS_SET(arg->max_csum) |
-			     arg->min_c, RKISP1_CIF_ISP_AWB_THRESH);
+			     arg->min_c, RKISP1_CIF_ISP_AWB_THRESH_V10);
 	}
 
-	reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP);
+	reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP_V10);
 	if (arg->enable_ymax_cmp)
 		reg_val |= RKISP1_CIF_ISP_AWB_YMAX_CMP_EN;
 	else
 		reg_val &= ~RKISP1_CIF_ISP_AWB_YMAX_CMP_EN;
-	rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP);
+	rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP_V10);
 
 	/* window offset */
 	rkisp1_write(params->rkisp1,
-		     arg->awb_wnd.v_offs, RKISP1_CIF_ISP_AWB_WND_V_OFFS);
+		     arg->awb_wnd.v_offs, RKISP1_CIF_ISP_AWB_WND_V_OFFS_V10);
 	rkisp1_write(params->rkisp1,
-		     arg->awb_wnd.h_offs, RKISP1_CIF_ISP_AWB_WND_H_OFFS);
+		     arg->awb_wnd.h_offs, RKISP1_CIF_ISP_AWB_WND_H_OFFS_V10);
 	/* AWB window size */
 	rkisp1_write(params->rkisp1,
-		     arg->awb_wnd.v_size, RKISP1_CIF_ISP_AWB_WND_V_SIZE);
+		     arg->awb_wnd.v_size, RKISP1_CIF_ISP_AWB_WND_V_SIZE_V10);
 	rkisp1_write(params->rkisp1,
-		     arg->awb_wnd.h_size, RKISP1_CIF_ISP_AWB_WND_H_SIZE);
+		     arg->awb_wnd.h_size, RKISP1_CIF_ISP_AWB_WND_H_SIZE_V10);
 	/* Number of frames */
 	rkisp1_write(params->rkisp1,
-		     arg->frames, RKISP1_CIF_ISP_AWB_FRAMES);
+		     arg->frames, RKISP1_CIF_ISP_AWB_FRAMES_V10);
+}
+
+static void rkisp1_awb_meas_config_v12(struct rkisp1_params *params,
+				       const struct rkisp1_cif_isp_awb_meas_config *arg)
+{
+	u32 reg_val = 0;
+	/* based on the mode,configure the awb module */
+	if (arg->awb_mode == RKISP1_CIF_ISP_AWB_MODE_YCBCR) {
+		/* Reference Cb and Cr */
+		rkisp1_write(params->rkisp1,
+			     RKISP1_CIF_ISP_AWB_REF_CR_SET(arg->awb_ref_cr) |
+			     arg->awb_ref_cb, RKISP1_CIF_ISP_AWB_REF_V12);
+		/* Yc Threshold */
+		rkisp1_write(params->rkisp1,
+			     RKISP1_CIF_ISP_AWB_MAX_Y_SET(arg->max_y) |
+			     RKISP1_CIF_ISP_AWB_MIN_Y_SET(arg->min_y) |
+			     RKISP1_CIF_ISP_AWB_MAX_CS_SET(arg->max_csum) |
+			     arg->min_c, RKISP1_CIF_ISP_AWB_THRESH_V12);
+	}
+
+	reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP_V12);
+	if (arg->enable_ymax_cmp)
+		reg_val |= RKISP1_CIF_ISP_AWB_YMAX_CMP_EN;
+	else
+		reg_val &= ~RKISP1_CIF_ISP_AWB_YMAX_CMP_EN;
+	reg_val &= ~RKISP1_CIF_ISP_AWB_SET_FRAMES_MASK_V12;
+	reg_val |= RKISP1_CIF_ISP_AWB_SET_FRAMES_V12(arg->frames);
+	rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP_V12);
+
+	/* window offset */
+	rkisp1_write(params->rkisp1,
+		     arg->awb_wnd.v_offs << 16 |
+		     arg->awb_wnd.h_offs,
+		     RKISP1_CIF_ISP_AWB_OFFS_V12);
+	/* AWB window size */
+	rkisp1_write(params->rkisp1,
+		     arg->awb_wnd.v_size << 16 |
+		     arg->awb_wnd.h_size,
+		     RKISP1_CIF_ISP_AWB_SIZE_V12);
 }
 
 static void
-rkisp1_awb_meas_enable(struct rkisp1_params *params,
-		       const struct rkisp1_cif_isp_awb_meas_config *arg,
-		       bool en)
+rkisp1_awb_meas_enable_v10(struct rkisp1_params *params,
+			   const struct rkisp1_cif_isp_awb_meas_config *arg,
+			   bool en)
 {
-	u32 reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP);
+	u32 reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP_V10);
 
 	/* switch off */
 	reg_val &= RKISP1_CIF_ISP_AWB_MODE_MASK_NONE;
@@ -489,34 +619,76 @@ rkisp1_awb_meas_enable(struct rkisp1_params *params,
 		else
 			reg_val |= RKISP1_CIF_ISP_AWB_MODE_YCBCR_EN;
 
-		rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP);
+		rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP_V10);
 
 		/* Measurements require AWB block be active. */
 		rkisp1_param_set_bits(params, RKISP1_CIF_ISP_CTRL,
 				      RKISP1_CIF_ISP_CTRL_ISP_AWB_ENA);
 	} else {
 		rkisp1_write(params->rkisp1,
-			     reg_val, RKISP1_CIF_ISP_AWB_PROP);
+			     reg_val, RKISP1_CIF_ISP_AWB_PROP_V10);
 		rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_CTRL,
 					RKISP1_CIF_ISP_CTRL_ISP_AWB_ENA);
 	}
 }
 
 static void
-rkisp1_awb_gain_config(struct rkisp1_params *params,
-		       const struct rkisp1_cif_isp_awb_gain_config *arg)
+rkisp1_awb_meas_enable_v12(struct rkisp1_params *params,
+			   const struct rkisp1_cif_isp_awb_meas_config *arg,
+			   bool en)
+{
+	u32 reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP_V12);
+
+	/* switch off */
+	reg_val &= RKISP1_CIF_ISP_AWB_MODE_MASK_NONE;
+
+	if (en) {
+		if (arg->awb_mode == RKISP1_CIF_ISP_AWB_MODE_RGB)
+			reg_val |= RKISP1_CIF_ISP_AWB_MODE_RGB_EN;
+		else
+			reg_val |= RKISP1_CIF_ISP_AWB_MODE_YCBCR_EN;
+
+		rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP_V12);
+
+		/* Measurements require AWB block be active. */
+		rkisp1_param_set_bits(params, RKISP1_CIF_ISP_CTRL,
+				      RKISP1_CIF_ISP_CTRL_ISP_AWB_ENA);
+	} else {
+		rkisp1_write(params->rkisp1,
+			     reg_val, RKISP1_CIF_ISP_AWB_PROP_V12);
+		rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_CTRL,
+					RKISP1_CIF_ISP_CTRL_ISP_AWB_ENA);
+	}
+}
+
+static void
+rkisp1_awb_gain_config_v10(struct rkisp1_params *params,
+			   const struct rkisp1_cif_isp_awb_gain_config *arg)
+{
+	rkisp1_write(params->rkisp1,
+		     RKISP1_CIF_ISP_AWB_GAIN_R_SET(arg->gain_green_r) |
+		     arg->gain_green_b, RKISP1_CIF_ISP_AWB_GAIN_G_V10);
+
+	rkisp1_write(params->rkisp1,
+		     RKISP1_CIF_ISP_AWB_GAIN_R_SET(arg->gain_red) |
+		     arg->gain_blue, RKISP1_CIF_ISP_AWB_GAIN_RB_V10);
+}
+
+static void
+rkisp1_awb_gain_config_v12(struct rkisp1_params *params,
+			   const struct rkisp1_cif_isp_awb_gain_config *arg)
 {
 	rkisp1_write(params->rkisp1,
 		     RKISP1_CIF_ISP_AWB_GAIN_R_SET(arg->gain_green_r) |
-		     arg->gain_green_b, RKISP1_CIF_ISP_AWB_GAIN_G);
+		     arg->gain_green_b, RKISP1_CIF_ISP_AWB_GAIN_G_V12);
 
 	rkisp1_write(params->rkisp1,
 		     RKISP1_CIF_ISP_AWB_GAIN_R_SET(arg->gain_red) |
-		     arg->gain_blue, RKISP1_CIF_ISP_AWB_GAIN_RB);
+		     arg->gain_blue, RKISP1_CIF_ISP_AWB_GAIN_RB_V12);
 }
 
-static void rkisp1_aec_config(struct rkisp1_params *params,
-			      const struct rkisp1_cif_isp_aec_config *arg)
+static void rkisp1_aec_config_v10(struct rkisp1_params *params,
+				  const struct rkisp1_cif_isp_aec_config *arg)
 {
 	unsigned int block_hsize, block_vsize;
 	u32 exp_ctrl;
@@ -531,21 +703,55 @@ static void rkisp1_aec_config(struct rkisp1_params *params,
 	rkisp1_write(params->rkisp1, exp_ctrl, RKISP1_CIF_ISP_EXP_CTRL);
 
 	rkisp1_write(params->rkisp1,
-		     arg->meas_window.h_offs, RKISP1_CIF_ISP_EXP_H_OFFSET);
+		     arg->meas_window.h_offs, RKISP1_CIF_ISP_EXP_H_OFFSET_V10);
 	rkisp1_write(params->rkisp1,
-		     arg->meas_window.v_offs, RKISP1_CIF_ISP_EXP_V_OFFSET);
+		     arg->meas_window.v_offs, RKISP1_CIF_ISP_EXP_V_OFFSET_V10);
 
 	block_hsize = arg->meas_window.h_size /
-		      RKISP1_CIF_ISP_EXP_COLUMN_NUM - 1;
+		      RKISP1_CIF_ISP_EXP_COLUMN_NUM_V10 - 1;
 	block_vsize = arg->meas_window.v_size /
-		      RKISP1_CIF_ISP_EXP_ROW_NUM - 1;
+		      RKISP1_CIF_ISP_EXP_ROW_NUM_V10 - 1;
+
+	rkisp1_write(params->rkisp1,
+		     RKISP1_CIF_ISP_EXP_H_SIZE_SET_V10(block_hsize),
+		     RKISP1_CIF_ISP_EXP_H_SIZE_V10);
+	rkisp1_write(params->rkisp1,
+		     RKISP1_CIF_ISP_EXP_V_SIZE_SET_V10(block_vsize),
+		     RKISP1_CIF_ISP_EXP_V_SIZE_V10);
+}
+
+static void rkisp1_aec_config_v12(struct rkisp1_params *params,
+			       const struct rkisp1_cif_isp_aec_config *arg)
+{
+	u32 exp_ctrl;
+	u32 block_hsize, block_vsize;
+	u32 wnd_num_idx = 1;
+	const u32 ae_wnd_num[] = {
+		5, 9, 15, 15
+	};
+
+	/* avoid to override the old enable value */
+	exp_ctrl = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_EXP_CTRL);
+	exp_ctrl &= RKISP1_CIF_ISP_EXP_ENA;
+	if (arg->autostop)
+		exp_ctrl |= RKISP1_CIF_ISP_EXP_CTRL_AUTOSTOP;
+	if (arg->mode == RKISP1_CIF_ISP_EXP_MEASURING_MODE_1)
+		exp_ctrl |= RKISP1_CIF_ISP_EXP_CTRL_MEASMODE_1;
+	exp_ctrl |= RKISP1_CIF_ISP_EXP_CTRL_WNDNUM_SET_V12(wnd_num_idx);
+	rkisp1_write(params->rkisp1, exp_ctrl, RKISP1_CIF_ISP_EXP_CTRL);
 
 	rkisp1_write(params->rkisp1,
-		     RKISP1_CIF_ISP_EXP_H_SIZE_SET(block_hsize),
-		     RKISP1_CIF_ISP_EXP_H_SIZE);
+		     RKISP1_CIF_ISP_EXP_V_OFFSET_SET_V12(arg->meas_window.v_offs) |
+		     RKISP1_CIF_ISP_EXP_H_OFFSET_SET_V12(arg->meas_window.h_offs),
+		     RKISP1_CIF_ISP_EXP_OFFS_V12);
+
+	block_hsize = arg->meas_window.h_size / ae_wnd_num[wnd_num_idx] - 1;
+	block_vsize = arg->meas_window.v_size / ae_wnd_num[wnd_num_idx] - 1;
+
 	rkisp1_write(params->rkisp1,
-		     RKISP1_CIF_ISP_EXP_V_SIZE_SET(block_vsize),
-		     RKISP1_CIF_ISP_EXP_V_SIZE);
+		     RKISP1_CIF_ISP_EXP_V_SIZE_SET_V12(block_vsize) |
+		     RKISP1_CIF_ISP_EXP_H_SIZE_SET_V12(block_hsize),
+		     RKISP1_CIF_ISP_EXP_SIZE_V12);
 }
 
 static void rkisp1_cproc_config(struct rkisp1_params *params,
@@ -578,72 +784,154 @@ static void rkisp1_cproc_config(struct rkisp1_params *params,
 	}
 }
 
-static void rkisp1_hst_config(struct rkisp1_params *params,
-			      const struct rkisp1_cif_isp_hst_config *arg)
+static void rkisp1_hst_config_v10(struct rkisp1_params *params,
+				  const struct rkisp1_cif_isp_hst_config *arg)
 {
 	unsigned int block_hsize, block_vsize;
 	static const u32 hist_weight_regs[] = {
-		RKISP1_CIF_ISP_HIST_WEIGHT_00TO30,
-		RKISP1_CIF_ISP_HIST_WEIGHT_40TO21,
-		RKISP1_CIF_ISP_HIST_WEIGHT_31TO12,
-		RKISP1_CIF_ISP_HIST_WEIGHT_22TO03,
-		RKISP1_CIF_ISP_HIST_WEIGHT_13TO43,
-		RKISP1_CIF_ISP_HIST_WEIGHT_04TO34,
-		RKISP1_CIF_ISP_HIST_WEIGHT_44,
+		RKISP1_CIF_ISP_HIST_WEIGHT_00TO30_V10,
+		RKISP1_CIF_ISP_HIST_WEIGHT_40TO21_V10,
+		RKISP1_CIF_ISP_HIST_WEIGHT_31TO12_V10,
+		RKISP1_CIF_ISP_HIST_WEIGHT_22TO03_V10,
+		RKISP1_CIF_ISP_HIST_WEIGHT_13TO43_V10,
+		RKISP1_CIF_ISP_HIST_WEIGHT_04TO34_V10,
+		RKISP1_CIF_ISP_HIST_WEIGHT_44_V10,
 	};
 	const u8 *weight;
 	unsigned int i;
 	u32 hist_prop;
 
 	/* avoid to override the old enable value */
-	hist_prop = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_HIST_PROP);
-	hist_prop &= RKISP1_CIF_ISP_HIST_PROP_MODE_MASK;
-	hist_prop |= RKISP1_CIF_ISP_HIST_PREDIV_SET(arg->histogram_predivider);
-	rkisp1_write(params->rkisp1, hist_prop, RKISP1_CIF_ISP_HIST_PROP);
+	hist_prop = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_HIST_PROP_V10);
+	hist_prop &= RKISP1_CIF_ISP_HIST_PROP_MODE_MASK_V10;
+	hist_prop |= RKISP1_CIF_ISP_HIST_PREDIV_SET_V10(arg->histogram_predivider);
+	rkisp1_write(params->rkisp1, hist_prop, RKISP1_CIF_ISP_HIST_PROP_V10);
 	rkisp1_write(params->rkisp1,
 		     arg->meas_window.h_offs,
-		     RKISP1_CIF_ISP_HIST_H_OFFS);
+		     RKISP1_CIF_ISP_HIST_H_OFFS_V10);
 	rkisp1_write(params->rkisp1,
 		     arg->meas_window.v_offs,
-		     RKISP1_CIF_ISP_HIST_V_OFFS);
+		     RKISP1_CIF_ISP_HIST_V_OFFS_V10);
 
 	block_hsize = arg->meas_window.h_size /
-		      RKISP1_CIF_ISP_HIST_COLUMN_NUM - 1;
-	block_vsize = arg->meas_window.v_size / RKISP1_CIF_ISP_HIST_ROW_NUM - 1;
+		      RKISP1_CIF_ISP_HIST_COLUMN_NUM_V10 - 1;
+	block_vsize = arg->meas_window.v_size / RKISP1_CIF_ISP_HIST_ROW_NUM_V10 - 1;
 
-	rkisp1_write(params->rkisp1, block_hsize, RKISP1_CIF_ISP_HIST_H_SIZE);
-	rkisp1_write(params->rkisp1, block_vsize, RKISP1_CIF_ISP_HIST_V_SIZE);
+	rkisp1_write(params->rkisp1, block_hsize, RKISP1_CIF_ISP_HIST_H_SIZE_V10);
+	rkisp1_write(params->rkisp1, block_vsize, RKISP1_CIF_ISP_HIST_V_SIZE_V10);
 
 	weight = arg->hist_weight;
 	for (i = 0; i < ARRAY_SIZE(hist_weight_regs); ++i, weight += 4)
 		rkisp1_write(params->rkisp1,
-			     RKISP1_CIF_ISP_HIST_WEIGHT_SET(weight[0],
+			     RKISP1_CIF_ISP_HIST_WEIGHT_SET_V10(weight[0],
 							    weight[1],
 							    weight[2],
 							    weight[3]),
 				 hist_weight_regs[i]);
 }
 
+static void rkisp1_hst_config_v12(struct rkisp1_params *params,
+				  const struct rkisp1_cif_isp_hst_config *arg)
+{
+	u32 i, j;
+	u32 value;
+	u32 hist_ctrl;
+	u32 block_hsize, block_vsize;
+	u32 wnd_num_idx, hist_weight_num;
+	u8 weight15x15[RKISP1_CIF_ISP_HIST_WEIGHT_REG_SIZE_V12];
+	const u32 hist_wnd_num[] = {
+		5, 9, 15, 15
+	};
+
+	/* now we just support 9x9 window */
+	wnd_num_idx = 1;
+	memset(weight15x15, 0x00, sizeof(weight15x15));
+	/* avoid to override the old enable value */
+	hist_ctrl = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_HIST_CTRL_V12);
+	hist_ctrl &= RKISP1_CIF_ISP_HIST_CTRL_MODE_MASK_V12 |
+		     RKISP1_CIF_ISP_HIST_CTRL_EN_MASK_V12;
+	hist_ctrl = hist_ctrl |
+		    RKISP1_CIF_ISP_HIST_CTRL_INTRSEL_SET_V12(1) |
+		    RKISP1_CIF_ISP_HIST_CTRL_DATASEL_SET_V12(0) |
+		    RKISP1_CIF_ISP_HIST_CTRL_WATERLINE_SET_V12(0) |
+		    RKISP1_CIF_ISP_HIST_CTRL_AUTOSTOP_SET_V12(0) |
+		    RKISP1_CIF_ISP_HIST_CTRL_WNDNUM_SET_V12(1) |
+		    RKISP1_CIF_ISP_HIST_CTRL_STEPSIZE_SET_V12(arg->histogram_predivider);
+	rkisp1_write(params->rkisp1, hist_ctrl, RKISP1_CIF_ISP_HIST_CTRL_V12);
+
+	rkisp1_write(params->rkisp1,
+		     RKISP1_CIF_ISP_HIST_OFFS_SET_V12(arg->meas_window.h_offs,
+						      arg->meas_window.v_offs),
+		     RKISP1_CIF_ISP_HIST_OFFS_V12);
+
+	block_hsize = arg->meas_window.h_size / hist_wnd_num[wnd_num_idx] - 1;
+	block_vsize = arg->meas_window.v_size / hist_wnd_num[wnd_num_idx] - 1;
+	rkisp1_write(params->rkisp1,
+		     RKISP1_CIF_ISP_HIST_SIZE_SET_V12(block_hsize, block_vsize),
+		     RKISP1_CIF_ISP_HIST_SIZE_V12);
+
+	for (i = 0; i < hist_wnd_num[wnd_num_idx]; i++) {
+		for (j = 0; j < hist_wnd_num[wnd_num_idx]; j++) {
+			weight15x15[i * RKISP1_CIF_ISP_HIST_ROW_NUM_V12 + j] =
+				arg->hist_weight[i * hist_wnd_num[wnd_num_idx] + j];
+		}
+	}
+
+	hist_weight_num = RKISP1_CIF_ISP_HIST_WEIGHT_REG_SIZE_V12;
+	for (i = 0; i < (hist_weight_num / 4); i++) {
+		value = RKISP1_CIF_ISP_HIST_WEIGHT_SET_V12(
+				 weight15x15[4 * i + 0],
+				 weight15x15[4 * i + 1],
+				 weight15x15[4 * i + 2],
+				 weight15x15[4 * i + 3]);
+		rkisp1_write(params->rkisp1, value,
+				 RKISP1_CIF_ISP_HIST_WEIGHT_V12 + 4 * i);
+	}
+	value = RKISP1_CIF_ISP_HIST_WEIGHT_SET_V12(weight15x15[4 * i + 0], 0, 0, 0);
+	rkisp1_write(params->rkisp1, value,
+				 RKISP1_CIF_ISP_HIST_WEIGHT_V12 + 4 * i);
+}
+
 static void
-rkisp1_hst_enable(struct rkisp1_params *params,
-		  const struct rkisp1_cif_isp_hst_config *arg, bool en)
+rkisp1_hst_enable_v10(struct rkisp1_params *params,
+		      const struct rkisp1_cif_isp_hst_config *arg, bool en)
 {
 	if (en)	{
 		u32 hist_prop = rkisp1_read(params->rkisp1,
-					    RKISP1_CIF_ISP_HIST_PROP);
+					    RKISP1_CIF_ISP_HIST_PROP_V10);
 
-		hist_prop &= ~RKISP1_CIF_ISP_HIST_PROP_MODE_MASK;
+		hist_prop &= ~RKISP1_CIF_ISP_HIST_PROP_MODE_MASK_V10;
 		hist_prop |= arg->mode;
-		rkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_PROP,
+		rkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_PROP_V10,
 				      hist_prop);
 	} else {
-		rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_HIST_PROP,
-					RKISP1_CIF_ISP_HIST_PROP_MODE_MASK);
+		rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_HIST_PROP_V10,
+					RKISP1_CIF_ISP_HIST_PROP_MODE_MASK_V10);
+	}
+}
+
+static void
+rkisp1_hst_enable_v12(struct rkisp1_params *params,
+		      const struct rkisp1_cif_isp_hst_config *arg, bool en)
+{
+	if (en) {
+		u32 hist_ctrl = rkisp1_read(params->rkisp1,
+					    RKISP1_CIF_ISP_HIST_CTRL_V12);
+
+		hist_ctrl &= ~RKISP1_CIF_ISP_HIST_CTRL_MODE_MASK_V12;
+		hist_ctrl |= RKISP1_CIF_ISP_HIST_CTRL_MODE_SET_V12(arg->mode);
+		hist_ctrl |= RKISP1_CIF_ISP_HIST_CTRL_EN_SET_V12(1);
+		rkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_CTRL_V12,
+				      hist_ctrl);
+	} else {
+		rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_HIST_CTRL_V12,
+					RKISP1_CIF_ISP_HIST_CTRL_MODE_MASK_V12 |
+					RKISP1_CIF_ISP_HIST_CTRL_EN_MASK_V12);
 	}
 }
 
-static void rkisp1_afm_config(struct rkisp1_params *params,
-			      const struct rkisp1_cif_isp_afc_config *arg)
+static void rkisp1_afm_config_v10(struct rkisp1_params *params,
+				  const struct rkisp1_cif_isp_afc_config *arg)
 {
 	size_t num_of_win = min_t(size_t, ARRAY_SIZE(arg->afm_win),
 				  arg->num_afm_win);
@@ -673,6 +961,45 @@ static void rkisp1_afm_config(struct rkisp1_params *params,
 	rkisp1_write(params->rkisp1, afm_ctrl, RKISP1_CIF_ISP_AFM_CTRL);
 }
 
+static void rkisp1_afm_config_v12(struct rkisp1_params *params,
+				  const struct rkisp1_cif_isp_afc_config *arg)
+{
+	size_t num_of_win = min_t(size_t, ARRAY_SIZE(arg->afm_win),
+				  arg->num_afm_win);
+	u32 afm_ctrl = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AFM_CTRL);
+	u32 lum_var_shift, afm_var_shift;
+	unsigned int i;
+
+	/* Switch off to configure. */
+	rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_AFM_CTRL,
+				RKISP1_CIF_ISP_AFM_ENA);
+
+	for (i = 0; i < num_of_win; i++) {
+		rkisp1_write(params->rkisp1,
+			     RKISP1_CIF_ISP_AFM_WINDOW_X(arg->afm_win[i].h_offs) |
+			     RKISP1_CIF_ISP_AFM_WINDOW_Y(arg->afm_win[i].v_offs),
+			     RKISP1_CIF_ISP_AFM_LT_A + i * 8);
+		rkisp1_write(params->rkisp1,
+			     RKISP1_CIF_ISP_AFM_WINDOW_X(arg->afm_win[i].h_size +
+							 arg->afm_win[i].h_offs) |
+			     RKISP1_CIF_ISP_AFM_WINDOW_Y(arg->afm_win[i].v_size +
+							 arg->afm_win[i].v_offs),
+			     RKISP1_CIF_ISP_AFM_RB_A + i * 8);
+	}
+	rkisp1_write(params->rkisp1, arg->thres, RKISP1_CIF_ISP_AFM_THRES);
+
+	lum_var_shift = RKISP1_CIF_ISP_AFM_GET_LUM_SHIFT_a_V12(arg->var_shift);
+	afm_var_shift = RKISP1_CIF_ISP_AFM_GET_AFM_SHIFT_a_V12(arg->var_shift);
+	rkisp1_write(params->rkisp1,
+		     RKISP1_CIF_ISP_AFM_SET_SHIFT_a_V12(lum_var_shift, afm_var_shift) |
+		     RKISP1_CIF_ISP_AFM_SET_SHIFT_b_V12(lum_var_shift, afm_var_shift) |
+		     RKISP1_CIF_ISP_AFM_SET_SHIFT_c_V12(lum_var_shift, afm_var_shift),
+		     RKISP1_CIF_ISP_AFM_VAR_SHIFT);
+
+	/* restore afm status */
+	rkisp1_write(params->rkisp1, afm_ctrl, RKISP1_CIF_ISP_AFM_CTRL);
+}
+
 static void rkisp1_ie_config(struct rkisp1_params *params,
 			     const struct rkisp1_cif_isp_ie_config *arg)
 {
@@ -1286,8 +1613,8 @@ static void rkisp1_params_config_parameter(struct rkisp1_params *params)
 
 	memset(hst.hist_weight, 0x01, sizeof(hst.hist_weight));
 	params->ops->hst_config(params, &hst);
-	rkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_PROP,
-			      ~RKISP1_CIF_ISP_HIST_PROP_MODE_MASK |
+	rkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_PROP_V10,
+			      ~RKISP1_CIF_ISP_HIST_PROP_MODE_MASK_V10 |
 			      rkisp1_hst_params_default_config.mode);
 
 	/* set the  range */
@@ -1346,22 +1673,38 @@ void rkisp1_params_disable(struct rkisp1_params *params)
 				RKISP1_CIF_ISP_DPF_MODE_EN);
 }
 
-static struct rkisp1_params_ops rkisp1_params_ops = {
-	.lsc_matrix_config = rkisp1_lsc_matrix_config,
-	.goc_config = rkisp1_goc_config,
-	.awb_meas_config = rkisp1_awb_meas_config,
-	.awb_meas_enable = rkisp1_awb_meas_enable,
-	.awb_gain_config = rkisp1_awb_gain_config,
-	.aec_config = rkisp1_aec_config,
-	.hst_config = rkisp1_hst_config,
-	.hst_enable = rkisp1_hst_enable,
-	.afm_config = rkisp1_afm_config,
+static struct rkisp1_params_ops rkisp1_v10_params_ops = {
+	.lsc_matrix_config = rkisp1_lsc_matrix_config_v10,
+	.goc_config = rkisp1_goc_config_v10,
+	.awb_meas_config = rkisp1_awb_meas_config_v10,
+	.awb_meas_enable = rkisp1_awb_meas_enable_v10,
+	.awb_gain_config = rkisp1_awb_gain_config_v10,
+	.aec_config = rkisp1_aec_config_v10,
+	.hst_config = rkisp1_hst_config_v10,
+	.hst_enable = rkisp1_hst_enable_v10,
+	.afm_config = rkisp1_afm_config_v10,
 };
 
-static struct rkisp1_params_config rkisp1_params_config = {
+static struct rkisp1_params_config rkisp1_v10_params_config = {
 	.gamma_out_max_samples = 17,
 };
 
+static struct rkisp1_params_ops rkisp1_v12_params_ops = {
+	.lsc_matrix_config = rkisp1_lsc_matrix_config_v12,
+	.goc_config = rkisp1_goc_config_v12,
+	.awb_meas_config = rkisp1_awb_meas_config_v12,
+	.awb_meas_enable = rkisp1_awb_meas_enable_v12,
+	.awb_gain_config = rkisp1_awb_gain_config_v12,
+	.aec_config = rkisp1_aec_config_v12,
+	.hst_config = rkisp1_hst_config_v12,
+	.hst_enable = rkisp1_hst_enable_v12,
+	.afm_config = rkisp1_afm_config_v12,
+};
+
+static struct rkisp1_params_config rkisp1_v12_params_config = {
+	.gamma_out_max_samples = 34,
+};
+
 static int rkisp1_params_enum_fmt_meta_out(struct file *file, void *priv,
 					   struct v4l2_fmtdesc *f)
 {
@@ -1528,8 +1871,14 @@ static void rkisp1_init_params(struct rkisp1_params *params)
 		V4L2_META_FMT_RK_ISP1_PARAMS;
 	params->vdev_fmt.fmt.meta.buffersize =
 		sizeof(struct rkisp1_params_cfg);
-	params->ops = &rkisp1_params_ops;
-	params->config = &rkisp1_params_config;
+
+	if (params->rkisp1->isp_ver == RKISP1_V12) {
+		params->ops = &rkisp1_v12_params_ops;
+		params->config = &rkisp1_v12_params_config;
+	} else {
+		params->ops = &rkisp1_v10_params_ops;
+		params->config = &rkisp1_v10_params_config;
+	}
 }
 
 int rkisp1_params_register(struct rkisp1_device *rkisp1)
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
index 8a8d960a679c..388adee3beff 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
@@ -212,6 +212,35 @@
 
 /* CCL */
 #define RKISP1_CIF_CCL_CIF_CLK_DIS			BIT(2)
+/* VI_ISP_CLK_CTRL */
+#define RKISP1_CIF_CLK_CTRL_ISP_RAW			BIT(0)
+#define RKISP1_CIF_CLK_CTRL_ISP_RGB			BIT(1)
+#define RKISP1_CIF_CLK_CTRL_ISP_YUV			BIT(2)
+#define RKISP1_CIF_CLK_CTRL_ISP_3A			BIT(3)
+#define RKISP1_CIF_CLK_CTRL_MIPI_RAW			BIT(4)
+#define RKISP1_CIF_CLK_CTRL_ISP_IE			BIT(5)
+#define RKISP1_CIF_CLK_CTRL_RSZ_RAM			BIT(6)
+#define RKISP1_CIF_CLK_CTRL_JPEG_RAM			BIT(7)
+#define RKISP1_CIF_CLK_CTRL_ACLK_ISP			BIT(8)
+#define RKISP1_CIF_CLK_CTRL_MI_IDC			BIT(9)
+#define RKISP1_CIF_CLK_CTRL_MI_MP			BIT(10)
+#define RKISP1_CIF_CLK_CTRL_MI_JPEG			BIT(11)
+#define RKISP1_CIF_CLK_CTRL_MI_DP			BIT(12)
+#define RKISP1_CIF_CLK_CTRL_MI_Y12			BIT(13)
+#define RKISP1_CIF_CLK_CTRL_MI_SP			BIT(14)
+#define RKISP1_CIF_CLK_CTRL_MI_RAW0			BIT(15)
+#define RKISP1_CIF_CLK_CTRL_MI_RAW1			BIT(16)
+#define RKISP1_CIF_CLK_CTRL_MI_READ			BIT(17)
+#define RKISP1_CIF_CLK_CTRL_MI_RAWRD			BIT(18)
+#define RKISP1_CIF_CLK_CTRL_CP				BIT(19)
+#define RKISP1_CIF_CLK_CTRL_IE				BIT(20)
+#define RKISP1_CIF_CLK_CTRL_SI				BIT(21)
+#define RKISP1_CIF_CLK_CTRL_RSZM			BIT(22)
+#define RKISP1_CIF_CLK_CTRL_DPMUX			BIT(23)
+#define RKISP1_CIF_CLK_CTRL_JPEG			BIT(24)
+#define RKISP1_CIF_CLK_CTRL_RSZS			BIT(25)
+#define RKISP1_CIF_CLK_CTRL_MIPI			BIT(26)
+#define RKISP1_CIF_CLK_CTRL_MARVINMI			BIT(27)
 /* ICCL */
 #define RKISP1_CIF_ICCL_ISP_CLK				BIT(0)
 #define RKISP1_CIF_ICCL_CP_CLK				BIT(1)
@@ -346,25 +375,57 @@
 #define RKISP1_CIF_SUPER_IMP_CTRL_TRANSP_DIS		BIT(2)
 
 /* ISP HISTOGRAM CALCULATION : ISP_HIST_PROP */
-#define RKISP1_CIF_ISP_HIST_PROP_MODE_DIS		(0 << 0)
-#define RKISP1_CIF_ISP_HIST_PROP_MODE_RGB		BIT(0)
-#define RKISP1_CIF_ISP_HIST_PROP_MODE_RED		(2 << 0)
-#define RKISP1_CIF_ISP_HIST_PROP_MODE_GREEN		(3 << 0)
-#define RKISP1_CIF_ISP_HIST_PROP_MODE_BLUE		(4 << 0)
-#define RKISP1_CIF_ISP_HIST_PROP_MODE_LUM		(5 << 0)
-#define RKISP1_CIF_ISP_HIST_PROP_MODE_MASK		0x7
-#define RKISP1_CIF_ISP_HIST_PREDIV_SET(x)		(((x) & 0x7F) << 3)
-#define RKISP1_CIF_ISP_HIST_WEIGHT_SET(v0, v1, v2, v3)	\
+#define RKISP1_CIF_ISP_HIST_PROP_MODE_DIS_V10		(0 << 0)
+#define RKISP1_CIF_ISP_HIST_PROP_MODE_RGB_V10		BIT(0)
+#define RKISP1_CIF_ISP_HIST_PROP_MODE_RED_V10		(2 << 0)
+#define RKISP1_CIF_ISP_HIST_PROP_MODE_GREEN_V10		(3 << 0)
+#define RKISP1_CIF_ISP_HIST_PROP_MODE_BLUE_V10		(4 << 0)
+#define RKISP1_CIF_ISP_HIST_PROP_MODE_LUM_V10		(5 << 0)
+#define RKISP1_CIF_ISP_HIST_PROP_MODE_MASK_V10		0x7
+#define RKISP1_CIF_ISP_HIST_PREDIV_SET_V10(x)		(((x) & 0x7F) << 3)
+#define RKISP1_CIF_ISP_HIST_WEIGHT_SET_V10(v0, v1, v2, v3)	\
 				     (((v0) & 0x1F) | (((v1) & 0x1F) << 8)  |\
 				     (((v2) & 0x1F) << 16) | \
 				     (((v3) & 0x1F) << 24))
 
-#define RKISP1_CIF_ISP_HIST_WINDOW_OFFSET_RESERVED	0xFFFFF000
-#define RKISP1_CIF_ISP_HIST_WINDOW_SIZE_RESERVED	0xFFFFF800
-#define RKISP1_CIF_ISP_HIST_WEIGHT_RESERVED		0xE0E0E0E0
-#define RKISP1_CIF_ISP_MAX_HIST_PREDIVIDER		0x0000007F
-#define RKISP1_CIF_ISP_HIST_ROW_NUM			5
-#define RKISP1_CIF_ISP_HIST_COLUMN_NUM			5
+#define RKISP1_CIF_ISP_HIST_WINDOW_OFFSET_RESERVED_V10	0xFFFFF000
+#define RKISP1_CIF_ISP_HIST_WINDOW_SIZE_RESERVED_V10	0xFFFFF800
+#define RKISP1_CIF_ISP_HIST_WEIGHT_RESERVED_V10		0xE0E0E0E0
+#define RKISP1_CIF_ISP_MAX_HIST_PREDIVIDER_V10		0x0000007F
+#define RKISP1_CIF_ISP_HIST_ROW_NUM_V10			5
+#define RKISP1_CIF_ISP_HIST_COLUMN_NUM_V10		5
+
+/* ISP HISTOGRAM CALCULATION : CIF_ISP_HIST */
+#define RKISP1_CIF_ISP_HIST_CTRL_EN_SET_V12(x)		(((x) & 0x01) << 0)
+#define RKISP1_CIF_ISP_HIST_CTRL_EN_MASK_V12		RKISP1_CIF_ISP_HIST_CTRL_EN_SET_V12(0x01)
+#define RKISP1_CIF_ISP_HIST_CTRL_STEPSIZE_SET_V12(x)	(((x) & 0x7F) << 1)
+#define RKISP1_CIF_ISP_HIST_CTRL_MODE_SET_V12(x)	(((x) & 0x07) << 8)
+#define RKISP1_CIF_ISP_HIST_CTRL_MODE_MASK_V12		RKISP1_CIF_ISP_HIST_CTRL_MODE_SET_V12(0x07)
+#define RKISP1_CIF_ISP_HIST_CTRL_AUTOSTOP_SET_V12(x)	(((x) & 0x01) << 11)
+#define RKISP1_CIF_ISP_HIST_CTRL_WATERLINE_SET_V12(x)	(((x) & 0xFFF) << 12)
+#define RKISP1_CIF_ISP_HIST_CTRL_DATASEL_SET_V12(x)	(((x) & 0x07) << 24)
+#define RKISP1_CIF_ISP_HIST_CTRL_INTRSEL_SET_V12(x)	(((x) & 0x01) << 27)
+#define RKISP1_CIF_ISP_HIST_CTRL_WNDNUM_SET_V12(x)	(((x) & 0x03) << 28)
+#define RKISP1_CIF_ISP_HIST_CTRL_DBGEN_SET_V12(x)	(((x) & 0x01) << 30)
+#define RKISP1_CIF_ISP_HIST_ROW_NUM_V12		15
+#define RKISP1_CIF_ISP_HIST_COLUMN_NUM_V12		15
+#define RKISP1_CIF_ISP_HIST_WEIGHT_REG_SIZE_V12	\
+				(RKISP1_CIF_ISP_HIST_ROW_NUM_V12 * RKISP1_CIF_ISP_HIST_COLUMN_NUM_V12)
+
+#define RKISP1_CIF_ISP_HIST_WEIGHT_SET_V12(v0, v1, v2, v3)	\
+				(((v0) & 0x3F) | (((v1) & 0x3F) << 8) |\
+				(((v2) & 0x3F) << 16) |\
+				(((v3) & 0x3F) << 24))
+
+#define RKISP1_CIF_ISP_HIST_OFFS_SET_V12(v0, v1)	\
+				(((v0) & 0x1FFF) | (((v1) & 0x1FFF) << 16))
+#define RKISP1_CIF_ISP_HIST_SIZE_SET_V12(v0, v1)	\
+				(((v0) & 0x7FF) | (((v1) & 0x7FF) << 16))
+
+#define RKISP1_CIF_ISP_HIST_GET_BIN0_V12(x)	\
+				((x) & 0xFFFF)
+#define RKISP1_CIF_ISP_HIST_GET_BIN1_V12(x)	\
+				(((x) >> 16) & 0xFFFF)
 
 /* AUTO FOCUS MEASUREMENT:  ISP_AFM_CTRL */
 #define RKISP1_ISP_AFM_CTRL_ENABLE			BIT(0)
@@ -400,6 +461,8 @@
 #define RKISP1_CIF_ISP_AWB_MODE_YCBCR_EN		((0 << 31) | (0x2 << 0))
 #define RKISP1_CIF_ISP_AWB_MODE_MASK_NONE		0xFFFFFFFC
 #define RKISP1_CIF_ISP_AWB_MODE_READ(x)			((x) & 3)
+#define RKISP1_CIF_ISP_AWB_SET_FRAMES_V12(x)		(((x) & 0x07) << 28)
+#define RKISP1_CIF_ISP_AWB_SET_FRAMES_MASK_V12		RKISP1_CIF_ISP_AWB_SET_FRAMES_V12(0x07)
 /* ISP_AWB_GAIN_RB, ISP_AWB_GAIN_G  */
 #define RKISP1_CIF_ISP_AWB_GAIN_R_SET(x)		(((x) & 0x3FF) << 16)
 #define RKISP1_CIF_ISP_AWB_GAIN_R_READ(x)		(((x) >> 16) & 0x3FF)
@@ -434,6 +497,7 @@
 /* ISP_EXP_CTRL */
 #define RKISP1_CIF_ISP_EXP_ENA				BIT(0)
 #define RKISP1_CIF_ISP_EXP_CTRL_AUTOSTOP		BIT(1)
+#define RKISP1_CIF_ISP_EXP_CTRL_WNDNUM_SET_V12(x)	(((x) & 0x03) << 2)
 /*
  *'1' luminance calculation according to  Y=(R+G+B) x 0.332 (85/256)
  *'0' luminance calculation according to Y=16+0.25R+0.5G+0.1094B
@@ -441,42 +505,76 @@
 #define RKISP1_CIF_ISP_EXP_CTRL_MEASMODE_1		BIT(31)
 
 /* ISP_EXP_H_SIZE */
-#define RKISP1_CIF_ISP_EXP_H_SIZE_SET(x)		((x) & 0x7FF)
-#define RKISP1_CIF_ISP_EXP_HEIGHT_MASK			0x000007FF
+#define RKISP1_CIF_ISP_EXP_H_SIZE_SET_V10(x)		((x) & 0x7FF)
+#define RKISP1_CIF_ISP_EXP_HEIGHT_MASK_V10			0x000007FF
+#define RKISP1_CIF_ISP_EXP_H_SIZE_SET_V12(x)		((x) & 0x7FF)
+#define RKISP1_CIF_ISP_EXP_HEIGHT_MASK_V12		0x000007FF
 /* ISP_EXP_V_SIZE : vertical size must be a multiple of 2). */
-#define RKISP1_CIF_ISP_EXP_V_SIZE_SET(x)		((x) & 0x7FE)
+#define RKISP1_CIF_ISP_EXP_V_SIZE_SET_V10(x)		((x) & 0x7FE)
+#define RKISP1_CIF_ISP_EXP_V_SIZE_SET_V12(x)		(((x) & 0x7FE) << 16)
 
 /* ISP_EXP_H_OFFSET */
-#define RKISP1_CIF_ISP_EXP_H_OFFSET_SET(x)		((x) & 0x1FFF)
-#define RKISP1_CIF_ISP_EXP_MAX_HOFFS			2424
+#define RKISP1_CIF_ISP_EXP_H_OFFSET_SET_V10(x)		((x) & 0x1FFF)
+#define RKISP1_CIF_ISP_EXP_MAX_HOFFS_V10		2424
+#define RKISP1_CIF_ISP_EXP_H_OFFSET_SET_V12(x)		((x) & 0x1FFF)
+#define RKISP1_CIF_ISP_EXP_MAX_HOFFS_V12		0x1FFF
 /* ISP_EXP_V_OFFSET */
-#define RKISP1_CIF_ISP_EXP_V_OFFSET_SET(x)		((x) & 0x1FFF)
-#define RKISP1_CIF_ISP_EXP_MAX_VOFFS			1806
-
-#define RKISP1_CIF_ISP_EXP_ROW_NUM			5
-#define RKISP1_CIF_ISP_EXP_COLUMN_NUM			5
-#define RKISP1_CIF_ISP_EXP_NUM_LUMA_REGS \
-	(RKISP1_CIF_ISP_EXP_ROW_NUM * RKISP1_CIF_ISP_EXP_COLUMN_NUM)
-#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE		516
-#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE		35
-#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE		390
-#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE		28
-#define RKISP1_CIF_ISP_EXP_MAX_HSIZE	\
-	(RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE * RKISP1_CIF_ISP_EXP_COLUMN_NUM + 1)
-#define RKISP1_CIF_ISP_EXP_MIN_HSIZE	\
-	(RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE * RKISP1_CIF_ISP_EXP_COLUMN_NUM + 1)
-#define RKISP1_CIF_ISP_EXP_MAX_VSIZE	\
-	(RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE * RKISP1_CIF_ISP_EXP_ROW_NUM + 1)
-#define RKISP1_CIF_ISP_EXP_MIN_VSIZE	\
-	(RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE * RKISP1_CIF_ISP_EXP_ROW_NUM + 1)
+#define RKISP1_CIF_ISP_EXP_V_OFFSET_SET_V10(x)		((x) & 0x1FFF)
+#define RKISP1_CIF_ISP_EXP_MAX_VOFFS_V10		1806
+#define RKISP1_CIF_ISP_EXP_V_OFFSET_SET_V12(x)		(((x) & 0x1FFF) << 16)
+#define RKISP1_CIF_ISP_EXP_MAX_VOFFS_V12		0x1FFF
+
+#define RKISP1_CIF_ISP_EXP_ROW_NUM_V10			5
+#define RKISP1_CIF_ISP_EXP_COLUMN_NUM_V10			5
+#define RKISP1_CIF_ISP_EXP_NUM_LUMA_REGS_V10 \
+	(RKISP1_CIF_ISP_EXP_ROW_NUM_V10 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V10)
+#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE_V10		516
+#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE_V10		35
+#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE_V10		390
+#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE_V10		28
+#define RKISP1_CIF_ISP_EXP_MAX_HSIZE_V10	\
+	(RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE_V10 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V10 + 1)
+#define RKISP1_CIF_ISP_EXP_MIN_HSIZE_V10	\
+	(RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE_V10 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V10 + 1)
+#define RKISP1_CIF_ISP_EXP_MAX_VSIZE_V10	\
+	(RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE_V10 * RKISP1_CIF_ISP_EXP_ROW_NUM_V10 + 1)
+#define RKISP1_CIF_ISP_EXP_MIN_VSIZE_V10	\
+	(RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE_V10 * RKISP1_CIF_ISP_EXP_ROW_NUM_V10 + 1)
+
+#define RKISP1_CIF_ISP_EXP_ROW_NUM_V12			15
+#define RKISP1_CIF_ISP_EXP_COLUMN_NUM_V12		15
+#define RKISP1_CIF_ISP_EXP_NUM_LUMA_REGS_V12 \
+	(RKISP1_CIF_ISP_EXP_ROW_NUM_V12 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V12)
+
+#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE_V12		0x7FF
+#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE_V12		0xE
+#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE_V12		0x7FE
+#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE_V12		0xE
+#define RKISP1_CIF_ISP_EXP_MAX_HSIZE_V12	\
+	(RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE_V12 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V12 + 1)
+#define RKISP1_CIF_ISP_EXP_MIN_HSIZE_V12	\
+	(RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE_V12 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V12 + 1)
+#define RKISP1_CIF_ISP_EXP_MAX_VSIZE_V12	\
+	(RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE_V12 * RKISP1_CIF_ISP_EXP_ROW_NUM_V12 + 1)
+#define RKISP1_CIF_ISP_EXP_MIN_VSIZE_V12	\
+	(RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE_V12 * RKISP1_CIF_ISP_EXP_ROW_NUM_V12 + 1)
+
+#define RKISP1_CIF_ISP_EXP_GET_MEAN_xy0_V12(x)		((x) & 0xFF)
+#define RKISP1_CIF_ISP_EXP_GET_MEAN_xy1_V12(x)		(((x) >> 8) & 0xFF)
+#define RKISP1_CIF_ISP_EXP_GET_MEAN_xy2_V12(x)		(((x) >> 16) & 0xFF)
+#define RKISP1_CIF_ISP_EXP_GET_MEAN_xy3_V12(x)		(((x) >> 24) & 0xFF)
 
 /* LSC: ISP_LSC_CTRL */
 #define RKISP1_CIF_ISP_LSC_CTRL_ENA			BIT(0)
 #define RKISP1_CIF_ISP_LSC_SECT_SIZE_RESERVED		0xFC00FC00
-#define RKISP1_CIF_ISP_LSC_GRAD_RESERVED		0xF000F000
-#define RKISP1_CIF_ISP_LSC_SAMPLE_RESERVED		0xF000F000
-#define RKISP1_CIF_ISP_LSC_TABLE_DATA(v0, v1)     \
+#define RKISP1_CIF_ISP_LSC_GRAD_RESERVED_V10		0xF000F000
+#define RKISP1_CIF_ISP_LSC_SAMPLE_RESERVED_V10		0xF000F000
+#define RKISP1_CIF_ISP_LSC_GRAD_RESERVED_V12		0xE000E000
+#define RKISP1_CIF_ISP_LSC_SAMPLE_RESERVED_V12		0xE000E000
+#define RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(v0, v1)     \
 	(((v0) & 0xFFF) | (((v1) & 0xFFF) << 12))
+#define RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(v0, v1)     \
+	(((v0) & 0x1FFF) | (((v1) & 0x1FFF) << 13))
 #define RKISP1_CIF_ISP_LSC_SECT_SIZE(v0, v1)      \
 	(((v0) & 0xFFF) | (((v1) & 0xFFF) << 16))
 #define RKISP1_CIF_ISP_LSC_GRAD_SIZE(v0, v1)      \
@@ -549,6 +647,10 @@
 	(1 << 15) | (1 << 11) | (1 << 7) | (1 << 3))
 #define RKISP1_CIFISP_DEGAMMA_Y_RESERVED		0xFFFFF000
 
+/* GAMMA-OUT */
+#define RKISP1_CIF_ISP_GAMMA_VALUE_V12(x, y)	\
+	(((x) & 0xFFF) << 16 | ((y) & 0xFFF) << 0)
+
 /* AFM */
 #define RKISP1_CIF_ISP_AFM_ENA				BIT(0)
 #define RKISP1_CIF_ISP_AFM_THRES_RESERVED		0xFFFF0000
@@ -559,6 +661,11 @@
 #define RKISP1_CIF_ISP_AFM_WINDOW_Y_MIN			0x2
 #define RKISP1_CIF_ISP_AFM_WINDOW_X(x)			(((x) & 0x1FFF) << 16)
 #define RKISP1_CIF_ISP_AFM_WINDOW_Y(x)			((x) & 0x1FFF)
+#define RKISP1_CIF_ISP_AFM_SET_SHIFT_a_V12(x, y)	(((x) & 0x7) << 16 | ((y) & 0x7) << 0)
+#define RKISP1_CIF_ISP_AFM_SET_SHIFT_b_V12(x, y)	(((x) & 0x7) << 20 | ((y) & 0x7) << 4)
+#define RKISP1_CIF_ISP_AFM_SET_SHIFT_c_V12(x, y)	(((x) & 0x7) << 24 | ((y) & 0x7) << 8)
+#define RKISP1_CIF_ISP_AFM_GET_LUM_SHIFT_a_V12(x)	(((x) & 0x70000) >> 16)
+#define RKISP1_CIF_ISP_AFM_GET_AFM_SHIFT_a_V12(x)	((x) & 0x7)
 
 /* DPF */
 #define RKISP1_CIF_ISP_DPF_MODE_EN			BIT(0)
@@ -581,6 +688,7 @@
 #define RKISP1_CIF_CTRL_BASE			0x00000000
 #define RKISP1_CIF_CCL				(RKISP1_CIF_CTRL_BASE + 0x00000000)
 #define RKISP1_CIF_VI_ID			(RKISP1_CIF_CTRL_BASE + 0x00000008)
+#define RKISP1_CIF_VI_ISP_CLK_CTRL_V12		(RKISP1_CIF_CTRL_BASE + 0x0000000C)
 #define RKISP1_CIF_ICCL				(RKISP1_CIF_CTRL_BASE + 0x00000010)
 #define RKISP1_CIF_IRCL				(RKISP1_CIF_CTRL_BASE + 0x00000014)
 #define RKISP1_CIF_VI_DPCL			(RKISP1_CIF_CTRL_BASE + 0x00000018)
@@ -666,18 +774,35 @@
 #define RKISP1_CIF_ISP_GAMMA_B_Y14		(RKISP1_CIF_ISP_BASE + 0x000000E4)
 #define RKISP1_CIF_ISP_GAMMA_B_Y15		(RKISP1_CIF_ISP_BASE + 0x000000E8)
 #define RKISP1_CIF_ISP_GAMMA_B_Y16		(RKISP1_CIF_ISP_BASE + 0x000000EC)
-#define RKISP1_CIF_ISP_AWB_PROP			(RKISP1_CIF_ISP_BASE + 0x00000110)
-#define RKISP1_CIF_ISP_AWB_WND_H_OFFS		(RKISP1_CIF_ISP_BASE + 0x00000114)
-#define RKISP1_CIF_ISP_AWB_WND_V_OFFS		(RKISP1_CIF_ISP_BASE + 0x00000118)
-#define RKISP1_CIF_ISP_AWB_WND_H_SIZE		(RKISP1_CIF_ISP_BASE + 0x0000011C)
-#define RKISP1_CIF_ISP_AWB_WND_V_SIZE		(RKISP1_CIF_ISP_BASE + 0x00000120)
-#define RKISP1_CIF_ISP_AWB_FRAMES		(RKISP1_CIF_ISP_BASE + 0x00000124)
-#define RKISP1_CIF_ISP_AWB_REF			(RKISP1_CIF_ISP_BASE + 0x00000128)
-#define RKISP1_CIF_ISP_AWB_THRESH		(RKISP1_CIF_ISP_BASE + 0x0000012C)
-#define RKISP1_CIF_ISP_AWB_GAIN_G		(RKISP1_CIF_ISP_BASE + 0x00000138)
-#define RKISP1_CIF_ISP_AWB_GAIN_RB		(RKISP1_CIF_ISP_BASE + 0x0000013C)
-#define RKISP1_CIF_ISP_AWB_WHITE_CNT		(RKISP1_CIF_ISP_BASE + 0x00000140)
-#define RKISP1_CIF_ISP_AWB_MEAN			(RKISP1_CIF_ISP_BASE + 0x00000144)
+#define RKISP1_CIF_ISP_AWB_PROP_V10		(RKISP1_CIF_ISP_BASE + 0x00000110)
+#define RKISP1_CIF_ISP_AWB_WND_H_OFFS_V10	(RKISP1_CIF_ISP_BASE + 0x00000114)
+#define RKISP1_CIF_ISP_AWB_WND_V_OFFS_V10	(RKISP1_CIF_ISP_BASE + 0x00000118)
+#define RKISP1_CIF_ISP_AWB_WND_H_SIZE_V10	(RKISP1_CIF_ISP_BASE + 0x0000011C)
+#define RKISP1_CIF_ISP_AWB_WND_V_SIZE_V10	(RKISP1_CIF_ISP_BASE + 0x00000120)
+#define RKISP1_CIF_ISP_AWB_FRAMES_V10		(RKISP1_CIF_ISP_BASE + 0x00000124)
+#define RKISP1_CIF_ISP_AWB_REF_V10		(RKISP1_CIF_ISP_BASE + 0x00000128)
+#define RKISP1_CIF_ISP_AWB_THRESH_V10		(RKISP1_CIF_ISP_BASE + 0x0000012C)
+#define RKISP1_CIF_ISP_AWB_GAIN_G_V10		(RKISP1_CIF_ISP_BASE + 0x00000138)
+#define RKISP1_CIF_ISP_AWB_GAIN_RB_V10		(RKISP1_CIF_ISP_BASE + 0x0000013C)
+#define RKISP1_CIF_ISP_AWB_WHITE_CNT_V10	(RKISP1_CIF_ISP_BASE + 0x00000140)
+#define RKISP1_CIF_ISP_AWB_MEAN_V10		(RKISP1_CIF_ISP_BASE + 0x00000144)
+#define RKISP1_CIF_ISP_AWB_PROP_V12		(RKISP1_CIF_ISP_BASE + 0x00000110)
+#define RKISP1_CIF_ISP_AWB_SIZE_V12		(RKISP1_CIF_ISP_BASE + 0x00000114)
+#define RKISP1_CIF_ISP_AWB_OFFS_V12		(RKISP1_CIF_ISP_BASE + 0x00000118)
+#define RKISP1_CIF_ISP_AWB_REF_V12		(RKISP1_CIF_ISP_BASE + 0x0000011C)
+#define RKISP1_CIF_ISP_AWB_THRESH_V12		(RKISP1_CIF_ISP_BASE + 0x00000120)
+#define RKISP1_CIF_ISP_X_COOR12_V12		(RKISP1_CIF_ISP_BASE + 0x00000124)
+#define RKISP1_CIF_ISP_X_COOR34_V12		(RKISP1_CIF_ISP_BASE + 0x00000128)
+#define RKISP1_CIF_ISP_AWB_WHITE_CNT_V12	(RKISP1_CIF_ISP_BASE + 0x0000012C)
+#define RKISP1_CIF_ISP_AWB_MEAN_V12		(RKISP1_CIF_ISP_BASE + 0x00000130)
+#define RKISP1_CIF_ISP_DEGAIN_V12		(RKISP1_CIF_ISP_BASE + 0x00000134)
+#define RKISP1_CIF_ISP_AWB_GAIN_G_V12		(RKISP1_CIF_ISP_BASE + 0x00000138)
+#define RKISP1_CIF_ISP_AWB_GAIN_RB_V12		(RKISP1_CIF_ISP_BASE + 0x0000013C)
+#define RKISP1_CIF_ISP_REGION_LINE_V12		(RKISP1_CIF_ISP_BASE + 0x00000140)
+#define RKISP1_CIF_ISP_WP_CNT_REGION0_V12	(RKISP1_CIF_ISP_BASE + 0x00000160)
+#define RKISP1_CIF_ISP_WP_CNT_REGION1_V12	(RKISP1_CIF_ISP_BASE + 0x00000164)
+#define RKISP1_CIF_ISP_WP_CNT_REGION2_V12	(RKISP1_CIF_ISP_BASE + 0x00000168)
+#define RKISP1_CIF_ISP_WP_CNT_REGION3_V12	(RKISP1_CIF_ISP_BASE + 0x0000016C)
 #define RKISP1_CIF_ISP_CC_COEFF_0		(RKISP1_CIF_ISP_BASE + 0x00000170)
 #define RKISP1_CIF_ISP_CC_COEFF_1		(RKISP1_CIF_ISP_BASE + 0x00000174)
 #define RKISP1_CIF_ISP_CC_COEFF_2		(RKISP1_CIF_ISP_BASE + 0x00000178)
@@ -711,30 +836,32 @@
 #define RKISP1_CIF_ISP_CT_COEFF_6		(RKISP1_CIF_ISP_BASE + 0x000001E8)
 #define RKISP1_CIF_ISP_CT_COEFF_7		(RKISP1_CIF_ISP_BASE + 0x000001EC)
 #define RKISP1_CIF_ISP_CT_COEFF_8		(RKISP1_CIF_ISP_BASE + 0x000001F0)
-#define RKISP1_CIF_ISP_GAMMA_OUT_MODE		(RKISP1_CIF_ISP_BASE + 0x000001F4)
-#define RKISP1_CIF_ISP_GAMMA_OUT_Y_0		(RKISP1_CIF_ISP_BASE + 0x000001F8)
-#define RKISP1_CIF_ISP_GAMMA_OUT_Y_1		(RKISP1_CIF_ISP_BASE + 0x000001FC)
-#define RKISP1_CIF_ISP_GAMMA_OUT_Y_2		(RKISP1_CIF_ISP_BASE + 0x00000200)
-#define RKISP1_CIF_ISP_GAMMA_OUT_Y_3		(RKISP1_CIF_ISP_BASE + 0x00000204)
-#define RKISP1_CIF_ISP_GAMMA_OUT_Y_4		(RKISP1_CIF_ISP_BASE + 0x00000208)
-#define RKISP1_CIF_ISP_GAMMA_OUT_Y_5		(RKISP1_CIF_ISP_BASE + 0x0000020C)
-#define RKISP1_CIF_ISP_GAMMA_OUT_Y_6		(RKISP1_CIF_ISP_BASE + 0x00000210)
-#define RKISP1_CIF_ISP_GAMMA_OUT_Y_7		(RKISP1_CIF_ISP_BASE + 0x00000214)
-#define RKISP1_CIF_ISP_GAMMA_OUT_Y_8		(RKISP1_CIF_ISP_BASE + 0x00000218)
-#define RKISP1_CIF_ISP_GAMMA_OUT_Y_9		(RKISP1_CIF_ISP_BASE + 0x0000021C)
-#define RKISP1_CIF_ISP_GAMMA_OUT_Y_10		(RKISP1_CIF_ISP_BASE + 0x00000220)
-#define RKISP1_CIF_ISP_GAMMA_OUT_Y_11		(RKISP1_CIF_ISP_BASE + 0x00000224)
-#define RKISP1_CIF_ISP_GAMMA_OUT_Y_12		(RKISP1_CIF_ISP_BASE + 0x00000228)
-#define RKISP1_CIF_ISP_GAMMA_OUT_Y_13		(RKISP1_CIF_ISP_BASE + 0x0000022C)
-#define RKISP1_CIF_ISP_GAMMA_OUT_Y_14		(RKISP1_CIF_ISP_BASE + 0x00000230)
-#define RKISP1_CIF_ISP_GAMMA_OUT_Y_15		(RKISP1_CIF_ISP_BASE + 0x00000234)
-#define RKISP1_CIF_ISP_GAMMA_OUT_Y_16		(RKISP1_CIF_ISP_BASE + 0x00000238)
+#define RKISP1_CIF_ISP_GAMMA_OUT_MODE_V10	(RKISP1_CIF_ISP_BASE + 0x000001F4)
+#define RKISP1_CIF_ISP_GAMMA_OUT_Y_0_V10	(RKISP1_CIF_ISP_BASE + 0x000001F8)
+#define RKISP1_CIF_ISP_GAMMA_OUT_Y_1_V10	(RKISP1_CIF_ISP_BASE + 0x000001FC)
+#define RKISP1_CIF_ISP_GAMMA_OUT_Y_2_V10	(RKISP1_CIF_ISP_BASE + 0x00000200)
+#define RKISP1_CIF_ISP_GAMMA_OUT_Y_3_V10	(RKISP1_CIF_ISP_BASE + 0x00000204)
+#define RKISP1_CIF_ISP_GAMMA_OUT_Y_4_V10	(RKISP1_CIF_ISP_BASE + 0x00000208)
+#define RKISP1_CIF_ISP_GAMMA_OUT_Y_5_V10	(RKISP1_CIF_ISP_BASE + 0x0000020C)
+#define RKISP1_CIF_ISP_GAMMA_OUT_Y_6_V10	(RKISP1_CIF_ISP_BASE + 0x00000210)
+#define RKISP1_CIF_ISP_GAMMA_OUT_Y_7_V10	(RKISP1_CIF_ISP_BASE + 0x00000214)
+#define RKISP1_CIF_ISP_GAMMA_OUT_Y_8_V10	(RKISP1_CIF_ISP_BASE + 0x00000218)
+#define RKISP1_CIF_ISP_GAMMA_OUT_Y_9_V10	(RKISP1_CIF_ISP_BASE + 0x0000021C)
+#define RKISP1_CIF_ISP_GAMMA_OUT_Y_10_V10	(RKISP1_CIF_ISP_BASE + 0x00000220)
+#define RKISP1_CIF_ISP_GAMMA_OUT_Y_11_V10	(RKISP1_CIF_ISP_BASE + 0x00000224)
+#define RKISP1_CIF_ISP_GAMMA_OUT_Y_12_V10	(RKISP1_CIF_ISP_BASE + 0x00000228)
+#define RKISP1_CIF_ISP_GAMMA_OUT_Y_13_V10	(RKISP1_CIF_ISP_BASE + 0x0000022C)
+#define RKISP1_CIF_ISP_GAMMA_OUT_Y_14_V10	(RKISP1_CIF_ISP_BASE + 0x00000230)
+#define RKISP1_CIF_ISP_GAMMA_OUT_Y_15_V10	(RKISP1_CIF_ISP_BASE + 0x00000234)
+#define RKISP1_CIF_ISP_GAMMA_OUT_Y_16_V10	(RKISP1_CIF_ISP_BASE + 0x00000238)
 #define RKISP1_CIF_ISP_ERR			(RKISP1_CIF_ISP_BASE + 0x0000023C)
 #define RKISP1_CIF_ISP_ERR_CLR			(RKISP1_CIF_ISP_BASE + 0x00000240)
 #define RKISP1_CIF_ISP_FRAME_COUNT		(RKISP1_CIF_ISP_BASE + 0x00000244)
 #define RKISP1_CIF_ISP_CT_OFFSET_R		(RKISP1_CIF_ISP_BASE + 0x00000248)
 #define RKISP1_CIF_ISP_CT_OFFSET_G		(RKISP1_CIF_ISP_BASE + 0x0000024C)
 #define RKISP1_CIF_ISP_CT_OFFSET_B		(RKISP1_CIF_ISP_BASE + 0x00000250)
+#define RKISP1_CIF_ISP_GAMMA_OUT_MODE_V12	(RKISP1_CIF_ISP_BASE + 0x00000300)
+#define RKISP1_CIF_ISP_GAMMA_OUT_Y_0_V12	(RKISP1_CIF_ISP_BASE + 0x00000304)
 
 #define RKISP1_CIF_ISP_FLASH_BASE		0x00000660
 #define RKISP1_CIF_ISP_FLASH_CMD		(RKISP1_CIF_ISP_FLASH_BASE + 0x00000000)
@@ -1004,36 +1131,35 @@
 #define RKISP1_CIF_ISP_IS_H_SIZE_SHD		(RKISP1_CIF_ISP_IS_BASE + 0x0000002C)
 #define RKISP1_CIF_ISP_IS_V_SIZE_SHD		(RKISP1_CIF_ISP_IS_BASE + 0x00000030)
 
-#define RKISP1_CIF_ISP_HIST_BASE		0x00002400
-
-#define RKISP1_CIF_ISP_HIST_PROP		(RKISP1_CIF_ISP_HIST_BASE + 0x00000000)
-#define RKISP1_CIF_ISP_HIST_H_OFFS		(RKISP1_CIF_ISP_HIST_BASE + 0x00000004)
-#define RKISP1_CIF_ISP_HIST_V_OFFS		(RKISP1_CIF_ISP_HIST_BASE + 0x00000008)
-#define RKISP1_CIF_ISP_HIST_H_SIZE		(RKISP1_CIF_ISP_HIST_BASE + 0x0000000C)
-#define RKISP1_CIF_ISP_HIST_V_SIZE		(RKISP1_CIF_ISP_HIST_BASE + 0x00000010)
-#define RKISP1_CIF_ISP_HIST_BIN_0		(RKISP1_CIF_ISP_HIST_BASE + 0x00000014)
-#define RKISP1_CIF_ISP_HIST_BIN_1		(RKISP1_CIF_ISP_HIST_BASE + 0x00000018)
-#define RKISP1_CIF_ISP_HIST_BIN_2		(RKISP1_CIF_ISP_HIST_BASE + 0x0000001C)
-#define RKISP1_CIF_ISP_HIST_BIN_3		(RKISP1_CIF_ISP_HIST_BASE + 0x00000020)
-#define RKISP1_CIF_ISP_HIST_BIN_4		(RKISP1_CIF_ISP_HIST_BASE + 0x00000024)
-#define RKISP1_CIF_ISP_HIST_BIN_5		(RKISP1_CIF_ISP_HIST_BASE + 0x00000028)
-#define RKISP1_CIF_ISP_HIST_BIN_6		(RKISP1_CIF_ISP_HIST_BASE + 0x0000002C)
-#define RKISP1_CIF_ISP_HIST_BIN_7		(RKISP1_CIF_ISP_HIST_BASE + 0x00000030)
-#define RKISP1_CIF_ISP_HIST_BIN_8		(RKISP1_CIF_ISP_HIST_BASE + 0x00000034)
-#define RKISP1_CIF_ISP_HIST_BIN_9		(RKISP1_CIF_ISP_HIST_BASE + 0x00000038)
-#define RKISP1_CIF_ISP_HIST_BIN_10		(RKISP1_CIF_ISP_HIST_BASE + 0x0000003C)
-#define RKISP1_CIF_ISP_HIST_BIN_11		(RKISP1_CIF_ISP_HIST_BASE + 0x00000040)
-#define RKISP1_CIF_ISP_HIST_BIN_12		(RKISP1_CIF_ISP_HIST_BASE + 0x00000044)
-#define RKISP1_CIF_ISP_HIST_BIN_13		(RKISP1_CIF_ISP_HIST_BASE + 0x00000048)
-#define RKISP1_CIF_ISP_HIST_BIN_14		(RKISP1_CIF_ISP_HIST_BASE + 0x0000004C)
-#define RKISP1_CIF_ISP_HIST_BIN_15		(RKISP1_CIF_ISP_HIST_BASE + 0x00000050)
-#define RKISP1_CIF_ISP_HIST_WEIGHT_00TO30	(RKISP1_CIF_ISP_HIST_BASE + 0x00000054)
-#define RKISP1_CIF_ISP_HIST_WEIGHT_40TO21	(RKISP1_CIF_ISP_HIST_BASE + 0x00000058)
-#define RKISP1_CIF_ISP_HIST_WEIGHT_31TO12	(RKISP1_CIF_ISP_HIST_BASE + 0x0000005C)
-#define RKISP1_CIF_ISP_HIST_WEIGHT_22TO03	(RKISP1_CIF_ISP_HIST_BASE + 0x00000060)
-#define RKISP1_CIF_ISP_HIST_WEIGHT_13TO43	(RKISP1_CIF_ISP_HIST_BASE + 0x00000064)
-#define RKISP1_CIF_ISP_HIST_WEIGHT_04TO34	(RKISP1_CIF_ISP_HIST_BASE + 0x00000068)
-#define RKISP1_CIF_ISP_HIST_WEIGHT_44		(RKISP1_CIF_ISP_HIST_BASE + 0x0000006C)
+#define RKISP1_CIF_ISP_HIST_BASE_V10		0x00002400
+#define RKISP1_CIF_ISP_HIST_PROP_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000000)
+#define RKISP1_CIF_ISP_HIST_H_OFFS_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000004)
+#define RKISP1_CIF_ISP_HIST_V_OFFS_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000008)
+#define RKISP1_CIF_ISP_HIST_H_SIZE_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000000C)
+#define RKISP1_CIF_ISP_HIST_V_SIZE_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000010)
+#define RKISP1_CIF_ISP_HIST_BIN_0_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000014)
+#define RKISP1_CIF_ISP_HIST_BIN_1_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000018)
+#define RKISP1_CIF_ISP_HIST_BIN_2_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000001C)
+#define RKISP1_CIF_ISP_HIST_BIN_3_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000020)
+#define RKISP1_CIF_ISP_HIST_BIN_4_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000024)
+#define RKISP1_CIF_ISP_HIST_BIN_5_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000028)
+#define RKISP1_CIF_ISP_HIST_BIN_6_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000002C)
+#define RKISP1_CIF_ISP_HIST_BIN_7_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000030)
+#define RKISP1_CIF_ISP_HIST_BIN_8_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000034)
+#define RKISP1_CIF_ISP_HIST_BIN_9_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000038)
+#define RKISP1_CIF_ISP_HIST_BIN_10_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000003C)
+#define RKISP1_CIF_ISP_HIST_BIN_11_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000040)
+#define RKISP1_CIF_ISP_HIST_BIN_12_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000044)
+#define RKISP1_CIF_ISP_HIST_BIN_13_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000048)
+#define RKISP1_CIF_ISP_HIST_BIN_14_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000004C)
+#define RKISP1_CIF_ISP_HIST_BIN_15_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000050)
+#define RKISP1_CIF_ISP_HIST_WEIGHT_00TO30_V10	(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000054)
+#define RKISP1_CIF_ISP_HIST_WEIGHT_40TO21_V10	(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000058)
+#define RKISP1_CIF_ISP_HIST_WEIGHT_31TO12_V10	(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000005C)
+#define RKISP1_CIF_ISP_HIST_WEIGHT_22TO03_V10	(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000060)
+#define RKISP1_CIF_ISP_HIST_WEIGHT_13TO43_V10	(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000064)
+#define RKISP1_CIF_ISP_HIST_WEIGHT_04TO34_V10	(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000068)
+#define RKISP1_CIF_ISP_HIST_WEIGHT_44_V10	(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000006C)
 
 #define RKISP1_CIF_ISP_FILT_BASE		0x00002500
 #define RKISP1_CIF_ISP_FILT_MODE		(RKISP1_CIF_ISP_FILT_BASE + 0x00000000)
@@ -1059,35 +1185,38 @@
 
 #define RKISP1_CIF_ISP_EXP_BASE			0x00002600
 #define RKISP1_CIF_ISP_EXP_CTRL			(RKISP1_CIF_ISP_EXP_BASE + 0x00000000)
-#define RKISP1_CIF_ISP_EXP_H_OFFSET		(RKISP1_CIF_ISP_EXP_BASE + 0x00000004)
-#define RKISP1_CIF_ISP_EXP_V_OFFSET		(RKISP1_CIF_ISP_EXP_BASE + 0x00000008)
-#define RKISP1_CIF_ISP_EXP_H_SIZE		(RKISP1_CIF_ISP_EXP_BASE + 0x0000000C)
-#define RKISP1_CIF_ISP_EXP_V_SIZE		(RKISP1_CIF_ISP_EXP_BASE + 0x00000010)
-#define RKISP1_CIF_ISP_EXP_MEAN_00		(RKISP1_CIF_ISP_EXP_BASE + 0x00000014)
-#define RKISP1_CIF_ISP_EXP_MEAN_10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000018)
-#define RKISP1_CIF_ISP_EXP_MEAN_20		(RKISP1_CIF_ISP_EXP_BASE + 0x0000001c)
-#define RKISP1_CIF_ISP_EXP_MEAN_30		(RKISP1_CIF_ISP_EXP_BASE + 0x00000020)
-#define RKISP1_CIF_ISP_EXP_MEAN_40		(RKISP1_CIF_ISP_EXP_BASE + 0x00000024)
-#define RKISP1_CIF_ISP_EXP_MEAN_01		(RKISP1_CIF_ISP_EXP_BASE + 0x00000028)
-#define RKISP1_CIF_ISP_EXP_MEAN_11		(RKISP1_CIF_ISP_EXP_BASE + 0x0000002c)
-#define RKISP1_CIF_ISP_EXP_MEAN_21		(RKISP1_CIF_ISP_EXP_BASE + 0x00000030)
-#define RKISP1_CIF_ISP_EXP_MEAN_31		(RKISP1_CIF_ISP_EXP_BASE + 0x00000034)
-#define RKISP1_CIF_ISP_EXP_MEAN_41		(RKISP1_CIF_ISP_EXP_BASE + 0x00000038)
-#define RKISP1_CIF_ISP_EXP_MEAN_02		(RKISP1_CIF_ISP_EXP_BASE + 0x0000003c)
-#define RKISP1_CIF_ISP_EXP_MEAN_12		(RKISP1_CIF_ISP_EXP_BASE + 0x00000040)
-#define RKISP1_CIF_ISP_EXP_MEAN_22		(RKISP1_CIF_ISP_EXP_BASE + 0x00000044)
-#define RKISP1_CIF_ISP_EXP_MEAN_32		(RKISP1_CIF_ISP_EXP_BASE + 0x00000048)
-#define RKISP1_CIF_ISP_EXP_MEAN_42		(RKISP1_CIF_ISP_EXP_BASE + 0x0000004c)
-#define RKISP1_CIF_ISP_EXP_MEAN_03		(RKISP1_CIF_ISP_EXP_BASE + 0x00000050)
-#define RKISP1_CIF_ISP_EXP_MEAN_13		(RKISP1_CIF_ISP_EXP_BASE + 0x00000054)
-#define RKISP1_CIF_ISP_EXP_MEAN_23		(RKISP1_CIF_ISP_EXP_BASE + 0x00000058)
-#define RKISP1_CIF_ISP_EXP_MEAN_33		(RKISP1_CIF_ISP_EXP_BASE + 0x0000005c)
-#define RKISP1_CIF_ISP_EXP_MEAN_43		(RKISP1_CIF_ISP_EXP_BASE + 0x00000060)
-#define RKISP1_CIF_ISP_EXP_MEAN_04		(RKISP1_CIF_ISP_EXP_BASE + 0x00000064)
-#define RKISP1_CIF_ISP_EXP_MEAN_14		(RKISP1_CIF_ISP_EXP_BASE + 0x00000068)
-#define RKISP1_CIF_ISP_EXP_MEAN_24		(RKISP1_CIF_ISP_EXP_BASE + 0x0000006c)
-#define RKISP1_CIF_ISP_EXP_MEAN_34		(RKISP1_CIF_ISP_EXP_BASE + 0x00000070)
-#define RKISP1_CIF_ISP_EXP_MEAN_44		(RKISP1_CIF_ISP_EXP_BASE + 0x00000074)
+#define RKISP1_CIF_ISP_EXP_H_OFFSET_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000004)
+#define RKISP1_CIF_ISP_EXP_V_OFFSET_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000008)
+#define RKISP1_CIF_ISP_EXP_H_SIZE_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x0000000C)
+#define RKISP1_CIF_ISP_EXP_V_SIZE_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000010)
+#define RKISP1_CIF_ISP_EXP_MEAN_00_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000014)
+#define RKISP1_CIF_ISP_EXP_MEAN_10_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000018)
+#define RKISP1_CIF_ISP_EXP_MEAN_20_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x0000001c)
+#define RKISP1_CIF_ISP_EXP_MEAN_30_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000020)
+#define RKISP1_CIF_ISP_EXP_MEAN_40_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000024)
+#define RKISP1_CIF_ISP_EXP_MEAN_01_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000028)
+#define RKISP1_CIF_ISP_EXP_MEAN_11_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x0000002c)
+#define RKISP1_CIF_ISP_EXP_MEAN_21_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000030)
+#define RKISP1_CIF_ISP_EXP_MEAN_31_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000034)
+#define RKISP1_CIF_ISP_EXP_MEAN_41_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000038)
+#define RKISP1_CIF_ISP_EXP_MEAN_02_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x0000003c)
+#define RKISP1_CIF_ISP_EXP_MEAN_12_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000040)
+#define RKISP1_CIF_ISP_EXP_MEAN_22_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000044)
+#define RKISP1_CIF_ISP_EXP_MEAN_32_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000048)
+#define RKISP1_CIF_ISP_EXP_MEAN_42_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x0000004c)
+#define RKISP1_CIF_ISP_EXP_MEAN_03_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000050)
+#define RKISP1_CIF_ISP_EXP_MEAN_13_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000054)
+#define RKISP1_CIF_ISP_EXP_MEAN_23_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000058)
+#define RKISP1_CIF_ISP_EXP_MEAN_33_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x0000005c)
+#define RKISP1_CIF_ISP_EXP_MEAN_43_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000060)
+#define RKISP1_CIF_ISP_EXP_MEAN_04_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000064)
+#define RKISP1_CIF_ISP_EXP_MEAN_14_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000068)
+#define RKISP1_CIF_ISP_EXP_MEAN_24_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x0000006c)
+#define RKISP1_CIF_ISP_EXP_MEAN_34_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000070)
+#define RKISP1_CIF_ISP_EXP_MEAN_44_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000074)
+#define RKISP1_CIF_ISP_EXP_SIZE_V12		(RKISP1_CIF_ISP_EXP_BASE + 0x00000004)
+#define RKISP1_CIF_ISP_EXP_OFFS_V12		(RKISP1_CIF_ISP_EXP_BASE + 0x00000008)
+#define RKISP1_CIF_ISP_EXP_MEAN_V12		(RKISP1_CIF_ISP_EXP_BASE + 0x0000000c)
 
 #define RKISP1_CIF_ISP_BLS_BASE			0x00002700
 #define RKISP1_CIF_ISP_BLS_CTRL			(RKISP1_CIF_ISP_BLS_BASE + 0x00000000)
@@ -1248,6 +1377,16 @@
 #define RKISP1_CIF_ISP_WDR_TONECURVE_YM_31_SHD	(RKISP1_CIF_ISP_WDR_BASE + 0x0000012C)
 #define RKISP1_CIF_ISP_WDR_TONECURVE_YM_32_SHD	(RKISP1_CIF_ISP_WDR_BASE + 0x00000130)
 
+#define RKISP1_CIF_ISP_HIST_BASE_V12		0x00002C00
+#define RKISP1_CIF_ISP_HIST_CTRL_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x00000000)
+#define RKISP1_CIF_ISP_HIST_SIZE_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x00000004)
+#define RKISP1_CIF_ISP_HIST_OFFS_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x00000008)
+#define RKISP1_CIF_ISP_HIST_DBG1_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x0000000C)
+#define RKISP1_CIF_ISP_HIST_DBG2_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x0000001C)
+#define RKISP1_CIF_ISP_HIST_DBG3_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x0000002C)
+#define RKISP1_CIF_ISP_HIST_WEIGHT_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x0000003C)
+#define RKISP1_CIF_ISP_HIST_BIN_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x00000120)
+
 #define RKISP1_CIF_ISP_VSM_BASE			0x00002F00
 #define RKISP1_CIF_ISP_VSM_MODE			(RKISP1_CIF_ISP_VSM_BASE + 0x00000000)
 #define RKISP1_CIF_ISP_VSM_H_OFFS		(RKISP1_CIF_ISP_VSM_BASE + 0x00000004)
@@ -1259,4 +1398,7 @@
 #define RKISP1_CIF_ISP_VSM_DELTA_H		(RKISP1_CIF_ISP_VSM_BASE + 0x0000001C)
 #define RKISP1_CIF_ISP_VSM_DELTA_V		(RKISP1_CIF_ISP_VSM_BASE + 0x00000020)
 
+#define RKISP1_CIF_ISP_CSI0_BASE		0x00007000
+#define RKISP1_CIF_ISP_CSI0_CTRL0		(RKISP1_CIF_ISP_CSI0_BASE + 0x00000000)
+
 #endif /* _RKISP1_REGS_H */
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c
index 7136292039f6..5ce1a2974b55 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c
@@ -175,18 +175,18 @@ rkisp1_stats_init_vb2_queue(struct vb2_queue *q, struct rkisp1_stats *stats)
 	return vb2_queue_init(q);
 }
 
-static void rkisp1_stats_get_awb_meas(struct rkisp1_stats *stats,
-				      struct rkisp1_stat_buffer *pbuf)
+static void rkisp1_stats_get_awb_meas_v10(struct rkisp1_stats *stats,
+					  struct rkisp1_stat_buffer *pbuf)
 {
 	/* Protect against concurrent access from ISR? */
 	struct rkisp1_device *rkisp1 = stats->rkisp1;
 	u32 reg_val;
 
 	pbuf->meas_type |= RKISP1_CIF_ISP_STAT_AWB;
-	reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_WHITE_CNT);
+	reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_WHITE_CNT_V10);
 	pbuf->params.awb.awb_mean[0].cnt =
 				RKISP1_CIF_ISP_AWB_GET_PIXEL_CNT(reg_val);
-	reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_MEAN);
+	reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_MEAN_V10);
 
 	pbuf->params.awb.awb_mean[0].mean_cr_or_r =
 				RKISP1_CIF_ISP_AWB_GET_MEAN_CR_R(reg_val);
@@ -196,8 +196,29 @@ static void rkisp1_stats_get_awb_meas(struct rkisp1_stats *stats,
 				RKISP1_CIF_ISP_AWB_GET_MEAN_Y_G(reg_val);
 }
 
-static void rkisp1_stats_get_aec_meas(struct rkisp1_stats *stats,
-				      struct rkisp1_stat_buffer *pbuf)
+static void rkisp1_stats_get_awb_meas_v12(struct rkisp1_stats *stats,
+					  struct rkisp1_stat_buffer *pbuf)
+{
+	/* Protect against concurrent access from ISR? */
+	struct rkisp1_device *rkisp1 = stats->rkisp1;
+	u32 reg_val;
+
+	pbuf->meas_type |= RKISP1_CIF_ISP_STAT_AWB;
+	reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_WHITE_CNT_V12);
+	pbuf->params.awb.awb_mean[0].cnt =
+				RKISP1_CIF_ISP_AWB_GET_PIXEL_CNT(reg_val);
+	reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_MEAN_V12);
+
+	pbuf->params.awb.awb_mean[0].mean_cr_or_r =
+				RKISP1_CIF_ISP_AWB_GET_MEAN_CR_R(reg_val);
+	pbuf->params.awb.awb_mean[0].mean_cb_or_b =
+				RKISP1_CIF_ISP_AWB_GET_MEAN_CB_B(reg_val);
+	pbuf->params.awb.awb_mean[0].mean_y_or_g =
+				RKISP1_CIF_ISP_AWB_GET_MEAN_Y_G(reg_val);
+}
+
+static void rkisp1_stats_get_aec_meas_v10(struct rkisp1_stats *stats,
+					  struct rkisp1_stat_buffer *pbuf)
 {
 	struct rkisp1_device *rkisp1 = stats->rkisp1;
 	unsigned int i;
@@ -206,7 +227,31 @@ static void rkisp1_stats_get_aec_meas(struct rkisp1_stats *stats,
 	for (i = 0; i < stats->config->ae_mean_max; i++)
 		pbuf->params.ae.exp_mean[i] =
 			(u8)rkisp1_read(rkisp1,
-					RKISP1_CIF_ISP_EXP_MEAN_00 + i * 4);
+					RKISP1_CIF_ISP_EXP_MEAN_00_V10 + i * 4);
+}
+
+static void rkisp1_stats_get_aec_meas_v12(struct rkisp1_stats *stats,
+					  struct rkisp1_stat_buffer *pbuf)
+{
+	struct rkisp1_device *rkisp1 = stats->rkisp1;
+	u32 value;
+	int i;
+
+	pbuf->meas_type |= RKISP1_CIF_ISP_STAT_AUTOEXP;
+	for (i = 0; i < stats->config->ae_mean_max / 4; i++) {
+		value = rkisp1_read(rkisp1, RKISP1_CIF_ISP_EXP_MEAN_V12 + i * 4);
+		pbuf->params.ae.exp_mean[4 * i + 0] =
+				RKISP1_CIF_ISP_EXP_GET_MEAN_xy0_V12(value);
+		pbuf->params.ae.exp_mean[4 * i + 1] =
+				RKISP1_CIF_ISP_EXP_GET_MEAN_xy1_V12(value);
+		pbuf->params.ae.exp_mean[4 * i + 2] =
+				RKISP1_CIF_ISP_EXP_GET_MEAN_xy2_V12(value);
+		pbuf->params.ae.exp_mean[4 * i + 3] =
+				RKISP1_CIF_ISP_EXP_GET_MEAN_xy3_V12(value);
+	}
+
+	value = rkisp1_read(rkisp1, RKISP1_CIF_ISP_EXP_MEAN_V12 + i * 4);
+	pbuf->params.ae.exp_mean[4 * i + 0] = RKISP1_CIF_ISP_EXP_GET_MEAN_xy0_V12(value);
 }
 
 static void rkisp1_stats_get_afc_meas(struct rkisp1_stats *stats,
@@ -226,8 +271,8 @@ static void rkisp1_stats_get_afc_meas(struct rkisp1_stats *stats,
 	af->window[2].lum = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AFM_LUM_C);
 }
 
-static void rkisp1_stats_get_hst_meas(struct rkisp1_stats *stats,
-				      struct rkisp1_stat_buffer *pbuf)
+static void rkisp1_stats_get_hst_meas_v10(struct rkisp1_stats *stats,
+					  struct rkisp1_stat_buffer *pbuf)
 {
 	struct rkisp1_device *rkisp1 = stats->rkisp1;
 	unsigned int i;
@@ -236,7 +281,24 @@ static void rkisp1_stats_get_hst_meas(struct rkisp1_stats *stats,
 	for (i = 0; i < stats->config->hist_bin_n_max; i++)
 		pbuf->params.hist.hist_bins[i] =
 			(u8)rkisp1_read(rkisp1,
-					RKISP1_CIF_ISP_HIST_BIN_0 + i * 4);
+					RKISP1_CIF_ISP_HIST_BIN_0_V10 + i * 4);
+}
+
+static void rkisp1_stats_get_hst_meas_v12(struct rkisp1_stats *stats,
+					  struct rkisp1_stat_buffer *pbuf)
+{
+	struct rkisp1_device *rkisp1 = stats->rkisp1;
+	u32 value;
+	int i;
+
+	pbuf->meas_type |= RKISP1_CIF_ISP_STAT_HIST;
+	for (i = 0; i < stats->config->hist_bin_n_max / 2; i++) {
+		value = rkisp1_read(rkisp1, RKISP1_CIF_ISP_HIST_BIN_V12 + i * 4);
+		pbuf->params.hist.hist_bins[2 * i] =
+					RKISP1_CIF_ISP_HIST_GET_BIN0_V12(value);
+		pbuf->params.hist.hist_bins[2 * i + 1] =
+					RKISP1_CIF_ISP_HIST_GET_BIN1_V12(value);
+	}
 }
 
 static void rkisp1_stats_get_bls_meas(struct rkisp1_stats *stats,
@@ -286,17 +348,28 @@ static void rkisp1_stats_get_bls_meas(struct rkisp1_stats *stats,
 	}
 }
 
-static struct rkisp1_stats_ops rkisp1_stats_ops = {
-	.get_awb_meas = rkisp1_stats_get_awb_meas,
-	.get_aec_meas = rkisp1_stats_get_aec_meas,
-	.get_hst_meas = rkisp1_stats_get_hst_meas,
+static struct rkisp1_stats_ops rkisp1_v10_stats_ops = {
+	.get_awb_meas = rkisp1_stats_get_awb_meas_v10,
+	.get_aec_meas = rkisp1_stats_get_aec_meas_v10,
+	.get_hst_meas = rkisp1_stats_get_hst_meas_v10,
 };
 
-static struct rkisp1_stats_config rkisp1_stats_config = {
+static struct rkisp1_stats_config rkisp1_v10_stats_config = {
 	.ae_mean_max = 25,
 	.hist_bin_n_max = 16,
 };
 
+static struct rkisp1_stats_ops rkisp1_v12_stats_ops = {
+	.get_awb_meas = rkisp1_stats_get_awb_meas_v12,
+	.get_aec_meas = rkisp1_stats_get_aec_meas_v12,
+	.get_hst_meas = rkisp1_stats_get_hst_meas_v12,
+};
+
+static struct rkisp1_stats_config rkisp1_v12_stats_config = {
+	.ae_mean_max = 81,
+	.hist_bin_n_max = 32,
+};
+
 static void
 rkisp1_stats_send_measurement(struct rkisp1_stats *stats, u32 isp_ris)
 {
@@ -365,8 +438,13 @@ static void rkisp1_init_stats(struct rkisp1_stats *stats)
 	stats->vdev_fmt.fmt.meta.buffersize =
 		sizeof(struct rkisp1_stat_buffer);
 
-	stats->ops = &rkisp1_stats_ops;
-	stats->config = &rkisp1_stats_config;
+	if (stats->rkisp1->isp_ver == RKISP1_V12) {
+		stats->ops = &rkisp1_v12_stats_ops;
+		stats->config = &rkisp1_v12_stats_config;
+	} else {
+		stats->ops = &rkisp1_v10_stats_ops;
+		stats->config = &rkisp1_v10_stats_config;
+	}
 }
 
 int rkisp1_stats_register(struct rkisp1_device *rkisp1)
-- 
2.29.2

[PATCH RFC 11/11] media: rockchip: rkisp1: add support for px30 isp version

[Heiko Stuebner]

From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>

The px30 uses a V12 isp block so add compatible and matchdata
for it.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
---
 .../media/platform/rockchip/rkisp1/rkisp1-dev.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
index 0a01ffbc2cae..b617be5f2bd5 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
@@ -403,6 +403,19 @@ static irqreturn_t rkisp1_isr(int irq, void *ctx)
 	return IRQ_HANDLED;
 }
 
+static const char * const px30_isp_clks[] = {
+	"isp",
+	"aclk",
+	"hclk",
+	"pclk",
+};
+
+static const struct rkisp1_match_data px30_isp_match_data = {
+	.clks = px30_isp_clks,
+	.size = ARRAY_SIZE(px30_isp_clks),
+	.isp_ver = RKISP1_V12,
+};
+
 static const char * const rk3399_isp_clks[] = {
 	"isp",
 	"aclk",
@@ -416,6 +429,10 @@ static const struct rkisp1_match_data rk3399_isp_match_data = {
 };
 
 static const struct of_device_id rkisp1_of_match[] = {
+	{
+		.compatible = "rockchip,px30-cif-isp",
+		.data = &px30_isp_match_data,
+	},
 	{
 		.compatible = "rockchip,rk3399-cif-isp",
 		.data = &rk3399_isp_match_data,
-- 
2.29.2

Re: [PATCH RFC 05/11] media: rockchip: rkisp1: extend uapi array sizes

[Dafna Hirschfeld]

Am 08.01.21 um 20:33 schrieb Heiko Stuebner:
> From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> 
> Later variants of the rkisp1 block use more entries in some arrays:
> 
> RKISP1_CIF_ISP_AE_MEAN_MAX                 25 -> 81
> RKISP1_CIF_ISP_HIST_BIN_N_MAX              16 -> 32
> RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES       17 -> 34
> RKISP1_CIF_ISP_HISTOGRAM_WEIGHT_GRIDS_SIZE 28 -> 81
> 
> and we can still extend the uapi during the 5.11-rc cycle, so do that
> now to be on the safe side.
> 
> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> ---
>   include/uapi/linux/rkisp1-config.h | 8 ++++----
>   1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/include/uapi/linux/rkisp1-config.h b/include/uapi/linux/rkisp1-config.h
> index 6e449e784260..31a88bb65e03 100644
> --- a/include/uapi/linux/rkisp1-config.h
> +++ b/include/uapi/linux/rkisp1-config.h
> @@ -49,8 +49,8 @@
>   #define RKISP1_CIF_ISP_CTK_COEFF_MAX            0x100
>   #define RKISP1_CIF_ISP_CTK_OFFSET_MAX           0x800
>   
> -#define RKISP1_CIF_ISP_AE_MEAN_MAX              25
> -#define RKISP1_CIF_ISP_HIST_BIN_N_MAX           16
> +#define RKISP1_CIF_ISP_AE_MEAN_MAX              81
> +#define RKISP1_CIF_ISP_HIST_BIN_N_MAX           32
>   #define RKISP1_CIF_ISP_AFM_MAX_WINDOWS          3
>   #define RKISP1_CIF_ISP_DEGAMMA_CURVE_SIZE       17
>   
> @@ -86,7 +86,7 @@
>    * Gamma out
>    */
>   /* Maximum number of color samples supported */
> -#define RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES       17
> +#define RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES       34
>   
>   /*
>    * Lens shade correction
> @@ -103,7 +103,7 @@
>    * Histogram calculation
>    */
>   /* Last 3 values unused. */
> -#define RKISP1_CIF_ISP_HISTOGRAM_WEIGHT_GRIDS_SIZE 28
> +#define RKISP1_CIF_ISP_HISTOGRAM_WEIGHT_GRIDS_SIZE 81
>   

Hi,
We should have 3 defines for each of the changes,
to keep the values per version and then set the
array size to be the bigger of the two.
For example:


#define RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES_V10       17
#define RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES_v12       34
#define RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES       RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES_V12

Thanks,
Dafna

>   /*
>    * Defect Pixel Cluster Correction
> 

Re: [PATCH RFC 04/11] phy/rockchip: add Innosilicon-based CSI dphy

[Helen Koike]

Hello,

Just some nit comments from a quick look, that you would probably
catch those when removing the RFC tag, but since I spotted them, here
they are:

On 1/8/21 4:33 PM, Heiko Stuebner wrote:
> From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> 
> The CSI dphy found for example on the rk3326/px30 and rk3368 is based
> on an IP design from Innosilicon. Add a driver for it.
> 
> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> ---
>  drivers/phy/rockchip/Kconfig                  |   9 +
>  drivers/phy/rockchip/Makefile                 |   1 +
>  .../phy/rockchip/phy-rockchip-inno-csidphy.c  | 580 ++++++++++++++++++
>  3 files changed, 590 insertions(+)
>  create mode 100644 drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
> 
> diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
> index 159285f42e5c..e812adad7242 100644
> --- a/drivers/phy/rockchip/Kconfig
> +++ b/drivers/phy/rockchip/Kconfig
> @@ -48,6 +48,15 @@ config PHY_ROCKCHIP_INNO_USB2
>  	help
>  	  Support for Rockchip USB2.0 PHY with Innosilicon IP block.
>  
> +config PHY_ROCKCHIP_INNO_CSIDPHY
> +	tristate "Rockchip Innosilicon MIPI CSI PHY driver"
> +	depends on (ARCH_ROCKCHIP || COMPILE_TEST) && OF
> +	select GENERIC_PHY
> +	select GENERIC_PHY_MIPI_DPHY
> +	help
> +	  Enable this to support the Rockchip MIPI CSI PHY with
> +	  Innosilicon IP block.
> +
>  config PHY_ROCKCHIP_INNO_DSIDPHY
>  	tristate "Rockchip Innosilicon MIPI/LVDS/TTL PHY driver"
>  	depends on (ARCH_ROCKCHIP || COMPILE_TEST) && OF
> diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
> index c3cfc7f0af5c..f0eec212b2aa 100644
> --- a/drivers/phy/rockchip/Makefile
> +++ b/drivers/phy/rockchip/Makefile
> @@ -2,6 +2,7 @@
>  obj-$(CONFIG_PHY_ROCKCHIP_DP)		+= phy-rockchip-dp.o
>  obj-$(CONFIG_PHY_ROCKCHIP_DPHY_RX0)     += phy-rockchip-dphy-rx0.o
>  obj-$(CONFIG_PHY_ROCKCHIP_EMMC)		+= phy-rockchip-emmc.o
> +obj-$(CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY)	+= phy-rockchip-inno-csidphy.o
>  obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY)	+= phy-rockchip-inno-dsidphy.o
>  obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI)	+= phy-rockchip-inno-hdmi.o
>  obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)	+= phy-rockchip-inno-usb2.o
> diff --git a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
> new file mode 100644
> index 000000000000..96a7fe137bb9
> --- /dev/null
> +++ b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
> @@ -0,0 +1,580 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Rockchip MIPI RX Innosilicon DPHY driver
> + *
> + * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset.h>
> +#include <linux/phy/phy.h>

Alphabetical order

> +#include <linux/phy/phy-mipi-dphy.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/regmap.h>
> +#include <linux/mfd/syscon.h>
> +
> +/* GRF */
> +#define RK1808_GRF_PD_VI_CON_OFFSET	0x0430
> +
> +#define RK3326_GRF_IO_VSEL_OFFSET	0x0180
> +#define RK3326_GRF_PD_VI_CON_OFFSET	0x0430
> +
> +#define RK3368_GRF_SOC_CON6_OFFSET	0x0418
> +#define RK3368_GRF_IO_VSEL_OFFSET	0x0900

Some of those are "used" in commented lines.

> +
> +/* PHY */
> +#define CLOCK_LANE_HS_RX_CONTROL		0x34
> +#define LANE0_HS_RX_CONTROL			0x44
> +#define LANE1_HS_RX_CONTROL			0x54
> +#define LANE2_HS_RX_CONTROL			0x84
> +#define LANE3_HS_RX_CONTROL			0x94
> +#define HS_RX_DATA_LANES_THS_SETTLE_CONTROL	0x75

These defines are not used, should them be removed?

> +
> +#define CSIDPHY_CTRL_LANE_ENABLE		0x00
> +#define CSIDPHY_CTRL_LANE_ENABLE_CK		BIT(6)
> +#define CSIDPHY_CTRL_LANE_ENABLE_LANE3		BIT(5)
> +#define CSIDPHY_CTRL_LANE_ENABLE_LANE2		BIT(4)
> +#define CSIDPHY_CTRL_LANE_ENABLE_LANE1		BIT(3)> +#define CSIDPHY_CTRL_LANE_ENABLE_LANE0		BIT(2)

same for *_LANEx macros.

> +#define CSIDPHY_CTRL_LANE_ENABLE_UNDEFINED	BIT(0)
> +
> +#define CSIDPHY_CTRL_LANE_ENABLE_SHIFT		2
> +
> +/* not present on all variants */
> +#define CSIDPHY_CTRL_PWRCTL		0x04
> +#define CSIDPHY_CTRL_PWRCTL_UNDEFINED	GENMASK(7, 5)
> +#define CSIDPHY_CTRL_PWRCTL_SYNCRST	BIT(2)
> +#define CSIDPHY_CTRL_PWRCTL_LDO_PD	BIT(1)
> +#define CSIDPHY_CTRL_PWRCTL_PLL_PD	BIT(0)
> +
> +#define CSIDPHY_CTRL_DIG_RST			0x80
> +#define CSIDPHY_CTRL_DIG_RST_UNDEFINED		0x1e
> +#define CSIDPHY_CTRL_DIG_RST_RESET		BIT(0)
> +
> +
> +
> +

Too many new lines.

> +/* offset after CLK_THS_SETTLE */
> +#define CSIDPHY_CLK_THS_SETTLE			0
> +#define CSIDPHY_LANE_THS_SETTLE(n)		((n + 1) * 0x80)
> +#define CSIDPHY_THS_SETTLE_MASK			0x7f
> +
> +/* Configure the count time of the THS-SETTLE by protocol. */
> +#define RK1808_CSIDPHY_CLK_WR_THS_SETTLE	0x160
> +#define RK3326_CSIDPHY_CLK_WR_THS_SETTLE	0x100
> +#define RK3368_CSIDPHY_CLK_WR_THS_SETTLE	0x100
> +
> +
> +#define RK1808_CSI_DPHY_LANE0_WR_THS_SETTLE	\
> +		(RK1808_CSI_DPHY_CLK_WR_THS_SETTLE + 0x80)
> +#define RK1808_CSI_DPHY_LANE1_WR_THS_SETTLE	\
> +		(RK1808_CSI_DPHY_LANE0_WR_THS_SETTLE + 0x80)
> +#define RK1808_CSI_DPHY_LANE2_WR_THS_SETTLE	\
> +		(RK1808_CSI_DPHY_LANE1_WR_THS_SETTLE + 0x80)
> +#define RK1808_CSI_DPHY_LANE3_WR_THS_SETTLE	\
> +		(RK1808_CSI_DPHY_LANE2_WR_THS_SETTLE + 0x80)
> +
> +#define RK3326_CSI_DPHY_LANE0_WR_THS_SETTLE	\
> +		(RK3326_CSI_DPHY_CLK_WR_THS_SETTLE + 0x80)
> +#define RK3326_CSI_DPHY_LANE1_WR_THS_SETTLE	\
> +		(RK3326_CSI_DPHY_LANE0_WR_THS_SETTLE + 0x80)
> +#define RK3326_CSI_DPHY_LANE2_WR_THS_SETTLE	\
> +		(RK3326_CSI_DPHY_LANE1_WR_THS_SETTLE + 0x80)
> +#define RK3326_CSI_DPHY_LANE3_WR_THS_SETTLE	\
> +		(RK3326_CSI_DPHY_LANE2_WR_THS_SETTLE + 0x80)
> +
> +#define RK3368_CSI_DPHY_LANE0_WR_THS_SETTLE	\
> +		(RK3368_CSI_DPHY_CLK_WR_THS_SETTLE + 0x80)
> +#define RK3368_CSI_DPHY_LANE1_WR_THS_SETTLE	\
> +		(RK3368_CSI_DPHY_LANE0_WR_THS_SETTLE + 0x80)
> +#define RK3368_CSI_DPHY_LANE2_WR_THS_SETTLE	\
> +		(RK3368_CSI_DPHY_LANE1_WR_THS_SETTLE + 0x80)
> +#define RK3368_CSI_DPHY_LANE3_WR_THS_SETTLE	\
> +		(RK3368_CSI_DPHY_LANE2_WR_THS_SETTLE + 0x80)
> +
> +/* Calibration reception enable */
> +#define RK1808_CSIDPHY_CLK_CALIB_EN		0x168
> +
> +#define RK1808_CSI_DPHY_LANE0_CALIB_EN		0x1e8
> +#define RK1808_CSI_DPHY_LANE1_CALIB_EN		0x268
> +#define RK1808_CSI_DPHY_LANE2_CALIB_EN		0x2e8
> +#define RK1808_CSI_DPHY_LANE3_CALIB_EN		0x368
> +
> +#define RK3326_CSI_DPHY_CLK_CALIB_EN		\
> +		MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
> +#define RK3326_CSI_DPHY_LANE0_CALIB_EN		\
> +		MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
> +#define RK3326_CSI_DPHY_LANE1_CALIB_EN		\
> +		MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
> +#define RK3326_CSI_DPHY_LANE2_CALIB_EN		\
> +		MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
> +#define RK3326_CSI_DPHY_LANE3_CALIB_EN		\
> +		MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
> +
> +#define RK3368_CSI_DPHY_CLK_CALIB_EN		\
> +		MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
> +#define RK3368_CSI_DPHY_LANE0_CALIB_EN		\
> +		MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
> +#define RK3368_CSI_DPHY_LANE1_CALIB_EN		\
> +		MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
> +#define RK3368_CSI_DPHY_LANE2_CALIB_EN		\
> +		MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
> +#define RK3368_CSI_DPHY_LANE3_CALIB_EN		\
> +		MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
> +
> +#define HIWORD_UPDATE(val, mask, shift) \
> +	((val) << (shift) | (mask) << ((shift) + 16))
> +
> +enum dphy_reg_id {
> +	GRF_DPHY_RX0_TURNDISABLE = 0,
> +	GRF_DPHY_RX0_FORCERXMODE,
> +	GRF_DPHY_RX0_FORCETXSTOPMODE,
> +	GRF_DPHY_RX0_ENABLE,
> +	GRF_DPHY_RX0_TURNREQUEST,
> +	GRF_DPHY_TX0_TURNDISABLE,
> +	GRF_DPHY_TX0_FORCERXMODE,
> +	GRF_DPHY_TX0_FORCETXSTOPMODE,
> +	GRF_DPHY_TX0_TURNREQUEST,
> +	GRF_DPHY_RX1_SRC_SEL,
> +//	GRF_DVP_V18SEL,
> +	/* rk1808 & rk3326 */
> +	GRF_DPHY_CSIPHY_FORCERXMODE,
> +	GRF_DPHY_CSIPHY_CLKLANE_EN,
> +	GRF_DPHY_CSIPHY_DATALANE_EN,
> +	/* rk3368 only */
> +	GRF_ISP_MIPI_CSI_HOST_SEL,
> +};
> +
> +struct dphy_reg {
> +	u32 offset;
> +	u32 mask;
> +	u32 shift;
> +};
> +
> +#define PHY_REG(_offset, _width, _shift) \
> +	{ .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
> +
> +static const struct dphy_reg rk1808_grf_dphy_regs[] = {
> +	[GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4, 0),
> +	[GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 1, 8),
> +	[GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4, 4),
> +};
> +
> +static const struct dphy_reg rk3326_grf_dphy_regs[] = {
> +//	[GRF_DVP_V18SEL] = PHY_REG(RK3326_GRF_IO_VSEL_OFFSET, 1, 4),

Should this commented line be removed?

> +	[GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 4, 0),
> +	[GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 1, 8),
> +	[GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 4, 4),
> +};
> +
> +static const struct dphy_reg rk3368_grf_dphy_regs[] = {
> +//	[GRF_DVP_V18SEL] = PHY_REG(RK3368_GRF_IO_VSEL_OFFSET, 1, 1),

Ditto.

> +	[GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3368_GRF_SOC_CON6_OFFSET, 4, 8),
> +	[GRF_ISP_MIPI_CSI_HOST_SEL] = PHY_REG(RK3368_GRF_SOC_CON6_OFFSET, 1, 1),
> +//	[GRF_CON_DISABLE_ISP] = PHY_REG(RK3368_GRF_SOC_CON6_OFFSET, 1, 0),

Ditto.

> +};
> +
> +struct hsfreq_range {
> +	u32 range_h;
> +	u8 cfg_bit;
> +};
> +
> +struct rockchip_inno_csidphy;
> +
> +struct dphy_drv_data {
> +	int pwrctl_offset;
> +	int ths_settle_offset;
> +	int calib_offset;
> +	const struct hsfreq_range *hsfreq_ranges;
> +	int num_hsfreq_ranges;
> +	const struct dphy_reg *grf_regs;
> +	void (*individual_init)(struct rockchip_inno_csidphy *priv);
> +};
> +
> +struct rockchip_inno_csidphy {
> +	struct device *dev;
> +	void __iomem *phy_base;
> +	struct clk *pclk;
> +	struct regmap *grf;
> +	struct reset_control *rst;
> +	const struct dphy_drv_data *drv_data;
> +	struct phy_configure_opts_mipi_dphy config;
> +	u8 hsfreq;
> +};
> +
> +static inline void write_grf_reg(struct rockchip_inno_csidphy *priv,

It seems it would be better to receive struct dphy_drv_data instead.

> +				 int index, u8 value)
> +{
> +	struct dphy_drv_data *drv_data = priv->drv_data;
> +	const struct dphy_reg *reg = &drv_data->grf_regs[index];
> +	unsigned int val = HIWORD_UPDATE(value, reg->mask, reg->shift);
> +
> +	if (reg->offset)

Is this check required?

> +		regmap_write(priv->grf, reg->offset, val);
> +}
> +
> +static inline u32 read_grf_reg(struct rockchip_inno_csidphy *priv, int index)

This function seems to be unused.

> +{
> +	struct dphy_drv_data *drv_data = priv->drv_data;
> +	const struct dphy_reg *reg = &drv_data->grf_regs[index];
> +	unsigned int val = 0;
> +
> +	if (reg->offset) {

Is this check required?

> +		regmap_read(priv->grf, reg->offset, &val);
> +		val = (val >> reg->shift) & reg->mask;
> +	}
> +	return val;
> +}
> +
> +/* These tables must be sorted by .range_h ascending. */
> +static const struct hsfreq_range rk1808_mipidphy_hsfreq_ranges[] = {
> +	{ 109, 0x02}, { 149, 0x03}, { 199, 0x06}, { 249, 0x06},
> +	{ 299, 0x06}, { 399, 0x08}, { 499, 0x0b}, { 599, 0x0e},
> +	{ 699, 0x10}, { 799, 0x12}, { 999, 0x16}, {1199, 0x1e},
> +	{1399, 0x23}, {1599, 0x2d}, {1799, 0x32}, {1999, 0x37},
> +	{2199, 0x3c}, {2399, 0x41}, {2499, 0x46}
> +};
> +
> +static const struct hsfreq_range rk3326_mipidphy_hsfreq_ranges[] = {
> +	{ 109, 0x00}, { 149, 0x01}, { 199, 0x02}, { 249, 0x03},
> +	{ 299, 0x04}, { 399, 0x05}, { 499, 0x06}, { 599, 0x07},
> +	{ 699, 0x08}, { 799, 0x09}, { 899, 0x0a}, {1099, 0x0b},
> +	{1249, 0x0c}, {1349, 0x0d}, {1500, 0x0e}
> +};
> +
> +static const struct hsfreq_range rk3368_mipidphy_hsfreq_ranges[] = {
> +	{ 109, 0x00}, { 149, 0x01}, { 199, 0x02}, { 249, 0x03},
> +	{ 299, 0x04}, { 399, 0x05}, { 499, 0x06}, { 599, 0x07},
> +	{ 699, 0x08}, { 799, 0x09}, { 899, 0x0a}, {1099, 0x0b},
> +	{1249, 0x0c}, {1349, 0x0d}, {1500, 0x0e}
> +};
> +
> +static void default_mipidphy_individual_init(struct rockchip_inno_csidphy *priv)
> +{
> +}
> +
> +static void rk3368_mipidphy_individual_init(struct rockchip_inno_csidphy *priv)
> +{
> +	/* isp select */
> +	write_grf_reg(priv, GRF_ISP_MIPI_CSI_HOST_SEL, 1);
> +}
> +
> +static void rockchip_inno_csidphy_ths_settle(struct rockchip_inno_csidphy *priv,
> +					     int hsfreq, int offset)
> +{
> +	struct dphy_drv_data *drv_data = priv->drv_data;
> +	u32 val;
> +
> +	val = readl(priv->phy_base + drv_data->ths_settle_offset + offset);
> +	val &= ~CSIDPHY_THS_SETTLE_MASK;
> +	val |= hsfreq;
> +	writel(val, priv->phy_base + drv_data->ths_settle_offset + offset);
> +}
> +
> +static int rockchip_inno_csidphy_configure(struct phy *phy,
> +					   union phy_configure_opts *opts)
> +{
> +	struct rockchip_inno_csidphy *priv = phy_get_drvdata(phy);
> +	struct dphy_drv_data *drv_data = priv->drv_data;
> +	struct phy_configure_opts_mipi_dphy *config = &opts->mipi_dphy;
> +	unsigned int hsfreq = 0;
> +	unsigned int i;
> +	u64 data_rate_mbps;
> +	int ret;
> +
> +	/* pass with phy_mipi_dphy_get_default_config (with pixel rate?) */
> +	ret = phy_mipi_dphy_config_validate(config);
> +	if (ret)
> +		return ret;
> +
> +	data_rate_mbps = div_u64(config->hs_clk_rate, 1000 * 1000);
> +
> +	dev_dbg(priv->dev, "lanes %d - data_rate_mbps %llu\n",
> +		config->lanes, data_rate_mbps);
> +	for (i = 0; i < drv_data->num_hsfreq_ranges; i++) {
> +		if (drv_data->hsfreq_ranges[i].range_h >= data_rate_mbps) {
> +			hsfreq = drv_data->hsfreq_ranges[i].cfg_bit;
> +			break;
> +		}
> +	}
> +	if (!hsfreq)
> +		return -EINVAL;
> +
> +	priv->hsfreq = hsfreq;
> +	priv->config = *config;
> +	return 0;
> +}
> +
> +static int rockchip_inno_csidphy_power_on(struct phy *phy)
> +{
> +	struct rockchip_inno_csidphy *priv = phy_get_drvdata(phy);
> +	struct dphy_drv_data *drv_data = priv->drv_data;
> +	u32 val = 0;
> +	int ret, i;
> +
> +	u64 data_rate_mbps;
> +
> +	data_rate_mbps = div_u64(priv->config.hs_clk_rate, 1000 * 1000);
> +
> +	ret = clk_enable(priv->pclk);
> +	if (ret < 0)
> +		return ret;
> +
> +//	write_grf_reg(priv, GRF_DVP_V18SEL, 0x1);
> +
> +	/* phy start */
> +	if (drv_data->pwrctl_offset >= 0)
> +		writel(CSIDPHY_CTRL_PWRCTL_UNDEFINED |
> +		       CSIDPHY_CTRL_PWRCTL_SYNCRST,
> +		       priv->phy_base + drv_data->pwrctl_offset);
> +
> +	/* set data lane num and enable clock lane */
> +	val = GENMASK(priv->config.lanes - 1, 0) << CSIDPHY_CTRL_LANE_ENABLE_SHIFT;
> +	writel(val | CSIDPHY_CTRL_LANE_ENABLE_CK |
> +	       CSIDPHY_CTRL_LANE_ENABLE_UNDEFINED,
> +	       priv->phy_base + CSIDPHY_CTRL_LANE_ENABLE);
> +
> +	/* Reset dphy analog part */
> +	if (drv_data->pwrctl_offset >= 0)
> +		writel(CSIDPHY_CTRL_PWRCTL_UNDEFINED,
> +		       priv->phy_base + drv_data->pwrctl_offset);
> +	usleep_range(500, 1000);
> +
> +

double new line.

> +	/* Reset dphy digital part */
> +	writel(CSIDPHY_CTRL_DIG_RST_UNDEFINED,
> +	       priv->phy_base + CSIDPHY_CTRL_DIG_RST);
> +	writel(CSIDPHY_CTRL_DIG_RST_UNDEFINED + CSIDPHY_CTRL_DIG_RST_RESET,
> +	       priv->phy_base + CSIDPHY_CTRL_DIG_RST);
> +
> +	/* not into receive mode/wait stopstate */
> +	write_grf_reg(priv, GRF_DPHY_CSIPHY_FORCERXMODE, 0x0);
> +
> +	/* enable calibration */
> +/* FIXME: reenable
> +	if (data_rate_mbps > 1500) {
> +		write_csiphy_reg(priv, CSIPHY_CLK_CALIB_ENABLE, 0x80);
> +		if (priv->config.lanes > 0)
> +			write_csiphy_reg(priv, CSIPHY_LANE0_CALIB_ENABLE, 0x80);
> +		if (priv->config.lanes > 1)
> +			write_csiphy_reg(priv, CSIPHY_LANE1_CALIB_ENABLE, 0x80);
> +		if (priv->config.lanes > 2)
> +			write_csiphy_reg(priv, CSIPHY_LANE2_CALIB_ENABLE, 0x80);
> +		if (priv->config.lanes > 3)
> +			write_csiphy_reg(priv, CSIPHY_LANE3_CALIB_ENABLE, 0x80);
> +	} */

maybe fix identation and add an explanation explaning why this is commented?
#if 0 ?

> +
> +	rockchip_inno_csidphy_ths_settle(priv, priv->hsfreq,
> +					 CSIDPHY_CLK_THS_SETTLE);
> +	for (i = 0; i < priv->config.lanes; i++)
> +		rockchip_inno_csidphy_ths_settle(priv, priv->hsfreq,
> +						 CSIDPHY_LANE_THS_SETTLE(i));
> +
> +//	write_grf_reg(priv, GRF_DPHY_CLK_INV_SEL, 0x1);

commented code line.

> +	write_grf_reg(priv, GRF_DPHY_CSIPHY_CLKLANE_EN, 0x1);
> +	write_grf_reg(priv, GRF_DPHY_CSIPHY_DATALANE_EN,
> +		      GENMASK(priv->config.lanes - 1, 0));
> +
> +	return 0;
> +}
> +
> +static int rockchip_inno_csidphy_power_off(struct phy *phy)
> +{
> +	struct rockchip_inno_csidphy *priv = phy_get_drvdata(phy);
> +	struct dphy_drv_data *drv_data = priv->drv_data;
> +
> +	/* disable all lanes */
> +	writel(CSIDPHY_CTRL_LANE_ENABLE_UNDEFINED,
> +	       priv->phy_base + CSIDPHY_CTRL_LANE_ENABLE);
> +
> +	/* disable pll and ldo */
> +	if (drv_data->pwrctl_offset >= 0)
> +		writel(CSIDPHY_CTRL_PWRCTL_UNDEFINED |
> +		       CSIDPHY_CTRL_PWRCTL_LDO_PD |
> +		       CSIDPHY_CTRL_PWRCTL_PLL_PD,
> +		       priv->phy_base + drv_data->pwrctl_offset);
> +	usleep_range(500, 1000);
> +
> +	clk_disable(priv->pclk);
> +
> +	return 0;
> +}
> +
> +static int rockchip_inno_csidphy_init(struct phy *phy)
> +{
> +	struct rockchip_inno_csidphy *priv = phy_get_drvdata(phy);
> +
> +	return clk_prepare(priv->pclk);
> +}
> +
> +static int rockchip_inno_csidphy_exit(struct phy *phy)
> +{
> +	struct rockchip_inno_csidphy *priv = phy_get_drvdata(phy);
> +
> +	clk_unprepare(priv->pclk);
> +
> +	return 0;
> +}
> +
> +static const struct phy_ops rockchip_inno_csidphy_ops = {
> +	.power_on	= rockchip_inno_csidphy_power_on,
> +	.power_off	= rockchip_inno_csidphy_power_off,
> +	.init		= rockchip_inno_csidphy_init,
> +	.exit		= rockchip_inno_csidphy_exit,
> +	.configure	= rockchip_inno_csidphy_configure,
> +	.owner		= THIS_MODULE,
> +};
> +
> +
> +static const struct dphy_drv_data rk1808_mipidphy_drv_data = {
> +	.pwrctl_offset = -1,
> +	.ths_settle_offset = RK1808_CSIDPHY_CLK_WR_THS_SETTLE,
> +	.calib_offset = RK1808_CSIDPHY_CLK_CALIB_EN,
> +	.hsfreq_ranges = rk1808_mipidphy_hsfreq_ranges,
> +	.num_hsfreq_ranges = ARRAY_SIZE(rk1808_mipidphy_hsfreq_ranges),
> +	.grf_regs = rk1808_grf_dphy_regs,
> +
> +	.individual_init = default_mipidphy_individual_init,
> +};
> +
> +static const struct dphy_drv_data rk3326_mipidphy_drv_data = {
> +	.pwrctl_offset = CSIDPHY_CTRL_PWRCTL,
> +	.ths_settle_offset = RK3326_CSIDPHY_CLK_WR_THS_SETTLE,
> +	.calib_offset = -1,
> +	.hsfreq_ranges = rk3326_mipidphy_hsfreq_ranges,
> +	.num_hsfreq_ranges = ARRAY_SIZE(rk3326_mipidphy_hsfreq_ranges),
> +	.grf_regs = rk3326_grf_dphy_regs,
> +
> +	.individual_init = default_mipidphy_individual_init,
> +};
> +
> +static const struct dphy_drv_data rk3368_mipidphy_drv_data = {
> +	.pwrctl_offset = CSIDPHY_CTRL_PWRCTL,
> +	.ths_settle_offset = RK3368_CSIDPHY_CLK_WR_THS_SETTLE,
> +	.calib_offset = -1,
> +	.hsfreq_ranges = rk3368_mipidphy_hsfreq_ranges,
> +	.num_hsfreq_ranges = ARRAY_SIZE(rk3368_mipidphy_hsfreq_ranges),
> +	.grf_regs = rk3368_grf_dphy_regs,
> +
> +	.individual_init = rk3368_mipidphy_individual_init,
> +};
> +
> +static const struct of_device_id rockchip_inno_csidphy_match_id[] = {
> +	{
> +		.compatible = "rockchip,px30-mipi-dphy",
> +		.data = &rk3326_mipidphy_drv_data,
> +	},
> +	{
> +		.compatible = "rockchip,rk1808-mipi-dphy-rx",
> +		.data = &rk1808_mipidphy_drv_data,
> +	},
> +	{
> +		.compatible = "rockchip,rk3326-mipi-dphy",
> +		.data = &rk3326_mipidphy_drv_data,
> +	},
> +	{
> +		.compatible = "rockchip,rk3368-mipi-dphy",
> +		.data = &rk3368_mipidphy_drv_data,
> +	},
> +	{}
> +};
> +MODULE_DEVICE_TABLE(of, rockchip_inno_csidphy_match_id);
> +
> +
> +static int rockchip_inno_csidphy_probe(struct platform_device *pdev)
> +{
> +	struct rockchip_inno_csidphy *priv;
> +	struct device *dev = &pdev->dev;
> +	struct regmap *grf;
> +	struct phy_provider *phy_provider;
> +	struct phy *phy;
> +	int i, ret;

unused i.

> +
> +	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> +	if (!priv)
> +		return -ENOMEM;
> +
> +	priv->dev = dev;
> +	platform_set_drvdata(pdev, priv);
> +
> +	priv->phy_base = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(priv->phy_base))
> +		return PTR_ERR(priv->phy_base);
> +
> +	priv->pclk = devm_clk_get(dev, "pclk");
> +	if (IS_ERR(priv->pclk)) {
> +		ret = PTR_ERR(priv->pclk);
> +		dev_err(dev, "failed to get pclk: %d\n", ret);
> +		return ret;

Maybe just:

dev_err(dev, "failed to get pclk: %d\n", ret);
return PTR_ERR(priv->pclk);

> +	}
> +
> +	priv->rst = devm_reset_control_get(dev, "apb");
> +	if (IS_ERR(priv->rst)) {
> +		ret = PTR_ERR(priv->rst);
> +		dev_err(dev, "failed to get system reset control: %d\n", ret);
> +		return ret;

Ditto.

> +	}
> +
> +	priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
> +						    "rockchip,grf");
> +	if (IS_ERR(priv->grf)) {
> +		dev_err(dev, "Can't find GRF syscon\n");
> +		return PTR_ERR(priv->grf);
> +	}
> +
> +	priv->drv_data = of_device_get_match_data(dev);
> +	if (!priv->drv_data) {
> +		dev_err(dev, "Can't find device data\n");
> +		return -ENODEV;
> +	}
> +
> +	phy = devm_phy_create(dev, NULL, &rockchip_inno_csidphy_ops);
> +	if (IS_ERR(phy)) {
> +		ret = PTR_ERR(phy);
> +		dev_err(dev, "failed to create phy: %d\n", ret);
> +		return ret;

Ditto.

> +	}
> +
> +	phy_set_drvdata(phy, priv);
> +
> +	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> +	if (IS_ERR(phy_provider)) {
> +		ret = PTR_ERR(phy_provider);
> +		dev_err(dev, "failed to register phy provider: %d\n", ret);
> +		return ret;

Ditto.

> +	}
> +
> +	pm_runtime_enable(dev);
> +
> +	priv->drv_data->individual_init(priv);
> +	return 0;
> +}
> +
> +static int rockchip_inno_csidphy_remove(struct platform_device *pdev)
> +{
> +	struct rockchip_inno_csidphy *priv = platform_get_drvdata(pdev);
> +
> +	pm_runtime_disable(priv->dev);
> +
> +	return 0;
> +}
> +
> +static struct platform_driver rockchip_inno_csidphy_driver = {
> +	.driver = {
> +			.name = "rockchip-inno-csidphy",
> +			.of_match_table = rockchip_inno_csidphy_match_id,
> +	},
> +	.probe = rockchip_inno_csidphy_probe,
> +	.remove = rockchip_inno_csidphy_remove,
> +};
> +
> +module_platform_driver(rockchip_inno_csidphy_driver);
> +MODULE_AUTHOR("Rockchip Camera/ISP team");
> +MODULE_DESCRIPTION("Rockchip MIPI RX DPHY driver");

Just to follow the model of phy-rockchip-dphy-rx0.c, maybe
"Rockchip MIPI Innosilicon RX DPHY driver"

Regards,
Helen

> +MODULE_LICENSE("Dual BSD/GPL");
> 

Re: [PATCH RFC 06/11] media: rockchip: rkisp1: allow separate interrupts

[Helen Koike]

Hi Heiko,

On 1/8/21 4:33 PM, Heiko Stuebner wrote:
> From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> 
> Depending on the per-soc implementation there can be one interrupt
> for isp, mipi and capture events or separate per-event interrupts.
> 
> So simply check for the presence of a named "mi" interrupt
> to differentiate between the two cases.
> 
> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> ---
>  .../platform/rockchip/rkisp1/rkisp1-capture.c |  9 ++-
>  .../platform/rockchip/rkisp1/rkisp1-common.h  |  7 ++-
>  .../platform/rockchip/rkisp1/rkisp1-dev.c     | 58 ++++++++++++++-----
>  .../platform/rockchip/rkisp1/rkisp1-isp.c     | 16 +++--
>  4 files changed, 69 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
> index 5f6c9d1623e4..f70c66c2a1d7 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
> @@ -685,12 +685,17 @@ static void rkisp1_handle_buffer(struct rkisp1_capture *cap)
>  	spin_unlock(&cap->buf.lock);
>  }
>  
> -void rkisp1_capture_isr(struct rkisp1_device *rkisp1)
> +irqreturn_t rkisp1_capture_isr(int irq, void *ctx)
>  {
> +	struct device *dev = ctx;
> +	struct rkisp1_device *rkisp1 = dev_get_drvdata(dev);
>  	unsigned int i;
>  	u32 status;
>  
>  	status = rkisp1_read(rkisp1, RKISP1_CIF_MI_MIS);
> +	if (!status)
> +		return IRQ_NONE;
> +
>  	rkisp1_write(rkisp1, status, RKISP1_CIF_MI_ICR);
>  
>  	for (i = 0; i < ARRAY_SIZE(rkisp1->capture_devs); ++i) {
> @@ -718,6 +723,8 @@ void rkisp1_capture_isr(struct rkisp1_device *rkisp1)
>  		cap->is_streaming = false;
>  		wake_up(&cap->done);
>  	}
> +
> +	return IRQ_HANDLED;
>  }
>  
>  /* ----------------------------------------------------------------------------
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
> index 038c303a8aed..44f333bf5d6a 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
> @@ -12,6 +12,7 @@
>  #define _RKISP1_COMMON_H
>  
>  #include <linux/clk.h>
> +#include <linux/interrupt.h>
>  #include <linux/mutex.h>
>  #include <linux/rkisp1-config.h>
>  #include <media/media-device.h>
> @@ -460,9 +461,9 @@ void rkisp1_params_configure(struct rkisp1_params *params,
>  void rkisp1_params_disable(struct rkisp1_params *params);
>  
>  /* irq handlers */
> -void rkisp1_isp_isr(struct rkisp1_device *rkisp1);
> -void rkisp1_mipi_isr(struct rkisp1_device *rkisp1);
> -void rkisp1_capture_isr(struct rkisp1_device *rkisp1);
> +irqreturn_t rkisp1_isp_isr(int irq, void *ctx);
> +irqreturn_t rkisp1_mipi_isr(int irq, void *ctx);
> +irqreturn_t rkisp1_capture_isr(int irq, void *ctx);>  void rkisp1_stats_isr(struct rkisp1_stats *stats, u32 isp_ris);
>  void rkisp1_params_isr(struct rkisp1_device *rkisp1);
>  
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
> index 68da1eed753d..96afc1d1a914 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
> @@ -389,18 +389,15 @@ static int rkisp1_entities_register(struct rkisp1_device *rkisp1)
>  
>  static irqreturn_t rkisp1_isr(int irq, void *ctx)
>  {
> -	struct device *dev = ctx;
> -	struct rkisp1_device *rkisp1 = dev_get_drvdata(dev);
> -
>  	/*
>  	 * Call rkisp1_capture_isr() first to handle the frame that
>  	 * potentially completed using the current frame_sequence number before
>  	 * it is potentially incremented by rkisp1_isp_isr() in the vertical
>  	 * sync.
>  	 */
> -	rkisp1_capture_isr(rkisp1);
> -	rkisp1_isp_isr(rkisp1);
> -	rkisp1_mipi_isr(rkisp1);
> +	rkisp1_capture_isr(irq, ctx);
> +	rkisp1_isp_isr(irq, ctx);
> +	rkisp1_mipi_isr(irq, ctx);
>  
>  	return IRQ_HANDLED;
>  }
> @@ -481,15 +478,50 @@ static int rkisp1_probe(struct platform_device *pdev)
>  	if (IS_ERR(rkisp1->base_addr))
>  		return PTR_ERR(rkisp1->base_addr);
>  
> -	irq = platform_get_irq(pdev, 0);
> -	if (irq < 0)
> +	irq = platform_get_irq_byname_optional(pdev, "mi");
> +	if (irq == -EPROBE_DEFER) {
>  		return irq;
> +	} else if (irq < 0) {
> +		irq = platform_get_irq(pdev, 0);
> +		if (irq < 0)
> +			return irq;
> +
> +		ret = devm_request_irq(dev, irq, rkisp1_isr, IRQF_SHARED,
> +				       dev_driver_string(dev), dev);
> +		if (ret) {
> +			dev_err(dev, "request irq failed: %d\n", ret);
> +			return ret;
> +		}
> +	} else {
> +		/* we test-got the MI (capture) interrupt */
> +		ret = devm_request_irq(dev, irq, rkisp1_capture_isr, IRQF_SHARED,
> +				       dev_driver_string(dev), dev);
> +		if (ret) {
> +			dev_err(dev, "request mi irq failed: %d\n", ret);
> +			return ret;
> +		}
>  
> -	ret = devm_request_irq(dev, irq, rkisp1_isr, IRQF_SHARED,
> -			       dev_driver_string(dev), dev);
> -	if (ret) {
> -		dev_err(dev, "request irq failed: %d\n", ret);
> -		return ret;
> +		irq = platform_get_irq_byname_optional(pdev, "mipi");
> +		if (irq < 0)
> +			return irq;
> +
> +		ret = devm_request_irq(dev, irq, rkisp1_mipi_isr, IRQF_SHARED,
> +				       dev_driver_string(dev), dev);
> +		if (ret) {
> +			dev_err(dev, "request mipi irq failed: %d\n", ret);
> +			return ret;
> +		}
> +
> +		irq = platform_get_irq_byname_optional(pdev, "isp");
> +		if (irq < 0)
> +			return irq;
> +
> +		ret = devm_request_irq(dev, irq, rkisp1_isp_isr, IRQF_SHARED,
> +				       dev_driver_string(dev), dev);
> +		if (ret) {
> +			dev_err(dev, "request isp irq failed: %d\n", ret);
> +			return ret;
> +		}
>  	}
>  
>  	rkisp1->irq = irq;

Could you also remove this? It seems unused and it doesn't make sense for separated interrupts.

Thanks
Helen

> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
> index 889982d8ca41..84440aa71210 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
> @@ -1056,13 +1056,15 @@ void rkisp1_isp_unregister(struct rkisp1_device *rkisp1)
>   * Interrupt handlers
>   */
>  
> -void rkisp1_mipi_isr(struct rkisp1_device *rkisp1)
> +irqreturn_t rkisp1_mipi_isr(int irq, void *ctx)
>  {
> +	struct device *dev = ctx;
> +	struct rkisp1_device *rkisp1 = dev_get_drvdata(dev);
>  	u32 val, status;
>  
>  	status = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_MIS);
>  	if (!status)
> -		return;
> +		return IRQ_NONE;
>  
>  	rkisp1_write(rkisp1, status, RKISP1_CIF_MIPI_ICR);
>  
> @@ -1097,6 +1099,8 @@ void rkisp1_mipi_isr(struct rkisp1_device *rkisp1)
>  	} else {
>  		rkisp1->debug.mipi_error++;
>  	}
> +
> +	return IRQ_HANDLED;
>  }
>  
>  static void rkisp1_isp_queue_event_sof(struct rkisp1_isp *isp)
> @@ -1109,13 +1113,15 @@ static void rkisp1_isp_queue_event_sof(struct rkisp1_isp *isp)
>  	v4l2_event_queue(isp->sd.devnode, &event);
>  }
>  
> -void rkisp1_isp_isr(struct rkisp1_device *rkisp1)
> +irqreturn_t rkisp1_isp_isr(int irq, void *ctx)
>  {
> +	struct device *dev = ctx;
> +	struct rkisp1_device *rkisp1 = dev_get_drvdata(dev);
>  	u32 status, isp_err;
>  
>  	status = rkisp1_read(rkisp1, RKISP1_CIF_ISP_MIS);
>  	if (!status)
> -		return;
> +		return IRQ_NONE;
>  
>  	rkisp1_write(rkisp1, status, RKISP1_CIF_ISP_ICR);
>  
> @@ -1157,4 +1163,6 @@ void rkisp1_isp_isr(struct rkisp1_device *rkisp1)
>  		 */
>  		rkisp1_params_isr(rkisp1);
>  	}
> +
> +	return IRQ_HANDLED;
>  }
> 

Re: [PATCH RFC 08/11] media: rockchip: rkisp1: make some isp-param functions variable

[Helen Koike]

On 1/8/21 4:33 PM, Heiko Stuebner wrote:
> From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> 
> The isp block evolved in subsequent socs, so some functions
> will behave differently on newer variants.
> 
> Therefore make it possible to override the needed params functions.
> 
> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>

Acked-by: Helen Koike <helen.koike@collabora.com>

> ---
>  .../platform/rockchip/rkisp1/rkisp1-common.h  | 30 ++++++++
>  .../platform/rockchip/rkisp1/rkisp1-params.c  | 76 ++++++++++++-------
>  2 files changed, 77 insertions(+), 29 deletions(-)
> 
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
> index 7678eabc9ffc..4034a05ef9d2 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
> @@ -258,11 +258,39 @@ struct rkisp1_stats {
>  	struct v4l2_format vdev_fmt;
>  };
>  
> +struct rkisp1_params;
> +struct rkisp1_params_ops {
> +	void (*lsc_matrix_config)(struct rkisp1_params *params,
> +				  const struct rkisp1_cif_isp_lsc_config *pconfig);
> +	void (*goc_config)(struct rkisp1_params *params,
> +			   const struct rkisp1_cif_isp_goc_config *arg);
> +	void (*awb_meas_config)(struct rkisp1_params *params,
> +				const struct rkisp1_cif_isp_awb_meas_config *arg);
> +	void (*awb_meas_enable)(struct rkisp1_params *params,
> +				const struct rkisp1_cif_isp_awb_meas_config *arg,
> +				bool en);
> +	void (*awb_gain_config)(struct rkisp1_params *params,
> +				const struct rkisp1_cif_isp_awb_gain_config *arg);
> +	void (*aec_config)(struct rkisp1_params *params,
> +			   const struct rkisp1_cif_isp_aec_config *arg);
> +	void (*hst_config)(struct rkisp1_params *params,
> +			   const struct rkisp1_cif_isp_hst_config *arg);
> +	void (*hst_enable)(struct rkisp1_params *params,
> +			   const struct rkisp1_cif_isp_hst_config *arg, bool en);
> +	void (*afm_config)(struct rkisp1_params *params,
> +			   const struct rkisp1_cif_isp_afc_config *arg);
> +};
> +
> +struct rkisp1_params_config {
> +	const int gamma_out_max_samples;
> +};
> +
>  /*
>   * struct rkisp1_params - ISP input parameters device
>   *
>   * @vnode:		video node
>   * @rkisp1:		pointer to the rkisp1 device
> + * @ops:		pointer to the variant-specific operations
>   * @config_lock:	locks the buffer list 'params'
>   * @params:		queue of rkisp1_buffer
>   * @vdev_fmt:		v4l2_format of the metadata format
> @@ -272,6 +300,8 @@ struct rkisp1_stats {
>  struct rkisp1_params {
>  	struct rkisp1_vdev_node vnode;
>  	struct rkisp1_device *rkisp1;
> +	struct rkisp1_params_ops *ops;
> +	struct rkisp1_params_config *config;
>  
>  	spinlock_t config_lock; /* locks the buffers list 'params' */
>  	struct list_head params;
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
> index 6af4d551ffb5..008584caaad0 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
> @@ -185,8 +185,8 @@ static void rkisp1_bls_config(struct rkisp1_params *params,
>  
>  /* ISP LS correction interface function */
>  static void
> -rkisp1_lsc_correct_matrix_config(struct rkisp1_params *params,
> -				 const struct rkisp1_cif_isp_lsc_config *pconfig)
> +rkisp1_lsc_matrix_config(struct rkisp1_params *params,
> +			 const struct rkisp1_cif_isp_lsc_config *pconfig)
>  {
>  	unsigned int isp_lsc_status, sram_addr, isp_lsc_table_sel, i, j, data;
>  
> @@ -265,7 +265,7 @@ static void rkisp1_lsc_config(struct rkisp1_params *params,
>  	lsc_ctrl = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_LSC_CTRL);
>  	rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_LSC_CTRL,
>  				RKISP1_CIF_ISP_LSC_CTRL_ENA);
> -	rkisp1_lsc_correct_matrix_config(params, arg);
> +	params->ops->lsc_matrix_config(params, arg);
>  
>  	for (i = 0; i < RKISP1_CIF_ISP_LSC_SECTORS_TBL_SIZE / 2; i++) {
>  		/* program x size tables */
> @@ -391,7 +391,7 @@ static void rkisp1_goc_config(struct rkisp1_params *params,
>  				RKISP1_CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA);
>  	rkisp1_write(params->rkisp1, arg->mode, RKISP1_CIF_ISP_GAMMA_OUT_MODE);
>  
> -	for (i = 0; i < RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES; i++)
> +	for (i = 0; i < params->config->gamma_out_max_samples; i++)
>  		rkisp1_write(params->rkisp1, arg->gamma_y[i],
>  			     RKISP1_CIF_ISP_GAMMA_OUT_Y_0 + i * 4);
>  }
> @@ -968,8 +968,8 @@ rkisp1_isp_isr_other_config(struct rkisp1_params *params,
>  	    (module_cfg_update & RKISP1_CIF_ISP_MODULE_AWB_GAIN)) {
>  		/* update awb gains */
>  		if (module_cfg_update & RKISP1_CIF_ISP_MODULE_AWB_GAIN)
> -			rkisp1_awb_gain_config(params,
> -					       &new_params->others.awb_gain_config);
> +			params->ops->awb_gain_config(params,
> +						     &new_params->others.awb_gain_config);
>  
>  		if (module_en_update & RKISP1_CIF_ISP_MODULE_AWB_GAIN) {
>  			if (module_ens & RKISP1_CIF_ISP_MODULE_AWB_GAIN)
> @@ -1037,8 +1037,8 @@ rkisp1_isp_isr_other_config(struct rkisp1_params *params,
>  	    (module_cfg_update & RKISP1_CIF_ISP_MODULE_GOC)) {
>  		/* update goc config */
>  		if (module_cfg_update & RKISP1_CIF_ISP_MODULE_GOC)
> -			rkisp1_goc_config(params,
> -					  &new_params->others.goc_config);
> +			params->ops->goc_config(params,
> +						&new_params->others.goc_config);
>  
>  		if (module_en_update & RKISP1_CIF_ISP_MODULE_GOC) {
>  			if (module_ens & RKISP1_CIF_ISP_MODULE_GOC)
> @@ -1124,20 +1124,20 @@ static void rkisp1_isp_isr_meas_config(struct rkisp1_params *params,
>  	    (module_cfg_update & RKISP1_CIF_ISP_MODULE_AWB)) {
>  		/* update awb config */
>  		if (module_cfg_update & RKISP1_CIF_ISP_MODULE_AWB)
> -			rkisp1_awb_meas_config(params,
> -					       &new_params->meas.awb_meas_config);
> +			params->ops->awb_meas_config(params,
> +						     &new_params->meas.awb_meas_config);
>  
>  		if (module_en_update & RKISP1_CIF_ISP_MODULE_AWB)
> -			rkisp1_awb_meas_enable(params,
> -					       &new_params->meas.awb_meas_config,
> -					       !!(module_ens & RKISP1_CIF_ISP_MODULE_AWB));
> +			params->ops->awb_meas_enable(params,
> +						     &new_params->meas.awb_meas_config,
> +						     !!(module_ens & RKISP1_CIF_ISP_MODULE_AWB));
>  	}
>  
>  	if ((module_en_update & RKISP1_CIF_ISP_MODULE_AFC) ||
>  	    (module_cfg_update & RKISP1_CIF_ISP_MODULE_AFC)) {
>  		/* update afc config */
>  		if (module_cfg_update & RKISP1_CIF_ISP_MODULE_AFC)
> -			rkisp1_afm_config(params,
> +			params->ops->afm_config(params,
>  					  &new_params->meas.afc_config);
>  
>  		if (module_en_update & RKISP1_CIF_ISP_MODULE_AFC) {
> @@ -1156,21 +1156,21 @@ static void rkisp1_isp_isr_meas_config(struct rkisp1_params *params,
>  	    (module_cfg_update & RKISP1_CIF_ISP_MODULE_HST)) {
>  		/* update hst config */
>  		if (module_cfg_update & RKISP1_CIF_ISP_MODULE_HST)
> -			rkisp1_hst_config(params,
> -					  &new_params->meas.hst_config);
> +			params->ops->hst_config(params,
> +						&new_params->meas.hst_config);
>  
>  		if (module_en_update & RKISP1_CIF_ISP_MODULE_HST)
> -			rkisp1_hst_enable(params,
> -					  &new_params->meas.hst_config,
> -					  !!(module_ens & RKISP1_CIF_ISP_MODULE_HST));
> +			params->ops->hst_enable(params,
> +						&new_params->meas.hst_config,
> +						!!(module_ens & RKISP1_CIF_ISP_MODULE_HST));
>  	}
>  
>  	if ((module_en_update & RKISP1_CIF_ISP_MODULE_AEC) ||
>  	    (module_cfg_update & RKISP1_CIF_ISP_MODULE_AEC)) {
>  		/* update aec config */
>  		if (module_cfg_update & RKISP1_CIF_ISP_MODULE_AEC)
> -			rkisp1_aec_config(params,
> -					  &new_params->meas.aec_config);
> +			params->ops->aec_config(params,
> +						&new_params->meas.aec_config);
>  
>  		if (module_en_update & RKISP1_CIF_ISP_MODULE_AEC) {
>  			if (module_ens & RKISP1_CIF_ISP_MODULE_AEC)
> @@ -1272,20 +1272,20 @@ static void rkisp1_params_config_parameter(struct rkisp1_params *params)
>  {
>  	struct rkisp1_cif_isp_hst_config hst = rkisp1_hst_params_default_config;
>  
> -	rkisp1_awb_meas_config(params, &rkisp1_awb_params_default_config);
> -	rkisp1_awb_meas_enable(params, &rkisp1_awb_params_default_config,
> -			       true);
> +	params->ops->awb_meas_config(params, &rkisp1_awb_params_default_config);
> +	params->ops->awb_meas_enable(params, &rkisp1_awb_params_default_config,
> +				     true);
>  
> -	rkisp1_aec_config(params, &rkisp1_aec_params_default_config);
> +	params->ops->aec_config(params, &rkisp1_aec_params_default_config);
>  	rkisp1_param_set_bits(params, RKISP1_CIF_ISP_EXP_CTRL,
>  			      RKISP1_CIF_ISP_EXP_ENA);
>  
> -	rkisp1_afm_config(params, &rkisp1_afc_params_default_config);
> +	params->ops->afm_config(params, &rkisp1_afc_params_default_config);
>  	rkisp1_param_set_bits(params, RKISP1_CIF_ISP_AFM_CTRL,
>  			      RKISP1_CIF_ISP_AFM_ENA);
>  
>  	memset(hst.hist_weight, 0x01, sizeof(hst.hist_weight));
> -	rkisp1_hst_config(params, &hst);
> +	params->ops->hst_config(params, &hst);
>  	rkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_PROP,
>  			      ~RKISP1_CIF_ISP_HIST_PROP_MODE_MASK |
>  			      rkisp1_hst_params_default_config.mode);
> @@ -1330,7 +1330,7 @@ void rkisp1_params_disable(struct rkisp1_params *params)
>  				RKISP1_CIF_ISP_DEMOSAIC_BYPASS);
>  	rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_FILT_MODE,
>  				RKISP1_CIF_ISP_FLT_ENA);
> -	rkisp1_awb_meas_enable(params, NULL, false);
> +	params->ops->awb_meas_enable(params, NULL, false);
>  	rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_CTRL,
>  				RKISP1_CIF_ISP_CTRL_ISP_AWB_ENA);
>  	rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_EXP_CTRL,
> @@ -1338,7 +1338,7 @@ void rkisp1_params_disable(struct rkisp1_params *params)
>  	rkisp1_ctk_enable(params, false);
>  	rkisp1_param_clear_bits(params, RKISP1_CIF_C_PROC_CTRL,
>  				RKISP1_CIF_C_PROC_CTR_ENABLE);
> -	rkisp1_hst_enable(params, NULL, false);
> +	params->ops->hst_enable(params, NULL, false);
>  	rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_AFM_CTRL,
>  				RKISP1_CIF_ISP_AFM_ENA);
>  	rkisp1_ie_enable(params, false);
> @@ -1346,6 +1346,22 @@ void rkisp1_params_disable(struct rkisp1_params *params)
>  				RKISP1_CIF_ISP_DPF_MODE_EN);
>  }
>  
> +static struct rkisp1_params_ops rkisp1_params_ops = {
> +	.lsc_matrix_config = rkisp1_lsc_matrix_config,
> +	.goc_config = rkisp1_goc_config,
> +	.awb_meas_config = rkisp1_awb_meas_config,
> +	.awb_meas_enable = rkisp1_awb_meas_enable,
> +	.awb_gain_config = rkisp1_awb_gain_config,
> +	.aec_config = rkisp1_aec_config,
> +	.hst_config = rkisp1_hst_config,
> +	.hst_enable = rkisp1_hst_enable,
> +	.afm_config = rkisp1_afm_config,
> +};
> +
> +static struct rkisp1_params_config rkisp1_params_config = {
> +	.gamma_out_max_samples = 17,
> +};
> +
>  static int rkisp1_params_enum_fmt_meta_out(struct file *file, void *priv,
>  					   struct v4l2_fmtdesc *f)
>  {
> @@ -1512,6 +1528,8 @@ static void rkisp1_init_params(struct rkisp1_params *params)
>  		V4L2_META_FMT_RK_ISP1_PARAMS;
>  	params->vdev_fmt.fmt.meta.buffersize =
>  		sizeof(struct rkisp1_params_cfg);
> +	params->ops = &rkisp1_params_ops;
> +	params->config = &rkisp1_params_config;
>  }
>  
>  int rkisp1_params_register(struct rkisp1_device *rkisp1)
> 

Re: [PATCH RFC 09/11] media: rockchip: rkisp1: make some isp-stats functions variable

[Helen Koike]

On 1/8/21 4:33 PM, Heiko Stuebner wrote:
> From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> 
> The isp block evolved in subsequent socs, so some functions
> will behave differently on newer variants.
> 
> Therefore make it possible to override the needed stats functions.
> 
> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>

Acked-by: Helen Koike <helen.koike@collabora.com>

> ---
>  .../platform/rockchip/rkisp1/rkisp1-common.h  | 17 +++++++++++++
>  .../platform/rockchip/rkisp1/rkisp1-stats.c   | 24 +++++++++++++++----
>  2 files changed, 36 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
> index 4034a05ef9d2..be0ae02165c9 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
> @@ -240,6 +240,21 @@ struct rkisp1_capture {
>  	} pix;
>  };
>  
> +struct rkisp1_stats;
> +struct rkisp1_stats_ops {
> +	void (*get_awb_meas)(struct rkisp1_stats *stats,
> +			     struct rkisp1_stat_buffer *pbuf);
> +	void (*get_aec_meas)(struct rkisp1_stats *stats,
> +			     struct rkisp1_stat_buffer *pbuf);
> +	void (*get_hst_meas)(struct rkisp1_stats *stats,
> +			     struct rkisp1_stat_buffer *pbuf);
> +};
> +
> +struct rkisp1_stats_config {
> +	const int ae_mean_max;
> +	const int hist_bin_n_max;
> +};
> +
>  /*
>   * struct rkisp1_stats - ISP Statistics device
>   *
> @@ -252,6 +267,8 @@ struct rkisp1_capture {
>  struct rkisp1_stats {
>  	struct rkisp1_vdev_node vnode;
>  	struct rkisp1_device *rkisp1;
> +	struct rkisp1_stats_ops *ops;
> +	struct rkisp1_stats_config *config;
>  
>  	spinlock_t lock; /* locks the buffers list 'stats' */
>  	struct list_head stat;
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c
> index 3ddab8fa8f2d..7136292039f6 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c
> @@ -203,7 +203,7 @@ static void rkisp1_stats_get_aec_meas(struct rkisp1_stats *stats,
>  	unsigned int i;
>  
>  	pbuf->meas_type |= RKISP1_CIF_ISP_STAT_AUTOEXP;
> -	for (i = 0; i < RKISP1_CIF_ISP_AE_MEAN_MAX; i++)
> +	for (i = 0; i < stats->config->ae_mean_max; i++)
>  		pbuf->params.ae.exp_mean[i] =
>  			(u8)rkisp1_read(rkisp1,
>  					RKISP1_CIF_ISP_EXP_MEAN_00 + i * 4);
> @@ -233,7 +233,7 @@ static void rkisp1_stats_get_hst_meas(struct rkisp1_stats *stats,
>  	unsigned int i;
>  
>  	pbuf->meas_type |= RKISP1_CIF_ISP_STAT_HIST;
> -	for (i = 0; i < RKISP1_CIF_ISP_HIST_BIN_N_MAX; i++)
> +	for (i = 0; i < stats->config->hist_bin_n_max; i++)
>  		pbuf->params.hist.hist_bins[i] =
>  			(u8)rkisp1_read(rkisp1,
>  					RKISP1_CIF_ISP_HIST_BIN_0 + i * 4);
> @@ -286,6 +286,17 @@ static void rkisp1_stats_get_bls_meas(struct rkisp1_stats *stats,
>  	}
>  }
>  
> +static struct rkisp1_stats_ops rkisp1_stats_ops = {
> +	.get_awb_meas = rkisp1_stats_get_awb_meas,
> +	.get_aec_meas = rkisp1_stats_get_aec_meas,
> +	.get_hst_meas = rkisp1_stats_get_hst_meas,
> +};
> +
> +static struct rkisp1_stats_config rkisp1_stats_config = {
> +	.ae_mean_max = 25,
> +	.hist_bin_n_max = 16,
> +};
> +
>  static void
>  rkisp1_stats_send_measurement(struct rkisp1_stats *stats, u32 isp_ris)
>  {
> @@ -308,18 +319,18 @@ rkisp1_stats_send_measurement(struct rkisp1_stats *stats, u32 isp_ris)
>  		(struct rkisp1_stat_buffer *)(cur_buf->vaddr);
>  
>  	if (isp_ris & RKISP1_CIF_ISP_AWB_DONE)
> -		rkisp1_stats_get_awb_meas(stats, cur_stat_buf);
> +		stats->ops->get_awb_meas(stats, cur_stat_buf);
>  
>  	if (isp_ris & RKISP1_CIF_ISP_AFM_FIN)
>  		rkisp1_stats_get_afc_meas(stats, cur_stat_buf);
>  
>  	if (isp_ris & RKISP1_CIF_ISP_EXP_END) {
> -		rkisp1_stats_get_aec_meas(stats, cur_stat_buf);
> +		stats->ops->get_aec_meas(stats, cur_stat_buf);
>  		rkisp1_stats_get_bls_meas(stats, cur_stat_buf);
>  	}
>  
>  	if (isp_ris & RKISP1_CIF_ISP_HIST_MEASURE_RDY)
> -		rkisp1_stats_get_hst_meas(stats, cur_stat_buf);
> +		stats->ops->get_hst_meas(stats, cur_stat_buf);
>  
>  	vb2_set_plane_payload(&cur_buf->vb.vb2_buf, 0,
>  			      sizeof(struct rkisp1_stat_buffer));
> @@ -353,6 +364,9 @@ static void rkisp1_init_stats(struct rkisp1_stats *stats)
>  		V4L2_META_FMT_RK_ISP1_STAT_3A;
>  	stats->vdev_fmt.fmt.meta.buffersize =
>  		sizeof(struct rkisp1_stat_buffer);
> +
> +	stats->ops = &rkisp1_stats_ops;
> +	stats->config = &rkisp1_stats_config;
>  }
>  
>  int rkisp1_stats_register(struct rkisp1_device *rkisp1)
> 

Re: [PATCH RFC 10/11] media: rockchip: rkisp1: add support for v12 isp variants

[Helen Koike]

Hi Heiko,

On 1/8/21 4:33 PM, Heiko Stuebner wrote:
> From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> 
> The rkisp1 evolved over soc generations and the rk3326/px30 introduced
> the so called v12 - probably meaning v1.2.
> 
> Add the changed register definitions.
> 
> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> ---
>  .../platform/rockchip/rkisp1/rkisp1-common.h  |   1 +
>  .../platform/rockchip/rkisp1/rkisp1-isp.c     |  13 +
>  .../platform/rockchip/rkisp1/rkisp1-params.c  | 535 +++++++++++++++---
>  .../platform/rockchip/rkisp1/rkisp1-regs.h    | 404 ++++++++-----
>  .../platform/rockchip/rkisp1/rkisp1-stats.c   | 112 +++-
>  5 files changed, 824 insertions(+), 241 deletions(-)
> 
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
> index be0ae02165c9..9deb1ef1aa8b 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
> @@ -61,6 +61,7 @@
>  
>  enum rkisp1_isp_ver {
>  	RKISP1_V10 = 0,
> +	RKISP1_V12,
>  };
>  
>  /* enum for the resizer pads */
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
> index 84440aa71210..306cc96f8230 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
> @@ -408,6 +408,10 @@ static int rkisp1_config_mipi(struct rkisp1_device *rkisp1)
>  
>  	rkisp1_write(rkisp1, mipi_ctrl, RKISP1_CIF_MIPI_CTRL);
>  
> +	/* V12 could also use a newer csi2-host, but we don't want that yet */
> +	if (rkisp1->isp_ver == RKISP1_V12)
> +		rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_CSI0_CTRL0);
> +
>  	/* Configure Data Type and Virtual Channel */
>  	rkisp1_write(rkisp1,
>  		     RKISP1_CIF_MIPI_DATA_SEL_DT(sink_fmt->mipi_dt) |
> @@ -527,6 +531,15 @@ static void rkisp1_config_clk(struct rkisp1_device *rkisp1)
>  		  RKISP1_CIF_ICCL_DCROP_CLK;
>  
>  	rkisp1_write(rkisp1, val, RKISP1_CIF_ICCL);
> +
> +	/* ensure sp and mp can run at the same time in V12 */
> +	if (rkisp1->isp_ver == RKISP1_V12) {
> +		val = RKISP1_CIF_CLK_CTRL_MI_Y12 | RKISP1_CIF_CLK_CTRL_MI_SP |
> +		      RKISP1_CIF_CLK_CTRL_MI_RAW0 | RKISP1_CIF_CLK_CTRL_MI_RAW1 |
> +		      RKISP1_CIF_CLK_CTRL_MI_READ | RKISP1_CIF_CLK_CTRL_MI_RAWRD |
> +		      RKISP1_CIF_CLK_CTRL_CP | RKISP1_CIF_CLK_CTRL_IE;
> +		rkisp1_write(rkisp1, val, RKISP1_CIF_VI_ISP_CLK_CTRL_V12);
> +	}
>  }
>  
>  static void rkisp1_isp_start(struct rkisp1_device *rkisp1)
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
> index 008584caaad0..408fa33bdc30 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
> @@ -185,8 +185,8 @@ static void rkisp1_bls_config(struct rkisp1_params *params,
>  
>  /* ISP LS correction interface function */
>  static void
> -rkisp1_lsc_matrix_config(struct rkisp1_params *params,
> -			 const struct rkisp1_cif_isp_lsc_config *pconfig)
> +rkisp1_lsc_matrix_config_v10(struct rkisp1_params *params,
> +			     const struct rkisp1_cif_isp_lsc_config *pconfig)
>  {
>  	unsigned int isp_lsc_status, sram_addr, isp_lsc_table_sel, i, j, data;
>  
> @@ -212,39 +212,111 @@ rkisp1_lsc_matrix_config(struct rkisp1_params *params,
>  		 * DWORDs (2nd value of last DWORD unused)
>  		 */
>  		for (j = 0; j < RKISP1_CIF_ISP_LSC_SAMPLES_MAX - 1; j += 2) {
> -			data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->r_data_tbl[i][j],
> -							     pconfig->r_data_tbl[i][j + 1]);
> +			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->r_data_tbl[i][j],
> +								 pconfig->r_data_tbl[i][j + 1]);
>  			rkisp1_write(params->rkisp1, data,
>  				     RKISP1_CIF_ISP_LSC_R_TABLE_DATA);
>  
> -			data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->gr_data_tbl[i][j],
> -							     pconfig->gr_data_tbl[i][j + 1]);
> +			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->gr_data_tbl[i][j],
> +								 pconfig->gr_data_tbl[i][j + 1]);
>  			rkisp1_write(params->rkisp1, data,
>  				     RKISP1_CIF_ISP_LSC_GR_TABLE_DATA);
>  
> -			data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->gb_data_tbl[i][j],
> -							     pconfig->gb_data_tbl[i][j + 1]);
> +			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->gb_data_tbl[i][j],
> +								 pconfig->gb_data_tbl[i][j + 1]);
>  			rkisp1_write(params->rkisp1, data,
>  				     RKISP1_CIF_ISP_LSC_GB_TABLE_DATA);
>  
> -			data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->b_data_tbl[i][j],
> -							     pconfig->b_data_tbl[i][j + 1]);
> +			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->b_data_tbl[i][j],
> +								 pconfig->b_data_tbl[i][j + 1]);
>  			rkisp1_write(params->rkisp1, data,
>  				     RKISP1_CIF_ISP_LSC_B_TABLE_DATA);
>  		}
> -		data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->r_data_tbl[i][j], 0);
> +		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->r_data_tbl[i][j], 0);
>  		rkisp1_write(params->rkisp1, data,
>  			     RKISP1_CIF_ISP_LSC_R_TABLE_DATA);
>  
> -		data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->gr_data_tbl[i][j], 0);
> +		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->gr_data_tbl[i][j], 0);
>  		rkisp1_write(params->rkisp1, data,
>  			     RKISP1_CIF_ISP_LSC_GR_TABLE_DATA);
>  
> -		data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->gb_data_tbl[i][j], 0);
> +		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->gb_data_tbl[i][j], 0);
>  		rkisp1_write(params->rkisp1, data,
>  			     RKISP1_CIF_ISP_LSC_GB_TABLE_DATA);
>  
> -		data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->b_data_tbl[i][j], 0);
> +		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->b_data_tbl[i][j], 0);
> +		rkisp1_write(params->rkisp1, data,
> +			     RKISP1_CIF_ISP_LSC_B_TABLE_DATA);

I understand this patch shouldn't change v10 behaviour, shouldn't this write be in a
separate patch?

> +	}
> +	isp_lsc_table_sel = (isp_lsc_status & RKISP1_CIF_ISP_LSC_ACTIVE_TABLE) ?
> +			    RKISP1_CIF_ISP_LSC_TABLE_0 :
> +			    RKISP1_CIF_ISP_LSC_TABLE_1;
> +	rkisp1_write(params->rkisp1, isp_lsc_table_sel,
> +		     RKISP1_CIF_ISP_LSC_TABLE_SEL);

Same here.

> +}
> +
> +static void
> +rkisp1_lsc_matrix_config_v12(struct rkisp1_params *params,
> +			     const struct rkisp1_cif_isp_lsc_config *pconfig)
> +{
> +	unsigned int isp_lsc_status, sram_addr, isp_lsc_table_sel, i, j, data;
> +
> +	isp_lsc_status = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_LSC_STATUS);
> +
> +	/* RKISP1_CIF_ISP_LSC_TABLE_ADDRESS_153 = ( 17 * 18 ) >> 1 */
> +	sram_addr = (isp_lsc_status & RKISP1_CIF_ISP_LSC_ACTIVE_TABLE) ?
> +		     RKISP1_CIF_ISP_LSC_TABLE_ADDRESS_0 :
> +		     RKISP1_CIF_ISP_LSC_TABLE_ADDRESS_153;
> +	rkisp1_write(params->rkisp1, sram_addr, RKISP1_CIF_ISP_LSC_R_TABLE_ADDR);
> +	rkisp1_write(params->rkisp1, sram_addr, RKISP1_CIF_ISP_LSC_GR_TABLE_ADDR);
> +	rkisp1_write(params->rkisp1, sram_addr, RKISP1_CIF_ISP_LSC_GB_TABLE_ADDR);
> +	rkisp1_write(params->rkisp1, sram_addr, RKISP1_CIF_ISP_LSC_B_TABLE_ADDR);
> +
> +	/* program data tables (table size is 9 * 17 = 153) */
> +	for (i = 0; i < RKISP1_CIF_ISP_LSC_SAMPLES_MAX; i++) {
> +		/*
> +		 * 17 sectors with 2 values in one DWORD = 9
> +		 * DWORDs (2nd value of last DWORD unused)
> +		 */
> +		for (j = 0; j < RKISP1_CIF_ISP_LSC_SAMPLES_MAX - 1; j += 2) {
> +			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(
> +					pconfig->r_data_tbl[i][j],
> +					pconfig->r_data_tbl[i][j + 1]);
> +			rkisp1_write(params->rkisp1, data,
> +				     RKISP1_CIF_ISP_LSC_R_TABLE_DATA);
> +
> +			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(
> +					pconfig->gr_data_tbl[i][j],
> +					pconfig->gr_data_tbl[i][j + 1]);
> +			rkisp1_write(params->rkisp1, data,
> +				     RKISP1_CIF_ISP_LSC_GR_TABLE_DATA);
> +
> +			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(
> +					pconfig->gb_data_tbl[i][j],
> +					pconfig->gb_data_tbl[i][j + 1]);
> +			rkisp1_write(params->rkisp1, data,
> +				     RKISP1_CIF_ISP_LSC_GB_TABLE_DATA);
> +
> +			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(
> +					pconfig->b_data_tbl[i][j],
> +					pconfig->b_data_tbl[i][j + 1]);
> +			rkisp1_write(params->rkisp1, data,
> +				     RKISP1_CIF_ISP_LSC_B_TABLE_DATA);
> +		}
> +
> +		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(pconfig->r_data_tbl[i][j], 0);
> +		rkisp1_write(params->rkisp1, data,
> +			     RKISP1_CIF_ISP_LSC_R_TABLE_DATA);
> +
> +		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(pconfig->gr_data_tbl[i][j], 0);
> +		rkisp1_write(params->rkisp1, data,
> +			     RKISP1_CIF_ISP_LSC_GR_TABLE_DATA);
> +
> +		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(pconfig->gb_data_tbl[i][j], 0);
> +		rkisp1_write(params->rkisp1, data,
> +			     RKISP1_CIF_ISP_LSC_GB_TABLE_DATA);
> +
> +		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(pconfig->b_data_tbl[i][j], 0);
>  		rkisp1_write(params->rkisp1, data,
>  			     RKISP1_CIF_ISP_LSC_B_TABLE_DATA);
>  	}
> @@ -382,18 +454,37 @@ static void rkisp1_sdg_config(struct rkisp1_params *params,
>  }
>  
>  /* ISP GAMMA correction interface function */
> -static void rkisp1_goc_config(struct rkisp1_params *params,
> -			      const struct rkisp1_cif_isp_goc_config *arg)
> +static void rkisp1_goc_config_v10(struct rkisp1_params *params,
> +				  const struct rkisp1_cif_isp_goc_config *arg)
>  {
>  	unsigned int i;
>  
>  	rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_CTRL,
>  				RKISP1_CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA);
> -	rkisp1_write(params->rkisp1, arg->mode, RKISP1_CIF_ISP_GAMMA_OUT_MODE);
> +	rkisp1_write(params->rkisp1, arg->mode, RKISP1_CIF_ISP_GAMMA_OUT_MODE_V10);
>  
>  	for (i = 0; i < params->config->gamma_out_max_samples; i++)
>  		rkisp1_write(params->rkisp1, arg->gamma_y[i],
> -			     RKISP1_CIF_ISP_GAMMA_OUT_Y_0 + i * 4);
> +			     RKISP1_CIF_ISP_GAMMA_OUT_Y_0_V10 + i * 4);
> +}
> +
> +static void rkisp1_goc_config_v12(struct rkisp1_params *params,
> +				  const struct rkisp1_cif_isp_goc_config *arg)
> +{
> +	int i;

unsigned int

> +	u32 value;
> +
> +	rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_CTRL,
> +				RKISP1_CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA);
> +	rkisp1_write(params->rkisp1, arg->mode, RKISP1_CIF_ISP_GAMMA_OUT_MODE_V12);
> +
> +	for (i = 0; i < params->config->gamma_out_max_samples / 2; i++) {
> +		value = RKISP1_CIF_ISP_GAMMA_VALUE_V12(
> +			arg->gamma_y[2 * i + 1],
> +			arg->gamma_y[2 * i]);
> +		rkisp1_write(params->rkisp1, value,
> +			     RKISP1_CIF_ISP_GAMMA_OUT_Y_0_V12 + i * 4);
> +	}
>  }
>  
>  /* ISP Cross Talk */
> @@ -433,8 +524,8 @@ static void rkisp1_ctk_enable(struct rkisp1_params *params, bool en)
>  }
>  
>  /* ISP White Balance Mode */
> -static void rkisp1_awb_meas_config(struct rkisp1_params *params,
> -				   const struct rkisp1_cif_isp_awb_meas_config *arg)
> +static void rkisp1_awb_meas_config_v10(struct rkisp1_params *params,
> +				       const struct rkisp1_cif_isp_awb_meas_config *arg)
>  {
>  	u32 reg_val = 0;
>  	/* based on the mode,configure the awb module */
> @@ -442,43 +533,82 @@ static void rkisp1_awb_meas_config(struct rkisp1_params *params,
>  		/* Reference Cb and Cr */
>  		rkisp1_write(params->rkisp1,
>  			     RKISP1_CIF_ISP_AWB_REF_CR_SET(arg->awb_ref_cr) |
> -			     arg->awb_ref_cb, RKISP1_CIF_ISP_AWB_REF);
> +			     arg->awb_ref_cb, RKISP1_CIF_ISP_AWB_REF_V10);
>  		/* Yc Threshold */
>  		rkisp1_write(params->rkisp1,
>  			     RKISP1_CIF_ISP_AWB_MAX_Y_SET(arg->max_y) |
>  			     RKISP1_CIF_ISP_AWB_MIN_Y_SET(arg->min_y) |
>  			     RKISP1_CIF_ISP_AWB_MAX_CS_SET(arg->max_csum) |
> -			     arg->min_c, RKISP1_CIF_ISP_AWB_THRESH);
> +			     arg->min_c, RKISP1_CIF_ISP_AWB_THRESH_V10);
>  	}
>  
> -	reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP);
> +	reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP_V10);
>  	if (arg->enable_ymax_cmp)
>  		reg_val |= RKISP1_CIF_ISP_AWB_YMAX_CMP_EN;
>  	else
>  		reg_val &= ~RKISP1_CIF_ISP_AWB_YMAX_CMP_EN;
> -	rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP);
> +	rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP_V10);
>  
>  	/* window offset */
>  	rkisp1_write(params->rkisp1,
> -		     arg->awb_wnd.v_offs, RKISP1_CIF_ISP_AWB_WND_V_OFFS);
> +		     arg->awb_wnd.v_offs, RKISP1_CIF_ISP_AWB_WND_V_OFFS_V10);
>  	rkisp1_write(params->rkisp1,
> -		     arg->awb_wnd.h_offs, RKISP1_CIF_ISP_AWB_WND_H_OFFS);
> +		     arg->awb_wnd.h_offs, RKISP1_CIF_ISP_AWB_WND_H_OFFS_V10);
>  	/* AWB window size */
>  	rkisp1_write(params->rkisp1,
> -		     arg->awb_wnd.v_size, RKISP1_CIF_ISP_AWB_WND_V_SIZE);
> +		     arg->awb_wnd.v_size, RKISP1_CIF_ISP_AWB_WND_V_SIZE_V10);
>  	rkisp1_write(params->rkisp1,
> -		     arg->awb_wnd.h_size, RKISP1_CIF_ISP_AWB_WND_H_SIZE);
> +		     arg->awb_wnd.h_size, RKISP1_CIF_ISP_AWB_WND_H_SIZE_V10);
>  	/* Number of frames */
>  	rkisp1_write(params->rkisp1,
> -		     arg->frames, RKISP1_CIF_ISP_AWB_FRAMES);
> +		     arg->frames, RKISP1_CIF_ISP_AWB_FRAMES_V10);
> +}
> +
> +static void rkisp1_awb_meas_config_v12(struct rkisp1_params *params,
> +				       const struct rkisp1_cif_isp_awb_meas_config *arg)
> +{
> +	u32 reg_val = 0;> +	/* based on the mode,configure the awb module */
> +	if (arg->awb_mode == RKISP1_CIF_ISP_AWB_MODE_YCBCR) {
> +		/* Reference Cb and Cr */
> +		rkisp1_write(params->rkisp1,
> +			     RKISP1_CIF_ISP_AWB_REF_CR_SET(arg->awb_ref_cr) |
> +			     arg->awb_ref_cb, RKISP1_CIF_ISP_AWB_REF_V12);
> +		/* Yc Threshold */
> +		rkisp1_write(params->rkisp1,
> +			     RKISP1_CIF_ISP_AWB_MAX_Y_SET(arg->max_y) |
> +			     RKISP1_CIF_ISP_AWB_MIN_Y_SET(arg->min_y) |
> +			     RKISP1_CIF_ISP_AWB_MAX_CS_SET(arg->max_csum) |
> +			     arg->min_c, RKISP1_CIF_ISP_AWB_THRESH_V12);
> +	}
> +
> +	reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP_V12);
> +	if (arg->enable_ymax_cmp)
> +		reg_val |= RKISP1_CIF_ISP_AWB_YMAX_CMP_EN;
> +	else
> +		reg_val &= ~RKISP1_CIF_ISP_AWB_YMAX_CMP_EN;
> +	reg_val &= ~RKISP1_CIF_ISP_AWB_SET_FRAMES_MASK_V12;
> +	reg_val |= RKISP1_CIF_ISP_AWB_SET_FRAMES_V12(arg->frames);
> +	rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP_V12);
> +
> +	/* window offset */
> +	rkisp1_write(params->rkisp1,
> +		     arg->awb_wnd.v_offs << 16 |
> +		     arg->awb_wnd.h_offs,
> +		     RKISP1_CIF_ISP_AWB_OFFS_V12);
> +	/* AWB window size */
> +	rkisp1_write(params->rkisp1,
> +		     arg->awb_wnd.v_size << 16 |
> +		     arg->awb_wnd.h_size,
> +		     RKISP1_CIF_ISP_AWB_SIZE_V12);
>  }
>  
>  static void
> -rkisp1_awb_meas_enable(struct rkisp1_params *params,
> -		       const struct rkisp1_cif_isp_awb_meas_config *arg,
> -		       bool en)
> +rkisp1_awb_meas_enable_v10(struct rkisp1_params *params,
> +			   const struct rkisp1_cif_isp_awb_meas_config *arg,
> +			   bool en)
>  {
> -	u32 reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP);
> +	u32 reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP_V10);
>  
>  	/* switch off */
>  	reg_val &= RKISP1_CIF_ISP_AWB_MODE_MASK_NONE;
> @@ -489,34 +619,76 @@ rkisp1_awb_meas_enable(struct rkisp1_params *params,
>  		else
>  			reg_val |= RKISP1_CIF_ISP_AWB_MODE_YCBCR_EN;
>  
> -		rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP);
> +		rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP_V10);
>  
>  		/* Measurements require AWB block be active. */
>  		rkisp1_param_set_bits(params, RKISP1_CIF_ISP_CTRL,
>  				      RKISP1_CIF_ISP_CTRL_ISP_AWB_ENA);
>  	} else {
>  		rkisp1_write(params->rkisp1,
> -			     reg_val, RKISP1_CIF_ISP_AWB_PROP);
> +			     reg_val, RKISP1_CIF_ISP_AWB_PROP_V10);
>  		rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_CTRL,
>  					RKISP1_CIF_ISP_CTRL_ISP_AWB_ENA);
>  	}
>  }
>  
>  static void
> -rkisp1_awb_gain_config(struct rkisp1_params *params,
> -		       const struct rkisp1_cif_isp_awb_gain_config *arg)
> +rkisp1_awb_meas_enable_v12(struct rkisp1_params *params,
> +			   const struct rkisp1_cif_isp_awb_meas_config *arg,
> +			   bool en)
> +{
> +	u32 reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP_V12);
> +
> +	/* switch off */
> +	reg_val &= RKISP1_CIF_ISP_AWB_MODE_MASK_NONE;
> +
> +	if (en) {
> +		if (arg->awb_mode == RKISP1_CIF_ISP_AWB_MODE_RGB)
> +			reg_val |= RKISP1_CIF_ISP_AWB_MODE_RGB_EN;
> +		else
> +			reg_val |= RKISP1_CIF_ISP_AWB_MODE_YCBCR_EN;
> +
> +		rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP_V12);
> +
> +		/* Measurements require AWB block be active. */
> +		rkisp1_param_set_bits(params, RKISP1_CIF_ISP_CTRL,
> +				      RKISP1_CIF_ISP_CTRL_ISP_AWB_ENA);
> +	} else {
> +		rkisp1_write(params->rkisp1,
> +			     reg_val, RKISP1_CIF_ISP_AWB_PROP_V12);
> +		rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_CTRL,
> +					RKISP1_CIF_ISP_CTRL_ISP_AWB_ENA);
> +	}
> +}
> +
> +static void
> +rkisp1_awb_gain_config_v10(struct rkisp1_params *params,
> +			   const struct rkisp1_cif_isp_awb_gain_config *arg)
> +{
> +	rkisp1_write(params->rkisp1,
> +		     RKISP1_CIF_ISP_AWB_GAIN_R_SET(arg->gain_green_r) |
> +		     arg->gain_green_b, RKISP1_CIF_ISP_AWB_GAIN_G_V10);
> +
> +	rkisp1_write(params->rkisp1,
> +		     RKISP1_CIF_ISP_AWB_GAIN_R_SET(arg->gain_red) |
> +		     arg->gain_blue, RKISP1_CIF_ISP_AWB_GAIN_RB_V10);
> +}
> +
> +static void
> +rkisp1_awb_gain_config_v12(struct rkisp1_params *params,
> +			   const struct rkisp1_cif_isp_awb_gain_config *arg)
>  {
>  	rkisp1_write(params->rkisp1,
>  		     RKISP1_CIF_ISP_AWB_GAIN_R_SET(arg->gain_green_r) |
> -		     arg->gain_green_b, RKISP1_CIF_ISP_AWB_GAIN_G);
> +		     arg->gain_green_b, RKISP1_CIF_ISP_AWB_GAIN_G_V12);
>  
>  	rkisp1_write(params->rkisp1,
>  		     RKISP1_CIF_ISP_AWB_GAIN_R_SET(arg->gain_red) |
> -		     arg->gain_blue, RKISP1_CIF_ISP_AWB_GAIN_RB);
> +		     arg->gain_blue, RKISP1_CIF_ISP_AWB_GAIN_RB_V12);
>  }
>  
> -static void rkisp1_aec_config(struct rkisp1_params *params,
> -			      const struct rkisp1_cif_isp_aec_config *arg)
> +static void rkisp1_aec_config_v10(struct rkisp1_params *params,
> +				  const struct rkisp1_cif_isp_aec_config *arg)
>  {
>  	unsigned int block_hsize, block_vsize;
>  	u32 exp_ctrl;
> @@ -531,21 +703,55 @@ static void rkisp1_aec_config(struct rkisp1_params *params,
>  	rkisp1_write(params->rkisp1, exp_ctrl, RKISP1_CIF_ISP_EXP_CTRL);
>  
>  	rkisp1_write(params->rkisp1,
> -		     arg->meas_window.h_offs, RKISP1_CIF_ISP_EXP_H_OFFSET);
> +		     arg->meas_window.h_offs, RKISP1_CIF_ISP_EXP_H_OFFSET_V10);
>  	rkisp1_write(params->rkisp1,
> -		     arg->meas_window.v_offs, RKISP1_CIF_ISP_EXP_V_OFFSET);
> +		     arg->meas_window.v_offs, RKISP1_CIF_ISP_EXP_V_OFFSET_V10);
>  
>  	block_hsize = arg->meas_window.h_size /
> -		      RKISP1_CIF_ISP_EXP_COLUMN_NUM - 1;
> +		      RKISP1_CIF_ISP_EXP_COLUMN_NUM_V10 - 1;
>  	block_vsize = arg->meas_window.v_size /
> -		      RKISP1_CIF_ISP_EXP_ROW_NUM - 1;
> +		      RKISP1_CIF_ISP_EXP_ROW_NUM_V10 - 1;
> +
> +	rkisp1_write(params->rkisp1,
> +		     RKISP1_CIF_ISP_EXP_H_SIZE_SET_V10(block_hsize),
> +		     RKISP1_CIF_ISP_EXP_H_SIZE_V10);
> +	rkisp1_write(params->rkisp1,
> +		     RKISP1_CIF_ISP_EXP_V_SIZE_SET_V10(block_vsize),
> +		     RKISP1_CIF_ISP_EXP_V_SIZE_V10);
> +}
> +
> +static void rkisp1_aec_config_v12(struct rkisp1_params *params,
> +			       const struct rkisp1_cif_isp_aec_config *arg)
> +{
> +	u32 exp_ctrl;
> +	u32 block_hsize, block_vsize;
> +	u32 wnd_num_idx = 1;
> +	const u32 ae_wnd_num[] = {
> +		5, 9, 15, 15
> +	};

I think it would be better to declare in the same line.

> +
> +	/* avoid to override the old enable value */
> +	exp_ctrl = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_EXP_CTRL);
> +	exp_ctrl &= RKISP1_CIF_ISP_EXP_ENA;
> +	if (arg->autostop)
> +		exp_ctrl |= RKISP1_CIF_ISP_EXP_CTRL_AUTOSTOP;
> +	if (arg->mode == RKISP1_CIF_ISP_EXP_MEASURING_MODE_1)
> +		exp_ctrl |= RKISP1_CIF_ISP_EXP_CTRL_MEASMODE_1;
> +	exp_ctrl |= RKISP1_CIF_ISP_EXP_CTRL_WNDNUM_SET_V12(wnd_num_idx);
> +	rkisp1_write(params->rkisp1, exp_ctrl, RKISP1_CIF_ISP_EXP_CTRL);
>  
>  	rkisp1_write(params->rkisp1,
> -		     RKISP1_CIF_ISP_EXP_H_SIZE_SET(block_hsize),
> -		     RKISP1_CIF_ISP_EXP_H_SIZE);
> +		     RKISP1_CIF_ISP_EXP_V_OFFSET_SET_V12(arg->meas_window.v_offs) |
> +		     RKISP1_CIF_ISP_EXP_H_OFFSET_SET_V12(arg->meas_window.h_offs),
> +		     RKISP1_CIF_ISP_EXP_OFFS_V12);
> +
> +	block_hsize = arg->meas_window.h_size / ae_wnd_num[wnd_num_idx] - 1;
> +	block_vsize = arg->meas_window.v_size / ae_wnd_num[wnd_num_idx] - 1;
> +
>  	rkisp1_write(params->rkisp1,
> -		     RKISP1_CIF_ISP_EXP_V_SIZE_SET(block_vsize),
> -		     RKISP1_CIF_ISP_EXP_V_SIZE);
> +		     RKISP1_CIF_ISP_EXP_V_SIZE_SET_V12(block_vsize) |
> +		     RKISP1_CIF_ISP_EXP_H_SIZE_SET_V12(block_hsize),
> +		     RKISP1_CIF_ISP_EXP_SIZE_V12);
>  }
>  
>  static void rkisp1_cproc_config(struct rkisp1_params *params,
> @@ -578,72 +784,154 @@ static void rkisp1_cproc_config(struct rkisp1_params *params,
>  	}
>  }
>  
> -static void rkisp1_hst_config(struct rkisp1_params *params,
> -			      const struct rkisp1_cif_isp_hst_config *arg)
> +static void rkisp1_hst_config_v10(struct rkisp1_params *params,
> +				  const struct rkisp1_cif_isp_hst_config *arg)
>  {
>  	unsigned int block_hsize, block_vsize;
>  	static const u32 hist_weight_regs[] = {
> -		RKISP1_CIF_ISP_HIST_WEIGHT_00TO30,
> -		RKISP1_CIF_ISP_HIST_WEIGHT_40TO21,
> -		RKISP1_CIF_ISP_HIST_WEIGHT_31TO12,
> -		RKISP1_CIF_ISP_HIST_WEIGHT_22TO03,
> -		RKISP1_CIF_ISP_HIST_WEIGHT_13TO43,
> -		RKISP1_CIF_ISP_HIST_WEIGHT_04TO34,
> -		RKISP1_CIF_ISP_HIST_WEIGHT_44,
> +		RKISP1_CIF_ISP_HIST_WEIGHT_00TO30_V10,
> +		RKISP1_CIF_ISP_HIST_WEIGHT_40TO21_V10,
> +		RKISP1_CIF_ISP_HIST_WEIGHT_31TO12_V10,
> +		RKISP1_CIF_ISP_HIST_WEIGHT_22TO03_V10,
> +		RKISP1_CIF_ISP_HIST_WEIGHT_13TO43_V10,
> +		RKISP1_CIF_ISP_HIST_WEIGHT_04TO34_V10,
> +		RKISP1_CIF_ISP_HIST_WEIGHT_44_V10,
>  	};
>  	const u8 *weight;
>  	unsigned int i;
>  	u32 hist_prop;
>  
>  	/* avoid to override the old enable value */
> -	hist_prop = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_HIST_PROP);
> -	hist_prop &= RKISP1_CIF_ISP_HIST_PROP_MODE_MASK;
> -	hist_prop |= RKISP1_CIF_ISP_HIST_PREDIV_SET(arg->histogram_predivider);
> -	rkisp1_write(params->rkisp1, hist_prop, RKISP1_CIF_ISP_HIST_PROP);
> +	hist_prop = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_HIST_PROP_V10);
> +	hist_prop &= RKISP1_CIF_ISP_HIST_PROP_MODE_MASK_V10;
> +	hist_prop |= RKISP1_CIF_ISP_HIST_PREDIV_SET_V10(arg->histogram_predivider);
> +	rkisp1_write(params->rkisp1, hist_prop, RKISP1_CIF_ISP_HIST_PROP_V10);
>  	rkisp1_write(params->rkisp1,
>  		     arg->meas_window.h_offs,
> -		     RKISP1_CIF_ISP_HIST_H_OFFS);
> +		     RKISP1_CIF_ISP_HIST_H_OFFS_V10);
>  	rkisp1_write(params->rkisp1,
>  		     arg->meas_window.v_offs,
> -		     RKISP1_CIF_ISP_HIST_V_OFFS);
> +		     RKISP1_CIF_ISP_HIST_V_OFFS_V10);
>  
>  	block_hsize = arg->meas_window.h_size /
> -		      RKISP1_CIF_ISP_HIST_COLUMN_NUM - 1;
> -	block_vsize = arg->meas_window.v_size / RKISP1_CIF_ISP_HIST_ROW_NUM - 1;
> +		      RKISP1_CIF_ISP_HIST_COLUMN_NUM_V10 - 1;
> +	block_vsize = arg->meas_window.v_size / RKISP1_CIF_ISP_HIST_ROW_NUM_V10 - 1;
>  
> -	rkisp1_write(params->rkisp1, block_hsize, RKISP1_CIF_ISP_HIST_H_SIZE);
> -	rkisp1_write(params->rkisp1, block_vsize, RKISP1_CIF_ISP_HIST_V_SIZE);
> +	rkisp1_write(params->rkisp1, block_hsize, RKISP1_CIF_ISP_HIST_H_SIZE_V10);
> +	rkisp1_write(params->rkisp1, block_vsize, RKISP1_CIF_ISP_HIST_V_SIZE_V10);
>  
>  	weight = arg->hist_weight;
>  	for (i = 0; i < ARRAY_SIZE(hist_weight_regs); ++i, weight += 4)
>  		rkisp1_write(params->rkisp1,
> -			     RKISP1_CIF_ISP_HIST_WEIGHT_SET(weight[0],
> +			     RKISP1_CIF_ISP_HIST_WEIGHT_SET_V10(weight[0],
>  							    weight[1],
>  							    weight[2],
>  							    weight[3]),
>  				 hist_weight_regs[i]);
>  }
>  
> +static void rkisp1_hst_config_v12(struct rkisp1_params *params,
> +				  const struct rkisp1_cif_isp_hst_config *arg)
> +{
> +	u32 i, j;

unsigned int

> +	u32 value;
> +	u32 hist_ctrl;
> +	u32 block_hsize, block_vsize;
> +	u32 wnd_num_idx, hist_weight_num;

Maybe organize those in the same line.

> +	u8 weight15x15[RKISP1_CIF_ISP_HIST_WEIGHT_REG_SIZE_V12];
> +	const u32 hist_wnd_num[] = {
> +		5, 9, 15, 15
> +	};
> +
> +	/* now we just support 9x9 window */
> +	wnd_num_idx = 1;
> +	memset(weight15x15, 0x00, sizeof(weight15x15));
> +	/* avoid to override the old enable value */
> +	hist_ctrl = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_HIST_CTRL_V12);
> +	hist_ctrl &= RKISP1_CIF_ISP_HIST_CTRL_MODE_MASK_V12 |
> +		     RKISP1_CIF_ISP_HIST_CTRL_EN_MASK_V12;
> +	hist_ctrl = hist_ctrl |
> +		    RKISP1_CIF_ISP_HIST_CTRL_INTRSEL_SET_V12(1) |
> +		    RKISP1_CIF_ISP_HIST_CTRL_DATASEL_SET_V12(0) |
> +		    RKISP1_CIF_ISP_HIST_CTRL_WATERLINE_SET_V12(0) |
> +		    RKISP1_CIF_ISP_HIST_CTRL_AUTOSTOP_SET_V12(0) |
> +		    RKISP1_CIF_ISP_HIST_CTRL_WNDNUM_SET_V12(1) |
> +		    RKISP1_CIF_ISP_HIST_CTRL_STEPSIZE_SET_V12(arg->histogram_predivider);
> +	rkisp1_write(params->rkisp1, hist_ctrl, RKISP1_CIF_ISP_HIST_CTRL_V12);
> +
> +	rkisp1_write(params->rkisp1,
> +		     RKISP1_CIF_ISP_HIST_OFFS_SET_V12(arg->meas_window.h_offs,
> +						      arg->meas_window.v_offs),
> +		     RKISP1_CIF_ISP_HIST_OFFS_V12);
> +
> +	block_hsize = arg->meas_window.h_size / hist_wnd_num[wnd_num_idx] - 1;
> +	block_vsize = arg->meas_window.v_size / hist_wnd_num[wnd_num_idx] - 1;
> +	rkisp1_write(params->rkisp1,
> +		     RKISP1_CIF_ISP_HIST_SIZE_SET_V12(block_hsize, block_vsize),
> +		     RKISP1_CIF_ISP_HIST_SIZE_V12);
> +
> +	for (i = 0; i < hist_wnd_num[wnd_num_idx]; i++) {
> +		for (j = 0; j < hist_wnd_num[wnd_num_idx]; j++) {
> +			weight15x15[i * RKISP1_CIF_ISP_HIST_ROW_NUM_V12 + j] =
> +				arg->hist_weight[i * hist_wnd_num[wnd_num_idx] + j];
> +		}
> +	}
> +
> +	hist_weight_num = RKISP1_CIF_ISP_HIST_WEIGHT_REG_SIZE_V12;
> +	for (i = 0; i < (hist_weight_num / 4); i++) {
> +		value = RKISP1_CIF_ISP_HIST_WEIGHT_SET_V12(
> +				 weight15x15[4 * i + 0],
> +				 weight15x15[4 * i + 1],
> +				 weight15x15[4 * i + 2],
> +				 weight15x15[4 * i + 3]);
> +		rkisp1_write(params->rkisp1, value,
> +				 RKISP1_CIF_ISP_HIST_WEIGHT_V12 + 4 * i);
> +	}
> +	value = RKISP1_CIF_ISP_HIST_WEIGHT_SET_V12(weight15x15[4 * i + 0], 0, 0, 0);
> +	rkisp1_write(params->rkisp1, value,
> +				 RKISP1_CIF_ISP_HIST_WEIGHT_V12 + 4 * i);
> +}
> +
>  static void
> -rkisp1_hst_enable(struct rkisp1_params *params,
> -		  const struct rkisp1_cif_isp_hst_config *arg, bool en)
> +rkisp1_hst_enable_v10(struct rkisp1_params *params,
> +		      const struct rkisp1_cif_isp_hst_config *arg, bool en)
>  {
>  	if (en)	{
>  		u32 hist_prop = rkisp1_read(params->rkisp1,
> -					    RKISP1_CIF_ISP_HIST_PROP);
> +					    RKISP1_CIF_ISP_HIST_PROP_V10);
>  
> -		hist_prop &= ~RKISP1_CIF_ISP_HIST_PROP_MODE_MASK;
> +		hist_prop &= ~RKISP1_CIF_ISP_HIST_PROP_MODE_MASK_V10;
>  		hist_prop |= arg->mode;
> -		rkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_PROP,
> +		rkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_PROP_V10,
>  				      hist_prop);
>  	} else {
> -		rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_HIST_PROP,
> -					RKISP1_CIF_ISP_HIST_PROP_MODE_MASK);
> +		rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_HIST_PROP_V10,
> +					RKISP1_CIF_ISP_HIST_PROP_MODE_MASK_V10);
> +	}
> +}
> +
> +static void
> +rkisp1_hst_enable_v12(struct rkisp1_params *params,
> +		      const struct rkisp1_cif_isp_hst_config *arg, bool en)
> +{
> +	if (en) {
> +		u32 hist_ctrl = rkisp1_read(params->rkisp1,
> +					    RKISP1_CIF_ISP_HIST_CTRL_V12);
> +
> +		hist_ctrl &= ~RKISP1_CIF_ISP_HIST_CTRL_MODE_MASK_V12;
> +		hist_ctrl |= RKISP1_CIF_ISP_HIST_CTRL_MODE_SET_V12(arg->mode);
> +		hist_ctrl |= RKISP1_CIF_ISP_HIST_CTRL_EN_SET_V12(1);
> +		rkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_CTRL_V12,
> +				      hist_ctrl);
> +	} else {
> +		rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_HIST_CTRL_V12,
> +					RKISP1_CIF_ISP_HIST_CTRL_MODE_MASK_V12 |
> +					RKISP1_CIF_ISP_HIST_CTRL_EN_MASK_V12);
>  	}
>  }
>  
> -static void rkisp1_afm_config(struct rkisp1_params *params,
> -			      const struct rkisp1_cif_isp_afc_config *arg)
> +static void rkisp1_afm_config_v10(struct rkisp1_params *params,
> +				  const struct rkisp1_cif_isp_afc_config *arg)
>  {
>  	size_t num_of_win = min_t(size_t, ARRAY_SIZE(arg->afm_win),
>  				  arg->num_afm_win);
> @@ -673,6 +961,45 @@ static void rkisp1_afm_config(struct rkisp1_params *params,
>  	rkisp1_write(params->rkisp1, afm_ctrl, RKISP1_CIF_ISP_AFM_CTRL);
>  }
>  
> +static void rkisp1_afm_config_v12(struct rkisp1_params *params,
> +				  const struct rkisp1_cif_isp_afc_config *arg)
> +{
> +	size_t num_of_win = min_t(size_t, ARRAY_SIZE(arg->afm_win),
> +				  arg->num_afm_win);
> +	u32 afm_ctrl = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AFM_CTRL);
> +	u32 lum_var_shift, afm_var_shift;
> +	unsigned int i;
> +
> +	/* Switch off to configure. */
> +	rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_AFM_CTRL,
> +				RKISP1_CIF_ISP_AFM_ENA);
> +
> +	for (i = 0; i < num_of_win; i++) {
> +		rkisp1_write(params->rkisp1,
> +			     RKISP1_CIF_ISP_AFM_WINDOW_X(arg->afm_win[i].h_offs) |
> +			     RKISP1_CIF_ISP_AFM_WINDOW_Y(arg->afm_win[i].v_offs),
> +			     RKISP1_CIF_ISP_AFM_LT_A + i * 8);
> +		rkisp1_write(params->rkisp1,
> +			     RKISP1_CIF_ISP_AFM_WINDOW_X(arg->afm_win[i].h_size +
> +							 arg->afm_win[i].h_offs) |
> +			     RKISP1_CIF_ISP_AFM_WINDOW_Y(arg->afm_win[i].v_size +
> +							 arg->afm_win[i].v_offs),
> +			     RKISP1_CIF_ISP_AFM_RB_A + i * 8);
> +	}
> +	rkisp1_write(params->rkisp1, arg->thres, RKISP1_CIF_ISP_AFM_THRES);
> +
> +	lum_var_shift = RKISP1_CIF_ISP_AFM_GET_LUM_SHIFT_a_V12(arg->var_shift);
> +	afm_var_shift = RKISP1_CIF_ISP_AFM_GET_AFM_SHIFT_a_V12(arg->var_shift);
> +	rkisp1_write(params->rkisp1,
> +		     RKISP1_CIF_ISP_AFM_SET_SHIFT_a_V12(lum_var_shift, afm_var_shift) |
> +		     RKISP1_CIF_ISP_AFM_SET_SHIFT_b_V12(lum_var_shift, afm_var_shift) |
> +		     RKISP1_CIF_ISP_AFM_SET_SHIFT_c_V12(lum_var_shift, afm_var_shift),
> +		     RKISP1_CIF_ISP_AFM_VAR_SHIFT);
> +
> +	/* restore afm status */
> +	rkisp1_write(params->rkisp1, afm_ctrl, RKISP1_CIF_ISP_AFM_CTRL);
> +}
> +
>  static void rkisp1_ie_config(struct rkisp1_params *params,
>  			     const struct rkisp1_cif_isp_ie_config *arg)
>  {
> @@ -1286,8 +1613,8 @@ static void rkisp1_params_config_parameter(struct rkisp1_params *params)
>  
>  	memset(hst.hist_weight, 0x01, sizeof(hst.hist_weight));
>  	params->ops->hst_config(params, &hst);
> -	rkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_PROP,
> -			      ~RKISP1_CIF_ISP_HIST_PROP_MODE_MASK |
> +	rkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_PROP_V10,
> +			      ~RKISP1_CIF_ISP_HIST_PROP_MODE_MASK_V10 |
>  			      rkisp1_hst_params_default_config.mode);
>  
>  	/* set the  range */
> @@ -1346,22 +1673,38 @@ void rkisp1_params_disable(struct rkisp1_params *params)
>  				RKISP1_CIF_ISP_DPF_MODE_EN);
>  }
>  
> -static struct rkisp1_params_ops rkisp1_params_ops = {
> -	.lsc_matrix_config = rkisp1_lsc_matrix_config,
> -	.goc_config = rkisp1_goc_config,
> -	.awb_meas_config = rkisp1_awb_meas_config,
> -	.awb_meas_enable = rkisp1_awb_meas_enable,
> -	.awb_gain_config = rkisp1_awb_gain_config,
> -	.aec_config = rkisp1_aec_config,
> -	.hst_config = rkisp1_hst_config,
> -	.hst_enable = rkisp1_hst_enable,
> -	.afm_config = rkisp1_afm_config,
> +static struct rkisp1_params_ops rkisp1_v10_params_ops = {
> +	.lsc_matrix_config = rkisp1_lsc_matrix_config_v10,
> +	.goc_config = rkisp1_goc_config_v10,
> +	.awb_meas_config = rkisp1_awb_meas_config_v10,
> +	.awb_meas_enable = rkisp1_awb_meas_enable_v10,
> +	.awb_gain_config = rkisp1_awb_gain_config_v10,
> +	.aec_config = rkisp1_aec_config_v10,
> +	.hst_config = rkisp1_hst_config_v10,
> +	.hst_enable = rkisp1_hst_enable_v10,
> +	.afm_config = rkisp1_afm_config_v10,
>  };
>  
> -static struct rkisp1_params_config rkisp1_params_config = {
> +static struct rkisp1_params_config rkisp1_v10_params_config = {
>  	.gamma_out_max_samples = 17,
>  };
>  
> +static struct rkisp1_params_ops rkisp1_v12_params_ops = {
> +	.lsc_matrix_config = rkisp1_lsc_matrix_config_v12,
> +	.goc_config = rkisp1_goc_config_v12,
> +	.awb_meas_config = rkisp1_awb_meas_config_v12,
> +	.awb_meas_enable = rkisp1_awb_meas_enable_v12,
> +	.awb_gain_config = rkisp1_awb_gain_config_v12,
> +	.aec_config = rkisp1_aec_config_v12,
> +	.hst_config = rkisp1_hst_config_v12,
> +	.hst_enable = rkisp1_hst_enable_v12,
> +	.afm_config = rkisp1_afm_config_v12,
> +};
> +
> +static struct rkisp1_params_config rkisp1_v12_params_config = {
> +	.gamma_out_max_samples = 34,
> +};
> +
>  static int rkisp1_params_enum_fmt_meta_out(struct file *file, void *priv,
>  					   struct v4l2_fmtdesc *f)
>  {
> @@ -1528,8 +1871,14 @@ static void rkisp1_init_params(struct rkisp1_params *params)
>  		V4L2_META_FMT_RK_ISP1_PARAMS;
>  	params->vdev_fmt.fmt.meta.buffersize =
>  		sizeof(struct rkisp1_params_cfg);
> -	params->ops = &rkisp1_params_ops;
> -	params->config = &rkisp1_params_config;
> +
> +	if (params->rkisp1->isp_ver == RKISP1_V12) {
> +		params->ops = &rkisp1_v12_params_ops;
> +		params->config = &rkisp1_v12_params_config;
> +	} else {
> +		params->ops = &rkisp1_v10_params_ops;
> +		params->config = &rkisp1_v10_params_config;
> +	}
>  }
>  
>  int rkisp1_params_register(struct rkisp1_device *rkisp1)
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
> index 8a8d960a679c..388adee3beff 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
> @@ -212,6 +212,35 @@
>  
>  /* CCL */
>  #define RKISP1_CIF_CCL_CIF_CLK_DIS			BIT(2)
> +/* VI_ISP_CLK_CTRL */
> +#define RKISP1_CIF_CLK_CTRL_ISP_RAW			BIT(0)
> +#define RKISP1_CIF_CLK_CTRL_ISP_RGB			BIT(1)
> +#define RKISP1_CIF_CLK_CTRL_ISP_YUV			BIT(2)
> +#define RKISP1_CIF_CLK_CTRL_ISP_3A			BIT(3)
> +#define RKISP1_CIF_CLK_CTRL_MIPI_RAW			BIT(4)
> +#define RKISP1_CIF_CLK_CTRL_ISP_IE			BIT(5)
> +#define RKISP1_CIF_CLK_CTRL_RSZ_RAM			BIT(6)
> +#define RKISP1_CIF_CLK_CTRL_JPEG_RAM			BIT(7)
> +#define RKISP1_CIF_CLK_CTRL_ACLK_ISP			BIT(8)
> +#define RKISP1_CIF_CLK_CTRL_MI_IDC			BIT(9)
> +#define RKISP1_CIF_CLK_CTRL_MI_MP			BIT(10)
> +#define RKISP1_CIF_CLK_CTRL_MI_JPEG			BIT(11)
> +#define RKISP1_CIF_CLK_CTRL_MI_DP			BIT(12)
> +#define RKISP1_CIF_CLK_CTRL_MI_Y12			BIT(13)
> +#define RKISP1_CIF_CLK_CTRL_MI_SP			BIT(14)
> +#define RKISP1_CIF_CLK_CTRL_MI_RAW0			BIT(15)
> +#define RKISP1_CIF_CLK_CTRL_MI_RAW1			BIT(16)
> +#define RKISP1_CIF_CLK_CTRL_MI_READ			BIT(17)
> +#define RKISP1_CIF_CLK_CTRL_MI_RAWRD			BIT(18)
> +#define RKISP1_CIF_CLK_CTRL_CP				BIT(19)
> +#define RKISP1_CIF_CLK_CTRL_IE				BIT(20)
> +#define RKISP1_CIF_CLK_CTRL_SI				BIT(21)
> +#define RKISP1_CIF_CLK_CTRL_RSZM			BIT(22)
> +#define RKISP1_CIF_CLK_CTRL_DPMUX			BIT(23)
> +#define RKISP1_CIF_CLK_CTRL_JPEG			BIT(24)
> +#define RKISP1_CIF_CLK_CTRL_RSZS			BIT(25)
> +#define RKISP1_CIF_CLK_CTRL_MIPI			BIT(26)
> +#define RKISP1_CIF_CLK_CTRL_MARVINMI			BIT(27)
>  /* ICCL */
>  #define RKISP1_CIF_ICCL_ISP_CLK				BIT(0)
>  #define RKISP1_CIF_ICCL_CP_CLK				BIT(1)
> @@ -346,25 +375,57 @@
>  #define RKISP1_CIF_SUPER_IMP_CTRL_TRANSP_DIS		BIT(2)
>  
>  /* ISP HISTOGRAM CALCULATION : ISP_HIST_PROP */
> -#define RKISP1_CIF_ISP_HIST_PROP_MODE_DIS		(0 << 0)
> -#define RKISP1_CIF_ISP_HIST_PROP_MODE_RGB		BIT(0)
> -#define RKISP1_CIF_ISP_HIST_PROP_MODE_RED		(2 << 0)
> -#define RKISP1_CIF_ISP_HIST_PROP_MODE_GREEN		(3 << 0)
> -#define RKISP1_CIF_ISP_HIST_PROP_MODE_BLUE		(4 << 0)
> -#define RKISP1_CIF_ISP_HIST_PROP_MODE_LUM		(5 << 0)
> -#define RKISP1_CIF_ISP_HIST_PROP_MODE_MASK		0x7
> -#define RKISP1_CIF_ISP_HIST_PREDIV_SET(x)		(((x) & 0x7F) << 3)
> -#define RKISP1_CIF_ISP_HIST_WEIGHT_SET(v0, v1, v2, v3)	\
> +#define RKISP1_CIF_ISP_HIST_PROP_MODE_DIS_V10		(0 << 0)
> +#define RKISP1_CIF_ISP_HIST_PROP_MODE_RGB_V10		BIT(0)
> +#define RKISP1_CIF_ISP_HIST_PROP_MODE_RED_V10		(2 << 0)
> +#define RKISP1_CIF_ISP_HIST_PROP_MODE_GREEN_V10		(3 << 0)
> +#define RKISP1_CIF_ISP_HIST_PROP_MODE_BLUE_V10		(4 << 0)
> +#define RKISP1_CIF_ISP_HIST_PROP_MODE_LUM_V10		(5 << 0)
> +#define RKISP1_CIF_ISP_HIST_PROP_MODE_MASK_V10		0x7
> +#define RKISP1_CIF_ISP_HIST_PREDIV_SET_V10(x)		(((x) & 0x7F) << 3)
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_SET_V10(v0, v1, v2, v3)	\
>  				     (((v0) & 0x1F) | (((v1) & 0x1F) << 8)  |\
>  				     (((v2) & 0x1F) << 16) | \
>  				     (((v3) & 0x1F) << 24))
>  
> -#define RKISP1_CIF_ISP_HIST_WINDOW_OFFSET_RESERVED	0xFFFFF000
> -#define RKISP1_CIF_ISP_HIST_WINDOW_SIZE_RESERVED	0xFFFFF800
> -#define RKISP1_CIF_ISP_HIST_WEIGHT_RESERVED		0xE0E0E0E0
> -#define RKISP1_CIF_ISP_MAX_HIST_PREDIVIDER		0x0000007F
> -#define RKISP1_CIF_ISP_HIST_ROW_NUM			5
> -#define RKISP1_CIF_ISP_HIST_COLUMN_NUM			5
> +#define RKISP1_CIF_ISP_HIST_WINDOW_OFFSET_RESERVED_V10	0xFFFFF000
> +#define RKISP1_CIF_ISP_HIST_WINDOW_SIZE_RESERVED_V10	0xFFFFF800
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_RESERVED_V10		0xE0E0E0E0
> +#define RKISP1_CIF_ISP_MAX_HIST_PREDIVIDER_V10		0x0000007F
> +#define RKISP1_CIF_ISP_HIST_ROW_NUM_V10			5
> +#define RKISP1_CIF_ISP_HIST_COLUMN_NUM_V10		5
> +
> +/* ISP HISTOGRAM CALCULATION : CIF_ISP_HIST */
> +#define RKISP1_CIF_ISP_HIST_CTRL_EN_SET_V12(x)		(((x) & 0x01) << 0)
> +#define RKISP1_CIF_ISP_HIST_CTRL_EN_MASK_V12		RKISP1_CIF_ISP_HIST_CTRL_EN_SET_V12(0x01)
> +#define RKISP1_CIF_ISP_HIST_CTRL_STEPSIZE_SET_V12(x)	(((x) & 0x7F) << 1)
> +#define RKISP1_CIF_ISP_HIST_CTRL_MODE_SET_V12(x)	(((x) & 0x07) << 8)
> +#define RKISP1_CIF_ISP_HIST_CTRL_MODE_MASK_V12		RKISP1_CIF_ISP_HIST_CTRL_MODE_SET_V12(0x07)
> +#define RKISP1_CIF_ISP_HIST_CTRL_AUTOSTOP_SET_V12(x)	(((x) & 0x01) << 11)
> +#define RKISP1_CIF_ISP_HIST_CTRL_WATERLINE_SET_V12(x)	(((x) & 0xFFF) << 12)
> +#define RKISP1_CIF_ISP_HIST_CTRL_DATASEL_SET_V12(x)	(((x) & 0x07) << 24)
> +#define RKISP1_CIF_ISP_HIST_CTRL_INTRSEL_SET_V12(x)	(((x) & 0x01) << 27)
> +#define RKISP1_CIF_ISP_HIST_CTRL_WNDNUM_SET_V12(x)	(((x) & 0x03) << 28)
> +#define RKISP1_CIF_ISP_HIST_CTRL_DBGEN_SET_V12(x)	(((x) & 0x01) << 30)
> +#define RKISP1_CIF_ISP_HIST_ROW_NUM_V12		15
> +#define RKISP1_CIF_ISP_HIST_COLUMN_NUM_V12		15
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_REG_SIZE_V12	\
> +				(RKISP1_CIF_ISP_HIST_ROW_NUM_V12 * RKISP1_CIF_ISP_HIST_COLUMN_NUM_V12)
> +
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_SET_V12(v0, v1, v2, v3)	\
> +				(((v0) & 0x3F) | (((v1) & 0x3F) << 8) |\
> +				(((v2) & 0x3F) << 16) |\
> +				(((v3) & 0x3F) << 24))
> +
> +#define RKISP1_CIF_ISP_HIST_OFFS_SET_V12(v0, v1)	\
> +				(((v0) & 0x1FFF) | (((v1) & 0x1FFF) << 16))
> +#define RKISP1_CIF_ISP_HIST_SIZE_SET_V12(v0, v1)	\
> +				(((v0) & 0x7FF) | (((v1) & 0x7FF) << 16))
> +
> +#define RKISP1_CIF_ISP_HIST_GET_BIN0_V12(x)	\
> +				((x) & 0xFFFF)
> +#define RKISP1_CIF_ISP_HIST_GET_BIN1_V12(x)	\
> +				(((x) >> 16) & 0xFFFF)
>  
>  /* AUTO FOCUS MEASUREMENT:  ISP_AFM_CTRL */
>  #define RKISP1_ISP_AFM_CTRL_ENABLE			BIT(0)
> @@ -400,6 +461,8 @@
>  #define RKISP1_CIF_ISP_AWB_MODE_YCBCR_EN		((0 << 31) | (0x2 << 0))
>  #define RKISP1_CIF_ISP_AWB_MODE_MASK_NONE		0xFFFFFFFC
>  #define RKISP1_CIF_ISP_AWB_MODE_READ(x)			((x) & 3)
> +#define RKISP1_CIF_ISP_AWB_SET_FRAMES_V12(x)		(((x) & 0x07) << 28)
> +#define RKISP1_CIF_ISP_AWB_SET_FRAMES_MASK_V12		RKISP1_CIF_ISP_AWB_SET_FRAMES_V12(0x07)
>  /* ISP_AWB_GAIN_RB, ISP_AWB_GAIN_G  */
>  #define RKISP1_CIF_ISP_AWB_GAIN_R_SET(x)		(((x) & 0x3FF) << 16)
>  #define RKISP1_CIF_ISP_AWB_GAIN_R_READ(x)		(((x) >> 16) & 0x3FF)
> @@ -434,6 +497,7 @@
>  /* ISP_EXP_CTRL */
>  #define RKISP1_CIF_ISP_EXP_ENA				BIT(0)
>  #define RKISP1_CIF_ISP_EXP_CTRL_AUTOSTOP		BIT(1)
> +#define RKISP1_CIF_ISP_EXP_CTRL_WNDNUM_SET_V12(x)	(((x) & 0x03) << 2)
>  /*
>   *'1' luminance calculation according to  Y=(R+G+B) x 0.332 (85/256)
>   *'0' luminance calculation according to Y=16+0.25R+0.5G+0.1094B
> @@ -441,42 +505,76 @@
>  #define RKISP1_CIF_ISP_EXP_CTRL_MEASMODE_1		BIT(31)
>  
>  /* ISP_EXP_H_SIZE */
> -#define RKISP1_CIF_ISP_EXP_H_SIZE_SET(x)		((x) & 0x7FF)
> -#define RKISP1_CIF_ISP_EXP_HEIGHT_MASK			0x000007FF
> +#define RKISP1_CIF_ISP_EXP_H_SIZE_SET_V10(x)		((x) & 0x7FF)
> +#define RKISP1_CIF_ISP_EXP_HEIGHT_MASK_V10			0x000007FF
> +#define RKISP1_CIF_ISP_EXP_H_SIZE_SET_V12(x)		((x) & 0x7FF)
> +#define RKISP1_CIF_ISP_EXP_HEIGHT_MASK_V12		0x000007FF
>  /* ISP_EXP_V_SIZE : vertical size must be a multiple of 2). */
> -#define RKISP1_CIF_ISP_EXP_V_SIZE_SET(x)		((x) & 0x7FE)
> +#define RKISP1_CIF_ISP_EXP_V_SIZE_SET_V10(x)		((x) & 0x7FE)
> +#define RKISP1_CIF_ISP_EXP_V_SIZE_SET_V12(x)		(((x) & 0x7FE) << 16)
>  
>  /* ISP_EXP_H_OFFSET */
> -#define RKISP1_CIF_ISP_EXP_H_OFFSET_SET(x)		((x) & 0x1FFF)
> -#define RKISP1_CIF_ISP_EXP_MAX_HOFFS			2424
> +#define RKISP1_CIF_ISP_EXP_H_OFFSET_SET_V10(x)		((x) & 0x1FFF)
> +#define RKISP1_CIF_ISP_EXP_MAX_HOFFS_V10		2424
> +#define RKISP1_CIF_ISP_EXP_H_OFFSET_SET_V12(x)		((x) & 0x1FFF)
> +#define RKISP1_CIF_ISP_EXP_MAX_HOFFS_V12		0x1FFF
>  /* ISP_EXP_V_OFFSET */
> -#define RKISP1_CIF_ISP_EXP_V_OFFSET_SET(x)		((x) & 0x1FFF)
> -#define RKISP1_CIF_ISP_EXP_MAX_VOFFS			1806
> -
> -#define RKISP1_CIF_ISP_EXP_ROW_NUM			5
> -#define RKISP1_CIF_ISP_EXP_COLUMN_NUM			5
> -#define RKISP1_CIF_ISP_EXP_NUM_LUMA_REGS \
> -	(RKISP1_CIF_ISP_EXP_ROW_NUM * RKISP1_CIF_ISP_EXP_COLUMN_NUM)
> -#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE		516
> -#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE		35
> -#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE		390
> -#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE		28
> -#define RKISP1_CIF_ISP_EXP_MAX_HSIZE	\
> -	(RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE * RKISP1_CIF_ISP_EXP_COLUMN_NUM + 1)
> -#define RKISP1_CIF_ISP_EXP_MIN_HSIZE	\
> -	(RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE * RKISP1_CIF_ISP_EXP_COLUMN_NUM + 1)
> -#define RKISP1_CIF_ISP_EXP_MAX_VSIZE	\
> -	(RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE * RKISP1_CIF_ISP_EXP_ROW_NUM + 1)
> -#define RKISP1_CIF_ISP_EXP_MIN_VSIZE	\
> -	(RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE * RKISP1_CIF_ISP_EXP_ROW_NUM + 1)
> +#define RKISP1_CIF_ISP_EXP_V_OFFSET_SET_V10(x)		((x) & 0x1FFF)
> +#define RKISP1_CIF_ISP_EXP_MAX_VOFFS_V10		1806
> +#define RKISP1_CIF_ISP_EXP_V_OFFSET_SET_V12(x)		(((x) & 0x1FFF) << 16)
> +#define RKISP1_CIF_ISP_EXP_MAX_VOFFS_V12		0x1FFF
> +
> +#define RKISP1_CIF_ISP_EXP_ROW_NUM_V10			5
> +#define RKISP1_CIF_ISP_EXP_COLUMN_NUM_V10			5
> +#define RKISP1_CIF_ISP_EXP_NUM_LUMA_REGS_V10 \
> +	(RKISP1_CIF_ISP_EXP_ROW_NUM_V10 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V10)
> +#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE_V10		516
> +#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE_V10		35
> +#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE_V10		390
> +#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE_V10		28
> +#define RKISP1_CIF_ISP_EXP_MAX_HSIZE_V10	\
> +	(RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE_V10 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V10 + 1)
> +#define RKISP1_CIF_ISP_EXP_MIN_HSIZE_V10	\
> +	(RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE_V10 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V10 + 1)
> +#define RKISP1_CIF_ISP_EXP_MAX_VSIZE_V10	\
> +	(RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE_V10 * RKISP1_CIF_ISP_EXP_ROW_NUM_V10 + 1)
> +#define RKISP1_CIF_ISP_EXP_MIN_VSIZE_V10	\
> +	(RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE_V10 * RKISP1_CIF_ISP_EXP_ROW_NUM_V10 + 1)
> +
> +#define RKISP1_CIF_ISP_EXP_ROW_NUM_V12			15
> +#define RKISP1_CIF_ISP_EXP_COLUMN_NUM_V12		15
> +#define RKISP1_CIF_ISP_EXP_NUM_LUMA_REGS_V12 \
> +	(RKISP1_CIF_ISP_EXP_ROW_NUM_V12 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V12)
> +
> +#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE_V12		0x7FF
> +#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE_V12		0xE
> +#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE_V12		0x7FE
> +#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE_V12		0xE
> +#define RKISP1_CIF_ISP_EXP_MAX_HSIZE_V12	\
> +	(RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE_V12 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V12 + 1)
> +#define RKISP1_CIF_ISP_EXP_MIN_HSIZE_V12	\
> +	(RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE_V12 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V12 + 1)
> +#define RKISP1_CIF_ISP_EXP_MAX_VSIZE_V12	\
> +	(RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE_V12 * RKISP1_CIF_ISP_EXP_ROW_NUM_V12 + 1)
> +#define RKISP1_CIF_ISP_EXP_MIN_VSIZE_V12	\
> +	(RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE_V12 * RKISP1_CIF_ISP_EXP_ROW_NUM_V12 + 1)
> +
> +#define RKISP1_CIF_ISP_EXP_GET_MEAN_xy0_V12(x)		((x) & 0xFF)
> +#define RKISP1_CIF_ISP_EXP_GET_MEAN_xy1_V12(x)		(((x) >> 8) & 0xFF)
> +#define RKISP1_CIF_ISP_EXP_GET_MEAN_xy2_V12(x)		(((x) >> 16) & 0xFF)
> +#define RKISP1_CIF_ISP_EXP_GET_MEAN_xy3_V12(x)		(((x) >> 24) & 0xFF)
>  
>  /* LSC: ISP_LSC_CTRL */
>  #define RKISP1_CIF_ISP_LSC_CTRL_ENA			BIT(0)
>  #define RKISP1_CIF_ISP_LSC_SECT_SIZE_RESERVED		0xFC00FC00
> -#define RKISP1_CIF_ISP_LSC_GRAD_RESERVED		0xF000F000
> -#define RKISP1_CIF_ISP_LSC_SAMPLE_RESERVED		0xF000F000
> -#define RKISP1_CIF_ISP_LSC_TABLE_DATA(v0, v1)     \
> +#define RKISP1_CIF_ISP_LSC_GRAD_RESERVED_V10		0xF000F000
> +#define RKISP1_CIF_ISP_LSC_SAMPLE_RESERVED_V10		0xF000F000
> +#define RKISP1_CIF_ISP_LSC_GRAD_RESERVED_V12		0xE000E000
> +#define RKISP1_CIF_ISP_LSC_SAMPLE_RESERVED_V12		0xE000E000
> +#define RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(v0, v1)     \
>  	(((v0) & 0xFFF) | (((v1) & 0xFFF) << 12))
> +#define RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(v0, v1)     \
> +	(((v0) & 0x1FFF) | (((v1) & 0x1FFF) << 13))
>  #define RKISP1_CIF_ISP_LSC_SECT_SIZE(v0, v1)      \
>  	(((v0) & 0xFFF) | (((v1) & 0xFFF) << 16))
>  #define RKISP1_CIF_ISP_LSC_GRAD_SIZE(v0, v1)      \
> @@ -549,6 +647,10 @@
>  	(1 << 15) | (1 << 11) | (1 << 7) | (1 << 3))
>  #define RKISP1_CIFISP_DEGAMMA_Y_RESERVED		0xFFFFF000
>  
> +/* GAMMA-OUT */
> +#define RKISP1_CIF_ISP_GAMMA_VALUE_V12(x, y)	\
> +	(((x) & 0xFFF) << 16 | ((y) & 0xFFF) << 0)
> +
>  /* AFM */
>  #define RKISP1_CIF_ISP_AFM_ENA				BIT(0)
>  #define RKISP1_CIF_ISP_AFM_THRES_RESERVED		0xFFFF0000
> @@ -559,6 +661,11 @@
>  #define RKISP1_CIF_ISP_AFM_WINDOW_Y_MIN			0x2
>  #define RKISP1_CIF_ISP_AFM_WINDOW_X(x)			(((x) & 0x1FFF) << 16)
>  #define RKISP1_CIF_ISP_AFM_WINDOW_Y(x)			((x) & 0x1FFF)
> +#define RKISP1_CIF_ISP_AFM_SET_SHIFT_a_V12(x, y)	(((x) & 0x7) << 16 | ((y) & 0x7) << 0)
> +#define RKISP1_CIF_ISP_AFM_SET_SHIFT_b_V12(x, y)	(((x) & 0x7) << 20 | ((y) & 0x7) << 4)
> +#define RKISP1_CIF_ISP_AFM_SET_SHIFT_c_V12(x, y)	(((x) & 0x7) << 24 | ((y) & 0x7) << 8)
> +#define RKISP1_CIF_ISP_AFM_GET_LUM_SHIFT_a_V12(x)	(((x) & 0x70000) >> 16)
> +#define RKISP1_CIF_ISP_AFM_GET_AFM_SHIFT_a_V12(x)	((x) & 0x7)
>  
>  /* DPF */
>  #define RKISP1_CIF_ISP_DPF_MODE_EN			BIT(0)
> @@ -581,6 +688,7 @@
>  #define RKISP1_CIF_CTRL_BASE			0x00000000
>  #define RKISP1_CIF_CCL				(RKISP1_CIF_CTRL_BASE + 0x00000000)
>  #define RKISP1_CIF_VI_ID			(RKISP1_CIF_CTRL_BASE + 0x00000008)
> +#define RKISP1_CIF_VI_ISP_CLK_CTRL_V12		(RKISP1_CIF_CTRL_BASE + 0x0000000C)
>  #define RKISP1_CIF_ICCL				(RKISP1_CIF_CTRL_BASE + 0x00000010)
>  #define RKISP1_CIF_IRCL				(RKISP1_CIF_CTRL_BASE + 0x00000014)
>  #define RKISP1_CIF_VI_DPCL			(RKISP1_CIF_CTRL_BASE + 0x00000018)
> @@ -666,18 +774,35 @@
>  #define RKISP1_CIF_ISP_GAMMA_B_Y14		(RKISP1_CIF_ISP_BASE + 0x000000E4)
>  #define RKISP1_CIF_ISP_GAMMA_B_Y15		(RKISP1_CIF_ISP_BASE + 0x000000E8)
>  #define RKISP1_CIF_ISP_GAMMA_B_Y16		(RKISP1_CIF_ISP_BASE + 0x000000EC)
> -#define RKISP1_CIF_ISP_AWB_PROP			(RKISP1_CIF_ISP_BASE + 0x00000110)
> -#define RKISP1_CIF_ISP_AWB_WND_H_OFFS		(RKISP1_CIF_ISP_BASE + 0x00000114)
> -#define RKISP1_CIF_ISP_AWB_WND_V_OFFS		(RKISP1_CIF_ISP_BASE + 0x00000118)
> -#define RKISP1_CIF_ISP_AWB_WND_H_SIZE		(RKISP1_CIF_ISP_BASE + 0x0000011C)
> -#define RKISP1_CIF_ISP_AWB_WND_V_SIZE		(RKISP1_CIF_ISP_BASE + 0x00000120)
> -#define RKISP1_CIF_ISP_AWB_FRAMES		(RKISP1_CIF_ISP_BASE + 0x00000124)
> -#define RKISP1_CIF_ISP_AWB_REF			(RKISP1_CIF_ISP_BASE + 0x00000128)
> -#define RKISP1_CIF_ISP_AWB_THRESH		(RKISP1_CIF_ISP_BASE + 0x0000012C)
> -#define RKISP1_CIF_ISP_AWB_GAIN_G		(RKISP1_CIF_ISP_BASE + 0x00000138)
> -#define RKISP1_CIF_ISP_AWB_GAIN_RB		(RKISP1_CIF_ISP_BASE + 0x0000013C)
> -#define RKISP1_CIF_ISP_AWB_WHITE_CNT		(RKISP1_CIF_ISP_BASE + 0x00000140)
> -#define RKISP1_CIF_ISP_AWB_MEAN			(RKISP1_CIF_ISP_BASE + 0x00000144)
> +#define RKISP1_CIF_ISP_AWB_PROP_V10		(RKISP1_CIF_ISP_BASE + 0x00000110)
> +#define RKISP1_CIF_ISP_AWB_WND_H_OFFS_V10	(RKISP1_CIF_ISP_BASE + 0x00000114)
> +#define RKISP1_CIF_ISP_AWB_WND_V_OFFS_V10	(RKISP1_CIF_ISP_BASE + 0x00000118)
> +#define RKISP1_CIF_ISP_AWB_WND_H_SIZE_V10	(RKISP1_CIF_ISP_BASE + 0x0000011C)
> +#define RKISP1_CIF_ISP_AWB_WND_V_SIZE_V10	(RKISP1_CIF_ISP_BASE + 0x00000120)
> +#define RKISP1_CIF_ISP_AWB_FRAMES_V10		(RKISP1_CIF_ISP_BASE + 0x00000124)
> +#define RKISP1_CIF_ISP_AWB_REF_V10		(RKISP1_CIF_ISP_BASE + 0x00000128)
> +#define RKISP1_CIF_ISP_AWB_THRESH_V10		(RKISP1_CIF_ISP_BASE + 0x0000012C)
> +#define RKISP1_CIF_ISP_AWB_GAIN_G_V10		(RKISP1_CIF_ISP_BASE + 0x00000138)
> +#define RKISP1_CIF_ISP_AWB_GAIN_RB_V10		(RKISP1_CIF_ISP_BASE + 0x0000013C)
> +#define RKISP1_CIF_ISP_AWB_WHITE_CNT_V10	(RKISP1_CIF_ISP_BASE + 0x00000140)
> +#define RKISP1_CIF_ISP_AWB_MEAN_V10		(RKISP1_CIF_ISP_BASE + 0x00000144)
> +#define RKISP1_CIF_ISP_AWB_PROP_V12		(RKISP1_CIF_ISP_BASE + 0x00000110)
> +#define RKISP1_CIF_ISP_AWB_SIZE_V12		(RKISP1_CIF_ISP_BASE + 0x00000114)
> +#define RKISP1_CIF_ISP_AWB_OFFS_V12		(RKISP1_CIF_ISP_BASE + 0x00000118)
> +#define RKISP1_CIF_ISP_AWB_REF_V12		(RKISP1_CIF_ISP_BASE + 0x0000011C)
> +#define RKISP1_CIF_ISP_AWB_THRESH_V12		(RKISP1_CIF_ISP_BASE + 0x00000120)
> +#define RKISP1_CIF_ISP_X_COOR12_V12		(RKISP1_CIF_ISP_BASE + 0x00000124)
> +#define RKISP1_CIF_ISP_X_COOR34_V12		(RKISP1_CIF_ISP_BASE + 0x00000128)
> +#define RKISP1_CIF_ISP_AWB_WHITE_CNT_V12	(RKISP1_CIF_ISP_BASE + 0x0000012C)
> +#define RKISP1_CIF_ISP_AWB_MEAN_V12		(RKISP1_CIF_ISP_BASE + 0x00000130)
> +#define RKISP1_CIF_ISP_DEGAIN_V12		(RKISP1_CIF_ISP_BASE + 0x00000134)
> +#define RKISP1_CIF_ISP_AWB_GAIN_G_V12		(RKISP1_CIF_ISP_BASE + 0x00000138)
> +#define RKISP1_CIF_ISP_AWB_GAIN_RB_V12		(RKISP1_CIF_ISP_BASE + 0x0000013C)
> +#define RKISP1_CIF_ISP_REGION_LINE_V12		(RKISP1_CIF_ISP_BASE + 0x00000140)
> +#define RKISP1_CIF_ISP_WP_CNT_REGION0_V12	(RKISP1_CIF_ISP_BASE + 0x00000160)
> +#define RKISP1_CIF_ISP_WP_CNT_REGION1_V12	(RKISP1_CIF_ISP_BASE + 0x00000164)
> +#define RKISP1_CIF_ISP_WP_CNT_REGION2_V12	(RKISP1_CIF_ISP_BASE + 0x00000168)
> +#define RKISP1_CIF_ISP_WP_CNT_REGION3_V12	(RKISP1_CIF_ISP_BASE + 0x0000016C)
>  #define RKISP1_CIF_ISP_CC_COEFF_0		(RKISP1_CIF_ISP_BASE + 0x00000170)
>  #define RKISP1_CIF_ISP_CC_COEFF_1		(RKISP1_CIF_ISP_BASE + 0x00000174)
>  #define RKISP1_CIF_ISP_CC_COEFF_2		(RKISP1_CIF_ISP_BASE + 0x00000178)
> @@ -711,30 +836,32 @@
>  #define RKISP1_CIF_ISP_CT_COEFF_6		(RKISP1_CIF_ISP_BASE + 0x000001E8)
>  #define RKISP1_CIF_ISP_CT_COEFF_7		(RKISP1_CIF_ISP_BASE + 0x000001EC)
>  #define RKISP1_CIF_ISP_CT_COEFF_8		(RKISP1_CIF_ISP_BASE + 0x000001F0)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_MODE		(RKISP1_CIF_ISP_BASE + 0x000001F4)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_0		(RKISP1_CIF_ISP_BASE + 0x000001F8)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_1		(RKISP1_CIF_ISP_BASE + 0x000001FC)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_2		(RKISP1_CIF_ISP_BASE + 0x00000200)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_3		(RKISP1_CIF_ISP_BASE + 0x00000204)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_4		(RKISP1_CIF_ISP_BASE + 0x00000208)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_5		(RKISP1_CIF_ISP_BASE + 0x0000020C)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_6		(RKISP1_CIF_ISP_BASE + 0x00000210)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_7		(RKISP1_CIF_ISP_BASE + 0x00000214)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_8		(RKISP1_CIF_ISP_BASE + 0x00000218)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_9		(RKISP1_CIF_ISP_BASE + 0x0000021C)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_10		(RKISP1_CIF_ISP_BASE + 0x00000220)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_11		(RKISP1_CIF_ISP_BASE + 0x00000224)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_12		(RKISP1_CIF_ISP_BASE + 0x00000228)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_13		(RKISP1_CIF_ISP_BASE + 0x0000022C)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_14		(RKISP1_CIF_ISP_BASE + 0x00000230)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_15		(RKISP1_CIF_ISP_BASE + 0x00000234)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_16		(RKISP1_CIF_ISP_BASE + 0x00000238)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_MODE_V10	(RKISP1_CIF_ISP_BASE + 0x000001F4)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_0_V10	(RKISP1_CIF_ISP_BASE + 0x000001F8)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_1_V10	(RKISP1_CIF_ISP_BASE + 0x000001FC)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_2_V10	(RKISP1_CIF_ISP_BASE + 0x00000200)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_3_V10	(RKISP1_CIF_ISP_BASE + 0x00000204)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_4_V10	(RKISP1_CIF_ISP_BASE + 0x00000208)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_5_V10	(RKISP1_CIF_ISP_BASE + 0x0000020C)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_6_V10	(RKISP1_CIF_ISP_BASE + 0x00000210)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_7_V10	(RKISP1_CIF_ISP_BASE + 0x00000214)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_8_V10	(RKISP1_CIF_ISP_BASE + 0x00000218)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_9_V10	(RKISP1_CIF_ISP_BASE + 0x0000021C)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_10_V10	(RKISP1_CIF_ISP_BASE + 0x00000220)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_11_V10	(RKISP1_CIF_ISP_BASE + 0x00000224)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_12_V10	(RKISP1_CIF_ISP_BASE + 0x00000228)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_13_V10	(RKISP1_CIF_ISP_BASE + 0x0000022C)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_14_V10	(RKISP1_CIF_ISP_BASE + 0x00000230)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_15_V10	(RKISP1_CIF_ISP_BASE + 0x00000234)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_16_V10	(RKISP1_CIF_ISP_BASE + 0x00000238)
>  #define RKISP1_CIF_ISP_ERR			(RKISP1_CIF_ISP_BASE + 0x0000023C)
>  #define RKISP1_CIF_ISP_ERR_CLR			(RKISP1_CIF_ISP_BASE + 0x00000240)
>  #define RKISP1_CIF_ISP_FRAME_COUNT		(RKISP1_CIF_ISP_BASE + 0x00000244)
>  #define RKISP1_CIF_ISP_CT_OFFSET_R		(RKISP1_CIF_ISP_BASE + 0x00000248)
>  #define RKISP1_CIF_ISP_CT_OFFSET_G		(RKISP1_CIF_ISP_BASE + 0x0000024C)
>  #define RKISP1_CIF_ISP_CT_OFFSET_B		(RKISP1_CIF_ISP_BASE + 0x00000250)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_MODE_V12	(RKISP1_CIF_ISP_BASE + 0x00000300)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_0_V12	(RKISP1_CIF_ISP_BASE + 0x00000304)
>  
>  #define RKISP1_CIF_ISP_FLASH_BASE		0x00000660
>  #define RKISP1_CIF_ISP_FLASH_CMD		(RKISP1_CIF_ISP_FLASH_BASE + 0x00000000)
> @@ -1004,36 +1131,35 @@
>  #define RKISP1_CIF_ISP_IS_H_SIZE_SHD		(RKISP1_CIF_ISP_IS_BASE + 0x0000002C)
>  #define RKISP1_CIF_ISP_IS_V_SIZE_SHD		(RKISP1_CIF_ISP_IS_BASE + 0x00000030)
>  
> -#define RKISP1_CIF_ISP_HIST_BASE		0x00002400
> -
> -#define RKISP1_CIF_ISP_HIST_PROP		(RKISP1_CIF_ISP_HIST_BASE + 0x00000000)
> -#define RKISP1_CIF_ISP_HIST_H_OFFS		(RKISP1_CIF_ISP_HIST_BASE + 0x00000004)
> -#define RKISP1_CIF_ISP_HIST_V_OFFS		(RKISP1_CIF_ISP_HIST_BASE + 0x00000008)
> -#define RKISP1_CIF_ISP_HIST_H_SIZE		(RKISP1_CIF_ISP_HIST_BASE + 0x0000000C)
> -#define RKISP1_CIF_ISP_HIST_V_SIZE		(RKISP1_CIF_ISP_HIST_BASE + 0x00000010)
> -#define RKISP1_CIF_ISP_HIST_BIN_0		(RKISP1_CIF_ISP_HIST_BASE + 0x00000014)
> -#define RKISP1_CIF_ISP_HIST_BIN_1		(RKISP1_CIF_ISP_HIST_BASE + 0x00000018)
> -#define RKISP1_CIF_ISP_HIST_BIN_2		(RKISP1_CIF_ISP_HIST_BASE + 0x0000001C)
> -#define RKISP1_CIF_ISP_HIST_BIN_3		(RKISP1_CIF_ISP_HIST_BASE + 0x00000020)
> -#define RKISP1_CIF_ISP_HIST_BIN_4		(RKISP1_CIF_ISP_HIST_BASE + 0x00000024)
> -#define RKISP1_CIF_ISP_HIST_BIN_5		(RKISP1_CIF_ISP_HIST_BASE + 0x00000028)
> -#define RKISP1_CIF_ISP_HIST_BIN_6		(RKISP1_CIF_ISP_HIST_BASE + 0x0000002C)
> -#define RKISP1_CIF_ISP_HIST_BIN_7		(RKISP1_CIF_ISP_HIST_BASE + 0x00000030)
> -#define RKISP1_CIF_ISP_HIST_BIN_8		(RKISP1_CIF_ISP_HIST_BASE + 0x00000034)
> -#define RKISP1_CIF_ISP_HIST_BIN_9		(RKISP1_CIF_ISP_HIST_BASE + 0x00000038)
> -#define RKISP1_CIF_ISP_HIST_BIN_10		(RKISP1_CIF_ISP_HIST_BASE + 0x0000003C)
> -#define RKISP1_CIF_ISP_HIST_BIN_11		(RKISP1_CIF_ISP_HIST_BASE + 0x00000040)
> -#define RKISP1_CIF_ISP_HIST_BIN_12		(RKISP1_CIF_ISP_HIST_BASE + 0x00000044)
> -#define RKISP1_CIF_ISP_HIST_BIN_13		(RKISP1_CIF_ISP_HIST_BASE + 0x00000048)
> -#define RKISP1_CIF_ISP_HIST_BIN_14		(RKISP1_CIF_ISP_HIST_BASE + 0x0000004C)
> -#define RKISP1_CIF_ISP_HIST_BIN_15		(RKISP1_CIF_ISP_HIST_BASE + 0x00000050)
> -#define RKISP1_CIF_ISP_HIST_WEIGHT_00TO30	(RKISP1_CIF_ISP_HIST_BASE + 0x00000054)
> -#define RKISP1_CIF_ISP_HIST_WEIGHT_40TO21	(RKISP1_CIF_ISP_HIST_BASE + 0x00000058)
> -#define RKISP1_CIF_ISP_HIST_WEIGHT_31TO12	(RKISP1_CIF_ISP_HIST_BASE + 0x0000005C)
> -#define RKISP1_CIF_ISP_HIST_WEIGHT_22TO03	(RKISP1_CIF_ISP_HIST_BASE + 0x00000060)
> -#define RKISP1_CIF_ISP_HIST_WEIGHT_13TO43	(RKISP1_CIF_ISP_HIST_BASE + 0x00000064)
> -#define RKISP1_CIF_ISP_HIST_WEIGHT_04TO34	(RKISP1_CIF_ISP_HIST_BASE + 0x00000068)
> -#define RKISP1_CIF_ISP_HIST_WEIGHT_44		(RKISP1_CIF_ISP_HIST_BASE + 0x0000006C)
> +#define RKISP1_CIF_ISP_HIST_BASE_V10		0x00002400
> +#define RKISP1_CIF_ISP_HIST_PROP_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000000)
> +#define RKISP1_CIF_ISP_HIST_H_OFFS_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000004)
> +#define RKISP1_CIF_ISP_HIST_V_OFFS_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000008)
> +#define RKISP1_CIF_ISP_HIST_H_SIZE_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000000C)
> +#define RKISP1_CIF_ISP_HIST_V_SIZE_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000010)
> +#define RKISP1_CIF_ISP_HIST_BIN_0_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000014)
> +#define RKISP1_CIF_ISP_HIST_BIN_1_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000018)
> +#define RKISP1_CIF_ISP_HIST_BIN_2_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000001C)
> +#define RKISP1_CIF_ISP_HIST_BIN_3_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000020)
> +#define RKISP1_CIF_ISP_HIST_BIN_4_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000024)
> +#define RKISP1_CIF_ISP_HIST_BIN_5_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000028)
> +#define RKISP1_CIF_ISP_HIST_BIN_6_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000002C)
> +#define RKISP1_CIF_ISP_HIST_BIN_7_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000030)
> +#define RKISP1_CIF_ISP_HIST_BIN_8_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000034)
> +#define RKISP1_CIF_ISP_HIST_BIN_9_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000038)
> +#define RKISP1_CIF_ISP_HIST_BIN_10_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000003C)
> +#define RKISP1_CIF_ISP_HIST_BIN_11_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000040)
> +#define RKISP1_CIF_ISP_HIST_BIN_12_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000044)
> +#define RKISP1_CIF_ISP_HIST_BIN_13_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000048)
> +#define RKISP1_CIF_ISP_HIST_BIN_14_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000004C)
> +#define RKISP1_CIF_ISP_HIST_BIN_15_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000050)
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_00TO30_V10	(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000054)
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_40TO21_V10	(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000058)
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_31TO12_V10	(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000005C)
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_22TO03_V10	(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000060)
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_13TO43_V10	(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000064)
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_04TO34_V10	(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000068)
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_44_V10	(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000006C)
>  
>  #define RKISP1_CIF_ISP_FILT_BASE		0x00002500
>  #define RKISP1_CIF_ISP_FILT_MODE		(RKISP1_CIF_ISP_FILT_BASE + 0x00000000)
> @@ -1059,35 +1185,38 @@
>  
>  #define RKISP1_CIF_ISP_EXP_BASE			0x00002600
>  #define RKISP1_CIF_ISP_EXP_CTRL			(RKISP1_CIF_ISP_EXP_BASE + 0x00000000)
> -#define RKISP1_CIF_ISP_EXP_H_OFFSET		(RKISP1_CIF_ISP_EXP_BASE + 0x00000004)
> -#define RKISP1_CIF_ISP_EXP_V_OFFSET		(RKISP1_CIF_ISP_EXP_BASE + 0x00000008)
> -#define RKISP1_CIF_ISP_EXP_H_SIZE		(RKISP1_CIF_ISP_EXP_BASE + 0x0000000C)
> -#define RKISP1_CIF_ISP_EXP_V_SIZE		(RKISP1_CIF_ISP_EXP_BASE + 0x00000010)
> -#define RKISP1_CIF_ISP_EXP_MEAN_00		(RKISP1_CIF_ISP_EXP_BASE + 0x00000014)
> -#define RKISP1_CIF_ISP_EXP_MEAN_10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000018)
> -#define RKISP1_CIF_ISP_EXP_MEAN_20		(RKISP1_CIF_ISP_EXP_BASE + 0x0000001c)
> -#define RKISP1_CIF_ISP_EXP_MEAN_30		(RKISP1_CIF_ISP_EXP_BASE + 0x00000020)
> -#define RKISP1_CIF_ISP_EXP_MEAN_40		(RKISP1_CIF_ISP_EXP_BASE + 0x00000024)
> -#define RKISP1_CIF_ISP_EXP_MEAN_01		(RKISP1_CIF_ISP_EXP_BASE + 0x00000028)
> -#define RKISP1_CIF_ISP_EXP_MEAN_11		(RKISP1_CIF_ISP_EXP_BASE + 0x0000002c)
> -#define RKISP1_CIF_ISP_EXP_MEAN_21		(RKISP1_CIF_ISP_EXP_BASE + 0x00000030)
> -#define RKISP1_CIF_ISP_EXP_MEAN_31		(RKISP1_CIF_ISP_EXP_BASE + 0x00000034)
> -#define RKISP1_CIF_ISP_EXP_MEAN_41		(RKISP1_CIF_ISP_EXP_BASE + 0x00000038)
> -#define RKISP1_CIF_ISP_EXP_MEAN_02		(RKISP1_CIF_ISP_EXP_BASE + 0x0000003c)
> -#define RKISP1_CIF_ISP_EXP_MEAN_12		(RKISP1_CIF_ISP_EXP_BASE + 0x00000040)
> -#define RKISP1_CIF_ISP_EXP_MEAN_22		(RKISP1_CIF_ISP_EXP_BASE + 0x00000044)
> -#define RKISP1_CIF_ISP_EXP_MEAN_32		(RKISP1_CIF_ISP_EXP_BASE + 0x00000048)
> -#define RKISP1_CIF_ISP_EXP_MEAN_42		(RKISP1_CIF_ISP_EXP_BASE + 0x0000004c)
> -#define RKISP1_CIF_ISP_EXP_MEAN_03		(RKISP1_CIF_ISP_EXP_BASE + 0x00000050)
> -#define RKISP1_CIF_ISP_EXP_MEAN_13		(RKISP1_CIF_ISP_EXP_BASE + 0x00000054)
> -#define RKISP1_CIF_ISP_EXP_MEAN_23		(RKISP1_CIF_ISP_EXP_BASE + 0x00000058)
> -#define RKISP1_CIF_ISP_EXP_MEAN_33		(RKISP1_CIF_ISP_EXP_BASE + 0x0000005c)
> -#define RKISP1_CIF_ISP_EXP_MEAN_43		(RKISP1_CIF_ISP_EXP_BASE + 0x00000060)
> -#define RKISP1_CIF_ISP_EXP_MEAN_04		(RKISP1_CIF_ISP_EXP_BASE + 0x00000064)
> -#define RKISP1_CIF_ISP_EXP_MEAN_14		(RKISP1_CIF_ISP_EXP_BASE + 0x00000068)
> -#define RKISP1_CIF_ISP_EXP_MEAN_24		(RKISP1_CIF_ISP_EXP_BASE + 0x0000006c)
> -#define RKISP1_CIF_ISP_EXP_MEAN_34		(RKISP1_CIF_ISP_EXP_BASE + 0x00000070)
> -#define RKISP1_CIF_ISP_EXP_MEAN_44		(RKISP1_CIF_ISP_EXP_BASE + 0x00000074)
> +#define RKISP1_CIF_ISP_EXP_H_OFFSET_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000004)
> +#define RKISP1_CIF_ISP_EXP_V_OFFSET_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000008)
> +#define RKISP1_CIF_ISP_EXP_H_SIZE_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x0000000C)
> +#define RKISP1_CIF_ISP_EXP_V_SIZE_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000010)
> +#define RKISP1_CIF_ISP_EXP_MEAN_00_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000014)
> +#define RKISP1_CIF_ISP_EXP_MEAN_10_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000018)
> +#define RKISP1_CIF_ISP_EXP_MEAN_20_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x0000001c)
> +#define RKISP1_CIF_ISP_EXP_MEAN_30_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000020)
> +#define RKISP1_CIF_ISP_EXP_MEAN_40_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000024)
> +#define RKISP1_CIF_ISP_EXP_MEAN_01_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000028)
> +#define RKISP1_CIF_ISP_EXP_MEAN_11_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x0000002c)
> +#define RKISP1_CIF_ISP_EXP_MEAN_21_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000030)
> +#define RKISP1_CIF_ISP_EXP_MEAN_31_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000034)
> +#define RKISP1_CIF_ISP_EXP_MEAN_41_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000038)
> +#define RKISP1_CIF_ISP_EXP_MEAN_02_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x0000003c)
> +#define RKISP1_CIF_ISP_EXP_MEAN_12_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000040)
> +#define RKISP1_CIF_ISP_EXP_MEAN_22_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000044)
> +#define RKISP1_CIF_ISP_EXP_MEAN_32_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000048)
> +#define RKISP1_CIF_ISP_EXP_MEAN_42_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x0000004c)
> +#define RKISP1_CIF_ISP_EXP_MEAN_03_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000050)
> +#define RKISP1_CIF_ISP_EXP_MEAN_13_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000054)
> +#define RKISP1_CIF_ISP_EXP_MEAN_23_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000058)
> +#define RKISP1_CIF_ISP_EXP_MEAN_33_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x0000005c)
> +#define RKISP1_CIF_ISP_EXP_MEAN_43_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000060)
> +#define RKISP1_CIF_ISP_EXP_MEAN_04_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000064)
> +#define RKISP1_CIF_ISP_EXP_MEAN_14_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000068)
> +#define RKISP1_CIF_ISP_EXP_MEAN_24_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x0000006c)
> +#define RKISP1_CIF_ISP_EXP_MEAN_34_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000070)
> +#define RKISP1_CIF_ISP_EXP_MEAN_44_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000074)
> +#define RKISP1_CIF_ISP_EXP_SIZE_V12		(RKISP1_CIF_ISP_EXP_BASE + 0x00000004)
> +#define RKISP1_CIF_ISP_EXP_OFFS_V12		(RKISP1_CIF_ISP_EXP_BASE + 0x00000008)
> +#define RKISP1_CIF_ISP_EXP_MEAN_V12		(RKISP1_CIF_ISP_EXP_BASE + 0x0000000c)
>  
>  #define RKISP1_CIF_ISP_BLS_BASE			0x00002700
>  #define RKISP1_CIF_ISP_BLS_CTRL			(RKISP1_CIF_ISP_BLS_BASE + 0x00000000)
> @@ -1248,6 +1377,16 @@
>  #define RKISP1_CIF_ISP_WDR_TONECURVE_YM_31_SHD	(RKISP1_CIF_ISP_WDR_BASE + 0x0000012C)
>  #define RKISP1_CIF_ISP_WDR_TONECURVE_YM_32_SHD	(RKISP1_CIF_ISP_WDR_BASE + 0x00000130)
>  
> +#define RKISP1_CIF_ISP_HIST_BASE_V12		0x00002C00
> +#define RKISP1_CIF_ISP_HIST_CTRL_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x00000000)
> +#define RKISP1_CIF_ISP_HIST_SIZE_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x00000004)
> +#define RKISP1_CIF_ISP_HIST_OFFS_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x00000008)
> +#define RKISP1_CIF_ISP_HIST_DBG1_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x0000000C)
> +#define RKISP1_CIF_ISP_HIST_DBG2_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x0000001C)
> +#define RKISP1_CIF_ISP_HIST_DBG3_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x0000002C)
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x0000003C)
> +#define RKISP1_CIF_ISP_HIST_BIN_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x00000120)
> +
>  #define RKISP1_CIF_ISP_VSM_BASE			0x00002F00
>  #define RKISP1_CIF_ISP_VSM_MODE			(RKISP1_CIF_ISP_VSM_BASE + 0x00000000)
>  #define RKISP1_CIF_ISP_VSM_H_OFFS		(RKISP1_CIF_ISP_VSM_BASE + 0x00000004)
> @@ -1259,4 +1398,7 @@
>  #define RKISP1_CIF_ISP_VSM_DELTA_H		(RKISP1_CIF_ISP_VSM_BASE + 0x0000001C)
>  #define RKISP1_CIF_ISP_VSM_DELTA_V		(RKISP1_CIF_ISP_VSM_BASE + 0x00000020)
>  
> +#define RKISP1_CIF_ISP_CSI0_BASE		0x00007000
> +#define RKISP1_CIF_ISP_CSI0_CTRL0		(RKISP1_CIF_ISP_CSI0_BASE + 0x00000000)
> +
>  #endif /* _RKISP1_REGS_H */
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c
> index 7136292039f6..5ce1a2974b55 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c
> @@ -175,18 +175,18 @@ rkisp1_stats_init_vb2_queue(struct vb2_queue *q, struct rkisp1_stats *stats)
>  	return vb2_queue_init(q);
>  }
>  
> -static void rkisp1_stats_get_awb_meas(struct rkisp1_stats *stats,
> -				      struct rkisp1_stat_buffer *pbuf)
> +static void rkisp1_stats_get_awb_meas_v10(struct rkisp1_stats *stats,
> +					  struct rkisp1_stat_buffer *pbuf)
>  {
>  	/* Protect against concurrent access from ISR? */
>  	struct rkisp1_device *rkisp1 = stats->rkisp1;
>  	u32 reg_val;
>  
>  	pbuf->meas_type |= RKISP1_CIF_ISP_STAT_AWB;
> -	reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_WHITE_CNT);
> +	reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_WHITE_CNT_V10);
>  	pbuf->params.awb.awb_mean[0].cnt =
>  				RKISP1_CIF_ISP_AWB_GET_PIXEL_CNT(reg_val);
> -	reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_MEAN);
> +	reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_MEAN_V10);
>  
>  	pbuf->params.awb.awb_mean[0].mean_cr_or_r =
>  				RKISP1_CIF_ISP_AWB_GET_MEAN_CR_R(reg_val);
> @@ -196,8 +196,29 @@ static void rkisp1_stats_get_awb_meas(struct rkisp1_stats *stats,
>  				RKISP1_CIF_ISP_AWB_GET_MEAN_Y_G(reg_val);
>  }
>  
> -static void rkisp1_stats_get_aec_meas(struct rkisp1_stats *stats,
> -				      struct rkisp1_stat_buffer *pbuf)
> +static void rkisp1_stats_get_awb_meas_v12(struct rkisp1_stats *stats,
> +					  struct rkisp1_stat_buffer *pbuf)
> +{
> +	/* Protect against concurrent access from ISR? */
> +	struct rkisp1_device *rkisp1 = stats->rkisp1;
> +	u32 reg_val;
> +
> +	pbuf->meas_type |= RKISP1_CIF_ISP_STAT_AWB;
> +	reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_WHITE_CNT_V12);
> +	pbuf->params.awb.awb_mean[0].cnt =
> +				RKISP1_CIF_ISP_AWB_GET_PIXEL_CNT(reg_val);
> +	reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_MEAN_V12);
> +
> +	pbuf->params.awb.awb_mean[0].mean_cr_or_r =
> +				RKISP1_CIF_ISP_AWB_GET_MEAN_CR_R(reg_val);
> +	pbuf->params.awb.awb_mean[0].mean_cb_or_b =
> +				RKISP1_CIF_ISP_AWB_GET_MEAN_CB_B(reg_val);
> +	pbuf->params.awb.awb_mean[0].mean_y_or_g =
> +				RKISP1_CIF_ISP_AWB_GET_MEAN_Y_G(reg_val);
> +}
> +
> +static void rkisp1_stats_get_aec_meas_v10(struct rkisp1_stats *stats,
> +					  struct rkisp1_stat_buffer *pbuf)
>  {
>  	struct rkisp1_device *rkisp1 = stats->rkisp1;
>  	unsigned int i;
> @@ -206,7 +227,31 @@ static void rkisp1_stats_get_aec_meas(struct rkisp1_stats *stats,
>  	for (i = 0; i < stats->config->ae_mean_max; i++)
>  		pbuf->params.ae.exp_mean[i] =
>  			(u8)rkisp1_read(rkisp1,
> -					RKISP1_CIF_ISP_EXP_MEAN_00 + i * 4);
> +					RKISP1_CIF_ISP_EXP_MEAN_00_V10 + i * 4);
> +}
> +
> +static void rkisp1_stats_get_aec_meas_v12(struct rkisp1_stats *stats,
> +					  struct rkisp1_stat_buffer *pbuf)
> +{
> +	struct rkisp1_device *rkisp1 = stats->rkisp1;
> +	u32 value;
> +	int i;
> +
> +	pbuf->meas_type |= RKISP1_CIF_ISP_STAT_AUTOEXP;
> +	for (i = 0; i < stats->config->ae_mean_max / 4; i++) {
> +		value = rkisp1_read(rkisp1, RKISP1_CIF_ISP_EXP_MEAN_V12 + i * 4);
> +		pbuf->params.ae.exp_mean[4 * i + 0] =
> +				RKISP1_CIF_ISP_EXP_GET_MEAN_xy0_V12(value);
> +		pbuf->params.ae.exp_mean[4 * i + 1] =
> +				RKISP1_CIF_ISP_EXP_GET_MEAN_xy1_V12(value);
> +		pbuf->params.ae.exp_mean[4 * i + 2] =
> +				RKISP1_CIF_ISP_EXP_GET_MEAN_xy2_V12(value);
> +		pbuf->params.ae.exp_mean[4 * i + 3] =
> +				RKISP1_CIF_ISP_EXP_GET_MEAN_xy3_V12(value);
> +	}
> +
> +	value = rkisp1_read(rkisp1, RKISP1_CIF_ISP_EXP_MEAN_V12 + i * 4);
> +	pbuf->params.ae.exp_mean[4 * i + 0] = RKISP1_CIF_ISP_EXP_GET_MEAN_xy0_V12(value);
>  }
>  
>  static void rkisp1_stats_get_afc_meas(struct rkisp1_stats *stats,
> @@ -226,8 +271,8 @@ static void rkisp1_stats_get_afc_meas(struct rkisp1_stats *stats,
>  	af->window[2].lum = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AFM_LUM_C);
>  }
>  
> -static void rkisp1_stats_get_hst_meas(struct rkisp1_stats *stats,
> -				      struct rkisp1_stat_buffer *pbuf)
> +static void rkisp1_stats_get_hst_meas_v10(struct rkisp1_stats *stats,
> +					  struct rkisp1_stat_buffer *pbuf)
>  {
>  	struct rkisp1_device *rkisp1 = stats->rkisp1;
>  	unsigned int i;
> @@ -236,7 +281,24 @@ static void rkisp1_stats_get_hst_meas(struct rkisp1_stats *stats,
>  	for (i = 0; i < stats->config->hist_bin_n_max; i++)
>  		pbuf->params.hist.hist_bins[i] =
>  			(u8)rkisp1_read(rkisp1,
> -					RKISP1_CIF_ISP_HIST_BIN_0 + i * 4);
> +					RKISP1_CIF_ISP_HIST_BIN_0_V10 + i * 4);
> +}
> +
> +static void rkisp1_stats_get_hst_meas_v12(struct rkisp1_stats *stats,
> +					  struct rkisp1_stat_buffer *pbuf)
> +{
> +	struct rkisp1_device *rkisp1 = stats->rkisp1;
> +	u32 value;
> +	int i;
> +
> +	pbuf->meas_type |= RKISP1_CIF_ISP_STAT_HIST;
> +	for (i = 0; i < stats->config->hist_bin_n_max / 2; i++) {
> +		value = rkisp1_read(rkisp1, RKISP1_CIF_ISP_HIST_BIN_V12 + i * 4);
> +		pbuf->params.hist.hist_bins[2 * i] =
> +					RKISP1_CIF_ISP_HIST_GET_BIN0_V12(value);
> +		pbuf->params.hist.hist_bins[2 * i + 1] =
> +					RKISP1_CIF_ISP_HIST_GET_BIN1_V12(value);
> +	}
>  }
>  
>  static void rkisp1_stats_get_bls_meas(struct rkisp1_stats *stats,
> @@ -286,17 +348,28 @@ static void rkisp1_stats_get_bls_meas(struct rkisp1_stats *stats,
>  	}
>  }
>  
> -static struct rkisp1_stats_ops rkisp1_stats_ops = {
> -	.get_awb_meas = rkisp1_stats_get_awb_meas,
> -	.get_aec_meas = rkisp1_stats_get_aec_meas,
> -	.get_hst_meas = rkisp1_stats_get_hst_meas,
> +static struct rkisp1_stats_ops rkisp1_v10_stats_ops = {
> +	.get_awb_meas = rkisp1_stats_get_awb_meas_v10,
> +	.get_aec_meas = rkisp1_stats_get_aec_meas_v10,
> +	.get_hst_meas = rkisp1_stats_get_hst_meas_v10,
>  };
>  
> -static struct rkisp1_stats_config rkisp1_stats_config = {
> +static struct rkisp1_stats_config rkisp1_v10_stats_config = {
>  	.ae_mean_max = 25,
>  	.hist_bin_n_max = 16,
>  };
>  
> +static struct rkisp1_stats_ops rkisp1_v12_stats_ops = {
> +	.get_awb_meas = rkisp1_stats_get_awb_meas_v12,
> +	.get_aec_meas = rkisp1_stats_get_aec_meas_v12,
> +	.get_hst_meas = rkisp1_stats_get_hst_meas_v12,
> +};
> +
> +static struct rkisp1_stats_config rkisp1_v12_stats_config = {
> +	.ae_mean_max = 81,
> +	.hist_bin_n_max = 32,
> +};
> +
>  static void
>  rkisp1_stats_send_measurement(struct rkisp1_stats *stats, u32 isp_ris)
>  {
> @@ -365,8 +438,13 @@ static void rkisp1_init_stats(struct rkisp1_stats *stats)
>  	stats->vdev_fmt.fmt.meta.buffersize =
>  		sizeof(struct rkisp1_stat_buffer);
>  
> -	stats->ops = &rkisp1_stats_ops;
> -	stats->config = &rkisp1_stats_config;
> +	if (stats->rkisp1->isp_ver == RKISP1_V12) {
> +		stats->ops = &rkisp1_v12_stats_ops;
> +		stats->config = &rkisp1_v12_stats_config;
> +	} else {
> +		stats->ops = &rkisp1_v10_stats_ops;
> +		stats->config = &rkisp1_v10_stats_config;
> +	}
>  }
>  
>  int rkisp1_stats_register(struct rkisp1_device *rkisp1)
> 

Re: [PATCH RFC 06/11] media: rockchip: rkisp1: allow separate interrupts

[Dafna Hirschfeld]

Hi

Am 08.01.21 um 20:33 schrieb Heiko Stuebner:
> From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> 
> Depending on the per-soc implementation there can be one interrupt
> for isp, mipi and capture events or separate per-event interrupts.
> 
> So simply check for the presence of a named "mi" interrupt
> to differentiate between the two cases.
> 
> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> ---
>   .../platform/rockchip/rkisp1/rkisp1-capture.c |  9 ++-
>   .../platform/rockchip/rkisp1/rkisp1-common.h  |  7 ++-
>   .../platform/rockchip/rkisp1/rkisp1-dev.c     | 58 ++++++++++++++-----
>   .../platform/rockchip/rkisp1/rkisp1-isp.c     | 16 +++--
>   4 files changed, 69 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
> index 5f6c9d1623e4..f70c66c2a1d7 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
> @@ -685,12 +685,17 @@ static void rkisp1_handle_buffer(struct rkisp1_capture *cap)
>   	spin_unlock(&cap->buf.lock);
>   }
>   
> -void rkisp1_capture_isr(struct rkisp1_device *rkisp1)
> +irqreturn_t rkisp1_capture_isr(int irq, void *ctx)
>   {
> +	struct device *dev = ctx;
> +	struct rkisp1_device *rkisp1 = dev_get_drvdata(dev);
>   	unsigned int i;
>   	u32 status;
>   
>   	status = rkisp1_read(rkisp1, RKISP1_CIF_MI_MIS);
> +	if (!status)
> +		return IRQ_NONE;
> +
>   	rkisp1_write(rkisp1, status, RKISP1_CIF_MI_ICR);
>   
>   	for (i = 0; i < ARRAY_SIZE(rkisp1->capture_devs); ++i) {
> @@ -718,6 +723,8 @@ void rkisp1_capture_isr(struct rkisp1_device *rkisp1)
>   		cap->is_streaming = false;
>   		wake_up(&cap->done);
>   	}
> +
> +	return IRQ_HANDLED;
>   }
>   
>   /* ----------------------------------------------------------------------------
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
> index 038c303a8aed..44f333bf5d6a 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
> @@ -12,6 +12,7 @@
>   #define _RKISP1_COMMON_H
>   
>   #include <linux/clk.h>
> +#include <linux/interrupt.h>
>   #include <linux/mutex.h>
>   #include <linux/rkisp1-config.h>
>   #include <media/media-device.h>
> @@ -460,9 +461,9 @@ void rkisp1_params_configure(struct rkisp1_params *params,
>   void rkisp1_params_disable(struct rkisp1_params *params);
>   
>   /* irq handlers */
> -void rkisp1_isp_isr(struct rkisp1_device *rkisp1);
> -void rkisp1_mipi_isr(struct rkisp1_device *rkisp1);
> -void rkisp1_capture_isr(struct rkisp1_device *rkisp1);
> +irqreturn_t rkisp1_isp_isr(int irq, void *ctx);
> +irqreturn_t rkisp1_mipi_isr(int irq, void *ctx);
> +irqreturn_t rkisp1_capture_isr(int irq, void *ctx);
>   void rkisp1_stats_isr(struct rkisp1_stats *stats, u32 isp_ris);
>   void rkisp1_params_isr(struct rkisp1_device *rkisp1);
>   
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
> index 68da1eed753d..96afc1d1a914 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
> @@ -389,18 +389,15 @@ static int rkisp1_entities_register(struct rkisp1_device *rkisp1)
>   
>   static irqreturn_t rkisp1_isr(int irq, void *ctx)
>   {
> -	struct device *dev = ctx;
> -	struct rkisp1_device *rkisp1 = dev_get_drvdata(dev);
> -
>   	/*
>   	 * Call rkisp1_capture_isr() first to handle the frame that
>   	 * potentially completed using the current frame_sequence number before
>   	 * it is potentially incremented by rkisp1_isp_isr() in the vertical
>   	 * sync.
>   	 */
> -	rkisp1_capture_isr(rkisp1);
> -	rkisp1_isp_isr(rkisp1);
> -	rkisp1_mipi_isr(rkisp1);
> +	rkisp1_capture_isr(irq, ctx);
> +	rkisp1_isp_isr(irq, ctx);
> +	rkisp1_mipi_isr(irq, ctx);
>   
>   	return IRQ_HANDLED;

I remember we had a patch that check if all the rkisp1_*_isr calls return IRQ_NONE then we also return IRQ_NONE from here
instead of always returning IRQ_HANDLED. I think now it is the opportunity to add this.
Maybe better in a separate patch before this one, where you only change the rkisp1_*_isr signatures and return
the right value from rkisp1_isr

Thanks,
Dafna

>   }
> @@ -481,15 +478,50 @@ static int rkisp1_probe(struct platform_device *pdev)
>   	if (IS_ERR(rkisp1->base_addr))
>   		return PTR_ERR(rkisp1->base_addr);
>   
> -	irq = platform_get_irq(pdev, 0);
> -	if (irq < 0)
> +	irq = platform_get_irq_byname_optional(pdev, "mi");
> +	if (irq == -EPROBE_DEFER) {
>   		return irq;
> +	} else if (irq < 0) {
> +		irq = platform_get_irq(pdev, 0);
> +		if (irq < 0)
> +			return irq;
> +
> +		ret = devm_request_irq(dev, irq, rkisp1_isr, IRQF_SHARED,
> +				       dev_driver_string(dev), dev);
> +		if (ret) {
> +			dev_err(dev, "request irq failed: %d\n", ret);
> +			return ret;
> +		}
> +	} else {
> +		/* we test-got the MI (capture) interrupt */
> +		ret = devm_request_irq(dev, irq, rkisp1_capture_isr, IRQF_SHARED,
> +				       dev_driver_string(dev), dev);
> +		if (ret) {
> +			dev_err(dev, "request mi irq failed: %d\n", ret);
> +			return ret;
> +		}
>   
> -	ret = devm_request_irq(dev, irq, rkisp1_isr, IRQF_SHARED,
> -			       dev_driver_string(dev), dev);
> -	if (ret) {
> -		dev_err(dev, "request irq failed: %d\n", ret);
> -		return ret;
> +		irq = platform_get_irq_byname_optional(pdev, "mipi");
> +		if (irq < 0)
> +			return irq;
> +
> +		ret = devm_request_irq(dev, irq, rkisp1_mipi_isr, IRQF_SHARED,
> +				       dev_driver_string(dev), dev);
> +		if (ret) {
> +			dev_err(dev, "request mipi irq failed: %d\n", ret);
> +			return ret;
> +		}
> +
> +		irq = platform_get_irq_byname_optional(pdev, "isp");
> +		if (irq < 0)
> +			return irq;
> +
> +		ret = devm_request_irq(dev, irq, rkisp1_isp_isr, IRQF_SHARED,
> +				       dev_driver_string(dev), dev);
> +		if (ret) {
> +			dev_err(dev, "request isp irq failed: %d\n", ret);
> +			return ret;
> +		}
>   	}
>   
>   	rkisp1->irq = irq;
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
> index 889982d8ca41..84440aa71210 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
> @@ -1056,13 +1056,15 @@ void rkisp1_isp_unregister(struct rkisp1_device *rkisp1)
>    * Interrupt handlers
>    */
>   
> -void rkisp1_mipi_isr(struct rkisp1_device *rkisp1)
> +irqreturn_t rkisp1_mipi_isr(int irq, void *ctx)
>   {
> +	struct device *dev = ctx;
> +	struct rkisp1_device *rkisp1 = dev_get_drvdata(dev);
>   	u32 val, status;
>   
>   	status = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_MIS);
>   	if (!status)
> -		return;
> +		return IRQ_NONE;
>   
>   	rkisp1_write(rkisp1, status, RKISP1_CIF_MIPI_ICR);
>   
> @@ -1097,6 +1099,8 @@ void rkisp1_mipi_isr(struct rkisp1_device *rkisp1)
>   	} else {
>   		rkisp1->debug.mipi_error++;
>   	}
> +
> +	return IRQ_HANDLED;
>   }
>   
>   static void rkisp1_isp_queue_event_sof(struct rkisp1_isp *isp)
> @@ -1109,13 +1113,15 @@ static void rkisp1_isp_queue_event_sof(struct rkisp1_isp *isp)
>   	v4l2_event_queue(isp->sd.devnode, &event);
>   }
>   
> -void rkisp1_isp_isr(struct rkisp1_device *rkisp1)
> +irqreturn_t rkisp1_isp_isr(int irq, void *ctx)
>   {
> +	struct device *dev = ctx;
> +	struct rkisp1_device *rkisp1 = dev_get_drvdata(dev);
>   	u32 status, isp_err;
>   
>   	status = rkisp1_read(rkisp1, RKISP1_CIF_ISP_MIS);
>   	if (!status)
> -		return;
> +		return IRQ_NONE;
>   
>   	rkisp1_write(rkisp1, status, RKISP1_CIF_ISP_ICR);
>   
> @@ -1157,4 +1163,6 @@ void rkisp1_isp_isr(struct rkisp1_device *rkisp1)
>   		 */
>   		rkisp1_params_isr(rkisp1);
>   	}
> +
> +	return IRQ_HANDLED;
>   }
> 

Re: [PATCH RFC 10/11] media: rockchip: rkisp1: add support for v12 isp variants

[Dafna Hirschfeld]

Am 08.01.21 um 20:33 schrieb Heiko Stuebner:
> From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> 
> The rkisp1 evolved over soc generations and the rk3326/px30 introduced
> the so called v12 - probably meaning v1.2.
> 
> Add the changed register definitions.
> 
> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> ---
>   .../platform/rockchip/rkisp1/rkisp1-common.h  |   1 +
>   .../platform/rockchip/rkisp1/rkisp1-isp.c     |  13 +
>   .../platform/rockchip/rkisp1/rkisp1-params.c  | 535 +++++++++++++++---
>   .../platform/rockchip/rkisp1/rkisp1-regs.h    | 404 ++++++++-----
>   .../platform/rockchip/rkisp1/rkisp1-stats.c   | 112 +++-
>   5 files changed, 824 insertions(+), 241 deletions(-)
> 
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
> index be0ae02165c9..9deb1ef1aa8b 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
> @@ -61,6 +61,7 @@
>   
>   enum rkisp1_isp_ver {
>   	RKISP1_V10 = 0,
> +	RKISP1_V12,
>   };
>   
>   /* enum for the resizer pads */
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
> index 84440aa71210..306cc96f8230 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
> @@ -408,6 +408,10 @@ static int rkisp1_config_mipi(struct rkisp1_device *rkisp1)
>   
>   	rkisp1_write(rkisp1, mipi_ctrl, RKISP1_CIF_MIPI_CTRL);
>   
> +	/* V12 could also use a newer csi2-host, but we don't want that yet */
> +	if (rkisp1->isp_ver == RKISP1_V12)
> +		rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_CSI0_CTRL0);
> +
>   	/* Configure Data Type and Virtual Channel */
>   	rkisp1_write(rkisp1,
>   		     RKISP1_CIF_MIPI_DATA_SEL_DT(sink_fmt->mipi_dt) |
> @@ -527,6 +531,15 @@ static void rkisp1_config_clk(struct rkisp1_device *rkisp1)
>   		  RKISP1_CIF_ICCL_DCROP_CLK;
>   
>   	rkisp1_write(rkisp1, val, RKISP1_CIF_ICCL);
> +
> +	/* ensure sp and mp can run at the same time in V12 */
> +	if (rkisp1->isp_ver == RKISP1_V12) {
> +		val = RKISP1_CIF_CLK_CTRL_MI_Y12 | RKISP1_CIF_CLK_CTRL_MI_SP |
> +		      RKISP1_CIF_CLK_CTRL_MI_RAW0 | RKISP1_CIF_CLK_CTRL_MI_RAW1 |
> +		      RKISP1_CIF_CLK_CTRL_MI_READ | RKISP1_CIF_CLK_CTRL_MI_RAWRD |
> +		      RKISP1_CIF_CLK_CTRL_CP | RKISP1_CIF_CLK_CTRL_IE;
> +		rkisp1_write(rkisp1, val, RKISP1_CIF_VI_ISP_CLK_CTRL_V12);
> +	}
>   }
>   
>   static void rkisp1_isp_start(struct rkisp1_device *rkisp1)
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
> index 008584caaad0..408fa33bdc30 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
> @@ -185,8 +185,8 @@ static void rkisp1_bls_config(struct rkisp1_params *params,
>   
>   /* ISP LS correction interface function */
>   static void
> -rkisp1_lsc_matrix_config(struct rkisp1_params *params,
> -			 const struct rkisp1_cif_isp_lsc_config *pconfig)
> +rkisp1_lsc_matrix_config_v10(struct rkisp1_params *params,
> +			     const struct rkisp1_cif_isp_lsc_config *pconfig)
>   {
>   	unsigned int isp_lsc_status, sram_addr, isp_lsc_table_sel, i, j, data;
>   
> @@ -212,39 +212,111 @@ rkisp1_lsc_matrix_config(struct rkisp1_params *params,
>   		 * DWORDs (2nd value of last DWORD unused)
>   		 */
>   		for (j = 0; j < RKISP1_CIF_ISP_LSC_SAMPLES_MAX - 1; j += 2) {
> -			data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->r_data_tbl[i][j],
> -							     pconfig->r_data_tbl[i][j + 1]);
> +			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->r_data_tbl[i][j],
> +								 pconfig->r_data_tbl[i][j + 1]);
>   			rkisp1_write(params->rkisp1, data,
>   				     RKISP1_CIF_ISP_LSC_R_TABLE_DATA);
>   
> -			data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->gr_data_tbl[i][j],
> -							     pconfig->gr_data_tbl[i][j + 1]);
> +			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->gr_data_tbl[i][j],
> +								 pconfig->gr_data_tbl[i][j + 1]);
>   			rkisp1_write(params->rkisp1, data,
>   				     RKISP1_CIF_ISP_LSC_GR_TABLE_DATA);
>   
> -			data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->gb_data_tbl[i][j],
> -							     pconfig->gb_data_tbl[i][j + 1]);
> +			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->gb_data_tbl[i][j],
> +								 pconfig->gb_data_tbl[i][j + 1]);
>   			rkisp1_write(params->rkisp1, data,
>   				     RKISP1_CIF_ISP_LSC_GB_TABLE_DATA);
>   
> -			data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->b_data_tbl[i][j],
> -							     pconfig->b_data_tbl[i][j + 1]);
> +			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->b_data_tbl[i][j],
> +								 pconfig->b_data_tbl[i][j + 1]);
>   			rkisp1_write(params->rkisp1, data,
>   				     RKISP1_CIF_ISP_LSC_B_TABLE_DATA);
>   		}
> -		data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->r_data_tbl[i][j], 0);
> +		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->r_data_tbl[i][j], 0);
>   		rkisp1_write(params->rkisp1, data,
>   			     RKISP1_CIF_ISP_LSC_R_TABLE_DATA);
>   
> -		data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->gr_data_tbl[i][j], 0);
> +		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->gr_data_tbl[i][j], 0);
>   		rkisp1_write(params->rkisp1, data,
>   			     RKISP1_CIF_ISP_LSC_GR_TABLE_DATA);
>   
> -		data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->gb_data_tbl[i][j], 0);
> +		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->gb_data_tbl[i][j], 0);
>   		rkisp1_write(params->rkisp1, data,
>   			     RKISP1_CIF_ISP_LSC_GB_TABLE_DATA);
>   
> -		data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->b_data_tbl[i][j], 0);
> +		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->b_data_tbl[i][j], 0);
> +		rkisp1_write(params->rkisp1, data,
> +			     RKISP1_CIF_ISP_LSC_B_TABLE_DATA);
> +	}
> +	isp_lsc_table_sel = (isp_lsc_status & RKISP1_CIF_ISP_LSC_ACTIVE_TABLE) ?
> +			    RKISP1_CIF_ISP_LSC_TABLE_0 :
> +			    RKISP1_CIF_ISP_LSC_TABLE_1;
> +	rkisp1_write(params->rkisp1, isp_lsc_table_sel,
> +		     RKISP1_CIF_ISP_LSC_TABLE_SEL);> +}
> +
> +static void
> +rkisp1_lsc_matrix_config_v12(struct rkisp1_params *params,
> +			     const struct rkisp1_cif_isp_lsc_config *pconfig)
> +{
> +	unsigned int isp_lsc_status, sram_addr, isp_lsc_table_sel, i, j, data;
> +
> +	isp_lsc_status = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_LSC_STATUS);
> +
> +	/* RKISP1_CIF_ISP_LSC_TABLE_ADDRESS_153 = ( 17 * 18 ) >> 1 */
> +	sram_addr = (isp_lsc_status & RKISP1_CIF_ISP_LSC_ACTIVE_TABLE) ?
> +		     RKISP1_CIF_ISP_LSC_TABLE_ADDRESS_0 :
> +		     RKISP1_CIF_ISP_LSC_TABLE_ADDRESS_153;
> +	rkisp1_write(params->rkisp1, sram_addr, RKISP1_CIF_ISP_LSC_R_TABLE_ADDR);
> +	rkisp1_write(params->rkisp1, sram_addr, RKISP1_CIF_ISP_LSC_GR_TABLE_ADDR);
> +	rkisp1_write(params->rkisp1, sram_addr, RKISP1_CIF_ISP_LSC_GB_TABLE_ADDR);
> +	rkisp1_write(params->rkisp1, sram_addr, RKISP1_CIF_ISP_LSC_B_TABLE_ADDR);
> +
> +	/* program data tables (table size is 9 * 17 = 153) */
> +	for (i = 0; i < RKISP1_CIF_ISP_LSC_SAMPLES_MAX; i++) {
> +		/*
> +		 * 17 sectors with 2 values in one DWORD = 9
> +		 * DWORDs (2nd value of last DWORD unused)
> +		 */
> +		for (j = 0; j < RKISP1_CIF_ISP_LSC_SAMPLES_MAX - 1; j += 2) {
> +			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(
> +					pconfig->r_data_tbl[i][j],
> +					pconfig->r_data_tbl[i][j + 1]);
> +			rkisp1_write(params->rkisp1, data,
> +				     RKISP1_CIF_ISP_LSC_R_TABLE_DATA);
> +
> +			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(
> +					pconfig->gr_data_tbl[i][j],
> +					pconfig->gr_data_tbl[i][j + 1]);
> +			rkisp1_write(params->rkisp1, data,
> +				     RKISP1_CIF_ISP_LSC_GR_TABLE_DATA);
> +
> +			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(
> +					pconfig->gb_data_tbl[i][j],
> +					pconfig->gb_data_tbl[i][j + 1]);
> +			rkisp1_write(params->rkisp1, data,
> +				     RKISP1_CIF_ISP_LSC_GB_TABLE_DATA);
> +
> +			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(
> +					pconfig->b_data_tbl[i][j],
> +					pconfig->b_data_tbl[i][j + 1]);
> +			rkisp1_write(params->rkisp1, data,
> +				     RKISP1_CIF_ISP_LSC_B_TABLE_DATA);
> +		}
> +
> +		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(pconfig->r_data_tbl[i][j], 0);
> +		rkisp1_write(params->rkisp1, data,
> +			     RKISP1_CIF_ISP_LSC_R_TABLE_DATA);
> +
> +		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(pconfig->gr_data_tbl[i][j], 0);
> +		rkisp1_write(params->rkisp1, data,
> +			     RKISP1_CIF_ISP_LSC_GR_TABLE_DATA);
> +
> +		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(pconfig->gb_data_tbl[i][j], 0);
> +		rkisp1_write(params->rkisp1, data,
> +			     RKISP1_CIF_ISP_LSC_GB_TABLE_DATA);
> +
> +		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(pconfig->b_data_tbl[i][j], 0);
>   		rkisp1_write(params->rkisp1, data,
>   			     RKISP1_CIF_ISP_LSC_B_TABLE_DATA);
>   	}
> @@ -382,18 +454,37 @@ static void rkisp1_sdg_config(struct rkisp1_params *params,
>   }
>   
>   /* ISP GAMMA correction interface function */
> -static void rkisp1_goc_config(struct rkisp1_params *params,
> -			      const struct rkisp1_cif_isp_goc_config *arg)
> +static void rkisp1_goc_config_v10(struct rkisp1_params *params,
> +				  const struct rkisp1_cif_isp_goc_config *arg)
>   {
>   	unsigned int i;
>   
>   	rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_CTRL,
>   				RKISP1_CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA);
> -	rkisp1_write(params->rkisp1, arg->mode, RKISP1_CIF_ISP_GAMMA_OUT_MODE);
> +	rkisp1_write(params->rkisp1, arg->mode, RKISP1_CIF_ISP_GAMMA_OUT_MODE_V10);
>   
>   	for (i = 0; i < params->config->gamma_out_max_samples; i++)
>   		rkisp1_write(params->rkisp1, arg->gamma_y[i],
> -			     RKISP1_CIF_ISP_GAMMA_OUT_Y_0 + i * 4);
> +			     RKISP1_CIF_ISP_GAMMA_OUT_Y_0_V10 + i * 4);
> +}
> +
> +static void rkisp1_goc_config_v12(struct rkisp1_params *params,
> +				  const struct rkisp1_cif_isp_goc_config *arg)
> +{
> +	int i;

unsigned int

> +	u32 value;
> +
> +	rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_CTRL,
> +				RKISP1_CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA);
> +	rkisp1_write(params->rkisp1, arg->mode, RKISP1_CIF_ISP_GAMMA_OUT_MODE_V12);
> +
> +	for (i = 0; i < params->config->gamma_out_max_samples / 2; i++) {

Since you already have two version for the 'goc_config; callback, there is no
need for the config to get the gamma_out_max_samples you can use
RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES_V* directly


> +		value = RKISP1_CIF_ISP_GAMMA_VALUE_V12(
> +			arg->gamma_y[2 * i + 1],
> +			arg->gamma_y[2 * i]);
> +		rkisp1_write(params->rkisp1, value,
> +			     RKISP1_CIF_ISP_GAMMA_OUT_Y_0_V12 + i * 4);
> +	}
>   }
>   
>   /* ISP Cross Talk */
> @@ -433,8 +524,8 @@ static void rkisp1_ctk_enable(struct rkisp1_params *params, bool en)
>   }
>   
>   /* ISP White Balance Mode */
> -static void rkisp1_awb_meas_config(struct rkisp1_params *params,
> -				   const struct rkisp1_cif_isp_awb_meas_config *arg)
> +static void rkisp1_awb_meas_config_v10(struct rkisp1_params *params,
> +				       const struct rkisp1_cif_isp_awb_meas_config *arg)
>   {
>   	u32 reg_val = 0;
>   	/* based on the mode,configure the awb module */
> @@ -442,43 +533,82 @@ static void rkisp1_awb_meas_config(struct rkisp1_params *params,
>   		/* Reference Cb and Cr */
>   		rkisp1_write(params->rkisp1,
>   			     RKISP1_CIF_ISP_AWB_REF_CR_SET(arg->awb_ref_cr) |
> -			     arg->awb_ref_cb, RKISP1_CIF_ISP_AWB_REF);
> +			     arg->awb_ref_cb, RKISP1_CIF_ISP_AWB_REF_V10);
>   		/* Yc Threshold */
>   		rkisp1_write(params->rkisp1,
>   			     RKISP1_CIF_ISP_AWB_MAX_Y_SET(arg->max_y) |
>   			     RKISP1_CIF_ISP_AWB_MIN_Y_SET(arg->min_y) |
>   			     RKISP1_CIF_ISP_AWB_MAX_CS_SET(arg->max_csum) |
> -			     arg->min_c, RKISP1_CIF_ISP_AWB_THRESH);
> +			     arg->min_c, RKISP1_CIF_ISP_AWB_THRESH_V10);
>   	}
>   
> -	reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP);
> +	reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP_V10);
>   	if (arg->enable_ymax_cmp)
>   		reg_val |= RKISP1_CIF_ISP_AWB_YMAX_CMP_EN;
>   	else
>   		reg_val &= ~RKISP1_CIF_ISP_AWB_YMAX_CMP_EN;
> -	rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP);
> +	rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP_V10);
>   
>   	/* window offset */
>   	rkisp1_write(params->rkisp1,
> -		     arg->awb_wnd.v_offs, RKISP1_CIF_ISP_AWB_WND_V_OFFS);
> +		     arg->awb_wnd.v_offs, RKISP1_CIF_ISP_AWB_WND_V_OFFS_V10);
>   	rkisp1_write(params->rkisp1,
> -		     arg->awb_wnd.h_offs, RKISP1_CIF_ISP_AWB_WND_H_OFFS);
> +		     arg->awb_wnd.h_offs, RKISP1_CIF_ISP_AWB_WND_H_OFFS_V10);
>   	/* AWB window size */
>   	rkisp1_write(params->rkisp1,
> -		     arg->awb_wnd.v_size, RKISP1_CIF_ISP_AWB_WND_V_SIZE);
> +		     arg->awb_wnd.v_size, RKISP1_CIF_ISP_AWB_WND_V_SIZE_V10);
>   	rkisp1_write(params->rkisp1,
> -		     arg->awb_wnd.h_size, RKISP1_CIF_ISP_AWB_WND_H_SIZE);
> +		     arg->awb_wnd.h_size, RKISP1_CIF_ISP_AWB_WND_H_SIZE_V10);
>   	/* Number of frames */
>   	rkisp1_write(params->rkisp1,
> -		     arg->frames, RKISP1_CIF_ISP_AWB_FRAMES);
> +		     arg->frames, RKISP1_CIF_ISP_AWB_FRAMES_V10);
> +}
> +
> +static void rkisp1_awb_meas_config_v12(struct rkisp1_params *params,
> +				       const struct rkisp1_cif_isp_awb_meas_config *arg)
> +{
> +	u32 reg_val = 0;
> +	/* based on the mode,configure the awb module */
> +	if (arg->awb_mode == RKISP1_CIF_ISP_AWB_MODE_YCBCR) {
> +		/* Reference Cb and Cr */
> +		rkisp1_write(params->rkisp1,
> +			     RKISP1_CIF_ISP_AWB_REF_CR_SET(arg->awb_ref_cr) |
> +			     arg->awb_ref_cb, RKISP1_CIF_ISP_AWB_REF_V12);
> +		/* Yc Threshold */
> +		rkisp1_write(params->rkisp1,
> +			     RKISP1_CIF_ISP_AWB_MAX_Y_SET(arg->max_y) |
> +			     RKISP1_CIF_ISP_AWB_MIN_Y_SET(arg->min_y) |
> +			     RKISP1_CIF_ISP_AWB_MAX_CS_SET(arg->max_csum) |
> +			     arg->min_c, RKISP1_CIF_ISP_AWB_THRESH_V12);
> +	}
> +
> +	reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP_V12);
> +	if (arg->enable_ymax_cmp)
> +		reg_val |= RKISP1_CIF_ISP_AWB_YMAX_CMP_EN;
> +	else
> +		reg_val &= ~RKISP1_CIF_ISP_AWB_YMAX_CMP_EN;
> +	reg_val &= ~RKISP1_CIF_ISP_AWB_SET_FRAMES_MASK_V12;
> +	reg_val |= RKISP1_CIF_ISP_AWB_SET_FRAMES_V12(arg->frames);
> +	rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP_V12);
> +
> +	/* window offset */
> +	rkisp1_write(params->rkisp1,
> +		     arg->awb_wnd.v_offs << 16 |
> +		     arg->awb_wnd.h_offs,
> +		     RKISP1_CIF_ISP_AWB_OFFS_V12);
> +	/* AWB window size */
> +	rkisp1_write(params->rkisp1,
> +		     arg->awb_wnd.v_size << 16 |
> +		     arg->awb_wnd.h_size,
> +		     RKISP1_CIF_ISP_AWB_SIZE_V12);
>   }
>   
>   static void
> -rkisp1_awb_meas_enable(struct rkisp1_params *params,
> -		       const struct rkisp1_cif_isp_awb_meas_config *arg,
> -		       bool en)
> +rkisp1_awb_meas_enable_v10(struct rkisp1_params *params,
> +			   const struct rkisp1_cif_isp_awb_meas_config *arg,
> +			   bool en)
>   {
> -	u32 reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP);
> +	u32 reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP_V10);
>   
>   	/* switch off */
>   	reg_val &= RKISP1_CIF_ISP_AWB_MODE_MASK_NONE;
> @@ -489,34 +619,76 @@ rkisp1_awb_meas_enable(struct rkisp1_params *params,
>   		else
>   			reg_val |= RKISP1_CIF_ISP_AWB_MODE_YCBCR_EN;
>   
> -		rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP);
> +		rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP_V10);
>   
>   		/* Measurements require AWB block be active. */
>   		rkisp1_param_set_bits(params, RKISP1_CIF_ISP_CTRL,
>   				      RKISP1_CIF_ISP_CTRL_ISP_AWB_ENA);
>   	} else {
>   		rkisp1_write(params->rkisp1,
> -			     reg_val, RKISP1_CIF_ISP_AWB_PROP);
> +			     reg_val, RKISP1_CIF_ISP_AWB_PROP_V10);
>   		rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_CTRL,
>   					RKISP1_CIF_ISP_CTRL_ISP_AWB_ENA);
>   	}
>   }
>   
>   static void
> -rkisp1_awb_gain_config(struct rkisp1_params *params,
> -		       const struct rkisp1_cif_isp_awb_gain_config *arg)
> +rkisp1_awb_meas_enable_v12(struct rkisp1_params *params,
> +			   const struct rkisp1_cif_isp_awb_meas_config *arg,
> +			   bool en)
> +{
> +	u32 reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP_V12);
> +
> +	/* switch off */
> +	reg_val &= RKISP1_CIF_ISP_AWB_MODE_MASK_NONE;
> +
> +	if (en) {
> +		if (arg->awb_mode == RKISP1_CIF_ISP_AWB_MODE_RGB)
> +			reg_val |= RKISP1_CIF_ISP_AWB_MODE_RGB_EN;
> +		else
> +			reg_val |= RKISP1_CIF_ISP_AWB_MODE_YCBCR_EN;
> +
> +		rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP_V12);
> +
> +		/* Measurements require AWB block be active. */
> +		rkisp1_param_set_bits(params, RKISP1_CIF_ISP_CTRL,
> +				      RKISP1_CIF_ISP_CTRL_ISP_AWB_ENA);
> +	} else {
> +		rkisp1_write(params->rkisp1,
> +			     reg_val, RKISP1_CIF_ISP_AWB_PROP_V12);
> +		rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_CTRL,
> +					RKISP1_CIF_ISP_CTRL_ISP_AWB_ENA);
> +	}
> +}
> +
> +static void
> +rkisp1_awb_gain_config_v10(struct rkisp1_params *params,
> +			   const struct rkisp1_cif_isp_awb_gain_config *arg)
> +{
> +	rkisp1_write(params->rkisp1,
> +		     RKISP1_CIF_ISP_AWB_GAIN_R_SET(arg->gain_green_r) |
> +		     arg->gain_green_b, RKISP1_CIF_ISP_AWB_GAIN_G_V10);
> +
> +	rkisp1_write(params->rkisp1,
> +		     RKISP1_CIF_ISP_AWB_GAIN_R_SET(arg->gain_red) |
> +		     arg->gain_blue, RKISP1_CIF_ISP_AWB_GAIN_RB_V10);
> +}
> +
> +static void
> +rkisp1_awb_gain_config_v12(struct rkisp1_params *params,
> +			   const struct rkisp1_cif_isp_awb_gain_config *arg)
>   {
>   	rkisp1_write(params->rkisp1,
>   		     RKISP1_CIF_ISP_AWB_GAIN_R_SET(arg->gain_green_r) |
> -		     arg->gain_green_b, RKISP1_CIF_ISP_AWB_GAIN_G);
> +		     arg->gain_green_b, RKISP1_CIF_ISP_AWB_GAIN_G_V12);
>   
>   	rkisp1_write(params->rkisp1,
>   		     RKISP1_CIF_ISP_AWB_GAIN_R_SET(arg->gain_red) |
> -		     arg->gain_blue, RKISP1_CIF_ISP_AWB_GAIN_RB);
> +		     arg->gain_blue, RKISP1_CIF_ISP_AWB_GAIN_RB_V12);
>   }
>   
> -static void rkisp1_aec_config(struct rkisp1_params *params,
> -			      const struct rkisp1_cif_isp_aec_config *arg)
> +static void rkisp1_aec_config_v10(struct rkisp1_params *params,
> +				  const struct rkisp1_cif_isp_aec_config *arg)
>   {
>   	unsigned int block_hsize, block_vsize;
>   	u32 exp_ctrl;
> @@ -531,21 +703,55 @@ static void rkisp1_aec_config(struct rkisp1_params *params,
>   	rkisp1_write(params->rkisp1, exp_ctrl, RKISP1_CIF_ISP_EXP_CTRL);
>   
>   	rkisp1_write(params->rkisp1,
> -		     arg->meas_window.h_offs, RKISP1_CIF_ISP_EXP_H_OFFSET);
> +		     arg->meas_window.h_offs, RKISP1_CIF_ISP_EXP_H_OFFSET_V10);
>   	rkisp1_write(params->rkisp1,
> -		     arg->meas_window.v_offs, RKISP1_CIF_ISP_EXP_V_OFFSET);
> +		     arg->meas_window.v_offs, RKISP1_CIF_ISP_EXP_V_OFFSET_V10);
>   
>   	block_hsize = arg->meas_window.h_size /
> -		      RKISP1_CIF_ISP_EXP_COLUMN_NUM - 1;
> +		      RKISP1_CIF_ISP_EXP_COLUMN_NUM_V10 - 1;
>   	block_vsize = arg->meas_window.v_size /
> -		      RKISP1_CIF_ISP_EXP_ROW_NUM - 1;
> +		      RKISP1_CIF_ISP_EXP_ROW_NUM_V10 - 1;
> +
> +	rkisp1_write(params->rkisp1,
> +		     RKISP1_CIF_ISP_EXP_H_SIZE_SET_V10(block_hsize),
> +		     RKISP1_CIF_ISP_EXP_H_SIZE_V10);
> +	rkisp1_write(params->rkisp1,
> +		     RKISP1_CIF_ISP_EXP_V_SIZE_SET_V10(block_vsize),
> +		     RKISP1_CIF_ISP_EXP_V_SIZE_V10);
> +}
> +
> +static void rkisp1_aec_config_v12(struct rkisp1_params *params,
> +			       const struct rkisp1_cif_isp_aec_config *arg)
> +{
> +	u32 exp_ctrl;
> +	u32 block_hsize, block_vsize;
> +	u32 wnd_num_idx = 1;
> +	const u32 ae_wnd_num[] = {
> +		5, 9, 15, 15
> +	};
> +
> +	/* avoid to override the old enable value */
> +	exp_ctrl = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_EXP_CTRL);
> +	exp_ctrl &= RKISP1_CIF_ISP_EXP_ENA;
> +	if (arg->autostop)
> +		exp_ctrl |= RKISP1_CIF_ISP_EXP_CTRL_AUTOSTOP;
> +	if (arg->mode == RKISP1_CIF_ISP_EXP_MEASURING_MODE_1)
> +		exp_ctrl |= RKISP1_CIF_ISP_EXP_CTRL_MEASMODE_1;
> +	exp_ctrl |= RKISP1_CIF_ISP_EXP_CTRL_WNDNUM_SET_V12(wnd_num_idx);
> +	rkisp1_write(params->rkisp1, exp_ctrl, RKISP1_CIF_ISP_EXP_CTRL);
>   
>   	rkisp1_write(params->rkisp1,
> -		     RKISP1_CIF_ISP_EXP_H_SIZE_SET(block_hsize),
> -		     RKISP1_CIF_ISP_EXP_H_SIZE);
> +		     RKISP1_CIF_ISP_EXP_V_OFFSET_SET_V12(arg->meas_window.v_offs) |
> +		     RKISP1_CIF_ISP_EXP_H_OFFSET_SET_V12(arg->meas_window.h_offs),
> +		     RKISP1_CIF_ISP_EXP_OFFS_V12);
> +
> +	block_hsize = arg->meas_window.h_size / ae_wnd_num[wnd_num_idx] - 1;
> +	block_vsize = arg->meas_window.v_size / ae_wnd_num[wnd_num_idx] - 1;
> +
>   	rkisp1_write(params->rkisp1,
> -		     RKISP1_CIF_ISP_EXP_V_SIZE_SET(block_vsize),
> -		     RKISP1_CIF_ISP_EXP_V_SIZE);
> +		     RKISP1_CIF_ISP_EXP_V_SIZE_SET_V12(block_vsize) |
> +		     RKISP1_CIF_ISP_EXP_H_SIZE_SET_V12(block_hsize),
> +		     RKISP1_CIF_ISP_EXP_SIZE_V12);
>   }
>   
>   static void rkisp1_cproc_config(struct rkisp1_params *params,
> @@ -578,72 +784,154 @@ static void rkisp1_cproc_config(struct rkisp1_params *params,
>   	}
>   }
>   
> -static void rkisp1_hst_config(struct rkisp1_params *params,
> -			      const struct rkisp1_cif_isp_hst_config *arg)
> +static void rkisp1_hst_config_v10(struct rkisp1_params *params,
> +				  const struct rkisp1_cif_isp_hst_config *arg)
>   {
>   	unsigned int block_hsize, block_vsize;
>   	static const u32 hist_weight_regs[] = {
> -		RKISP1_CIF_ISP_HIST_WEIGHT_00TO30,
> -		RKISP1_CIF_ISP_HIST_WEIGHT_40TO21,
> -		RKISP1_CIF_ISP_HIST_WEIGHT_31TO12,
> -		RKISP1_CIF_ISP_HIST_WEIGHT_22TO03,
> -		RKISP1_CIF_ISP_HIST_WEIGHT_13TO43,
> -		RKISP1_CIF_ISP_HIST_WEIGHT_04TO34,
> -		RKISP1_CIF_ISP_HIST_WEIGHT_44,
> +		RKISP1_CIF_ISP_HIST_WEIGHT_00TO30_V10,
> +		RKISP1_CIF_ISP_HIST_WEIGHT_40TO21_V10,
> +		RKISP1_CIF_ISP_HIST_WEIGHT_31TO12_V10,
> +		RKISP1_CIF_ISP_HIST_WEIGHT_22TO03_V10,
> +		RKISP1_CIF_ISP_HIST_WEIGHT_13TO43_V10,
> +		RKISP1_CIF_ISP_HIST_WEIGHT_04TO34_V10,
> +		RKISP1_CIF_ISP_HIST_WEIGHT_44_V10,
>   	};
>   	const u8 *weight;
>   	unsigned int i;
>   	u32 hist_prop;
>   
>   	/* avoid to override the old enable value */
> -	hist_prop = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_HIST_PROP);
> -	hist_prop &= RKISP1_CIF_ISP_HIST_PROP_MODE_MASK;
> -	hist_prop |= RKISP1_CIF_ISP_HIST_PREDIV_SET(arg->histogram_predivider);
> -	rkisp1_write(params->rkisp1, hist_prop, RKISP1_CIF_ISP_HIST_PROP);
> +	hist_prop = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_HIST_PROP_V10);
> +	hist_prop &= RKISP1_CIF_ISP_HIST_PROP_MODE_MASK_V10;
> +	hist_prop |= RKISP1_CIF_ISP_HIST_PREDIV_SET_V10(arg->histogram_predivider);
> +	rkisp1_write(params->rkisp1, hist_prop, RKISP1_CIF_ISP_HIST_PROP_V10);
>   	rkisp1_write(params->rkisp1,
>   		     arg->meas_window.h_offs,
> -		     RKISP1_CIF_ISP_HIST_H_OFFS);
> +		     RKISP1_CIF_ISP_HIST_H_OFFS_V10);
>   	rkisp1_write(params->rkisp1,
>   		     arg->meas_window.v_offs,
> -		     RKISP1_CIF_ISP_HIST_V_OFFS);
> +		     RKISP1_CIF_ISP_HIST_V_OFFS_V10);
>   
>   	block_hsize = arg->meas_window.h_size /
> -		      RKISP1_CIF_ISP_HIST_COLUMN_NUM - 1;
> -	block_vsize = arg->meas_window.v_size / RKISP1_CIF_ISP_HIST_ROW_NUM - 1;
> +		      RKISP1_CIF_ISP_HIST_COLUMN_NUM_V10 - 1;
> +	block_vsize = arg->meas_window.v_size / RKISP1_CIF_ISP_HIST_ROW_NUM_V10 - 1;
>   
> -	rkisp1_write(params->rkisp1, block_hsize, RKISP1_CIF_ISP_HIST_H_SIZE);
> -	rkisp1_write(params->rkisp1, block_vsize, RKISP1_CIF_ISP_HIST_V_SIZE);
> +	rkisp1_write(params->rkisp1, block_hsize, RKISP1_CIF_ISP_HIST_H_SIZE_V10);
> +	rkisp1_write(params->rkisp1, block_vsize, RKISP1_CIF_ISP_HIST_V_SIZE_V10);
>   
>   	weight = arg->hist_weight;
>   	for (i = 0; i < ARRAY_SIZE(hist_weight_regs); ++i, weight += 4)
>   		rkisp1_write(params->rkisp1,
> -			     RKISP1_CIF_ISP_HIST_WEIGHT_SET(weight[0],
> +			     RKISP1_CIF_ISP_HIST_WEIGHT_SET_V10(weight[0],
>   							    weight[1],
>   							    weight[2],
>   							    weight[3]),
>   				 hist_weight_regs[i]);
>   }
>   
> +static void rkisp1_hst_config_v12(struct rkisp1_params *params,
> +				  const struct rkisp1_cif_isp_hst_config *arg)
> +{
> +	u32 i, j;
> +	u32 value;
> +	u32 hist_ctrl;
> +	u32 block_hsize, block_vsize;
> +	u32 wnd_num_idx, hist_weight_num;
> +	u8 weight15x15[RKISP1_CIF_ISP_HIST_WEIGHT_REG_SIZE_V12];
> +	const u32 hist_wnd_num[] = {
> +		5, 9, 15, 15
> +	};
> +
> +	/* now we just support 9x9 window */
> +	wnd_num_idx = 1;
> +	memset(weight15x15, 0x00, sizeof(weight15x15));
> +	/* avoid to override the old enable value */
> +	hist_ctrl = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_HIST_CTRL_V12);
> +	hist_ctrl &= RKISP1_CIF_ISP_HIST_CTRL_MODE_MASK_V12 |
> +		     RKISP1_CIF_ISP_HIST_CTRL_EN_MASK_V12;
> +	hist_ctrl = hist_ctrl |
> +		    RKISP1_CIF_ISP_HIST_CTRL_INTRSEL_SET_V12(1) |
> +		    RKISP1_CIF_ISP_HIST_CTRL_DATASEL_SET_V12(0) |
> +		    RKISP1_CIF_ISP_HIST_CTRL_WATERLINE_SET_V12(0) |
> +		    RKISP1_CIF_ISP_HIST_CTRL_AUTOSTOP_SET_V12(0) |
> +		    RKISP1_CIF_ISP_HIST_CTRL_WNDNUM_SET_V12(1) |
> +		    RKISP1_CIF_ISP_HIST_CTRL_STEPSIZE_SET_V12(arg->histogram_predivider);
> +	rkisp1_write(params->rkisp1, hist_ctrl, RKISP1_CIF_ISP_HIST_CTRL_V12);
> +
> +	rkisp1_write(params->rkisp1,
> +		     RKISP1_CIF_ISP_HIST_OFFS_SET_V12(arg->meas_window.h_offs,
> +						      arg->meas_window.v_offs),
> +		     RKISP1_CIF_ISP_HIST_OFFS_V12);
> +
> +	block_hsize = arg->meas_window.h_size / hist_wnd_num[wnd_num_idx] - 1;
> +	block_vsize = arg->meas_window.v_size / hist_wnd_num[wnd_num_idx] - 1;
> +	rkisp1_write(params->rkisp1,
> +		     RKISP1_CIF_ISP_HIST_SIZE_SET_V12(block_hsize, block_vsize),
> +		     RKISP1_CIF_ISP_HIST_SIZE_V12);
> +
> +	for (i = 0; i < hist_wnd_num[wnd_num_idx]; i++) {
> +		for (j = 0; j < hist_wnd_num[wnd_num_idx]; j++) {
> +			weight15x15[i * RKISP1_CIF_ISP_HIST_ROW_NUM_V12 + j] =
> +				arg->hist_weight[i * hist_wnd_num[wnd_num_idx] + j];
> +		}
> +	}
> +
> +	hist_weight_num = RKISP1_CIF_ISP_HIST_WEIGHT_REG_SIZE_V12;
> +	for (i = 0; i < (hist_weight_num / 4); i++) {
> +		value = RKISP1_CIF_ISP_HIST_WEIGHT_SET_V12(
> +				 weight15x15[4 * i + 0],
> +				 weight15x15[4 * i + 1],
> +				 weight15x15[4 * i + 2],
> +				 weight15x15[4 * i + 3]);
> +		rkisp1_write(params->rkisp1, value,
> +				 RKISP1_CIF_ISP_HIST_WEIGHT_V12 + 4 * i);
> +	}
> +	value = RKISP1_CIF_ISP_HIST_WEIGHT_SET_V12(weight15x15[4 * i + 0], 0, 0, 0);
> +	rkisp1_write(params->rkisp1, value,
> +				 RKISP1_CIF_ISP_HIST_WEIGHT_V12 + 4 * i);
> +}
> +
>   static void
> -rkisp1_hst_enable(struct rkisp1_params *params,
> -		  const struct rkisp1_cif_isp_hst_config *arg, bool en)
> +rkisp1_hst_enable_v10(struct rkisp1_params *params,
> +		      const struct rkisp1_cif_isp_hst_config *arg, bool en)
>   {
>   	if (en)	{
>   		u32 hist_prop = rkisp1_read(params->rkisp1,
> -					    RKISP1_CIF_ISP_HIST_PROP);
> +					    RKISP1_CIF_ISP_HIST_PROP_V10);
>   
> -		hist_prop &= ~RKISP1_CIF_ISP_HIST_PROP_MODE_MASK;
> +		hist_prop &= ~RKISP1_CIF_ISP_HIST_PROP_MODE_MASK_V10;
>   		hist_prop |= arg->mode;
> -		rkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_PROP,
> +		rkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_PROP_V10,
>   				      hist_prop);
>   	} else {
> -		rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_HIST_PROP,
> -					RKISP1_CIF_ISP_HIST_PROP_MODE_MASK);
> +		rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_HIST_PROP_V10,
> +					RKISP1_CIF_ISP_HIST_PROP_MODE_MASK_V10);
> +	}
> +}
> +
> +static void
> +rkisp1_hst_enable_v12(struct rkisp1_params *params,
> +		      const struct rkisp1_cif_isp_hst_config *arg, bool en)
> +{
> +	if (en) {
> +		u32 hist_ctrl = rkisp1_read(params->rkisp1,
> +					    RKISP1_CIF_ISP_HIST_CTRL_V12);
> +
> +		hist_ctrl &= ~RKISP1_CIF_ISP_HIST_CTRL_MODE_MASK_V12;
> +		hist_ctrl |= RKISP1_CIF_ISP_HIST_CTRL_MODE_SET_V12(arg->mode);
> +		hist_ctrl |= RKISP1_CIF_ISP_HIST_CTRL_EN_SET_V12(1);
> +		rkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_CTRL_V12,
> +				      hist_ctrl);
> +	} else {
> +		rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_HIST_CTRL_V12,
> +					RKISP1_CIF_ISP_HIST_CTRL_MODE_MASK_V12 |
> +					RKISP1_CIF_ISP_HIST_CTRL_EN_MASK_V12);
>   	}
>   }
>   
> -static void rkisp1_afm_config(struct rkisp1_params *params,
> -			      const struct rkisp1_cif_isp_afc_config *arg)
> +static void rkisp1_afm_config_v10(struct rkisp1_params *params,
> +				  const struct rkisp1_cif_isp_afc_config *arg)
>   {
>   	size_t num_of_win = min_t(size_t, ARRAY_SIZE(arg->afm_win),
>   				  arg->num_afm_win);
> @@ -673,6 +961,45 @@ static void rkisp1_afm_config(struct rkisp1_params *params,
>   	rkisp1_write(params->rkisp1, afm_ctrl, RKISP1_CIF_ISP_AFM_CTRL);
>   }
>   
> +static void rkisp1_afm_config_v12(struct rkisp1_params *params,
> +				  const struct rkisp1_cif_isp_afc_config *arg)
> +{
> +	size_t num_of_win = min_t(size_t, ARRAY_SIZE(arg->afm_win),
> +				  arg->num_afm_win);
> +	u32 afm_ctrl = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AFM_CTRL);
> +	u32 lum_var_shift, afm_var_shift;
> +	unsigned int i;
> +
> +	/* Switch off to configure. */
> +	rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_AFM_CTRL,
> +				RKISP1_CIF_ISP_AFM_ENA);
> +
> +	for (i = 0; i < num_of_win; i++) {
> +		rkisp1_write(params->rkisp1,
> +			     RKISP1_CIF_ISP_AFM_WINDOW_X(arg->afm_win[i].h_offs) |
> +			     RKISP1_CIF_ISP_AFM_WINDOW_Y(arg->afm_win[i].v_offs),
> +			     RKISP1_CIF_ISP_AFM_LT_A + i * 8);
> +		rkisp1_write(params->rkisp1,
> +			     RKISP1_CIF_ISP_AFM_WINDOW_X(arg->afm_win[i].h_size +
> +							 arg->afm_win[i].h_offs) |
> +			     RKISP1_CIF_ISP_AFM_WINDOW_Y(arg->afm_win[i].v_size +
> +							 arg->afm_win[i].v_offs),
> +			     RKISP1_CIF_ISP_AFM_RB_A + i * 8);
> +	}
> +	rkisp1_write(params->rkisp1, arg->thres, RKISP1_CIF_ISP_AFM_THRES);
> +
> +	lum_var_shift = RKISP1_CIF_ISP_AFM_GET_LUM_SHIFT_a_V12(arg->var_shift);
> +	afm_var_shift = RKISP1_CIF_ISP_AFM_GET_AFM_SHIFT_a_V12(arg->var_shift);
> +	rkisp1_write(params->rkisp1,
> +		     RKISP1_CIF_ISP_AFM_SET_SHIFT_a_V12(lum_var_shift, afm_var_shift) |
> +		     RKISP1_CIF_ISP_AFM_SET_SHIFT_b_V12(lum_var_shift, afm_var_shift) |
> +		     RKISP1_CIF_ISP_AFM_SET_SHIFT_c_V12(lum_var_shift, afm_var_shift),
> +		     RKISP1_CIF_ISP_AFM_VAR_SHIFT);
> +
> +	/* restore afm status */
> +	rkisp1_write(params->rkisp1, afm_ctrl, RKISP1_CIF_ISP_AFM_CTRL);
> +}
> +
>   static void rkisp1_ie_config(struct rkisp1_params *params,
>   			     const struct rkisp1_cif_isp_ie_config *arg)
>   {
> @@ -1286,8 +1613,8 @@ static void rkisp1_params_config_parameter(struct rkisp1_params *params)
>   
>   	memset(hst.hist_weight, 0x01, sizeof(hst.hist_weight));
>   	params->ops->hst_config(params, &hst);
> -	rkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_PROP,
> -			      ~RKISP1_CIF_ISP_HIST_PROP_MODE_MASK |
> +	rkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_PROP_V10,
> +			      ~RKISP1_CIF_ISP_HIST_PROP_MODE_MASK_V10 |
>   			      rkisp1_hst_params_default_config.mode);
>   
>   	/* set the  range */
> @@ -1346,22 +1673,38 @@ void rkisp1_params_disable(struct rkisp1_params *params)
>   				RKISP1_CIF_ISP_DPF_MODE_EN);
>   }
>   
> -static struct rkisp1_params_ops rkisp1_params_ops = {
> -	.lsc_matrix_config = rkisp1_lsc_matrix_config,
> -	.goc_config = rkisp1_goc_config,
> -	.awb_meas_config = rkisp1_awb_meas_config,
> -	.awb_meas_enable = rkisp1_awb_meas_enable,
> -	.awb_gain_config = rkisp1_awb_gain_config,
> -	.aec_config = rkisp1_aec_config,
> -	.hst_config = rkisp1_hst_config,
> -	.hst_enable = rkisp1_hst_enable,
> -	.afm_config = rkisp1_afm_config,
> +static struct rkisp1_params_ops rkisp1_v10_params_ops = {
> +	.lsc_matrix_config = rkisp1_lsc_matrix_config_v10,
> +	.goc_config = rkisp1_goc_config_v10,
> +	.awb_meas_config = rkisp1_awb_meas_config_v10,
> +	.awb_meas_enable = rkisp1_awb_meas_enable_v10,
> +	.awb_gain_config = rkisp1_awb_gain_config_v10,
> +	.aec_config = rkisp1_aec_config_v10,
> +	.hst_config = rkisp1_hst_config_v10,
> +	.hst_enable = rkisp1_hst_enable_v10,
> +	.afm_config = rkisp1_afm_config_v10,
>   };
>   
> -static struct rkisp1_params_config rkisp1_params_config = {
> +static struct rkisp1_params_config rkisp1_v10_params_config = {
>   	.gamma_out_max_samples = 17,
>   };
>   
> +static struct rkisp1_params_ops rkisp1_v12_params_ops = {
> +	.lsc_matrix_config = rkisp1_lsc_matrix_config_v12,
> +	.goc_config = rkisp1_goc_config_v12,
> +	.awb_meas_config = rkisp1_awb_meas_config_v12,
> +	.awb_meas_enable = rkisp1_awb_meas_enable_v12,
> +	.awb_gain_config = rkisp1_awb_gain_config_v12,
> +	.aec_config = rkisp1_aec_config_v12,
> +	.hst_config = rkisp1_hst_config_v12,
> +	.hst_enable = rkisp1_hst_enable_v12,
> +	.afm_config = rkisp1_afm_config_v12,
> +};
> +
> +static struct rkisp1_params_config rkisp1_v12_params_config = {
> +	.gamma_out_max_samples = 34,
> +};
not needed

Thanks,
Dafna

> +
>   static int rkisp1_params_enum_fmt_meta_out(struct file *file, void *priv,
>   					   struct v4l2_fmtdesc *f)
>   {
> @@ -1528,8 +1871,14 @@ static void rkisp1_init_params(struct rkisp1_params *params)
>   		V4L2_META_FMT_RK_ISP1_PARAMS;
>   	params->vdev_fmt.fmt.meta.buffersize =
>   		sizeof(struct rkisp1_params_cfg);
> -	params->ops = &rkisp1_params_ops;
> -	params->config = &rkisp1_params_config;
> +
> +	if (params->rkisp1->isp_ver == RKISP1_V12) {
> +		params->ops = &rkisp1_v12_params_ops;
> +		params->config = &rkisp1_v12_params_config;
> +	} else {
> +		params->ops = &rkisp1_v10_params_ops;
> +		params->config = &rkisp1_v10_params_config;
> +	}
>   }
>   
>   int rkisp1_params_register(struct rkisp1_device *rkisp1)
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
> index 8a8d960a679c..388adee3beff 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
> @@ -212,6 +212,35 @@
>   
>   /* CCL */
>   #define RKISP1_CIF_CCL_CIF_CLK_DIS			BIT(2)
> +/* VI_ISP_CLK_CTRL */
> +#define RKISP1_CIF_CLK_CTRL_ISP_RAW			BIT(0)
> +#define RKISP1_CIF_CLK_CTRL_ISP_RGB			BIT(1)
> +#define RKISP1_CIF_CLK_CTRL_ISP_YUV			BIT(2)
> +#define RKISP1_CIF_CLK_CTRL_ISP_3A			BIT(3)
> +#define RKISP1_CIF_CLK_CTRL_MIPI_RAW			BIT(4)
> +#define RKISP1_CIF_CLK_CTRL_ISP_IE			BIT(5)
> +#define RKISP1_CIF_CLK_CTRL_RSZ_RAM			BIT(6)
> +#define RKISP1_CIF_CLK_CTRL_JPEG_RAM			BIT(7)
> +#define RKISP1_CIF_CLK_CTRL_ACLK_ISP			BIT(8)
> +#define RKISP1_CIF_CLK_CTRL_MI_IDC			BIT(9)
> +#define RKISP1_CIF_CLK_CTRL_MI_MP			BIT(10)
> +#define RKISP1_CIF_CLK_CTRL_MI_JPEG			BIT(11)
> +#define RKISP1_CIF_CLK_CTRL_MI_DP			BIT(12)
> +#define RKISP1_CIF_CLK_CTRL_MI_Y12			BIT(13)
> +#define RKISP1_CIF_CLK_CTRL_MI_SP			BIT(14)
> +#define RKISP1_CIF_CLK_CTRL_MI_RAW0			BIT(15)
> +#define RKISP1_CIF_CLK_CTRL_MI_RAW1			BIT(16)
> +#define RKISP1_CIF_CLK_CTRL_MI_READ			BIT(17)
> +#define RKISP1_CIF_CLK_CTRL_MI_RAWRD			BIT(18)
> +#define RKISP1_CIF_CLK_CTRL_CP				BIT(19)
> +#define RKISP1_CIF_CLK_CTRL_IE				BIT(20)
> +#define RKISP1_CIF_CLK_CTRL_SI				BIT(21)
> +#define RKISP1_CIF_CLK_CTRL_RSZM			BIT(22)
> +#define RKISP1_CIF_CLK_CTRL_DPMUX			BIT(23)
> +#define RKISP1_CIF_CLK_CTRL_JPEG			BIT(24)
> +#define RKISP1_CIF_CLK_CTRL_RSZS			BIT(25)
> +#define RKISP1_CIF_CLK_CTRL_MIPI			BIT(26)
> +#define RKISP1_CIF_CLK_CTRL_MARVINMI			BIT(27)
>   /* ICCL */
>   #define RKISP1_CIF_ICCL_ISP_CLK				BIT(0)
>   #define RKISP1_CIF_ICCL_CP_CLK				BIT(1)
> @@ -346,25 +375,57 @@
>   #define RKISP1_CIF_SUPER_IMP_CTRL_TRANSP_DIS		BIT(2)
>   
>   /* ISP HISTOGRAM CALCULATION : ISP_HIST_PROP */
> -#define RKISP1_CIF_ISP_HIST_PROP_MODE_DIS		(0 << 0)
> -#define RKISP1_CIF_ISP_HIST_PROP_MODE_RGB		BIT(0)
> -#define RKISP1_CIF_ISP_HIST_PROP_MODE_RED		(2 << 0)
> -#define RKISP1_CIF_ISP_HIST_PROP_MODE_GREEN		(3 << 0)
> -#define RKISP1_CIF_ISP_HIST_PROP_MODE_BLUE		(4 << 0)
> -#define RKISP1_CIF_ISP_HIST_PROP_MODE_LUM		(5 << 0)
> -#define RKISP1_CIF_ISP_HIST_PROP_MODE_MASK		0x7
> -#define RKISP1_CIF_ISP_HIST_PREDIV_SET(x)		(((x) & 0x7F) << 3)
> -#define RKISP1_CIF_ISP_HIST_WEIGHT_SET(v0, v1, v2, v3)	\
> +#define RKISP1_CIF_ISP_HIST_PROP_MODE_DIS_V10		(0 << 0)
> +#define RKISP1_CIF_ISP_HIST_PROP_MODE_RGB_V10		BIT(0)
> +#define RKISP1_CIF_ISP_HIST_PROP_MODE_RED_V10		(2 << 0)
> +#define RKISP1_CIF_ISP_HIST_PROP_MODE_GREEN_V10		(3 << 0)
> +#define RKISP1_CIF_ISP_HIST_PROP_MODE_BLUE_V10		(4 << 0)
> +#define RKISP1_CIF_ISP_HIST_PROP_MODE_LUM_V10		(5 << 0)
> +#define RKISP1_CIF_ISP_HIST_PROP_MODE_MASK_V10		0x7
> +#define RKISP1_CIF_ISP_HIST_PREDIV_SET_V10(x)		(((x) & 0x7F) << 3)
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_SET_V10(v0, v1, v2, v3)	\
>   				     (((v0) & 0x1F) | (((v1) & 0x1F) << 8)  |\
>   				     (((v2) & 0x1F) << 16) | \
>   				     (((v3) & 0x1F) << 24))
>   
> -#define RKISP1_CIF_ISP_HIST_WINDOW_OFFSET_RESERVED	0xFFFFF000
> -#define RKISP1_CIF_ISP_HIST_WINDOW_SIZE_RESERVED	0xFFFFF800
> -#define RKISP1_CIF_ISP_HIST_WEIGHT_RESERVED		0xE0E0E0E0
> -#define RKISP1_CIF_ISP_MAX_HIST_PREDIVIDER		0x0000007F
> -#define RKISP1_CIF_ISP_HIST_ROW_NUM			5
> -#define RKISP1_CIF_ISP_HIST_COLUMN_NUM			5
> +#define RKISP1_CIF_ISP_HIST_WINDOW_OFFSET_RESERVED_V10	0xFFFFF000
> +#define RKISP1_CIF_ISP_HIST_WINDOW_SIZE_RESERVED_V10	0xFFFFF800
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_RESERVED_V10		0xE0E0E0E0
> +#define RKISP1_CIF_ISP_MAX_HIST_PREDIVIDER_V10		0x0000007F
> +#define RKISP1_CIF_ISP_HIST_ROW_NUM_V10			5
> +#define RKISP1_CIF_ISP_HIST_COLUMN_NUM_V10		5
> +
> +/* ISP HISTOGRAM CALCULATION : CIF_ISP_HIST */
> +#define RKISP1_CIF_ISP_HIST_CTRL_EN_SET_V12(x)		(((x) & 0x01) << 0)
> +#define RKISP1_CIF_ISP_HIST_CTRL_EN_MASK_V12		RKISP1_CIF_ISP_HIST_CTRL_EN_SET_V12(0x01)
> +#define RKISP1_CIF_ISP_HIST_CTRL_STEPSIZE_SET_V12(x)	(((x) & 0x7F) << 1)
> +#define RKISP1_CIF_ISP_HIST_CTRL_MODE_SET_V12(x)	(((x) & 0x07) << 8)
> +#define RKISP1_CIF_ISP_HIST_CTRL_MODE_MASK_V12		RKISP1_CIF_ISP_HIST_CTRL_MODE_SET_V12(0x07)
> +#define RKISP1_CIF_ISP_HIST_CTRL_AUTOSTOP_SET_V12(x)	(((x) & 0x01) << 11)
> +#define RKISP1_CIF_ISP_HIST_CTRL_WATERLINE_SET_V12(x)	(((x) & 0xFFF) << 12)
> +#define RKISP1_CIF_ISP_HIST_CTRL_DATASEL_SET_V12(x)	(((x) & 0x07) << 24)
> +#define RKISP1_CIF_ISP_HIST_CTRL_INTRSEL_SET_V12(x)	(((x) & 0x01) << 27)
> +#define RKISP1_CIF_ISP_HIST_CTRL_WNDNUM_SET_V12(x)	(((x) & 0x03) << 28)
> +#define RKISP1_CIF_ISP_HIST_CTRL_DBGEN_SET_V12(x)	(((x) & 0x01) << 30)
> +#define RKISP1_CIF_ISP_HIST_ROW_NUM_V12		15
> +#define RKISP1_CIF_ISP_HIST_COLUMN_NUM_V12		15
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_REG_SIZE_V12	\
> +				(RKISP1_CIF_ISP_HIST_ROW_NUM_V12 * RKISP1_CIF_ISP_HIST_COLUMN_NUM_V12)
> +
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_SET_V12(v0, v1, v2, v3)	\
> +				(((v0) & 0x3F) | (((v1) & 0x3F) << 8) |\
> +				(((v2) & 0x3F) << 16) |\
> +				(((v3) & 0x3F) << 24))
> +
> +#define RKISP1_CIF_ISP_HIST_OFFS_SET_V12(v0, v1)	\
> +				(((v0) & 0x1FFF) | (((v1) & 0x1FFF) << 16))
> +#define RKISP1_CIF_ISP_HIST_SIZE_SET_V12(v0, v1)	\
> +				(((v0) & 0x7FF) | (((v1) & 0x7FF) << 16))
> +
> +#define RKISP1_CIF_ISP_HIST_GET_BIN0_V12(x)	\
> +				((x) & 0xFFFF)
> +#define RKISP1_CIF_ISP_HIST_GET_BIN1_V12(x)	\
> +				(((x) >> 16) & 0xFFFF)
>   
>   /* AUTO FOCUS MEASUREMENT:  ISP_AFM_CTRL */
>   #define RKISP1_ISP_AFM_CTRL_ENABLE			BIT(0)
> @@ -400,6 +461,8 @@
>   #define RKISP1_CIF_ISP_AWB_MODE_YCBCR_EN		((0 << 31) | (0x2 << 0))
>   #define RKISP1_CIF_ISP_AWB_MODE_MASK_NONE		0xFFFFFFFC
>   #define RKISP1_CIF_ISP_AWB_MODE_READ(x)			((x) & 3)
> +#define RKISP1_CIF_ISP_AWB_SET_FRAMES_V12(x)		(((x) & 0x07) << 28)
> +#define RKISP1_CIF_ISP_AWB_SET_FRAMES_MASK_V12		RKISP1_CIF_ISP_AWB_SET_FRAMES_V12(0x07)
>   /* ISP_AWB_GAIN_RB, ISP_AWB_GAIN_G  */
>   #define RKISP1_CIF_ISP_AWB_GAIN_R_SET(x)		(((x) & 0x3FF) << 16)
>   #define RKISP1_CIF_ISP_AWB_GAIN_R_READ(x)		(((x) >> 16) & 0x3FF)
> @@ -434,6 +497,7 @@
>   /* ISP_EXP_CTRL */
>   #define RKISP1_CIF_ISP_EXP_ENA				BIT(0)
>   #define RKISP1_CIF_ISP_EXP_CTRL_AUTOSTOP		BIT(1)
> +#define RKISP1_CIF_ISP_EXP_CTRL_WNDNUM_SET_V12(x)	(((x) & 0x03) << 2)
>   /*
>    *'1' luminance calculation according to  Y=(R+G+B) x 0.332 (85/256)
>    *'0' luminance calculation according to Y=16+0.25R+0.5G+0.1094B
> @@ -441,42 +505,76 @@
>   #define RKISP1_CIF_ISP_EXP_CTRL_MEASMODE_1		BIT(31)
>   
>   /* ISP_EXP_H_SIZE */
> -#define RKISP1_CIF_ISP_EXP_H_SIZE_SET(x)		((x) & 0x7FF)
> -#define RKISP1_CIF_ISP_EXP_HEIGHT_MASK			0x000007FF
> +#define RKISP1_CIF_ISP_EXP_H_SIZE_SET_V10(x)		((x) & 0x7FF)
> +#define RKISP1_CIF_ISP_EXP_HEIGHT_MASK_V10			0x000007FF
> +#define RKISP1_CIF_ISP_EXP_H_SIZE_SET_V12(x)		((x) & 0x7FF)
> +#define RKISP1_CIF_ISP_EXP_HEIGHT_MASK_V12		0x000007FF
>   /* ISP_EXP_V_SIZE : vertical size must be a multiple of 2). */
> -#define RKISP1_CIF_ISP_EXP_V_SIZE_SET(x)		((x) & 0x7FE)
> +#define RKISP1_CIF_ISP_EXP_V_SIZE_SET_V10(x)		((x) & 0x7FE)
> +#define RKISP1_CIF_ISP_EXP_V_SIZE_SET_V12(x)		(((x) & 0x7FE) << 16)
>   
>   /* ISP_EXP_H_OFFSET */
> -#define RKISP1_CIF_ISP_EXP_H_OFFSET_SET(x)		((x) & 0x1FFF)
> -#define RKISP1_CIF_ISP_EXP_MAX_HOFFS			2424
> +#define RKISP1_CIF_ISP_EXP_H_OFFSET_SET_V10(x)		((x) & 0x1FFF)
> +#define RKISP1_CIF_ISP_EXP_MAX_HOFFS_V10		2424
> +#define RKISP1_CIF_ISP_EXP_H_OFFSET_SET_V12(x)		((x) & 0x1FFF)
> +#define RKISP1_CIF_ISP_EXP_MAX_HOFFS_V12		0x1FFF
>   /* ISP_EXP_V_OFFSET */
> -#define RKISP1_CIF_ISP_EXP_V_OFFSET_SET(x)		((x) & 0x1FFF)
> -#define RKISP1_CIF_ISP_EXP_MAX_VOFFS			1806
> -
> -#define RKISP1_CIF_ISP_EXP_ROW_NUM			5
> -#define RKISP1_CIF_ISP_EXP_COLUMN_NUM			5
> -#define RKISP1_CIF_ISP_EXP_NUM_LUMA_REGS \
> -	(RKISP1_CIF_ISP_EXP_ROW_NUM * RKISP1_CIF_ISP_EXP_COLUMN_NUM)
> -#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE		516
> -#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE		35
> -#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE		390
> -#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE		28
> -#define RKISP1_CIF_ISP_EXP_MAX_HSIZE	\
> -	(RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE * RKISP1_CIF_ISP_EXP_COLUMN_NUM + 1)
> -#define RKISP1_CIF_ISP_EXP_MIN_HSIZE	\
> -	(RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE * RKISP1_CIF_ISP_EXP_COLUMN_NUM + 1)
> -#define RKISP1_CIF_ISP_EXP_MAX_VSIZE	\
> -	(RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE * RKISP1_CIF_ISP_EXP_ROW_NUM + 1)
> -#define RKISP1_CIF_ISP_EXP_MIN_VSIZE	\
> -	(RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE * RKISP1_CIF_ISP_EXP_ROW_NUM + 1)
> +#define RKISP1_CIF_ISP_EXP_V_OFFSET_SET_V10(x)		((x) & 0x1FFF)
> +#define RKISP1_CIF_ISP_EXP_MAX_VOFFS_V10		1806
> +#define RKISP1_CIF_ISP_EXP_V_OFFSET_SET_V12(x)		(((x) & 0x1FFF) << 16)
> +#define RKISP1_CIF_ISP_EXP_MAX_VOFFS_V12		0x1FFF
> +
> +#define RKISP1_CIF_ISP_EXP_ROW_NUM_V10			5
> +#define RKISP1_CIF_ISP_EXP_COLUMN_NUM_V10			5
> +#define RKISP1_CIF_ISP_EXP_NUM_LUMA_REGS_V10 \
> +	(RKISP1_CIF_ISP_EXP_ROW_NUM_V10 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V10)
> +#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE_V10		516
> +#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE_V10		35
> +#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE_V10		390
> +#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE_V10		28
> +#define RKISP1_CIF_ISP_EXP_MAX_HSIZE_V10	\
> +	(RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE_V10 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V10 + 1)
> +#define RKISP1_CIF_ISP_EXP_MIN_HSIZE_V10	\
> +	(RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE_V10 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V10 + 1)
> +#define RKISP1_CIF_ISP_EXP_MAX_VSIZE_V10	\
> +	(RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE_V10 * RKISP1_CIF_ISP_EXP_ROW_NUM_V10 + 1)
> +#define RKISP1_CIF_ISP_EXP_MIN_VSIZE_V10	\
> +	(RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE_V10 * RKISP1_CIF_ISP_EXP_ROW_NUM_V10 + 1)
> +
> +#define RKISP1_CIF_ISP_EXP_ROW_NUM_V12			15
> +#define RKISP1_CIF_ISP_EXP_COLUMN_NUM_V12		15
> +#define RKISP1_CIF_ISP_EXP_NUM_LUMA_REGS_V12 \
> +	(RKISP1_CIF_ISP_EXP_ROW_NUM_V12 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V12)
> +
> +#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE_V12		0x7FF
> +#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE_V12		0xE
> +#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE_V12		0x7FE
> +#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE_V12		0xE
> +#define RKISP1_CIF_ISP_EXP_MAX_HSIZE_V12	\
> +	(RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE_V12 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V12 + 1)
> +#define RKISP1_CIF_ISP_EXP_MIN_HSIZE_V12	\
> +	(RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE_V12 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V12 + 1)
> +#define RKISP1_CIF_ISP_EXP_MAX_VSIZE_V12	\
> +	(RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE_V12 * RKISP1_CIF_ISP_EXP_ROW_NUM_V12 + 1)
> +#define RKISP1_CIF_ISP_EXP_MIN_VSIZE_V12	\
> +	(RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE_V12 * RKISP1_CIF_ISP_EXP_ROW_NUM_V12 + 1)
> +
> +#define RKISP1_CIF_ISP_EXP_GET_MEAN_xy0_V12(x)		((x) & 0xFF)
> +#define RKISP1_CIF_ISP_EXP_GET_MEAN_xy1_V12(x)		(((x) >> 8) & 0xFF)
> +#define RKISP1_CIF_ISP_EXP_GET_MEAN_xy2_V12(x)		(((x) >> 16) & 0xFF)
> +#define RKISP1_CIF_ISP_EXP_GET_MEAN_xy3_V12(x)		(((x) >> 24) & 0xFF)
>   
>   /* LSC: ISP_LSC_CTRL */
>   #define RKISP1_CIF_ISP_LSC_CTRL_ENA			BIT(0)
>   #define RKISP1_CIF_ISP_LSC_SECT_SIZE_RESERVED		0xFC00FC00
> -#define RKISP1_CIF_ISP_LSC_GRAD_RESERVED		0xF000F000
> -#define RKISP1_CIF_ISP_LSC_SAMPLE_RESERVED		0xF000F000
> -#define RKISP1_CIF_ISP_LSC_TABLE_DATA(v0, v1)     \
> +#define RKISP1_CIF_ISP_LSC_GRAD_RESERVED_V10		0xF000F000
> +#define RKISP1_CIF_ISP_LSC_SAMPLE_RESERVED_V10		0xF000F000
> +#define RKISP1_CIF_ISP_LSC_GRAD_RESERVED_V12		0xE000E000
> +#define RKISP1_CIF_ISP_LSC_SAMPLE_RESERVED_V12		0xE000E000
> +#define RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(v0, v1)     \
>   	(((v0) & 0xFFF) | (((v1) & 0xFFF) << 12))
> +#define RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(v0, v1)     \
> +	(((v0) & 0x1FFF) | (((v1) & 0x1FFF) << 13))
>   #define RKISP1_CIF_ISP_LSC_SECT_SIZE(v0, v1)      \
>   	(((v0) & 0xFFF) | (((v1) & 0xFFF) << 16))
>   #define RKISP1_CIF_ISP_LSC_GRAD_SIZE(v0, v1)      \
> @@ -549,6 +647,10 @@
>   	(1 << 15) | (1 << 11) | (1 << 7) | (1 << 3))
>   #define RKISP1_CIFISP_DEGAMMA_Y_RESERVED		0xFFFFF000
>   
> +/* GAMMA-OUT */
> +#define RKISP1_CIF_ISP_GAMMA_VALUE_V12(x, y)	\
> +	(((x) & 0xFFF) << 16 | ((y) & 0xFFF) << 0)
> +
>   /* AFM */
>   #define RKISP1_CIF_ISP_AFM_ENA				BIT(0)
>   #define RKISP1_CIF_ISP_AFM_THRES_RESERVED		0xFFFF0000
> @@ -559,6 +661,11 @@
>   #define RKISP1_CIF_ISP_AFM_WINDOW_Y_MIN			0x2
>   #define RKISP1_CIF_ISP_AFM_WINDOW_X(x)			(((x) & 0x1FFF) << 16)
>   #define RKISP1_CIF_ISP_AFM_WINDOW_Y(x)			((x) & 0x1FFF)
> +#define RKISP1_CIF_ISP_AFM_SET_SHIFT_a_V12(x, y)	(((x) & 0x7) << 16 | ((y) & 0x7) << 0)
> +#define RKISP1_CIF_ISP_AFM_SET_SHIFT_b_V12(x, y)	(((x) & 0x7) << 20 | ((y) & 0x7) << 4)
> +#define RKISP1_CIF_ISP_AFM_SET_SHIFT_c_V12(x, y)	(((x) & 0x7) << 24 | ((y) & 0x7) << 8)
> +#define RKISP1_CIF_ISP_AFM_GET_LUM_SHIFT_a_V12(x)	(((x) & 0x70000) >> 16)
> +#define RKISP1_CIF_ISP_AFM_GET_AFM_SHIFT_a_V12(x)	((x) & 0x7)
>   
>   /* DPF */
>   #define RKISP1_CIF_ISP_DPF_MODE_EN			BIT(0)
> @@ -581,6 +688,7 @@
>   #define RKISP1_CIF_CTRL_BASE			0x00000000
>   #define RKISP1_CIF_CCL				(RKISP1_CIF_CTRL_BASE + 0x00000000)
>   #define RKISP1_CIF_VI_ID			(RKISP1_CIF_CTRL_BASE + 0x00000008)
> +#define RKISP1_CIF_VI_ISP_CLK_CTRL_V12		(RKISP1_CIF_CTRL_BASE + 0x0000000C)
>   #define RKISP1_CIF_ICCL				(RKISP1_CIF_CTRL_BASE + 0x00000010)
>   #define RKISP1_CIF_IRCL				(RKISP1_CIF_CTRL_BASE + 0x00000014)
>   #define RKISP1_CIF_VI_DPCL			(RKISP1_CIF_CTRL_BASE + 0x00000018)
> @@ -666,18 +774,35 @@
>   #define RKISP1_CIF_ISP_GAMMA_B_Y14		(RKISP1_CIF_ISP_BASE + 0x000000E4)
>   #define RKISP1_CIF_ISP_GAMMA_B_Y15		(RKISP1_CIF_ISP_BASE + 0x000000E8)
>   #define RKISP1_CIF_ISP_GAMMA_B_Y16		(RKISP1_CIF_ISP_BASE + 0x000000EC)
> -#define RKISP1_CIF_ISP_AWB_PROP			(RKISP1_CIF_ISP_BASE + 0x00000110)
> -#define RKISP1_CIF_ISP_AWB_WND_H_OFFS		(RKISP1_CIF_ISP_BASE + 0x00000114)
> -#define RKISP1_CIF_ISP_AWB_WND_V_OFFS		(RKISP1_CIF_ISP_BASE + 0x00000118)
> -#define RKISP1_CIF_ISP_AWB_WND_H_SIZE		(RKISP1_CIF_ISP_BASE + 0x0000011C)
> -#define RKISP1_CIF_ISP_AWB_WND_V_SIZE		(RKISP1_CIF_ISP_BASE + 0x00000120)
> -#define RKISP1_CIF_ISP_AWB_FRAMES		(RKISP1_CIF_ISP_BASE + 0x00000124)
> -#define RKISP1_CIF_ISP_AWB_REF			(RKISP1_CIF_ISP_BASE + 0x00000128)
> -#define RKISP1_CIF_ISP_AWB_THRESH		(RKISP1_CIF_ISP_BASE + 0x0000012C)
> -#define RKISP1_CIF_ISP_AWB_GAIN_G		(RKISP1_CIF_ISP_BASE + 0x00000138)
> -#define RKISP1_CIF_ISP_AWB_GAIN_RB		(RKISP1_CIF_ISP_BASE + 0x0000013C)
> -#define RKISP1_CIF_ISP_AWB_WHITE_CNT		(RKISP1_CIF_ISP_BASE + 0x00000140)
> -#define RKISP1_CIF_ISP_AWB_MEAN			(RKISP1_CIF_ISP_BASE + 0x00000144)
> +#define RKISP1_CIF_ISP_AWB_PROP_V10		(RKISP1_CIF_ISP_BASE + 0x00000110)
> +#define RKISP1_CIF_ISP_AWB_WND_H_OFFS_V10	(RKISP1_CIF_ISP_BASE + 0x00000114)
> +#define RKISP1_CIF_ISP_AWB_WND_V_OFFS_V10	(RKISP1_CIF_ISP_BASE + 0x00000118)
> +#define RKISP1_CIF_ISP_AWB_WND_H_SIZE_V10	(RKISP1_CIF_ISP_BASE + 0x0000011C)
> +#define RKISP1_CIF_ISP_AWB_WND_V_SIZE_V10	(RKISP1_CIF_ISP_BASE + 0x00000120)
> +#define RKISP1_CIF_ISP_AWB_FRAMES_V10		(RKISP1_CIF_ISP_BASE + 0x00000124)
> +#define RKISP1_CIF_ISP_AWB_REF_V10		(RKISP1_CIF_ISP_BASE + 0x00000128)
> +#define RKISP1_CIF_ISP_AWB_THRESH_V10		(RKISP1_CIF_ISP_BASE + 0x0000012C)
> +#define RKISP1_CIF_ISP_AWB_GAIN_G_V10		(RKISP1_CIF_ISP_BASE + 0x00000138)
> +#define RKISP1_CIF_ISP_AWB_GAIN_RB_V10		(RKISP1_CIF_ISP_BASE + 0x0000013C)
> +#define RKISP1_CIF_ISP_AWB_WHITE_CNT_V10	(RKISP1_CIF_ISP_BASE + 0x00000140)
> +#define RKISP1_CIF_ISP_AWB_MEAN_V10		(RKISP1_CIF_ISP_BASE + 0x00000144)
> +#define RKISP1_CIF_ISP_AWB_PROP_V12		(RKISP1_CIF_ISP_BASE + 0x00000110)
> +#define RKISP1_CIF_ISP_AWB_SIZE_V12		(RKISP1_CIF_ISP_BASE + 0x00000114)
> +#define RKISP1_CIF_ISP_AWB_OFFS_V12		(RKISP1_CIF_ISP_BASE + 0x00000118)
> +#define RKISP1_CIF_ISP_AWB_REF_V12		(RKISP1_CIF_ISP_BASE + 0x0000011C)
> +#define RKISP1_CIF_ISP_AWB_THRESH_V12		(RKISP1_CIF_ISP_BASE + 0x00000120)
> +#define RKISP1_CIF_ISP_X_COOR12_V12		(RKISP1_CIF_ISP_BASE + 0x00000124)
> +#define RKISP1_CIF_ISP_X_COOR34_V12		(RKISP1_CIF_ISP_BASE + 0x00000128)
> +#define RKISP1_CIF_ISP_AWB_WHITE_CNT_V12	(RKISP1_CIF_ISP_BASE + 0x0000012C)
> +#define RKISP1_CIF_ISP_AWB_MEAN_V12		(RKISP1_CIF_ISP_BASE + 0x00000130)
> +#define RKISP1_CIF_ISP_DEGAIN_V12		(RKISP1_CIF_ISP_BASE + 0x00000134)
> +#define RKISP1_CIF_ISP_AWB_GAIN_G_V12		(RKISP1_CIF_ISP_BASE + 0x00000138)
> +#define RKISP1_CIF_ISP_AWB_GAIN_RB_V12		(RKISP1_CIF_ISP_BASE + 0x0000013C)
> +#define RKISP1_CIF_ISP_REGION_LINE_V12		(RKISP1_CIF_ISP_BASE + 0x00000140)
> +#define RKISP1_CIF_ISP_WP_CNT_REGION0_V12	(RKISP1_CIF_ISP_BASE + 0x00000160)
> +#define RKISP1_CIF_ISP_WP_CNT_REGION1_V12	(RKISP1_CIF_ISP_BASE + 0x00000164)
> +#define RKISP1_CIF_ISP_WP_CNT_REGION2_V12	(RKISP1_CIF_ISP_BASE + 0x00000168)
> +#define RKISP1_CIF_ISP_WP_CNT_REGION3_V12	(RKISP1_CIF_ISP_BASE + 0x0000016C)
>   #define RKISP1_CIF_ISP_CC_COEFF_0		(RKISP1_CIF_ISP_BASE + 0x00000170)
>   #define RKISP1_CIF_ISP_CC_COEFF_1		(RKISP1_CIF_ISP_BASE + 0x00000174)
>   #define RKISP1_CIF_ISP_CC_COEFF_2		(RKISP1_CIF_ISP_BASE + 0x00000178)
> @@ -711,30 +836,32 @@
>   #define RKISP1_CIF_ISP_CT_COEFF_6		(RKISP1_CIF_ISP_BASE + 0x000001E8)
>   #define RKISP1_CIF_ISP_CT_COEFF_7		(RKISP1_CIF_ISP_BASE + 0x000001EC)
>   #define RKISP1_CIF_ISP_CT_COEFF_8		(RKISP1_CIF_ISP_BASE + 0x000001F0)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_MODE		(RKISP1_CIF_ISP_BASE + 0x000001F4)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_0		(RKISP1_CIF_ISP_BASE + 0x000001F8)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_1		(RKISP1_CIF_ISP_BASE + 0x000001FC)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_2		(RKISP1_CIF_ISP_BASE + 0x00000200)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_3		(RKISP1_CIF_ISP_BASE + 0x00000204)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_4		(RKISP1_CIF_ISP_BASE + 0x00000208)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_5		(RKISP1_CIF_ISP_BASE + 0x0000020C)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_6		(RKISP1_CIF_ISP_BASE + 0x00000210)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_7		(RKISP1_CIF_ISP_BASE + 0x00000214)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_8		(RKISP1_CIF_ISP_BASE + 0x00000218)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_9		(RKISP1_CIF_ISP_BASE + 0x0000021C)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_10		(RKISP1_CIF_ISP_BASE + 0x00000220)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_11		(RKISP1_CIF_ISP_BASE + 0x00000224)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_12		(RKISP1_CIF_ISP_BASE + 0x00000228)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_13		(RKISP1_CIF_ISP_BASE + 0x0000022C)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_14		(RKISP1_CIF_ISP_BASE + 0x00000230)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_15		(RKISP1_CIF_ISP_BASE + 0x00000234)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_16		(RKISP1_CIF_ISP_BASE + 0x00000238)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_MODE_V10	(RKISP1_CIF_ISP_BASE + 0x000001F4)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_0_V10	(RKISP1_CIF_ISP_BASE + 0x000001F8)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_1_V10	(RKISP1_CIF_ISP_BASE + 0x000001FC)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_2_V10	(RKISP1_CIF_ISP_BASE + 0x00000200)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_3_V10	(RKISP1_CIF_ISP_BASE + 0x00000204)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_4_V10	(RKISP1_CIF_ISP_BASE + 0x00000208)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_5_V10	(RKISP1_CIF_ISP_BASE + 0x0000020C)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_6_V10	(RKISP1_CIF_ISP_BASE + 0x00000210)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_7_V10	(RKISP1_CIF_ISP_BASE + 0x00000214)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_8_V10	(RKISP1_CIF_ISP_BASE + 0x00000218)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_9_V10	(RKISP1_CIF_ISP_BASE + 0x0000021C)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_10_V10	(RKISP1_CIF_ISP_BASE + 0x00000220)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_11_V10	(RKISP1_CIF_ISP_BASE + 0x00000224)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_12_V10	(RKISP1_CIF_ISP_BASE + 0x00000228)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_13_V10	(RKISP1_CIF_ISP_BASE + 0x0000022C)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_14_V10	(RKISP1_CIF_ISP_BASE + 0x00000230)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_15_V10	(RKISP1_CIF_ISP_BASE + 0x00000234)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_16_V10	(RKISP1_CIF_ISP_BASE + 0x00000238)
>   #define RKISP1_CIF_ISP_ERR			(RKISP1_CIF_ISP_BASE + 0x0000023C)
>   #define RKISP1_CIF_ISP_ERR_CLR			(RKISP1_CIF_ISP_BASE + 0x00000240)
>   #define RKISP1_CIF_ISP_FRAME_COUNT		(RKISP1_CIF_ISP_BASE + 0x00000244)
>   #define RKISP1_CIF_ISP_CT_OFFSET_R		(RKISP1_CIF_ISP_BASE + 0x00000248)
>   #define RKISP1_CIF_ISP_CT_OFFSET_G		(RKISP1_CIF_ISP_BASE + 0x0000024C)
>   #define RKISP1_CIF_ISP_CT_OFFSET_B		(RKISP1_CIF_ISP_BASE + 0x00000250)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_MODE_V12	(RKISP1_CIF_ISP_BASE + 0x00000300)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_0_V12	(RKISP1_CIF_ISP_BASE + 0x00000304)
>   
>   #define RKISP1_CIF_ISP_FLASH_BASE		0x00000660
>   #define RKISP1_CIF_ISP_FLASH_CMD		(RKISP1_CIF_ISP_FLASH_BASE + 0x00000000)
> @@ -1004,36 +1131,35 @@
>   #define RKISP1_CIF_ISP_IS_H_SIZE_SHD		(RKISP1_CIF_ISP_IS_BASE + 0x0000002C)
>   #define RKISP1_CIF_ISP_IS_V_SIZE_SHD		(RKISP1_CIF_ISP_IS_BASE + 0x00000030)
>   
> -#define RKISP1_CIF_ISP_HIST_BASE		0x00002400
> -
> -#define RKISP1_CIF_ISP_HIST_PROP		(RKISP1_CIF_ISP_HIST_BASE + 0x00000000)
> -#define RKISP1_CIF_ISP_HIST_H_OFFS		(RKISP1_CIF_ISP_HIST_BASE + 0x00000004)
> -#define RKISP1_CIF_ISP_HIST_V_OFFS		(RKISP1_CIF_ISP_HIST_BASE + 0x00000008)
> -#define RKISP1_CIF_ISP_HIST_H_SIZE		(RKISP1_CIF_ISP_HIST_BASE + 0x0000000C)
> -#define RKISP1_CIF_ISP_HIST_V_SIZE		(RKISP1_CIF_ISP_HIST_BASE + 0x00000010)
> -#define RKISP1_CIF_ISP_HIST_BIN_0		(RKISP1_CIF_ISP_HIST_BASE + 0x00000014)
> -#define RKISP1_CIF_ISP_HIST_BIN_1		(RKISP1_CIF_ISP_HIST_BASE + 0x00000018)
> -#define RKISP1_CIF_ISP_HIST_BIN_2		(RKISP1_CIF_ISP_HIST_BASE + 0x0000001C)
> -#define RKISP1_CIF_ISP_HIST_BIN_3		(RKISP1_CIF_ISP_HIST_BASE + 0x00000020)
> -#define RKISP1_CIF_ISP_HIST_BIN_4		(RKISP1_CIF_ISP_HIST_BASE + 0x00000024)
> -#define RKISP1_CIF_ISP_HIST_BIN_5		(RKISP1_CIF_ISP_HIST_BASE + 0x00000028)
> -#define RKISP1_CIF_ISP_HIST_BIN_6		(RKISP1_CIF_ISP_HIST_BASE + 0x0000002C)
> -#define RKISP1_CIF_ISP_HIST_BIN_7		(RKISP1_CIF_ISP_HIST_BASE + 0x00000030)
> -#define RKISP1_CIF_ISP_HIST_BIN_8		(RKISP1_CIF_ISP_HIST_BASE + 0x00000034)
> -#define RKISP1_CIF_ISP_HIST_BIN_9		(RKISP1_CIF_ISP_HIST_BASE + 0x00000038)
> -#define RKISP1_CIF_ISP_HIST_BIN_10		(RKISP1_CIF_ISP_HIST_BASE + 0x0000003C)
> -#define RKISP1_CIF_ISP_HIST_BIN_11		(RKISP1_CIF_ISP_HIST_BASE + 0x00000040)
> -#define RKISP1_CIF_ISP_HIST_BIN_12		(RKISP1_CIF_ISP_HIST_BASE + 0x00000044)
> -#define RKISP1_CIF_ISP_HIST_BIN_13		(RKISP1_CIF_ISP_HIST_BASE + 0x00000048)
> -#define RKISP1_CIF_ISP_HIST_BIN_14		(RKISP1_CIF_ISP_HIST_BASE + 0x0000004C)
> -#define RKISP1_CIF_ISP_HIST_BIN_15		(RKISP1_CIF_ISP_HIST_BASE + 0x00000050)
> -#define RKISP1_CIF_ISP_HIST_WEIGHT_00TO30	(RKISP1_CIF_ISP_HIST_BASE + 0x00000054)
> -#define RKISP1_CIF_ISP_HIST_WEIGHT_40TO21	(RKISP1_CIF_ISP_HIST_BASE + 0x00000058)
> -#define RKISP1_CIF_ISP_HIST_WEIGHT_31TO12	(RKISP1_CIF_ISP_HIST_BASE + 0x0000005C)
> -#define RKISP1_CIF_ISP_HIST_WEIGHT_22TO03	(RKISP1_CIF_ISP_HIST_BASE + 0x00000060)
> -#define RKISP1_CIF_ISP_HIST_WEIGHT_13TO43	(RKISP1_CIF_ISP_HIST_BASE + 0x00000064)
> -#define RKISP1_CIF_ISP_HIST_WEIGHT_04TO34	(RKISP1_CIF_ISP_HIST_BASE + 0x00000068)
> -#define RKISP1_CIF_ISP_HIST_WEIGHT_44		(RKISP1_CIF_ISP_HIST_BASE + 0x0000006C)
> +#define RKISP1_CIF_ISP_HIST_BASE_V10		0x00002400
> +#define RKISP1_CIF_ISP_HIST_PROP_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000000)
> +#define RKISP1_CIF_ISP_HIST_H_OFFS_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000004)
> +#define RKISP1_CIF_ISP_HIST_V_OFFS_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000008)
> +#define RKISP1_CIF_ISP_HIST_H_SIZE_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000000C)
> +#define RKISP1_CIF_ISP_HIST_V_SIZE_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000010)
> +#define RKISP1_CIF_ISP_HIST_BIN_0_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000014)
> +#define RKISP1_CIF_ISP_HIST_BIN_1_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000018)
> +#define RKISP1_CIF_ISP_HIST_BIN_2_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000001C)
> +#define RKISP1_CIF_ISP_HIST_BIN_3_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000020)
> +#define RKISP1_CIF_ISP_HIST_BIN_4_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000024)
> +#define RKISP1_CIF_ISP_HIST_BIN_5_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000028)
> +#define RKISP1_CIF_ISP_HIST_BIN_6_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000002C)
> +#define RKISP1_CIF_ISP_HIST_BIN_7_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000030)
> +#define RKISP1_CIF_ISP_HIST_BIN_8_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000034)
> +#define RKISP1_CIF_ISP_HIST_BIN_9_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000038)
> +#define RKISP1_CIF_ISP_HIST_BIN_10_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000003C)
> +#define RKISP1_CIF_ISP_HIST_BIN_11_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000040)
> +#define RKISP1_CIF_ISP_HIST_BIN_12_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000044)
> +#define RKISP1_CIF_ISP_HIST_BIN_13_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000048)
> +#define RKISP1_CIF_ISP_HIST_BIN_14_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000004C)
> +#define RKISP1_CIF_ISP_HIST_BIN_15_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000050)
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_00TO30_V10	(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000054)
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_40TO21_V10	(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000058)
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_31TO12_V10	(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000005C)
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_22TO03_V10	(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000060)
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_13TO43_V10	(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000064)
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_04TO34_V10	(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000068)
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_44_V10	(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000006C)
>   
>   #define RKISP1_CIF_ISP_FILT_BASE		0x00002500
>   #define RKISP1_CIF_ISP_FILT_MODE		(RKISP1_CIF_ISP_FILT_BASE + 0x00000000)
> @@ -1059,35 +1185,38 @@
>   
>   #define RKISP1_CIF_ISP_EXP_BASE			0x00002600
>   #define RKISP1_CIF_ISP_EXP_CTRL			(RKISP1_CIF_ISP_EXP_BASE + 0x00000000)
> -#define RKISP1_CIF_ISP_EXP_H_OFFSET		(RKISP1_CIF_ISP_EXP_BASE + 0x00000004)
> -#define RKISP1_CIF_ISP_EXP_V_OFFSET		(RKISP1_CIF_ISP_EXP_BASE + 0x00000008)
> -#define RKISP1_CIF_ISP_EXP_H_SIZE		(RKISP1_CIF_ISP_EXP_BASE + 0x0000000C)
> -#define RKISP1_CIF_ISP_EXP_V_SIZE		(RKISP1_CIF_ISP_EXP_BASE + 0x00000010)
> -#define RKISP1_CIF_ISP_EXP_MEAN_00		(RKISP1_CIF_ISP_EXP_BASE + 0x00000014)
> -#define RKISP1_CIF_ISP_EXP_MEAN_10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000018)
> -#define RKISP1_CIF_ISP_EXP_MEAN_20		(RKISP1_CIF_ISP_EXP_BASE + 0x0000001c)
> -#define RKISP1_CIF_ISP_EXP_MEAN_30		(RKISP1_CIF_ISP_EXP_BASE + 0x00000020)
> -#define RKISP1_CIF_ISP_EXP_MEAN_40		(RKISP1_CIF_ISP_EXP_BASE + 0x00000024)
> -#define RKISP1_CIF_ISP_EXP_MEAN_01		(RKISP1_CIF_ISP_EXP_BASE + 0x00000028)
> -#define RKISP1_CIF_ISP_EXP_MEAN_11		(RKISP1_CIF_ISP_EXP_BASE + 0x0000002c)
> -#define RKISP1_CIF_ISP_EXP_MEAN_21		(RKISP1_CIF_ISP_EXP_BASE + 0x00000030)
> -#define RKISP1_CIF_ISP_EXP_MEAN_31		(RKISP1_CIF_ISP_EXP_BASE + 0x00000034)
> -#define RKISP1_CIF_ISP_EXP_MEAN_41		(RKISP1_CIF_ISP_EXP_BASE + 0x00000038)
> -#define RKISP1_CIF_ISP_EXP_MEAN_02		(RKISP1_CIF_ISP_EXP_BASE + 0x0000003c)
> -#define RKISP1_CIF_ISP_EXP_MEAN_12		(RKISP1_CIF_ISP_EXP_BASE + 0x00000040)
> -#define RKISP1_CIF_ISP_EXP_MEAN_22		(RKISP1_CIF_ISP_EXP_BASE + 0x00000044)
> -#define RKISP1_CIF_ISP_EXP_MEAN_32		(RKISP1_CIF_ISP_EXP_BASE + 0x00000048)
> -#define RKISP1_CIF_ISP_EXP_MEAN_42		(RKISP1_CIF_ISP_EXP_BASE + 0x0000004c)
> -#define RKISP1_CIF_ISP_EXP_MEAN_03		(RKISP1_CIF_ISP_EXP_BASE + 0x00000050)
> -#define RKISP1_CIF_ISP_EXP_MEAN_13		(RKISP1_CIF_ISP_EXP_BASE + 0x00000054)
> -#define RKISP1_CIF_ISP_EXP_MEAN_23		(RKISP1_CIF_ISP_EXP_BASE + 0x00000058)
> -#define RKISP1_CIF_ISP_EXP_MEAN_33		(RKISP1_CIF_ISP_EXP_BASE + 0x0000005c)
> -#define RKISP1_CIF_ISP_EXP_MEAN_43		(RKISP1_CIF_ISP_EXP_BASE + 0x00000060)
> -#define RKISP1_CIF_ISP_EXP_MEAN_04		(RKISP1_CIF_ISP_EXP_BASE + 0x00000064)
> -#define RKISP1_CIF_ISP_EXP_MEAN_14		(RKISP1_CIF_ISP_EXP_BASE + 0x00000068)
> -#define RKISP1_CIF_ISP_EXP_MEAN_24		(RKISP1_CIF_ISP_EXP_BASE + 0x0000006c)
> -#define RKISP1_CIF_ISP_EXP_MEAN_34		(RKISP1_CIF_ISP_EXP_BASE + 0x00000070)
> -#define RKISP1_CIF_ISP_EXP_MEAN_44		(RKISP1_CIF_ISP_EXP_BASE + 0x00000074)
> +#define RKISP1_CIF_ISP_EXP_H_OFFSET_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000004)
> +#define RKISP1_CIF_ISP_EXP_V_OFFSET_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000008)
> +#define RKISP1_CIF_ISP_EXP_H_SIZE_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x0000000C)
> +#define RKISP1_CIF_ISP_EXP_V_SIZE_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000010)
> +#define RKISP1_CIF_ISP_EXP_MEAN_00_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000014)
> +#define RKISP1_CIF_ISP_EXP_MEAN_10_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000018)
> +#define RKISP1_CIF_ISP_EXP_MEAN_20_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x0000001c)
> +#define RKISP1_CIF_ISP_EXP_MEAN_30_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000020)
> +#define RKISP1_CIF_ISP_EXP_MEAN_40_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000024)
> +#define RKISP1_CIF_ISP_EXP_MEAN_01_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000028)
> +#define RKISP1_CIF_ISP_EXP_MEAN_11_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x0000002c)
> +#define RKISP1_CIF_ISP_EXP_MEAN_21_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000030)
> +#define RKISP1_CIF_ISP_EXP_MEAN_31_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000034)
> +#define RKISP1_CIF_ISP_EXP_MEAN_41_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000038)
> +#define RKISP1_CIF_ISP_EXP_MEAN_02_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x0000003c)
> +#define RKISP1_CIF_ISP_EXP_MEAN_12_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000040)
> +#define RKISP1_CIF_ISP_EXP_MEAN_22_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000044)
> +#define RKISP1_CIF_ISP_EXP_MEAN_32_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000048)
> +#define RKISP1_CIF_ISP_EXP_MEAN_42_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x0000004c)
> +#define RKISP1_CIF_ISP_EXP_MEAN_03_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000050)
> +#define RKISP1_CIF_ISP_EXP_MEAN_13_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000054)
> +#define RKISP1_CIF_ISP_EXP_MEAN_23_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000058)
> +#define RKISP1_CIF_ISP_EXP_MEAN_33_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x0000005c)
> +#define RKISP1_CIF_ISP_EXP_MEAN_43_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000060)
> +#define RKISP1_CIF_ISP_EXP_MEAN_04_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000064)
> +#define RKISP1_CIF_ISP_EXP_MEAN_14_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000068)
> +#define RKISP1_CIF_ISP_EXP_MEAN_24_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x0000006c)
> +#define RKISP1_CIF_ISP_EXP_MEAN_34_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000070)
> +#define RKISP1_CIF_ISP_EXP_MEAN_44_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000074)
> +#define RKISP1_CIF_ISP_EXP_SIZE_V12		(RKISP1_CIF_ISP_EXP_BASE + 0x00000004)
> +#define RKISP1_CIF_ISP_EXP_OFFS_V12		(RKISP1_CIF_ISP_EXP_BASE + 0x00000008)
> +#define RKISP1_CIF_ISP_EXP_MEAN_V12		(RKISP1_CIF_ISP_EXP_BASE + 0x0000000c)
>   
>   #define RKISP1_CIF_ISP_BLS_BASE			0x00002700
>   #define RKISP1_CIF_ISP_BLS_CTRL			(RKISP1_CIF_ISP_BLS_BASE + 0x00000000)
> @@ -1248,6 +1377,16 @@
>   #define RKISP1_CIF_ISP_WDR_TONECURVE_YM_31_SHD	(RKISP1_CIF_ISP_WDR_BASE + 0x0000012C)
>   #define RKISP1_CIF_ISP_WDR_TONECURVE_YM_32_SHD	(RKISP1_CIF_ISP_WDR_BASE + 0x00000130)
>   
> +#define RKISP1_CIF_ISP_HIST_BASE_V12		0x00002C00
> +#define RKISP1_CIF_ISP_HIST_CTRL_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x00000000)
> +#define RKISP1_CIF_ISP_HIST_SIZE_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x00000004)
> +#define RKISP1_CIF_ISP_HIST_OFFS_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x00000008)
> +#define RKISP1_CIF_ISP_HIST_DBG1_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x0000000C)
> +#define RKISP1_CIF_ISP_HIST_DBG2_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x0000001C)
> +#define RKISP1_CIF_ISP_HIST_DBG3_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x0000002C)
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x0000003C)
> +#define RKISP1_CIF_ISP_HIST_BIN_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x00000120)
> +
>   #define RKISP1_CIF_ISP_VSM_BASE			0x00002F00
>   #define RKISP1_CIF_ISP_VSM_MODE			(RKISP1_CIF_ISP_VSM_BASE + 0x00000000)
>   #define RKISP1_CIF_ISP_VSM_H_OFFS		(RKISP1_CIF_ISP_VSM_BASE + 0x00000004)
> @@ -1259,4 +1398,7 @@
>   #define RKISP1_CIF_ISP_VSM_DELTA_H		(RKISP1_CIF_ISP_VSM_BASE + 0x0000001C)
>   #define RKISP1_CIF_ISP_VSM_DELTA_V		(RKISP1_CIF_ISP_VSM_BASE + 0x00000020)
>   
> +#define RKISP1_CIF_ISP_CSI0_BASE		0x00007000
> +#define RKISP1_CIF_ISP_CSI0_CTRL0		(RKISP1_CIF_ISP_CSI0_BASE + 0x00000000)
> +
>   #endif /* _RKISP1_REGS_H */
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c
> index 7136292039f6..5ce1a2974b55 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c
> @@ -175,18 +175,18 @@ rkisp1_stats_init_vb2_queue(struct vb2_queue *q, struct rkisp1_stats *stats)
>   	return vb2_queue_init(q);
>   }
>   
> -static void rkisp1_stats_get_awb_meas(struct rkisp1_stats *stats,
> -				      struct rkisp1_stat_buffer *pbuf)
> +static void rkisp1_stats_get_awb_meas_v10(struct rkisp1_stats *stats,
> +					  struct rkisp1_stat_buffer *pbuf)
>   {
>   	/* Protect against concurrent access from ISR? */
>   	struct rkisp1_device *rkisp1 = stats->rkisp1;
>   	u32 reg_val;
>   
>   	pbuf->meas_type |= RKISP1_CIF_ISP_STAT_AWB;
> -	reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_WHITE_CNT);
> +	reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_WHITE_CNT_V10);
>   	pbuf->params.awb.awb_mean[0].cnt =
>   				RKISP1_CIF_ISP_AWB_GET_PIXEL_CNT(reg_val);
> -	reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_MEAN);
> +	reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_MEAN_V10);
>   
>   	pbuf->params.awb.awb_mean[0].mean_cr_or_r =
>   				RKISP1_CIF_ISP_AWB_GET_MEAN_CR_R(reg_val);
> @@ -196,8 +196,29 @@ static void rkisp1_stats_get_awb_meas(struct rkisp1_stats *stats,
>   				RKISP1_CIF_ISP_AWB_GET_MEAN_Y_G(reg_val);
>   }
>   
> -static void rkisp1_stats_get_aec_meas(struct rkisp1_stats *stats,
> -				      struct rkisp1_stat_buffer *pbuf)
> +static void rkisp1_stats_get_awb_meas_v12(struct rkisp1_stats *stats,
> +					  struct rkisp1_stat_buffer *pbuf)
> +{
> +	/* Protect against concurrent access from ISR? */
> +	struct rkisp1_device *rkisp1 = stats->rkisp1;
> +	u32 reg_val;
> +
> +	pbuf->meas_type |= RKISP1_CIF_ISP_STAT_AWB;
> +	reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_WHITE_CNT_V12);
> +	pbuf->params.awb.awb_mean[0].cnt =
> +				RKISP1_CIF_ISP_AWB_GET_PIXEL_CNT(reg_val);
> +	reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_MEAN_V12);
> +
> +	pbuf->params.awb.awb_mean[0].mean_cr_or_r =
> +				RKISP1_CIF_ISP_AWB_GET_MEAN_CR_R(reg_val);
> +	pbuf->params.awb.awb_mean[0].mean_cb_or_b =
> +				RKISP1_CIF_ISP_AWB_GET_MEAN_CB_B(reg_val);
> +	pbuf->params.awb.awb_mean[0].mean_y_or_g =
> +				RKISP1_CIF_ISP_AWB_GET_MEAN_Y_G(reg_val);
> +}
> +
> +static void rkisp1_stats_get_aec_meas_v10(struct rkisp1_stats *stats,
> +					  struct rkisp1_stat_buffer *pbuf)
>   {
>   	struct rkisp1_device *rkisp1 = stats->rkisp1;
>   	unsigned int i;
> @@ -206,7 +227,31 @@ static void rkisp1_stats_get_aec_meas(struct rkisp1_stats *stats,
>   	for (i = 0; i < stats->config->ae_mean_max; i++)
>   		pbuf->params.ae.exp_mean[i] =
>   			(u8)rkisp1_read(rkisp1,
> -					RKISP1_CIF_ISP_EXP_MEAN_00 + i * 4);
> +					RKISP1_CIF_ISP_EXP_MEAN_00_V10 + i * 4);
> +}
> +
> +static void rkisp1_stats_get_aec_meas_v12(struct rkisp1_stats *stats,
> +					  struct rkisp1_stat_buffer *pbuf)
> +{
> +	struct rkisp1_device *rkisp1 = stats->rkisp1;
> +	u32 value;
> +	int i;
> +
> +	pbuf->meas_type |= RKISP1_CIF_ISP_STAT_AUTOEXP;
> +	for (i = 0; i < stats->config->ae_mean_max / 4; i++) {
> +		value = rkisp1_read(rkisp1, RKISP1_CIF_ISP_EXP_MEAN_V12 + i * 4);
> +		pbuf->params.ae.exp_mean[4 * i + 0] =
> +				RKISP1_CIF_ISP_EXP_GET_MEAN_xy0_V12(value);
> +		pbuf->params.ae.exp_mean[4 * i + 1] =
> +				RKISP1_CIF_ISP_EXP_GET_MEAN_xy1_V12(value);
> +		pbuf->params.ae.exp_mean[4 * i + 2] =
> +				RKISP1_CIF_ISP_EXP_GET_MEAN_xy2_V12(value);
> +		pbuf->params.ae.exp_mean[4 * i + 3] =
> +				RKISP1_CIF_ISP_EXP_GET_MEAN_xy3_V12(value);
> +	}
> +
> +	value = rkisp1_read(rkisp1, RKISP1_CIF_ISP_EXP_MEAN_V12 + i * 4);
> +	pbuf->params.ae.exp_mean[4 * i + 0] = RKISP1_CIF_ISP_EXP_GET_MEAN_xy0_V12(value);
>   }
>   
>   static void rkisp1_stats_get_afc_meas(struct rkisp1_stats *stats,
> @@ -226,8 +271,8 @@ static void rkisp1_stats_get_afc_meas(struct rkisp1_stats *stats,
>   	af->window[2].lum = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AFM_LUM_C);
>   }
>   
> -static void rkisp1_stats_get_hst_meas(struct rkisp1_stats *stats,
> -				      struct rkisp1_stat_buffer *pbuf)
> +static void rkisp1_stats_get_hst_meas_v10(struct rkisp1_stats *stats,
> +					  struct rkisp1_stat_buffer *pbuf)
>   {
>   	struct rkisp1_device *rkisp1 = stats->rkisp1;
>   	unsigned int i;
> @@ -236,7 +281,24 @@ static void rkisp1_stats_get_hst_meas(struct rkisp1_stats *stats,
>   	for (i = 0; i < stats->config->hist_bin_n_max; i++)
>   		pbuf->params.hist.hist_bins[i] =
>   			(u8)rkisp1_read(rkisp1,
> -					RKISP1_CIF_ISP_HIST_BIN_0 + i * 4);
> +					RKISP1_CIF_ISP_HIST_BIN_0_V10 + i * 4);
> +}
> +
> +static void rkisp1_stats_get_hst_meas_v12(struct rkisp1_stats *stats,
> +					  struct rkisp1_stat_buffer *pbuf)
> +{
> +	struct rkisp1_device *rkisp1 = stats->rkisp1;
> +	u32 value;
> +	int i;
> +
> +	pbuf->meas_type |= RKISP1_CIF_ISP_STAT_HIST;
> +	for (i = 0; i < stats->config->hist_bin_n_max / 2; i++) {
> +		value = rkisp1_read(rkisp1, RKISP1_CIF_ISP_HIST_BIN_V12 + i * 4);
> +		pbuf->params.hist.hist_bins[2 * i] =
> +					RKISP1_CIF_ISP_HIST_GET_BIN0_V12(value);
> +		pbuf->params.hist.hist_bins[2 * i + 1] =
> +					RKISP1_CIF_ISP_HIST_GET_BIN1_V12(value);
> +	}
>   }
>   
>   static void rkisp1_stats_get_bls_meas(struct rkisp1_stats *stats,
> @@ -286,17 +348,28 @@ static void rkisp1_stats_get_bls_meas(struct rkisp1_stats *stats,
>   	}
>   }
>   
> -static struct rkisp1_stats_ops rkisp1_stats_ops = {
> -	.get_awb_meas = rkisp1_stats_get_awb_meas,
> -	.get_aec_meas = rkisp1_stats_get_aec_meas,
> -	.get_hst_meas = rkisp1_stats_get_hst_meas,
> +static struct rkisp1_stats_ops rkisp1_v10_stats_ops = {
> +	.get_awb_meas = rkisp1_stats_get_awb_meas_v10,
> +	.get_aec_meas = rkisp1_stats_get_aec_meas_v10,
> +	.get_hst_meas = rkisp1_stats_get_hst_meas_v10,
>   };
>   
> -static struct rkisp1_stats_config rkisp1_stats_config = {
> +static struct rkisp1_stats_config rkisp1_v10_stats_config = {
>   	.ae_mean_max = 25,
>   	.hist_bin_n_max = 16,
>   };
>   
> +static struct rkisp1_stats_ops rkisp1_v12_stats_ops = {
> +	.get_awb_meas = rkisp1_stats_get_awb_meas_v12,
> +	.get_aec_meas = rkisp1_stats_get_aec_meas_v12,
> +	.get_hst_meas = rkisp1_stats_get_hst_meas_v12,
> +};
> +
> +static struct rkisp1_stats_config rkisp1_v12_stats_config = {
> +	.ae_mean_max = 81,
> +	.hist_bin_n_max = 32,
> +};
> +
>   static void
>   rkisp1_stats_send_measurement(struct rkisp1_stats *stats, u32 isp_ris)
>   {
> @@ -365,8 +438,13 @@ static void rkisp1_init_stats(struct rkisp1_stats *stats)
>   	stats->vdev_fmt.fmt.meta.buffersize =
>   		sizeof(struct rkisp1_stat_buffer);
>   
> -	stats->ops = &rkisp1_stats_ops;
> -	stats->config = &rkisp1_stats_config;
> +	if (stats->rkisp1->isp_ver == RKISP1_V12) {
> +		stats->ops = &rkisp1_v12_stats_ops;
> +		stats->config = &rkisp1_v12_stats_config;
> +	} else {
> +		stats->ops = &rkisp1_v10_stats_ops;
> +		stats->config = &rkisp1_v10_stats_config;
> +	}
>   }
>   
>   int rkisp1_stats_register(struct rkisp1_device *rkisp1)
> 

Re: [PATCH RFC 08/11] media: rockchip: rkisp1: make some isp-param functions variable

[Dafna Hirschfeld]

Am 08.01.21 um 20:33 schrieb Heiko Stuebner:
> From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> 
> The isp block evolved in subsequent socs, so some functions
> will behave differently on newer variants.
> 
> Therefore make it possible to override the needed params functions.
> 
> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> ---
>   .../platform/rockchip/rkisp1/rkisp1-common.h  | 30 ++++++++
>   .../platform/rockchip/rkisp1/rkisp1-params.c  | 76 ++++++++++++-------
>   2 files changed, 77 insertions(+), 29 deletions(-)
> 
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
> index 7678eabc9ffc..4034a05ef9d2 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
> @@ -258,11 +258,39 @@ struct rkisp1_stats {
>   	struct v4l2_format vdev_fmt;
>   };
>   
> +struct rkisp1_params;
> +struct rkisp1_params_ops {

could you add a short inline doc of this stuct?

> +	void (*lsc_matrix_config)(struct rkisp1_params *params,
> +				  const struct rkisp1_cif_isp_lsc_config *pconfig);
> +	void (*goc_config)(struct rkisp1_params *params,
> +			   const struct rkisp1_cif_isp_goc_config *arg);
> +	void (*awb_meas_config)(struct rkisp1_params *params,
> +				const struct rkisp1_cif_isp_awb_meas_config *arg);
> +	void (*awb_meas_enable)(struct rkisp1_params *params,
> +				const struct rkisp1_cif_isp_awb_meas_config *arg,
> +				bool en);
> +	void (*awb_gain_config)(struct rkisp1_params *params,
> +				const struct rkisp1_cif_isp_awb_gain_config *arg);
> +	void (*aec_config)(struct rkisp1_params *params,
> +			   const struct rkisp1_cif_isp_aec_config *arg);
> +	void (*hst_config)(struct rkisp1_params *params,
> +			   const struct rkisp1_cif_isp_hst_config *arg);
> +	void (*hst_enable)(struct rkisp1_params *params,
> +			   const struct rkisp1_cif_isp_hst_config *arg, bool en);
> +	void (*afm_config)(struct rkisp1_params *params,
> +			   const struct rkisp1_cif_isp_afc_config *arg);
> +};
> +
> +struct rkisp1_params_config {
> +	const int gamma_out_max_samples;
> +};
> +
>   /*
>    * struct rkisp1_params - ISP input parameters device
>    *
>    * @vnode:		video node
>    * @rkisp1:		pointer to the rkisp1 device
> + * @ops:		pointer to the variant-specific operations

maybe change the doc here to "version-specific operations according to rkisp1_cif_isp_version"

>    * @config_lock:	locks the buffer list 'params'
>    * @params:		queue of rkisp1_buffer
>    * @vdev_fmt:		v4l2_format of the metadata format
> @@ -272,6 +300,8 @@ struct rkisp1_stats {
>   struct rkisp1_params {
>   	struct rkisp1_vdev_node vnode;
>   	struct rkisp1_device *rkisp1;
> +	struct rkisp1_params_ops *ops;
> +	struct rkisp1_params_config *config;

I think the field 'config' is not needed, see my comment in patch 10/11

>   
>   	spinlock_t config_lock; /* locks the buffers list 'params' */
>   	struct list_head params;
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
> index 6af4d551ffb5..008584caaad0 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
> @@ -185,8 +185,8 @@ static void rkisp1_bls_config(struct rkisp1_params *params,
>   
>   /* ISP LS correction interface function */
>   static void
> -rkisp1_lsc_correct_matrix_config(struct rkisp1_params *params,
> -				 const struct rkisp1_cif_isp_lsc_config *pconfig)
> +rkisp1_lsc_matrix_config(struct rkisp1_params *params,
> +			 const struct rkisp1_cif_isp_lsc_config *pconfig)

This is just a renaming of the function , I don't think this is needed

Thanks,
Dafna

>   {
>   	unsigned int isp_lsc_status, sram_addr, isp_lsc_table_sel, i, j, data;
>   
> @@ -265,7 +265,7 @@ static void rkisp1_lsc_config(struct rkisp1_params *params,
>   	lsc_ctrl = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_LSC_CTRL);
>   	rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_LSC_CTRL,
>   				RKISP1_CIF_ISP_LSC_CTRL_ENA);
> -	rkisp1_lsc_correct_matrix_config(params, arg);
> +	params->ops->lsc_matrix_config(params, arg);
>   
>   	for (i = 0; i < RKISP1_CIF_ISP_LSC_SECTORS_TBL_SIZE / 2; i++) {
>   		/* program x size tables */
> @@ -391,7 +391,7 @@ static void rkisp1_goc_config(struct rkisp1_params *params,
>   				RKISP1_CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA);
>   	rkisp1_write(params->rkisp1, arg->mode, RKISP1_CIF_ISP_GAMMA_OUT_MODE);
>   
> -	for (i = 0; i < RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES; i++)
> +	for (i = 0; i < params->config->gamma_out_max_samples; i++)
>   		rkisp1_write(params->rkisp1, arg->gamma_y[i],
>   			     RKISP1_CIF_ISP_GAMMA_OUT_Y_0 + i * 4);
>   }
> @@ -968,8 +968,8 @@ rkisp1_isp_isr_other_config(struct rkisp1_params *params,
>   	    (module_cfg_update & RKISP1_CIF_ISP_MODULE_AWB_GAIN)) {
>   		/* update awb gains */
>   		if (module_cfg_update & RKISP1_CIF_ISP_MODULE_AWB_GAIN)
> -			rkisp1_awb_gain_config(params,
> -					       &new_params->others.awb_gain_config);
> +			params->ops->awb_gain_config(params,
> +						     &new_params->others.awb_gain_config);
>   
>   		if (module_en_update & RKISP1_CIF_ISP_MODULE_AWB_GAIN) {
>   			if (module_ens & RKISP1_CIF_ISP_MODULE_AWB_GAIN)
> @@ -1037,8 +1037,8 @@ rkisp1_isp_isr_other_config(struct rkisp1_params *params,
>   	    (module_cfg_update & RKISP1_CIF_ISP_MODULE_GOC)) {
>   		/* update goc config */
>   		if (module_cfg_update & RKISP1_CIF_ISP_MODULE_GOC)
> -			rkisp1_goc_config(params,
> -					  &new_params->others.goc_config);
> +			params->ops->goc_config(params,
> +						&new_params->others.goc_config);
>   
>   		if (module_en_update & RKISP1_CIF_ISP_MODULE_GOC) {
>   			if (module_ens & RKISP1_CIF_ISP_MODULE_GOC)
> @@ -1124,20 +1124,20 @@ static void rkisp1_isp_isr_meas_config(struct rkisp1_params *params,
>   	    (module_cfg_update & RKISP1_CIF_ISP_MODULE_AWB)) {
>   		/* update awb config */
>   		if (module_cfg_update & RKISP1_CIF_ISP_MODULE_AWB)
> -			rkisp1_awb_meas_config(params,
> -					       &new_params->meas.awb_meas_config);
> +			params->ops->awb_meas_config(params,
> +						     &new_params->meas.awb_meas_config);
>   
>   		if (module_en_update & RKISP1_CIF_ISP_MODULE_AWB)
> -			rkisp1_awb_meas_enable(params,
> -					       &new_params->meas.awb_meas_config,
> -					       !!(module_ens & RKISP1_CIF_ISP_MODULE_AWB));
> +			params->ops->awb_meas_enable(params,
> +						     &new_params->meas.awb_meas_config,
> +						     !!(module_ens & RKISP1_CIF_ISP_MODULE_AWB));
>   	}
>   
>   	if ((module_en_update & RKISP1_CIF_ISP_MODULE_AFC) ||
>   	    (module_cfg_update & RKISP1_CIF_ISP_MODULE_AFC)) {
>   		/* update afc config */
>   		if (module_cfg_update & RKISP1_CIF_ISP_MODULE_AFC)
> -			rkisp1_afm_config(params,
> +			params->ops->afm_config(params,
>   					  &new_params->meas.afc_config);
>   
>   		if (module_en_update & RKISP1_CIF_ISP_MODULE_AFC) {
> @@ -1156,21 +1156,21 @@ static void rkisp1_isp_isr_meas_config(struct rkisp1_params *params,
>   	    (module_cfg_update & RKISP1_CIF_ISP_MODULE_HST)) {
>   		/* update hst config */
>   		if (module_cfg_update & RKISP1_CIF_ISP_MODULE_HST)
> -			rkisp1_hst_config(params,
> -					  &new_params->meas.hst_config);
> +			params->ops->hst_config(params,
> +						&new_params->meas.hst_config);
>   
>   		if (module_en_update & RKISP1_CIF_ISP_MODULE_HST)
> -			rkisp1_hst_enable(params,
> -					  &new_params->meas.hst_config,
> -					  !!(module_ens & RKISP1_CIF_ISP_MODULE_HST));
> +			params->ops->hst_enable(params,
> +						&new_params->meas.hst_config,
> +						!!(module_ens & RKISP1_CIF_ISP_MODULE_HST));
>   	}
>   
>   	if ((module_en_update & RKISP1_CIF_ISP_MODULE_AEC) ||
>   	    (module_cfg_update & RKISP1_CIF_ISP_MODULE_AEC)) {
>   		/* update aec config */
>   		if (module_cfg_update & RKISP1_CIF_ISP_MODULE_AEC)
> -			rkisp1_aec_config(params,
> -					  &new_params->meas.aec_config);
> +			params->ops->aec_config(params,
> +						&new_params->meas.aec_config);
>   
>   		if (module_en_update & RKISP1_CIF_ISP_MODULE_AEC) {
>   			if (module_ens & RKISP1_CIF_ISP_MODULE_AEC)
> @@ -1272,20 +1272,20 @@ static void rkisp1_params_config_parameter(struct rkisp1_params *params)
>   {
>   	struct rkisp1_cif_isp_hst_config hst = rkisp1_hst_params_default_config;
>   
> -	rkisp1_awb_meas_config(params, &rkisp1_awb_params_default_config);
> -	rkisp1_awb_meas_enable(params, &rkisp1_awb_params_default_config,
> -			       true);
> +	params->ops->awb_meas_config(params, &rkisp1_awb_params_default_config);
> +	params->ops->awb_meas_enable(params, &rkisp1_awb_params_default_config,
> +				     true);
>   
> -	rkisp1_aec_config(params, &rkisp1_aec_params_default_config);
> +	params->ops->aec_config(params, &rkisp1_aec_params_default_config);
>   	rkisp1_param_set_bits(params, RKISP1_CIF_ISP_EXP_CTRL,
>   			      RKISP1_CIF_ISP_EXP_ENA);
>   
> -	rkisp1_afm_config(params, &rkisp1_afc_params_default_config);
> +	params->ops->afm_config(params, &rkisp1_afc_params_default_config);
>   	rkisp1_param_set_bits(params, RKISP1_CIF_ISP_AFM_CTRL,
>   			      RKISP1_CIF_ISP_AFM_ENA);
>   
>   	memset(hst.hist_weight, 0x01, sizeof(hst.hist_weight));
> -	rkisp1_hst_config(params, &hst);
> +	params->ops->hst_config(params, &hst);
>   	rkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_PROP,
>   			      ~RKISP1_CIF_ISP_HIST_PROP_MODE_MASK |
>   			      rkisp1_hst_params_default_config.mode);
> @@ -1330,7 +1330,7 @@ void rkisp1_params_disable(struct rkisp1_params *params)
>   				RKISP1_CIF_ISP_DEMOSAIC_BYPASS);
>   	rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_FILT_MODE,
>   				RKISP1_CIF_ISP_FLT_ENA);
> -	rkisp1_awb_meas_enable(params, NULL, false);
> +	params->ops->awb_meas_enable(params, NULL, false);
>   	rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_CTRL,
>   				RKISP1_CIF_ISP_CTRL_ISP_AWB_ENA);
>   	rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_EXP_CTRL,
> @@ -1338,7 +1338,7 @@ void rkisp1_params_disable(struct rkisp1_params *params)
>   	rkisp1_ctk_enable(params, false);
>   	rkisp1_param_clear_bits(params, RKISP1_CIF_C_PROC_CTRL,
>   				RKISP1_CIF_C_PROC_CTR_ENABLE);
> -	rkisp1_hst_enable(params, NULL, false);
> +	params->ops->hst_enable(params, NULL, false);
>   	rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_AFM_CTRL,
>   				RKISP1_CIF_ISP_AFM_ENA);
>   	rkisp1_ie_enable(params, false);
> @@ -1346,6 +1346,22 @@ void rkisp1_params_disable(struct rkisp1_params *params)
>   				RKISP1_CIF_ISP_DPF_MODE_EN);
>   }
>   
> +static struct rkisp1_params_ops rkisp1_params_ops = {
> +	.lsc_matrix_config = rkisp1_lsc_matrix_config,
> +	.goc_config = rkisp1_goc_config,
> +	.awb_meas_config = rkisp1_awb_meas_config,
> +	.awb_meas_enable = rkisp1_awb_meas_enable,
> +	.awb_gain_config = rkisp1_awb_gain_config,
> +	.aec_config = rkisp1_aec_config,
> +	.hst_config = rkisp1_hst_config,
> +	.hst_enable = rkisp1_hst_enable,
> +	.afm_config = rkisp1_afm_config,
> +};
> +
> +static struct rkisp1_params_config rkisp1_params_config = {
> +	.gamma_out_max_samples = 17,
> +};> +
>   static int rkisp1_params_enum_fmt_meta_out(struct file *file, void *priv,
>   					   struct v4l2_fmtdesc *f)
>   {
> @@ -1512,6 +1528,8 @@ static void rkisp1_init_params(struct rkisp1_params *params)
>   		V4L2_META_FMT_RK_ISP1_PARAMS;
>   	params->vdev_fmt.fmt.meta.buffersize =
>   		sizeof(struct rkisp1_params_cfg);
> +	params->ops = &rkisp1_params_ops;
> +	params->config = &rkisp1_params_config;
>   }
>   
>   int rkisp1_params_register(struct rkisp1_device *rkisp1)
> 

Re: [PATCH RFC 10/11] media: rockchip: rkisp1: add support for v12 isp variants

[Dafna Hirschfeld]

Am 08.01.21 um 20:33 schrieb Heiko Stuebner:
> From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> 
> The rkisp1 evolved over soc generations and the rk3326/px30 introduced
> the so called v12 - probably meaning v1.2.
> 
> Add the changed register definitions.
> 
> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
> ---
>   .../platform/rockchip/rkisp1/rkisp1-common.h  |   1 +
>   .../platform/rockchip/rkisp1/rkisp1-isp.c     |  13 +
>   .../platform/rockchip/rkisp1/rkisp1-params.c  | 535 +++++++++++++++---
>   .../platform/rockchip/rkisp1/rkisp1-regs.h    | 404 ++++++++-----
>   .../platform/rockchip/rkisp1/rkisp1-stats.c   | 112 +++-
>   5 files changed, 824 insertions(+), 241 deletions(-)
> 
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
> index be0ae02165c9..9deb1ef1aa8b 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
> @@ -61,6 +61,7 @@
>   
>   enum rkisp1_isp_ver {
>   	RKISP1_V10 = 0,
> +	RKISP1_V12,
>   };
>   
>   /* enum for the resizer pads */
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
> index 84440aa71210..306cc96f8230 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
> @@ -408,6 +408,10 @@ static int rkisp1_config_mipi(struct rkisp1_device *rkisp1)
>   
>   	rkisp1_write(rkisp1, mipi_ctrl, RKISP1_CIF_MIPI_CTRL);
>   
> +	/* V12 could also use a newer csi2-host, but we don't want that yet */
> +	if (rkisp1->isp_ver == RKISP1_V12)
> +		rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_CSI0_CTRL0);
> +
>   	/* Configure Data Type and Virtual Channel */
>   	rkisp1_write(rkisp1,
>   		     RKISP1_CIF_MIPI_DATA_SEL_DT(sink_fmt->mipi_dt) |
> @@ -527,6 +531,15 @@ static void rkisp1_config_clk(struct rkisp1_device *rkisp1)
>   		  RKISP1_CIF_ICCL_DCROP_CLK;
>   
>   	rkisp1_write(rkisp1, val, RKISP1_CIF_ICCL);
> +
> +	/* ensure sp and mp can run at the same time in V12 */
> +	if (rkisp1->isp_ver == RKISP1_V12) {
> +		val = RKISP1_CIF_CLK_CTRL_MI_Y12 | RKISP1_CIF_CLK_CTRL_MI_SP |
> +		      RKISP1_CIF_CLK_CTRL_MI_RAW0 | RKISP1_CIF_CLK_CTRL_MI_RAW1 |
> +		      RKISP1_CIF_CLK_CTRL_MI_READ | RKISP1_CIF_CLK_CTRL_MI_RAWRD |
> +		      RKISP1_CIF_CLK_CTRL_CP | RKISP1_CIF_CLK_CTRL_IE;
> +		rkisp1_write(rkisp1, val, RKISP1_CIF_VI_ISP_CLK_CTRL_V12);
> +	}
>   }
>   
>   static void rkisp1_isp_start(struct rkisp1_device *rkisp1)
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
> index 008584caaad0..408fa33bdc30 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
> @@ -185,8 +185,8 @@ static void rkisp1_bls_config(struct rkisp1_params *params,
>   
>   /* ISP LS correction interface function */
>   static void
> -rkisp1_lsc_matrix_config(struct rkisp1_params *params,
> -			 const struct rkisp1_cif_isp_lsc_config *pconfig)
> +rkisp1_lsc_matrix_config_v10(struct rkisp1_params *params,
> +			     const struct rkisp1_cif_isp_lsc_config *pconfig)
>   {
>   	unsigned int isp_lsc_status, sram_addr, isp_lsc_table_sel, i, j, data;
>   
> @@ -212,39 +212,111 @@ rkisp1_lsc_matrix_config(struct rkisp1_params *params,
>   		 * DWORDs (2nd value of last DWORD unused)
>   		 */
>   		for (j = 0; j < RKISP1_CIF_ISP_LSC_SAMPLES_MAX - 1; j += 2) {
> -			data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->r_data_tbl[i][j],
> -							     pconfig->r_data_tbl[i][j + 1]);
> +			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->r_data_tbl[i][j],
> +								 pconfig->r_data_tbl[i][j + 1]);
>   			rkisp1_write(params->rkisp1, data,
>   				     RKISP1_CIF_ISP_LSC_R_TABLE_DATA);
>   
> -			data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->gr_data_tbl[i][j],
> -							     pconfig->gr_data_tbl[i][j + 1]);
> +			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->gr_data_tbl[i][j],
> +								 pconfig->gr_data_tbl[i][j + 1]);
>   			rkisp1_write(params->rkisp1, data,
>   				     RKISP1_CIF_ISP_LSC_GR_TABLE_DATA);
>   
> -			data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->gb_data_tbl[i][j],
> -							     pconfig->gb_data_tbl[i][j + 1]);
> +			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->gb_data_tbl[i][j],
> +								 pconfig->gb_data_tbl[i][j + 1]);
>   			rkisp1_write(params->rkisp1, data,
>   				     RKISP1_CIF_ISP_LSC_GB_TABLE_DATA);
>   
> -			data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->b_data_tbl[i][j],
> -							     pconfig->b_data_tbl[i][j + 1]);
> +			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->b_data_tbl[i][j],
> +								 pconfig->b_data_tbl[i][j + 1]);
>   			rkisp1_write(params->rkisp1, data,
>   				     RKISP1_CIF_ISP_LSC_B_TABLE_DATA);
>   		}
> -		data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->r_data_tbl[i][j], 0);
> +		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->r_data_tbl[i][j], 0);
>   		rkisp1_write(params->rkisp1, data,
>   			     RKISP1_CIF_ISP_LSC_R_TABLE_DATA);
>   
> -		data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->gr_data_tbl[i][j], 0);
> +		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->gr_data_tbl[i][j], 0);
>   		rkisp1_write(params->rkisp1, data,
>   			     RKISP1_CIF_ISP_LSC_GR_TABLE_DATA);
>   
> -		data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->gb_data_tbl[i][j], 0);
> +		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->gb_data_tbl[i][j], 0);
>   		rkisp1_write(params->rkisp1, data,
>   			     RKISP1_CIF_ISP_LSC_GB_TABLE_DATA);
>   
> -		data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->b_data_tbl[i][j], 0);
> +		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->b_data_tbl[i][j], 0);
> +		rkisp1_write(params->rkisp1, data,
> +			     RKISP1_CIF_ISP_LSC_B_TABLE_DATA);
> +	}
> +	isp_lsc_table_sel = (isp_lsc_status & RKISP1_CIF_ISP_LSC_ACTIVE_TABLE) ?
> +			    RKISP1_CIF_ISP_LSC_TABLE_0 :
> +			    RKISP1_CIF_ISP_LSC_TABLE_1;
> +	rkisp1_write(params->rkisp1, isp_lsc_table_sel,
> +		     RKISP1_CIF_ISP_LSC_TABLE_SEL);
> +}
> +
> +static void
> +rkisp1_lsc_matrix_config_v12(struct rkisp1_params *params,
> +			     const struct rkisp1_cif_isp_lsc_config *pconfig)
> +{
> +	unsigned int isp_lsc_status, sram_addr, isp_lsc_table_sel, i, j, data;
> +
> +	isp_lsc_status = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_LSC_STATUS);
> +
> +	/* RKISP1_CIF_ISP_LSC_TABLE_ADDRESS_153 = ( 17 * 18 ) >> 1 */
> +	sram_addr = (isp_lsc_status & RKISP1_CIF_ISP_LSC_ACTIVE_TABLE) ?
> +		     RKISP1_CIF_ISP_LSC_TABLE_ADDRESS_0 :
> +		     RKISP1_CIF_ISP_LSC_TABLE_ADDRESS_153;
> +	rkisp1_write(params->rkisp1, sram_addr, RKISP1_CIF_ISP_LSC_R_TABLE_ADDR);
> +	rkisp1_write(params->rkisp1, sram_addr, RKISP1_CIF_ISP_LSC_GR_TABLE_ADDR);
> +	rkisp1_write(params->rkisp1, sram_addr, RKISP1_CIF_ISP_LSC_GB_TABLE_ADDR);
> +	rkisp1_write(params->rkisp1, sram_addr, RKISP1_CIF_ISP_LSC_B_TABLE_ADDR);
> +
> +	/* program data tables (table size is 9 * 17 = 153) */
> +	for (i = 0; i < RKISP1_CIF_ISP_LSC_SAMPLES_MAX; i++) {
> +		/*
> +		 * 17 sectors with 2 values in one DWORD = 9
> +		 * DWORDs (2nd value of last DWORD unused)
> +		 */
> +		for (j = 0; j < RKISP1_CIF_ISP_LSC_SAMPLES_MAX - 1; j += 2) {
> +			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(
> +					pconfig->r_data_tbl[i][j],
> +					pconfig->r_data_tbl[i][j + 1]);
> +			rkisp1_write(params->rkisp1, data,
> +				     RKISP1_CIF_ISP_LSC_R_TABLE_DATA);
> +
> +			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(
> +					pconfig->gr_data_tbl[i][j],
> +					pconfig->gr_data_tbl[i][j + 1]);
> +			rkisp1_write(params->rkisp1, data,
> +				     RKISP1_CIF_ISP_LSC_GR_TABLE_DATA);
> +
> +			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(
> +					pconfig->gb_data_tbl[i][j],
> +					pconfig->gb_data_tbl[i][j + 1]);
> +			rkisp1_write(params->rkisp1, data,
> +				     RKISP1_CIF_ISP_LSC_GB_TABLE_DATA);
> +
> +			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(
> +					pconfig->b_data_tbl[i][j],
> +					pconfig->b_data_tbl[i][j + 1]);
> +			rkisp1_write(params->rkisp1, data,
> +				     RKISP1_CIF_ISP_LSC_B_TABLE_DATA);
> +		}
> +
> +		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(pconfig->r_data_tbl[i][j], 0);
> +		rkisp1_write(params->rkisp1, data,
> +			     RKISP1_CIF_ISP_LSC_R_TABLE_DATA);
> +
> +		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(pconfig->gr_data_tbl[i][j], 0);
> +		rkisp1_write(params->rkisp1, data,
> +			     RKISP1_CIF_ISP_LSC_GR_TABLE_DATA);
> +
> +		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(pconfig->gb_data_tbl[i][j], 0);
> +		rkisp1_write(params->rkisp1, data,
> +			     RKISP1_CIF_ISP_LSC_GB_TABLE_DATA);
> +
> +		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(pconfig->b_data_tbl[i][j], 0);
>   		rkisp1_write(params->rkisp1, data,
>   			     RKISP1_CIF_ISP_LSC_B_TABLE_DATA);
>   	}
> @@ -382,18 +454,37 @@ static void rkisp1_sdg_config(struct rkisp1_params *params,
>   }
>   
>   /* ISP GAMMA correction interface function */
> -static void rkisp1_goc_config(struct rkisp1_params *params,
> -			      const struct rkisp1_cif_isp_goc_config *arg)
> +static void rkisp1_goc_config_v10(struct rkisp1_params *params,
> +				  const struct rkisp1_cif_isp_goc_config *arg)
>   {
>   	unsigned int i;
>   
>   	rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_CTRL,
>   				RKISP1_CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA);
> -	rkisp1_write(params->rkisp1, arg->mode, RKISP1_CIF_ISP_GAMMA_OUT_MODE);
> +	rkisp1_write(params->rkisp1, arg->mode, RKISP1_CIF_ISP_GAMMA_OUT_MODE_V10);
>   
>   	for (i = 0; i < params->config->gamma_out_max_samples; i++)
>   		rkisp1_write(params->rkisp1, arg->gamma_y[i],
> -			     RKISP1_CIF_ISP_GAMMA_OUT_Y_0 + i * 4);
> +			     RKISP1_CIF_ISP_GAMMA_OUT_Y_0_V10 + i * 4);
> +}
> +
> +static void rkisp1_goc_config_v12(struct rkisp1_params *params,
> +				  const struct rkisp1_cif_isp_goc_config *arg)
> +{
> +	int i;
> +	u32 value;
> +
> +	rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_CTRL,
> +				RKISP1_CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA);
> +	rkisp1_write(params->rkisp1, arg->mode, RKISP1_CIF_ISP_GAMMA_OUT_MODE_V12);
> +
> +	for (i = 0; i < params->config->gamma_out_max_samples / 2; i++) {
> +		value = RKISP1_CIF_ISP_GAMMA_VALUE_V12(
> +			arg->gamma_y[2 * i + 1],
> +			arg->gamma_y[2 * i]);
> +		rkisp1_write(params->rkisp1, value,
> +			     RKISP1_CIF_ISP_GAMMA_OUT_Y_0_V12 + i * 4);
> +	}
>   }
>   
>   /* ISP Cross Talk */
> @@ -433,8 +524,8 @@ static void rkisp1_ctk_enable(struct rkisp1_params *params, bool en)
>   }
>   
>   /* ISP White Balance Mode */
> -static void rkisp1_awb_meas_config(struct rkisp1_params *params,
> -				   const struct rkisp1_cif_isp_awb_meas_config *arg)
> +static void rkisp1_awb_meas_config_v10(struct rkisp1_params *params,
> +				       const struct rkisp1_cif_isp_awb_meas_config *arg)
>   {
>   	u32 reg_val = 0;
>   	/* based on the mode,configure the awb module */
> @@ -442,43 +533,82 @@ static void rkisp1_awb_meas_config(struct rkisp1_params *params,
>   		/* Reference Cb and Cr */
>   		rkisp1_write(params->rkisp1,
>   			     RKISP1_CIF_ISP_AWB_REF_CR_SET(arg->awb_ref_cr) |
> -			     arg->awb_ref_cb, RKISP1_CIF_ISP_AWB_REF);
> +			     arg->awb_ref_cb, RKISP1_CIF_ISP_AWB_REF_V10);
>   		/* Yc Threshold */
>   		rkisp1_write(params->rkisp1,
>   			     RKISP1_CIF_ISP_AWB_MAX_Y_SET(arg->max_y) |
>   			     RKISP1_CIF_ISP_AWB_MIN_Y_SET(arg->min_y) |
>   			     RKISP1_CIF_ISP_AWB_MAX_CS_SET(arg->max_csum) |
> -			     arg->min_c, RKISP1_CIF_ISP_AWB_THRESH);
> +			     arg->min_c, RKISP1_CIF_ISP_AWB_THRESH_V10);
>   	}
>   
> -	reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP);
> +	reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP_V10);
>   	if (arg->enable_ymax_cmp)
>   		reg_val |= RKISP1_CIF_ISP_AWB_YMAX_CMP_EN;
>   	else
>   		reg_val &= ~RKISP1_CIF_ISP_AWB_YMAX_CMP_EN;
> -	rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP);
> +	rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP_V10);
>   
>   	/* window offset */
>   	rkisp1_write(params->rkisp1,
> -		     arg->awb_wnd.v_offs, RKISP1_CIF_ISP_AWB_WND_V_OFFS);
> +		     arg->awb_wnd.v_offs, RKISP1_CIF_ISP_AWB_WND_V_OFFS_V10);
>   	rkisp1_write(params->rkisp1,
> -		     arg->awb_wnd.h_offs, RKISP1_CIF_ISP_AWB_WND_H_OFFS);
> +		     arg->awb_wnd.h_offs, RKISP1_CIF_ISP_AWB_WND_H_OFFS_V10);
>   	/* AWB window size */
>   	rkisp1_write(params->rkisp1,
> -		     arg->awb_wnd.v_size, RKISP1_CIF_ISP_AWB_WND_V_SIZE);
> +		     arg->awb_wnd.v_size, RKISP1_CIF_ISP_AWB_WND_V_SIZE_V10);
>   	rkisp1_write(params->rkisp1,
> -		     arg->awb_wnd.h_size, RKISP1_CIF_ISP_AWB_WND_H_SIZE);
> +		     arg->awb_wnd.h_size, RKISP1_CIF_ISP_AWB_WND_H_SIZE_V10);
>   	/* Number of frames */
>   	rkisp1_write(params->rkisp1,
> -		     arg->frames, RKISP1_CIF_ISP_AWB_FRAMES);
> +		     arg->frames, RKISP1_CIF_ISP_AWB_FRAMES_V10);
> +}
> +
> +static void rkisp1_awb_meas_config_v12(struct rkisp1_params *params,
> +				       const struct rkisp1_cif_isp_awb_meas_config *arg)
> +{
> +	u32 reg_val = 0;
> +	/* based on the mode,configure the awb module */
> +	if (arg->awb_mode == RKISP1_CIF_ISP_AWB_MODE_YCBCR) {
> +		/* Reference Cb and Cr */
> +		rkisp1_write(params->rkisp1,
> +			     RKISP1_CIF_ISP_AWB_REF_CR_SET(arg->awb_ref_cr) |
> +			     arg->awb_ref_cb, RKISP1_CIF_ISP_AWB_REF_V12);
> +		/* Yc Threshold */
> +		rkisp1_write(params->rkisp1,
> +			     RKISP1_CIF_ISP_AWB_MAX_Y_SET(arg->max_y) |
> +			     RKISP1_CIF_ISP_AWB_MIN_Y_SET(arg->min_y) |
> +			     RKISP1_CIF_ISP_AWB_MAX_CS_SET(arg->max_csum) |
> +			     arg->min_c, RKISP1_CIF_ISP_AWB_THRESH_V12);
> +	}
> +
> +	reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP_V12);
> +	if (arg->enable_ymax_cmp)
> +		reg_val |= RKISP1_CIF_ISP_AWB_YMAX_CMP_EN;
> +	else
> +		reg_val &= ~RKISP1_CIF_ISP_AWB_YMAX_CMP_EN;
> +	reg_val &= ~RKISP1_CIF_ISP_AWB_SET_FRAMES_MASK_V12;
> +	reg_val |= RKISP1_CIF_ISP_AWB_SET_FRAMES_V12(arg->frames);
> +	rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP_V12);
> +
> +	/* window offset */
> +	rkisp1_write(params->rkisp1,
> +		     arg->awb_wnd.v_offs << 16 |
> +		     arg->awb_wnd.h_offs,
> +		     RKISP1_CIF_ISP_AWB_OFFS_V12);
> +	/* AWB window size */
> +	rkisp1_write(params->rkisp1,
> +		     arg->awb_wnd.v_size << 16 |
> +		     arg->awb_wnd.h_size,
> +		     RKISP1_CIF_ISP_AWB_SIZE_V12);
>   }
>   
>   static void
> -rkisp1_awb_meas_enable(struct rkisp1_params *params,
> -		       const struct rkisp1_cif_isp_awb_meas_config *arg,
> -		       bool en)
> +rkisp1_awb_meas_enable_v10(struct rkisp1_params *params,
> +			   const struct rkisp1_cif_isp_awb_meas_config *arg,
> +			   bool en)
>   {
> -	u32 reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP);
> +	u32 reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP_V10);
>   
>   	/* switch off */
>   	reg_val &= RKISP1_CIF_ISP_AWB_MODE_MASK_NONE;
> @@ -489,34 +619,76 @@ rkisp1_awb_meas_enable(struct rkisp1_params *params,
>   		else
>   			reg_val |= RKISP1_CIF_ISP_AWB_MODE_YCBCR_EN;
>   
> -		rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP);
> +		rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP_V10);
>   
>   		/* Measurements require AWB block be active. */
>   		rkisp1_param_set_bits(params, RKISP1_CIF_ISP_CTRL,
>   				      RKISP1_CIF_ISP_CTRL_ISP_AWB_ENA);
>   	} else {
>   		rkisp1_write(params->rkisp1,
> -			     reg_val, RKISP1_CIF_ISP_AWB_PROP);
> +			     reg_val, RKISP1_CIF_ISP_AWB_PROP_V10);
>   		rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_CTRL,
>   					RKISP1_CIF_ISP_CTRL_ISP_AWB_ENA);
>   	}
>   }
>   
>   static void
> -rkisp1_awb_gain_config(struct rkisp1_params *params,
> -		       const struct rkisp1_cif_isp_awb_gain_config *arg)
> +rkisp1_awb_meas_enable_v12(struct rkisp1_params *params,
> +			   const struct rkisp1_cif_isp_awb_meas_config *arg,
> +			   bool en)
> +{
> +	u32 reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP_V12);
> +
> +	/* switch off */
> +	reg_val &= RKISP1_CIF_ISP_AWB_MODE_MASK_NONE;
> +
> +	if (en) {
> +		if (arg->awb_mode == RKISP1_CIF_ISP_AWB_MODE_RGB)
> +			reg_val |= RKISP1_CIF_ISP_AWB_MODE_RGB_EN;
> +		else
> +			reg_val |= RKISP1_CIF_ISP_AWB_MODE_YCBCR_EN;
> +
> +		rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP_V12);
> +
> +		/* Measurements require AWB block be active. */
> +		rkisp1_param_set_bits(params, RKISP1_CIF_ISP_CTRL,
> +				      RKISP1_CIF_ISP_CTRL_ISP_AWB_ENA);
> +	} else {
> +		rkisp1_write(params->rkisp1,
> +			     reg_val, RKISP1_CIF_ISP_AWB_PROP_V12);
> +		rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_CTRL,
> +					RKISP1_CIF_ISP_CTRL_ISP_AWB_ENA);
> +	}
> +}
> +
> +static void
> +rkisp1_awb_gain_config_v10(struct rkisp1_params *params,
> +			   const struct rkisp1_cif_isp_awb_gain_config *arg)
> +{
> +	rkisp1_write(params->rkisp1,
> +		     RKISP1_CIF_ISP_AWB_GAIN_R_SET(arg->gain_green_r) |
> +		     arg->gain_green_b, RKISP1_CIF_ISP_AWB_GAIN_G_V10);
> +
> +	rkisp1_write(params->rkisp1,
> +		     RKISP1_CIF_ISP_AWB_GAIN_R_SET(arg->gain_red) |
> +		     arg->gain_blue, RKISP1_CIF_ISP_AWB_GAIN_RB_V10);
> +}
> +
> +static void
> +rkisp1_awb_gain_config_v12(struct rkisp1_params *params,
> +			   const struct rkisp1_cif_isp_awb_gain_config *arg)
>   {
>   	rkisp1_write(params->rkisp1,
>   		     RKISP1_CIF_ISP_AWB_GAIN_R_SET(arg->gain_green_r) |
> -		     arg->gain_green_b, RKISP1_CIF_ISP_AWB_GAIN_G);
> +		     arg->gain_green_b, RKISP1_CIF_ISP_AWB_GAIN_G_V12);
>   
>   	rkisp1_write(params->rkisp1,
>   		     RKISP1_CIF_ISP_AWB_GAIN_R_SET(arg->gain_red) |
> -		     arg->gain_blue, RKISP1_CIF_ISP_AWB_GAIN_RB);
> +		     arg->gain_blue, RKISP1_CIF_ISP_AWB_GAIN_RB_V12);
>   }
>   
> -static void rkisp1_aec_config(struct rkisp1_params *params,
> -			      const struct rkisp1_cif_isp_aec_config *arg)
> +static void rkisp1_aec_config_v10(struct rkisp1_params *params,
> +				  const struct rkisp1_cif_isp_aec_config *arg)
>   {
>   	unsigned int block_hsize, block_vsize;
>   	u32 exp_ctrl;
> @@ -531,21 +703,55 @@ static void rkisp1_aec_config(struct rkisp1_params *params,
>   	rkisp1_write(params->rkisp1, exp_ctrl, RKISP1_CIF_ISP_EXP_CTRL);
>   
>   	rkisp1_write(params->rkisp1,
> -		     arg->meas_window.h_offs, RKISP1_CIF_ISP_EXP_H_OFFSET);
> +		     arg->meas_window.h_offs, RKISP1_CIF_ISP_EXP_H_OFFSET_V10);
>   	rkisp1_write(params->rkisp1,
> -		     arg->meas_window.v_offs, RKISP1_CIF_ISP_EXP_V_OFFSET);
> +		     arg->meas_window.v_offs, RKISP1_CIF_ISP_EXP_V_OFFSET_V10);
>   
>   	block_hsize = arg->meas_window.h_size /
> -		      RKISP1_CIF_ISP_EXP_COLUMN_NUM - 1;
> +		      RKISP1_CIF_ISP_EXP_COLUMN_NUM_V10 - 1;
>   	block_vsize = arg->meas_window.v_size /
> -		      RKISP1_CIF_ISP_EXP_ROW_NUM - 1;
> +		      RKISP1_CIF_ISP_EXP_ROW_NUM_V10 - 1;
> +
> +	rkisp1_write(params->rkisp1,
> +		     RKISP1_CIF_ISP_EXP_H_SIZE_SET_V10(block_hsize),
> +		     RKISP1_CIF_ISP_EXP_H_SIZE_V10);
> +	rkisp1_write(params->rkisp1,
> +		     RKISP1_CIF_ISP_EXP_V_SIZE_SET_V10(block_vsize),
> +		     RKISP1_CIF_ISP_EXP_V_SIZE_V10);
> +}
> +
> +static void rkisp1_aec_config_v12(struct rkisp1_params *params,
> +			       const struct rkisp1_cif_isp_aec_config *arg)
> +{
> +	u32 exp_ctrl;
> +	u32 block_hsize, block_vsize;
> +	u32 wnd_num_idx = 1;
> +	const u32 ae_wnd_num[] = {
> +		5, 9, 15, 15
> +	};
> +
> +	/* avoid to override the old enable value */
> +	exp_ctrl = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_EXP_CTRL);
> +	exp_ctrl &= RKISP1_CIF_ISP_EXP_ENA;
> +	if (arg->autostop)
> +		exp_ctrl |= RKISP1_CIF_ISP_EXP_CTRL_AUTOSTOP;
> +	if (arg->mode == RKISP1_CIF_ISP_EXP_MEASURING_MODE_1)
> +		exp_ctrl |= RKISP1_CIF_ISP_EXP_CTRL_MEASMODE_1;
> +	exp_ctrl |= RKISP1_CIF_ISP_EXP_CTRL_WNDNUM_SET_V12(wnd_num_idx);
> +	rkisp1_write(params->rkisp1, exp_ctrl, RKISP1_CIF_ISP_EXP_CTRL);
>   
>   	rkisp1_write(params->rkisp1,
> -		     RKISP1_CIF_ISP_EXP_H_SIZE_SET(block_hsize),
> -		     RKISP1_CIF_ISP_EXP_H_SIZE);
> +		     RKISP1_CIF_ISP_EXP_V_OFFSET_SET_V12(arg->meas_window.v_offs) |
> +		     RKISP1_CIF_ISP_EXP_H_OFFSET_SET_V12(arg->meas_window.h_offs),
> +		     RKISP1_CIF_ISP_EXP_OFFS_V12);
> +
> +	block_hsize = arg->meas_window.h_size / ae_wnd_num[wnd_num_idx] - 1;
> +	block_vsize = arg->meas_window.v_size / ae_wnd_num[wnd_num_idx] - 1;
> +
>   	rkisp1_write(params->rkisp1,
> -		     RKISP1_CIF_ISP_EXP_V_SIZE_SET(block_vsize),
> -		     RKISP1_CIF_ISP_EXP_V_SIZE);
> +		     RKISP1_CIF_ISP_EXP_V_SIZE_SET_V12(block_vsize) |
> +		     RKISP1_CIF_ISP_EXP_H_SIZE_SET_V12(block_hsize),
> +		     RKISP1_CIF_ISP_EXP_SIZE_V12);
>   }
>   
>   static void rkisp1_cproc_config(struct rkisp1_params *params,
> @@ -578,72 +784,154 @@ static void rkisp1_cproc_config(struct rkisp1_params *params,
>   	}
>   }
>   
> -static void rkisp1_hst_config(struct rkisp1_params *params,
> -			      const struct rkisp1_cif_isp_hst_config *arg)
> +static void rkisp1_hst_config_v10(struct rkisp1_params *params,
> +				  const struct rkisp1_cif_isp_hst_config *arg)
>   {
>   	unsigned int block_hsize, block_vsize;
>   	static const u32 hist_weight_regs[] = {
> -		RKISP1_CIF_ISP_HIST_WEIGHT_00TO30,
> -		RKISP1_CIF_ISP_HIST_WEIGHT_40TO21,
> -		RKISP1_CIF_ISP_HIST_WEIGHT_31TO12,
> -		RKISP1_CIF_ISP_HIST_WEIGHT_22TO03,
> -		RKISP1_CIF_ISP_HIST_WEIGHT_13TO43,
> -		RKISP1_CIF_ISP_HIST_WEIGHT_04TO34,
> -		RKISP1_CIF_ISP_HIST_WEIGHT_44,
> +		RKISP1_CIF_ISP_HIST_WEIGHT_00TO30_V10,
> +		RKISP1_CIF_ISP_HIST_WEIGHT_40TO21_V10,
> +		RKISP1_CIF_ISP_HIST_WEIGHT_31TO12_V10,
> +		RKISP1_CIF_ISP_HIST_WEIGHT_22TO03_V10,
> +		RKISP1_CIF_ISP_HIST_WEIGHT_13TO43_V10,
> +		RKISP1_CIF_ISP_HIST_WEIGHT_04TO34_V10,
> +		RKISP1_CIF_ISP_HIST_WEIGHT_44_V10,
>   	};
>   	const u8 *weight;
>   	unsigned int i;
>   	u32 hist_prop;
>   
>   	/* avoid to override the old enable value */
> -	hist_prop = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_HIST_PROP);
> -	hist_prop &= RKISP1_CIF_ISP_HIST_PROP_MODE_MASK;
> -	hist_prop |= RKISP1_CIF_ISP_HIST_PREDIV_SET(arg->histogram_predivider);
> -	rkisp1_write(params->rkisp1, hist_prop, RKISP1_CIF_ISP_HIST_PROP);
> +	hist_prop = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_HIST_PROP_V10);
> +	hist_prop &= RKISP1_CIF_ISP_HIST_PROP_MODE_MASK_V10;
> +	hist_prop |= RKISP1_CIF_ISP_HIST_PREDIV_SET_V10(arg->histogram_predivider);
> +	rkisp1_write(params->rkisp1, hist_prop, RKISP1_CIF_ISP_HIST_PROP_V10);
>   	rkisp1_write(params->rkisp1,
>   		     arg->meas_window.h_offs,
> -		     RKISP1_CIF_ISP_HIST_H_OFFS);
> +		     RKISP1_CIF_ISP_HIST_H_OFFS_V10);
>   	rkisp1_write(params->rkisp1,
>   		     arg->meas_window.v_offs,
> -		     RKISP1_CIF_ISP_HIST_V_OFFS);
> +		     RKISP1_CIF_ISP_HIST_V_OFFS_V10);
>   
>   	block_hsize = arg->meas_window.h_size /
> -		      RKISP1_CIF_ISP_HIST_COLUMN_NUM - 1;
> -	block_vsize = arg->meas_window.v_size / RKISP1_CIF_ISP_HIST_ROW_NUM - 1;
> +		      RKISP1_CIF_ISP_HIST_COLUMN_NUM_V10 - 1;
> +	block_vsize = arg->meas_window.v_size / RKISP1_CIF_ISP_HIST_ROW_NUM_V10 - 1;
>   
> -	rkisp1_write(params->rkisp1, block_hsize, RKISP1_CIF_ISP_HIST_H_SIZE);
> -	rkisp1_write(params->rkisp1, block_vsize, RKISP1_CIF_ISP_HIST_V_SIZE);
> +	rkisp1_write(params->rkisp1, block_hsize, RKISP1_CIF_ISP_HIST_H_SIZE_V10);
> +	rkisp1_write(params->rkisp1, block_vsize, RKISP1_CIF_ISP_HIST_V_SIZE_V10);
>   
>   	weight = arg->hist_weight;
>   	for (i = 0; i < ARRAY_SIZE(hist_weight_regs); ++i, weight += 4)
>   		rkisp1_write(params->rkisp1,
> -			     RKISP1_CIF_ISP_HIST_WEIGHT_SET(weight[0],
> +			     RKISP1_CIF_ISP_HIST_WEIGHT_SET_V10(weight[0],
>   							    weight[1],
>   							    weight[2],
>   							    weight[3]),
>   				 hist_weight_regs[i]);
>   }
>   
> +static void rkisp1_hst_config_v12(struct rkisp1_params *params,
> +				  const struct rkisp1_cif_isp_hst_config *arg)
> +{
> +	u32 i, j;
> +	u32 value;
> +	u32 hist_ctrl;
> +	u32 block_hsize, block_vsize;
> +	u32 wnd_num_idx, hist_weight_num;
> +	u8 weight15x15[RKISP1_CIF_ISP_HIST_WEIGHT_REG_SIZE_V12];
> +	const u32 hist_wnd_num[] = {
> +		5, 9, 15, 15
> +	};
> +
> +	/* now we just support 9x9 window */
> +	wnd_num_idx = 1;
> +	memset(weight15x15, 0x00, sizeof(weight15x15));
> +	/* avoid to override the old enable value */
> +	hist_ctrl = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_HIST_CTRL_V12);
> +	hist_ctrl &= RKISP1_CIF_ISP_HIST_CTRL_MODE_MASK_V12 |
> +		     RKISP1_CIF_ISP_HIST_CTRL_EN_MASK_V12;
> +	hist_ctrl = hist_ctrl |
> +		    RKISP1_CIF_ISP_HIST_CTRL_INTRSEL_SET_V12(1) |
> +		    RKISP1_CIF_ISP_HIST_CTRL_DATASEL_SET_V12(0) |
> +		    RKISP1_CIF_ISP_HIST_CTRL_WATERLINE_SET_V12(0) |
> +		    RKISP1_CIF_ISP_HIST_CTRL_AUTOSTOP_SET_V12(0) |
> +		    RKISP1_CIF_ISP_HIST_CTRL_WNDNUM_SET_V12(1) |
> +		    RKISP1_CIF_ISP_HIST_CTRL_STEPSIZE_SET_V12(arg->histogram_predivider);
> +	rkisp1_write(params->rkisp1, hist_ctrl, RKISP1_CIF_ISP_HIST_CTRL_V12);
> +
> +	rkisp1_write(params->rkisp1,
> +		     RKISP1_CIF_ISP_HIST_OFFS_SET_V12(arg->meas_window.h_offs,
> +						      arg->meas_window.v_offs),
> +		     RKISP1_CIF_ISP_HIST_OFFS_V12);
> +
> +	block_hsize = arg->meas_window.h_size / hist_wnd_num[wnd_num_idx] - 1;
> +	block_vsize = arg->meas_window.v_size / hist_wnd_num[wnd_num_idx] - 1;
> +	rkisp1_write(params->rkisp1,
> +		     RKISP1_CIF_ISP_HIST_SIZE_SET_V12(block_hsize, block_vsize),
> +		     RKISP1_CIF_ISP_HIST_SIZE_V12);
> +
> +	for (i = 0; i < hist_wnd_num[wnd_num_idx]; i++) {
> +		for (j = 0; j < hist_wnd_num[wnd_num_idx]; j++) {
> +			weight15x15[i * RKISP1_CIF_ISP_HIST_ROW_NUM_V12 + j] =
> +				arg->hist_weight[i * hist_wnd_num[wnd_num_idx] + j];
> +		}
> +	}
> +
> +	hist_weight_num = RKISP1_CIF_ISP_HIST_WEIGHT_REG_SIZE_V12;
> +	for (i = 0; i < (hist_weight_num / 4); i++) {
> +		value = RKISP1_CIF_ISP_HIST_WEIGHT_SET_V12(
> +				 weight15x15[4 * i + 0],
> +				 weight15x15[4 * i + 1],
> +				 weight15x15[4 * i + 2],
> +				 weight15x15[4 * i + 3]);
> +		rkisp1_write(params->rkisp1, value,
> +				 RKISP1_CIF_ISP_HIST_WEIGHT_V12 + 4 * i);
> +	}
> +	value = RKISP1_CIF_ISP_HIST_WEIGHT_SET_V12(weight15x15[4 * i + 0], 0, 0, 0);
> +	rkisp1_write(params->rkisp1, value,
> +				 RKISP1_CIF_ISP_HIST_WEIGHT_V12 + 4 * i);
> +}
> +
>   static void
> -rkisp1_hst_enable(struct rkisp1_params *params,
> -		  const struct rkisp1_cif_isp_hst_config *arg, bool en)
> +rkisp1_hst_enable_v10(struct rkisp1_params *params,
> +		      const struct rkisp1_cif_isp_hst_config *arg, bool en)
>   {
>   	if (en)	{
>   		u32 hist_prop = rkisp1_read(params->rkisp1,
> -					    RKISP1_CIF_ISP_HIST_PROP);
> +					    RKISP1_CIF_ISP_HIST_PROP_V10);
>   
> -		hist_prop &= ~RKISP1_CIF_ISP_HIST_PROP_MODE_MASK;
> +		hist_prop &= ~RKISP1_CIF_ISP_HIST_PROP_MODE_MASK_V10;
>   		hist_prop |= arg->mode;
> -		rkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_PROP,
> +		rkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_PROP_V10,
>   				      hist_prop);
>   	} else {
> -		rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_HIST_PROP,
> -					RKISP1_CIF_ISP_HIST_PROP_MODE_MASK);
> +		rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_HIST_PROP_V10,
> +					RKISP1_CIF_ISP_HIST_PROP_MODE_MASK_V10);
> +	}
> +}
> +
> +static void
> +rkisp1_hst_enable_v12(struct rkisp1_params *params,
> +		      const struct rkisp1_cif_isp_hst_config *arg, bool en)
> +{
> +	if (en) {
> +		u32 hist_ctrl = rkisp1_read(params->rkisp1,
> +					    RKISP1_CIF_ISP_HIST_CTRL_V12);
> +
> +		hist_ctrl &= ~RKISP1_CIF_ISP_HIST_CTRL_MODE_MASK_V12;
> +		hist_ctrl |= RKISP1_CIF_ISP_HIST_CTRL_MODE_SET_V12(arg->mode);
> +		hist_ctrl |= RKISP1_CIF_ISP_HIST_CTRL_EN_SET_V12(1);
> +		rkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_CTRL_V12,
> +				      hist_ctrl);
> +	} else {
> +		rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_HIST_CTRL_V12,
> +					RKISP1_CIF_ISP_HIST_CTRL_MODE_MASK_V12 |
> +					RKISP1_CIF_ISP_HIST_CTRL_EN_MASK_V12);
>   	}
>   }
>   
> -static void rkisp1_afm_config(struct rkisp1_params *params,
> -			      const struct rkisp1_cif_isp_afc_config *arg)
> +static void rkisp1_afm_config_v10(struct rkisp1_params *params,
> +				  const struct rkisp1_cif_isp_afc_config *arg)
>   {
>   	size_t num_of_win = min_t(size_t, ARRAY_SIZE(arg->afm_win),
>   				  arg->num_afm_win);
> @@ -673,6 +961,45 @@ static void rkisp1_afm_config(struct rkisp1_params *params,
>   	rkisp1_write(params->rkisp1, afm_ctrl, RKISP1_CIF_ISP_AFM_CTRL);
>   }
>   
> +static void rkisp1_afm_config_v12(struct rkisp1_params *params,
> +				  const struct rkisp1_cif_isp_afc_config *arg)
> +{
> +	size_t num_of_win = min_t(size_t, ARRAY_SIZE(arg->afm_win),
> +				  arg->num_afm_win);
> +	u32 afm_ctrl = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AFM_CTRL);
> +	u32 lum_var_shift, afm_var_shift;
> +	unsigned int i;
> +
> +	/* Switch off to configure. */
> +	rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_AFM_CTRL,
> +				RKISP1_CIF_ISP_AFM_ENA);
> +
> +	for (i = 0; i < num_of_win; i++) {
> +		rkisp1_write(params->rkisp1,
> +			     RKISP1_CIF_ISP_AFM_WINDOW_X(arg->afm_win[i].h_offs) |
> +			     RKISP1_CIF_ISP_AFM_WINDOW_Y(arg->afm_win[i].v_offs),
> +			     RKISP1_CIF_ISP_AFM_LT_A + i * 8);
> +		rkisp1_write(params->rkisp1,
> +			     RKISP1_CIF_ISP_AFM_WINDOW_X(arg->afm_win[i].h_size +
> +							 arg->afm_win[i].h_offs) |
> +			     RKISP1_CIF_ISP_AFM_WINDOW_Y(arg->afm_win[i].v_size +
> +							 arg->afm_win[i].v_offs),
> +			     RKISP1_CIF_ISP_AFM_RB_A + i * 8);
> +	}
> +	rkisp1_write(params->rkisp1, arg->thres, RKISP1_CIF_ISP_AFM_THRES);
> +
> +	lum_var_shift = RKISP1_CIF_ISP_AFM_GET_LUM_SHIFT_a_V12(arg->var_shift);
> +	afm_var_shift = RKISP1_CIF_ISP_AFM_GET_AFM_SHIFT_a_V12(arg->var_shift);
> +	rkisp1_write(params->rkisp1,
> +		     RKISP1_CIF_ISP_AFM_SET_SHIFT_a_V12(lum_var_shift, afm_var_shift) |
> +		     RKISP1_CIF_ISP_AFM_SET_SHIFT_b_V12(lum_var_shift, afm_var_shift) |
> +		     RKISP1_CIF_ISP_AFM_SET_SHIFT_c_V12(lum_var_shift, afm_var_shift),
> +		     RKISP1_CIF_ISP_AFM_VAR_SHIFT);
> +
> +	/* restore afm status */
> +	rkisp1_write(params->rkisp1, afm_ctrl, RKISP1_CIF_ISP_AFM_CTRL);
> +}
> +
>   static void rkisp1_ie_config(struct rkisp1_params *params,
>   			     const struct rkisp1_cif_isp_ie_config *arg)
>   {
> @@ -1286,8 +1613,8 @@ static void rkisp1_params_config_parameter(struct rkisp1_params *params)
>   
>   	memset(hst.hist_weight, 0x01, sizeof(hst.hist_weight));
>   	params->ops->hst_config(params, &hst);
> -	rkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_PROP,
> -			      ~RKISP1_CIF_ISP_HIST_PROP_MODE_MASK |
> +	rkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_PROP_V10,
> +			      ~RKISP1_CIF_ISP_HIST_PROP_MODE_MASK_V10 |
>   			      rkisp1_hst_params_default_config.mode);
>   
>   	/* set the  range */
> @@ -1346,22 +1673,38 @@ void rkisp1_params_disable(struct rkisp1_params *params)
>   				RKISP1_CIF_ISP_DPF_MODE_EN);
>   }
>   
> -static struct rkisp1_params_ops rkisp1_params_ops = {
> -	.lsc_matrix_config = rkisp1_lsc_matrix_config,
> -	.goc_config = rkisp1_goc_config,
> -	.awb_meas_config = rkisp1_awb_meas_config,
> -	.awb_meas_enable = rkisp1_awb_meas_enable,
> -	.awb_gain_config = rkisp1_awb_gain_config,
> -	.aec_config = rkisp1_aec_config,
> -	.hst_config = rkisp1_hst_config,
> -	.hst_enable = rkisp1_hst_enable,
> -	.afm_config = rkisp1_afm_config,
> +static struct rkisp1_params_ops rkisp1_v10_params_ops = {
> +	.lsc_matrix_config = rkisp1_lsc_matrix_config_v10,
> +	.goc_config = rkisp1_goc_config_v10,
> +	.awb_meas_config = rkisp1_awb_meas_config_v10,
> +	.awb_meas_enable = rkisp1_awb_meas_enable_v10,
> +	.awb_gain_config = rkisp1_awb_gain_config_v10,
> +	.aec_config = rkisp1_aec_config_v10,
> +	.hst_config = rkisp1_hst_config_v10,
> +	.hst_enable = rkisp1_hst_enable_v10,
> +	.afm_config = rkisp1_afm_config_v10,
>   };
>   
> -static struct rkisp1_params_config rkisp1_params_config = {
> +static struct rkisp1_params_config rkisp1_v10_params_config = {
>   	.gamma_out_max_samples = 17,
>   };
>   
> +static struct rkisp1_params_ops rkisp1_v12_params_ops = {
> +	.lsc_matrix_config = rkisp1_lsc_matrix_config_v12,
> +	.goc_config = rkisp1_goc_config_v12,
> +	.awb_meas_config = rkisp1_awb_meas_config_v12,
> +	.awb_meas_enable = rkisp1_awb_meas_enable_v12,
> +	.awb_gain_config = rkisp1_awb_gain_config_v12,
> +	.aec_config = rkisp1_aec_config_v12,
> +	.hst_config = rkisp1_hst_config_v12,
> +	.hst_enable = rkisp1_hst_enable_v12,
> +	.afm_config = rkisp1_afm_config_v12,
> +};
> +
> +static struct rkisp1_params_config rkisp1_v12_params_config = {
> +	.gamma_out_max_samples = 34,
> +};
> +
>   static int rkisp1_params_enum_fmt_meta_out(struct file *file, void *priv,
>   					   struct v4l2_fmtdesc *f)
>   {
> @@ -1528,8 +1871,14 @@ static void rkisp1_init_params(struct rkisp1_params *params)
>   		V4L2_META_FMT_RK_ISP1_PARAMS;
>   	params->vdev_fmt.fmt.meta.buffersize =
>   		sizeof(struct rkisp1_params_cfg);
> -	params->ops = &rkisp1_params_ops;
> -	params->config = &rkisp1_params_config;
> +
> +	if (params->rkisp1->isp_ver == RKISP1_V12) {
> +		params->ops = &rkisp1_v12_params_ops;
> +		params->config = &rkisp1_v12_params_config;
> +	} else {
> +		params->ops = &rkisp1_v10_params_ops;
> +		params->config = &rkisp1_v10_params_config;
> +	}
>   }
>   
>   int rkisp1_params_register(struct rkisp1_device *rkisp1)
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
> index 8a8d960a679c..388adee3beff 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
> @@ -212,6 +212,35 @@
>   
>   /* CCL */
>   #define RKISP1_CIF_CCL_CIF_CLK_DIS			BIT(2)
> +/* VI_ISP_CLK_CTRL */
> +#define RKISP1_CIF_CLK_CTRL_ISP_RAW			BIT(0)
> +#define RKISP1_CIF_CLK_CTRL_ISP_RGB			BIT(1)
> +#define RKISP1_CIF_CLK_CTRL_ISP_YUV			BIT(2)
> +#define RKISP1_CIF_CLK_CTRL_ISP_3A			BIT(3)
> +#define RKISP1_CIF_CLK_CTRL_MIPI_RAW			BIT(4)
> +#define RKISP1_CIF_CLK_CTRL_ISP_IE			BIT(5)
> +#define RKISP1_CIF_CLK_CTRL_RSZ_RAM			BIT(6)
> +#define RKISP1_CIF_CLK_CTRL_JPEG_RAM			BIT(7)
> +#define RKISP1_CIF_CLK_CTRL_ACLK_ISP			BIT(8)
> +#define RKISP1_CIF_CLK_CTRL_MI_IDC			BIT(9)
> +#define RKISP1_CIF_CLK_CTRL_MI_MP			BIT(10)
> +#define RKISP1_CIF_CLK_CTRL_MI_JPEG			BIT(11)
> +#define RKISP1_CIF_CLK_CTRL_MI_DP			BIT(12)
> +#define RKISP1_CIF_CLK_CTRL_MI_Y12			BIT(13)
> +#define RKISP1_CIF_CLK_CTRL_MI_SP			BIT(14)
> +#define RKISP1_CIF_CLK_CTRL_MI_RAW0			BIT(15)
> +#define RKISP1_CIF_CLK_CTRL_MI_RAW1			BIT(16)
> +#define RKISP1_CIF_CLK_CTRL_MI_READ			BIT(17)
> +#define RKISP1_CIF_CLK_CTRL_MI_RAWRD			BIT(18)
> +#define RKISP1_CIF_CLK_CTRL_CP				BIT(19)
> +#define RKISP1_CIF_CLK_CTRL_IE				BIT(20)
> +#define RKISP1_CIF_CLK_CTRL_SI				BIT(21)
> +#define RKISP1_CIF_CLK_CTRL_RSZM			BIT(22)
> +#define RKISP1_CIF_CLK_CTRL_DPMUX			BIT(23)
> +#define RKISP1_CIF_CLK_CTRL_JPEG			BIT(24)
> +#define RKISP1_CIF_CLK_CTRL_RSZS			BIT(25)
> +#define RKISP1_CIF_CLK_CTRL_MIPI			BIT(26)
> +#define RKISP1_CIF_CLK_CTRL_MARVINMI			BIT(27)
>   /* ICCL */
>   #define RKISP1_CIF_ICCL_ISP_CLK				BIT(0)
>   #define RKISP1_CIF_ICCL_CP_CLK				BIT(1)
> @@ -346,25 +375,57 @@
>   #define RKISP1_CIF_SUPER_IMP_CTRL_TRANSP_DIS		BIT(2)
>   
>   /* ISP HISTOGRAM CALCULATION : ISP_HIST_PROP */
> -#define RKISP1_CIF_ISP_HIST_PROP_MODE_DIS		(0 << 0)
> -#define RKISP1_CIF_ISP_HIST_PROP_MODE_RGB		BIT(0)
> -#define RKISP1_CIF_ISP_HIST_PROP_MODE_RED		(2 << 0)
> -#define RKISP1_CIF_ISP_HIST_PROP_MODE_GREEN		(3 << 0)
> -#define RKISP1_CIF_ISP_HIST_PROP_MODE_BLUE		(4 << 0)
> -#define RKISP1_CIF_ISP_HIST_PROP_MODE_LUM		(5 << 0)
> -#define RKISP1_CIF_ISP_HIST_PROP_MODE_MASK		0x7
> -#define RKISP1_CIF_ISP_HIST_PREDIV_SET(x)		(((x) & 0x7F) << 3)
> -#define RKISP1_CIF_ISP_HIST_WEIGHT_SET(v0, v1, v2, v3)	\
> +#define RKISP1_CIF_ISP_HIST_PROP_MODE_DIS_V10		(0 << 0)
> +#define RKISP1_CIF_ISP_HIST_PROP_MODE_RGB_V10		BIT(0)
> +#define RKISP1_CIF_ISP_HIST_PROP_MODE_RED_V10		(2 << 0)
> +#define RKISP1_CIF_ISP_HIST_PROP_MODE_GREEN_V10		(3 << 0)
> +#define RKISP1_CIF_ISP_HIST_PROP_MODE_BLUE_V10		(4 << 0)
> +#define RKISP1_CIF_ISP_HIST_PROP_MODE_LUM_V10		(5 << 0)
> +#define RKISP1_CIF_ISP_HIST_PROP_MODE_MASK_V10		0x7
> +#define RKISP1_CIF_ISP_HIST_PREDIV_SET_V10(x)		(((x) & 0x7F) << 3)
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_SET_V10(v0, v1, v2, v3)	\
>   				     (((v0) & 0x1F) | (((v1) & 0x1F) << 8)  |\
>   				     (((v2) & 0x1F) << 16) | \
>   				     (((v3) & 0x1F) << 24))
>   
> -#define RKISP1_CIF_ISP_HIST_WINDOW_OFFSET_RESERVED	0xFFFFF000
> -#define RKISP1_CIF_ISP_HIST_WINDOW_SIZE_RESERVED	0xFFFFF800
> -#define RKISP1_CIF_ISP_HIST_WEIGHT_RESERVED		0xE0E0E0E0
> -#define RKISP1_CIF_ISP_MAX_HIST_PREDIVIDER		0x0000007F
> -#define RKISP1_CIF_ISP_HIST_ROW_NUM			5
> -#define RKISP1_CIF_ISP_HIST_COLUMN_NUM			5
> +#define RKISP1_CIF_ISP_HIST_WINDOW_OFFSET_RESERVED_V10	0xFFFFF000
> +#define RKISP1_CIF_ISP_HIST_WINDOW_SIZE_RESERVED_V10	0xFFFFF800
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_RESERVED_V10		0xE0E0E0E0
> +#define RKISP1_CIF_ISP_MAX_HIST_PREDIVIDER_V10		0x0000007F
> +#define RKISP1_CIF_ISP_HIST_ROW_NUM_V10			5
> +#define RKISP1_CIF_ISP_HIST_COLUMN_NUM_V10		5
> +
> +/* ISP HISTOGRAM CALCULATION : CIF_ISP_HIST */
> +#define RKISP1_CIF_ISP_HIST_CTRL_EN_SET_V12(x)		(((x) & 0x01) << 0)
> +#define RKISP1_CIF_ISP_HIST_CTRL_EN_MASK_V12		RKISP1_CIF_ISP_HIST_CTRL_EN_SET_V12(0x01)
> +#define RKISP1_CIF_ISP_HIST_CTRL_STEPSIZE_SET_V12(x)	(((x) & 0x7F) << 1)
> +#define RKISP1_CIF_ISP_HIST_CTRL_MODE_SET_V12(x)	(((x) & 0x07) << 8)
> +#define RKISP1_CIF_ISP_HIST_CTRL_MODE_MASK_V12		RKISP1_CIF_ISP_HIST_CTRL_MODE_SET_V12(0x07)
> +#define RKISP1_CIF_ISP_HIST_CTRL_AUTOSTOP_SET_V12(x)	(((x) & 0x01) << 11)
> +#define RKISP1_CIF_ISP_HIST_CTRL_WATERLINE_SET_V12(x)	(((x) & 0xFFF) << 12)
> +#define RKISP1_CIF_ISP_HIST_CTRL_DATASEL_SET_V12(x)	(((x) & 0x07) << 24)
> +#define RKISP1_CIF_ISP_HIST_CTRL_INTRSEL_SET_V12(x)	(((x) & 0x01) << 27)
> +#define RKISP1_CIF_ISP_HIST_CTRL_WNDNUM_SET_V12(x)	(((x) & 0x03) << 28)
> +#define RKISP1_CIF_ISP_HIST_CTRL_DBGEN_SET_V12(x)	(((x) & 0x01) << 30)
> +#define RKISP1_CIF_ISP_HIST_ROW_NUM_V12		15
> +#define RKISP1_CIF_ISP_HIST_COLUMN_NUM_V12		15
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_REG_SIZE_V12	\
> +				(RKISP1_CIF_ISP_HIST_ROW_NUM_V12 * RKISP1_CIF_ISP_HIST_COLUMN_NUM_V12)
> +
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_SET_V12(v0, v1, v2, v3)	\
> +				(((v0) & 0x3F) | (((v1) & 0x3F) << 8) |\
> +				(((v2) & 0x3F) << 16) |\
> +				(((v3) & 0x3F) << 24))
> +
> +#define RKISP1_CIF_ISP_HIST_OFFS_SET_V12(v0, v1)	\
> +				(((v0) & 0x1FFF) | (((v1) & 0x1FFF) << 16))
> +#define RKISP1_CIF_ISP_HIST_SIZE_SET_V12(v0, v1)	\
> +				(((v0) & 0x7FF) | (((v1) & 0x7FF) << 16))
> +
> +#define RKISP1_CIF_ISP_HIST_GET_BIN0_V12(x)	\
> +				((x) & 0xFFFF)
> +#define RKISP1_CIF_ISP_HIST_GET_BIN1_V12(x)	\
> +				(((x) >> 16) & 0xFFFF)
>   
>   /* AUTO FOCUS MEASUREMENT:  ISP_AFM_CTRL */
>   #define RKISP1_ISP_AFM_CTRL_ENABLE			BIT(0)
> @@ -400,6 +461,8 @@
>   #define RKISP1_CIF_ISP_AWB_MODE_YCBCR_EN		((0 << 31) | (0x2 << 0))
>   #define RKISP1_CIF_ISP_AWB_MODE_MASK_NONE		0xFFFFFFFC
>   #define RKISP1_CIF_ISP_AWB_MODE_READ(x)			((x) & 3)
> +#define RKISP1_CIF_ISP_AWB_SET_FRAMES_V12(x)		(((x) & 0x07) << 28)
> +#define RKISP1_CIF_ISP_AWB_SET_FRAMES_MASK_V12		RKISP1_CIF_ISP_AWB_SET_FRAMES_V12(0x07)
>   /* ISP_AWB_GAIN_RB, ISP_AWB_GAIN_G  */
>   #define RKISP1_CIF_ISP_AWB_GAIN_R_SET(x)		(((x) & 0x3FF) << 16)
>   #define RKISP1_CIF_ISP_AWB_GAIN_R_READ(x)		(((x) >> 16) & 0x3FF)
> @@ -434,6 +497,7 @@
>   /* ISP_EXP_CTRL */
>   #define RKISP1_CIF_ISP_EXP_ENA				BIT(0)
>   #define RKISP1_CIF_ISP_EXP_CTRL_AUTOSTOP		BIT(1)
> +#define RKISP1_CIF_ISP_EXP_CTRL_WNDNUM_SET_V12(x)	(((x) & 0x03) << 2)
>   /*
>    *'1' luminance calculation according to  Y=(R+G+B) x 0.332 (85/256)
>    *'0' luminance calculation according to Y=16+0.25R+0.5G+0.1094B
> @@ -441,42 +505,76 @@
>   #define RKISP1_CIF_ISP_EXP_CTRL_MEASMODE_1		BIT(31)
>   
>   /* ISP_EXP_H_SIZE */
> -#define RKISP1_CIF_ISP_EXP_H_SIZE_SET(x)		((x) & 0x7FF)
> -#define RKISP1_CIF_ISP_EXP_HEIGHT_MASK			0x000007FF
> +#define RKISP1_CIF_ISP_EXP_H_SIZE_SET_V10(x)		((x) & 0x7FF)
> +#define RKISP1_CIF_ISP_EXP_HEIGHT_MASK_V10			0x000007FF
> +#define RKISP1_CIF_ISP_EXP_H_SIZE_SET_V12(x)		((x) & 0x7FF)
> +#define RKISP1_CIF_ISP_EXP_HEIGHT_MASK_V12		0x000007FF
>   /* ISP_EXP_V_SIZE : vertical size must be a multiple of 2). */
> -#define RKISP1_CIF_ISP_EXP_V_SIZE_SET(x)		((x) & 0x7FE)
> +#define RKISP1_CIF_ISP_EXP_V_SIZE_SET_V10(x)		((x) & 0x7FE)
> +#define RKISP1_CIF_ISP_EXP_V_SIZE_SET_V12(x)		(((x) & 0x7FE) << 16)
>   
>   /* ISP_EXP_H_OFFSET */
> -#define RKISP1_CIF_ISP_EXP_H_OFFSET_SET(x)		((x) & 0x1FFF)
> -#define RKISP1_CIF_ISP_EXP_MAX_HOFFS			2424
> +#define RKISP1_CIF_ISP_EXP_H_OFFSET_SET_V10(x)		((x) & 0x1FFF)
> +#define RKISP1_CIF_ISP_EXP_MAX_HOFFS_V10		2424
> +#define RKISP1_CIF_ISP_EXP_H_OFFSET_SET_V12(x)		((x) & 0x1FFF)
> +#define RKISP1_CIF_ISP_EXP_MAX_HOFFS_V12		0x1FFF
>   /* ISP_EXP_V_OFFSET */
> -#define RKISP1_CIF_ISP_EXP_V_OFFSET_SET(x)		((x) & 0x1FFF)
> -#define RKISP1_CIF_ISP_EXP_MAX_VOFFS			1806
> -
> -#define RKISP1_CIF_ISP_EXP_ROW_NUM			5
> -#define RKISP1_CIF_ISP_EXP_COLUMN_NUM			5
> -#define RKISP1_CIF_ISP_EXP_NUM_LUMA_REGS \
> -	(RKISP1_CIF_ISP_EXP_ROW_NUM * RKISP1_CIF_ISP_EXP_COLUMN_NUM)
> -#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE		516
> -#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE		35
> -#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE		390
> -#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE		28
> -#define RKISP1_CIF_ISP_EXP_MAX_HSIZE	\
> -	(RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE * RKISP1_CIF_ISP_EXP_COLUMN_NUM + 1)
> -#define RKISP1_CIF_ISP_EXP_MIN_HSIZE	\
> -	(RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE * RKISP1_CIF_ISP_EXP_COLUMN_NUM + 1)
> -#define RKISP1_CIF_ISP_EXP_MAX_VSIZE	\
> -	(RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE * RKISP1_CIF_ISP_EXP_ROW_NUM + 1)
> -#define RKISP1_CIF_ISP_EXP_MIN_VSIZE	\
> -	(RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE * RKISP1_CIF_ISP_EXP_ROW_NUM + 1)
> +#define RKISP1_CIF_ISP_EXP_V_OFFSET_SET_V10(x)		((x) & 0x1FFF)
> +#define RKISP1_CIF_ISP_EXP_MAX_VOFFS_V10		1806
> +#define RKISP1_CIF_ISP_EXP_V_OFFSET_SET_V12(x)		(((x) & 0x1FFF) << 16)
> +#define RKISP1_CIF_ISP_EXP_MAX_VOFFS_V12		0x1FFF
> +
> +#define RKISP1_CIF_ISP_EXP_ROW_NUM_V10			5
> +#define RKISP1_CIF_ISP_EXP_COLUMN_NUM_V10			5
> +#define RKISP1_CIF_ISP_EXP_NUM_LUMA_REGS_V10 \
> +	(RKISP1_CIF_ISP_EXP_ROW_NUM_V10 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V10)
> +#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE_V10		516
> +#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE_V10		35
> +#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE_V10		390
> +#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE_V10		28
> +#define RKISP1_CIF_ISP_EXP_MAX_HSIZE_V10	\
> +	(RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE_V10 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V10 + 1)
> +#define RKISP1_CIF_ISP_EXP_MIN_HSIZE_V10	\
> +	(RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE_V10 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V10 + 1)
> +#define RKISP1_CIF_ISP_EXP_MAX_VSIZE_V10	\
> +	(RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE_V10 * RKISP1_CIF_ISP_EXP_ROW_NUM_V10 + 1)
> +#define RKISP1_CIF_ISP_EXP_MIN_VSIZE_V10	\
> +	(RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE_V10 * RKISP1_CIF_ISP_EXP_ROW_NUM_V10 + 1)
> +
> +#define RKISP1_CIF_ISP_EXP_ROW_NUM_V12			15
> +#define RKISP1_CIF_ISP_EXP_COLUMN_NUM_V12		15
> +#define RKISP1_CIF_ISP_EXP_NUM_LUMA_REGS_V12 \
> +	(RKISP1_CIF_ISP_EXP_ROW_NUM_V12 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V12)
> +
> +#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE_V12		0x7FF
> +#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE_V12		0xE
> +#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE_V12		0x7FE
> +#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE_V12		0xE
> +#define RKISP1_CIF_ISP_EXP_MAX_HSIZE_V12	\
> +	(RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE_V12 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V12 + 1)
> +#define RKISP1_CIF_ISP_EXP_MIN_HSIZE_V12	\
> +	(RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE_V12 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V12 + 1)
> +#define RKISP1_CIF_ISP_EXP_MAX_VSIZE_V12	\
> +	(RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE_V12 * RKISP1_CIF_ISP_EXP_ROW_NUM_V12 + 1)
> +#define RKISP1_CIF_ISP_EXP_MIN_VSIZE_V12	\
> +	(RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE_V12 * RKISP1_CIF_ISP_EXP_ROW_NUM_V12 + 1)
> +
> +#define RKISP1_CIF_ISP_EXP_GET_MEAN_xy0_V12(x)		((x) & 0xFF)
> +#define RKISP1_CIF_ISP_EXP_GET_MEAN_xy1_V12(x)		(((x) >> 8) & 0xFF)
> +#define RKISP1_CIF_ISP_EXP_GET_MEAN_xy2_V12(x)		(((x) >> 16) & 0xFF)
> +#define RKISP1_CIF_ISP_EXP_GET_MEAN_xy3_V12(x)		(((x) >> 24) & 0xFF)
>   
>   /* LSC: ISP_LSC_CTRL */
>   #define RKISP1_CIF_ISP_LSC_CTRL_ENA			BIT(0)
>   #define RKISP1_CIF_ISP_LSC_SECT_SIZE_RESERVED		0xFC00FC00
> -#define RKISP1_CIF_ISP_LSC_GRAD_RESERVED		0xF000F000
> -#define RKISP1_CIF_ISP_LSC_SAMPLE_RESERVED		0xF000F000
> -#define RKISP1_CIF_ISP_LSC_TABLE_DATA(v0, v1)     \
> +#define RKISP1_CIF_ISP_LSC_GRAD_RESERVED_V10		0xF000F000
> +#define RKISP1_CIF_ISP_LSC_SAMPLE_RESERVED_V10		0xF000F000
> +#define RKISP1_CIF_ISP_LSC_GRAD_RESERVED_V12		0xE000E000
> +#define RKISP1_CIF_ISP_LSC_SAMPLE_RESERVED_V12		0xE000E000
> +#define RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(v0, v1)     \
>   	(((v0) & 0xFFF) | (((v1) & 0xFFF) << 12))
> +#define RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(v0, v1)     \
> +	(((v0) & 0x1FFF) | (((v1) & 0x1FFF) << 13))
>   #define RKISP1_CIF_ISP_LSC_SECT_SIZE(v0, v1)      \
>   	(((v0) & 0xFFF) | (((v1) & 0xFFF) << 16))
>   #define RKISP1_CIF_ISP_LSC_GRAD_SIZE(v0, v1)      \
> @@ -549,6 +647,10 @@
>   	(1 << 15) | (1 << 11) | (1 << 7) | (1 << 3))
>   #define RKISP1_CIFISP_DEGAMMA_Y_RESERVED		0xFFFFF000
>   
> +/* GAMMA-OUT */
> +#define RKISP1_CIF_ISP_GAMMA_VALUE_V12(x, y)	\
> +	(((x) & 0xFFF) << 16 | ((y) & 0xFFF) << 0)
> +
>   /* AFM */
>   #define RKISP1_CIF_ISP_AFM_ENA				BIT(0)
>   #define RKISP1_CIF_ISP_AFM_THRES_RESERVED		0xFFFF0000
> @@ -559,6 +661,11 @@
>   #define RKISP1_CIF_ISP_AFM_WINDOW_Y_MIN			0x2
>   #define RKISP1_CIF_ISP_AFM_WINDOW_X(x)			(((x) & 0x1FFF) << 16)
>   #define RKISP1_CIF_ISP_AFM_WINDOW_Y(x)			((x) & 0x1FFF)
> +#define RKISP1_CIF_ISP_AFM_SET_SHIFT_a_V12(x, y)	(((x) & 0x7) << 16 | ((y) & 0x7) << 0)
> +#define RKISP1_CIF_ISP_AFM_SET_SHIFT_b_V12(x, y)	(((x) & 0x7) << 20 | ((y) & 0x7) << 4)
> +#define RKISP1_CIF_ISP_AFM_SET_SHIFT_c_V12(x, y)	(((x) & 0x7) << 24 | ((y) & 0x7) << 8)
> +#define RKISP1_CIF_ISP_AFM_GET_LUM_SHIFT_a_V12(x)	(((x) & 0x70000) >> 16)
> +#define RKISP1_CIF_ISP_AFM_GET_AFM_SHIFT_a_V12(x)	((x) & 0x7)
>   
>   /* DPF */
>   #define RKISP1_CIF_ISP_DPF_MODE_EN			BIT(0)
> @@ -581,6 +688,7 @@
>   #define RKISP1_CIF_CTRL_BASE			0x00000000
>   #define RKISP1_CIF_CCL				(RKISP1_CIF_CTRL_BASE + 0x00000000)
>   #define RKISP1_CIF_VI_ID			(RKISP1_CIF_CTRL_BASE + 0x00000008)
> +#define RKISP1_CIF_VI_ISP_CLK_CTRL_V12		(RKISP1_CIF_CTRL_BASE + 0x0000000C)
>   #define RKISP1_CIF_ICCL				(RKISP1_CIF_CTRL_BASE + 0x00000010)
>   #define RKISP1_CIF_IRCL				(RKISP1_CIF_CTRL_BASE + 0x00000014)
>   #define RKISP1_CIF_VI_DPCL			(RKISP1_CIF_CTRL_BASE + 0x00000018)
> @@ -666,18 +774,35 @@
>   #define RKISP1_CIF_ISP_GAMMA_B_Y14		(RKISP1_CIF_ISP_BASE + 0x000000E4)
>   #define RKISP1_CIF_ISP_GAMMA_B_Y15		(RKISP1_CIF_ISP_BASE + 0x000000E8)
>   #define RKISP1_CIF_ISP_GAMMA_B_Y16		(RKISP1_CIF_ISP_BASE + 0x000000EC)
> -#define RKISP1_CIF_ISP_AWB_PROP			(RKISP1_CIF_ISP_BASE + 0x00000110)
> -#define RKISP1_CIF_ISP_AWB_WND_H_OFFS		(RKISP1_CIF_ISP_BASE + 0x00000114)
> -#define RKISP1_CIF_ISP_AWB_WND_V_OFFS		(RKISP1_CIF_ISP_BASE + 0x00000118)
> -#define RKISP1_CIF_ISP_AWB_WND_H_SIZE		(RKISP1_CIF_ISP_BASE + 0x0000011C)
> -#define RKISP1_CIF_ISP_AWB_WND_V_SIZE		(RKISP1_CIF_ISP_BASE + 0x00000120)
> -#define RKISP1_CIF_ISP_AWB_FRAMES		(RKISP1_CIF_ISP_BASE + 0x00000124)
> -#define RKISP1_CIF_ISP_AWB_REF			(RKISP1_CIF_ISP_BASE + 0x00000128)
> -#define RKISP1_CIF_ISP_AWB_THRESH		(RKISP1_CIF_ISP_BASE + 0x0000012C)
> -#define RKISP1_CIF_ISP_AWB_GAIN_G		(RKISP1_CIF_ISP_BASE + 0x00000138)
> -#define RKISP1_CIF_ISP_AWB_GAIN_RB		(RKISP1_CIF_ISP_BASE + 0x0000013C)
> -#define RKISP1_CIF_ISP_AWB_WHITE_CNT		(RKISP1_CIF_ISP_BASE + 0x00000140)
> -#define RKISP1_CIF_ISP_AWB_MEAN			(RKISP1_CIF_ISP_BASE + 0x00000144)
> +#define RKISP1_CIF_ISP_AWB_PROP_V10		(RKISP1_CIF_ISP_BASE + 0x00000110)
> +#define RKISP1_CIF_ISP_AWB_WND_H_OFFS_V10	(RKISP1_CIF_ISP_BASE + 0x00000114)
> +#define RKISP1_CIF_ISP_AWB_WND_V_OFFS_V10	(RKISP1_CIF_ISP_BASE + 0x00000118)
> +#define RKISP1_CIF_ISP_AWB_WND_H_SIZE_V10	(RKISP1_CIF_ISP_BASE + 0x0000011C)
> +#define RKISP1_CIF_ISP_AWB_WND_V_SIZE_V10	(RKISP1_CIF_ISP_BASE + 0x00000120)
> +#define RKISP1_CIF_ISP_AWB_FRAMES_V10		(RKISP1_CIF_ISP_BASE + 0x00000124)
> +#define RKISP1_CIF_ISP_AWB_REF_V10		(RKISP1_CIF_ISP_BASE + 0x00000128)
> +#define RKISP1_CIF_ISP_AWB_THRESH_V10		(RKISP1_CIF_ISP_BASE + 0x0000012C)
> +#define RKISP1_CIF_ISP_AWB_GAIN_G_V10		(RKISP1_CIF_ISP_BASE + 0x00000138)
> +#define RKISP1_CIF_ISP_AWB_GAIN_RB_V10		(RKISP1_CIF_ISP_BASE + 0x0000013C)
> +#define RKISP1_CIF_ISP_AWB_WHITE_CNT_V10	(RKISP1_CIF_ISP_BASE + 0x00000140)
> +#define RKISP1_CIF_ISP_AWB_MEAN_V10		(RKISP1_CIF_ISP_BASE + 0x00000144)
> +#define RKISP1_CIF_ISP_AWB_PROP_V12		(RKISP1_CIF_ISP_BASE + 0x00000110)
> +#define RKISP1_CIF_ISP_AWB_SIZE_V12		(RKISP1_CIF_ISP_BASE + 0x00000114)
> +#define RKISP1_CIF_ISP_AWB_OFFS_V12		(RKISP1_CIF_ISP_BASE + 0x00000118)
> +#define RKISP1_CIF_ISP_AWB_REF_V12		(RKISP1_CIF_ISP_BASE + 0x0000011C)
> +#define RKISP1_CIF_ISP_AWB_THRESH_V12		(RKISP1_CIF_ISP_BASE + 0x00000120)
> +#define RKISP1_CIF_ISP_X_COOR12_V12		(RKISP1_CIF_ISP_BASE + 0x00000124)
> +#define RKISP1_CIF_ISP_X_COOR34_V12		(RKISP1_CIF_ISP_BASE + 0x00000128)
> +#define RKISP1_CIF_ISP_AWB_WHITE_CNT_V12	(RKISP1_CIF_ISP_BASE + 0x0000012C)
> +#define RKISP1_CIF_ISP_AWB_MEAN_V12		(RKISP1_CIF_ISP_BASE + 0x00000130)
> +#define RKISP1_CIF_ISP_DEGAIN_V12		(RKISP1_CIF_ISP_BASE + 0x00000134)
> +#define RKISP1_CIF_ISP_AWB_GAIN_G_V12		(RKISP1_CIF_ISP_BASE + 0x00000138)
> +#define RKISP1_CIF_ISP_AWB_GAIN_RB_V12		(RKISP1_CIF_ISP_BASE + 0x0000013C)
> +#define RKISP1_CIF_ISP_REGION_LINE_V12		(RKISP1_CIF_ISP_BASE + 0x00000140)
> +#define RKISP1_CIF_ISP_WP_CNT_REGION0_V12	(RKISP1_CIF_ISP_BASE + 0x00000160)
> +#define RKISP1_CIF_ISP_WP_CNT_REGION1_V12	(RKISP1_CIF_ISP_BASE + 0x00000164)
> +#define RKISP1_CIF_ISP_WP_CNT_REGION2_V12	(RKISP1_CIF_ISP_BASE + 0x00000168)
> +#define RKISP1_CIF_ISP_WP_CNT_REGION3_V12	(RKISP1_CIF_ISP_BASE + 0x0000016C)
>   #define RKISP1_CIF_ISP_CC_COEFF_0		(RKISP1_CIF_ISP_BASE + 0x00000170)
>   #define RKISP1_CIF_ISP_CC_COEFF_1		(RKISP1_CIF_ISP_BASE + 0x00000174)
>   #define RKISP1_CIF_ISP_CC_COEFF_2		(RKISP1_CIF_ISP_BASE + 0x00000178)
> @@ -711,30 +836,32 @@
>   #define RKISP1_CIF_ISP_CT_COEFF_6		(RKISP1_CIF_ISP_BASE + 0x000001E8)
>   #define RKISP1_CIF_ISP_CT_COEFF_7		(RKISP1_CIF_ISP_BASE + 0x000001EC)
>   #define RKISP1_CIF_ISP_CT_COEFF_8		(RKISP1_CIF_ISP_BASE + 0x000001F0)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_MODE		(RKISP1_CIF_ISP_BASE + 0x000001F4)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_0		(RKISP1_CIF_ISP_BASE + 0x000001F8)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_1		(RKISP1_CIF_ISP_BASE + 0x000001FC)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_2		(RKISP1_CIF_ISP_BASE + 0x00000200)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_3		(RKISP1_CIF_ISP_BASE + 0x00000204)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_4		(RKISP1_CIF_ISP_BASE + 0x00000208)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_5		(RKISP1_CIF_ISP_BASE + 0x0000020C)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_6		(RKISP1_CIF_ISP_BASE + 0x00000210)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_7		(RKISP1_CIF_ISP_BASE + 0x00000214)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_8		(RKISP1_CIF_ISP_BASE + 0x00000218)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_9		(RKISP1_CIF_ISP_BASE + 0x0000021C)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_10		(RKISP1_CIF_ISP_BASE + 0x00000220)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_11		(RKISP1_CIF_ISP_BASE + 0x00000224)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_12		(RKISP1_CIF_ISP_BASE + 0x00000228)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_13		(RKISP1_CIF_ISP_BASE + 0x0000022C)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_14		(RKISP1_CIF_ISP_BASE + 0x00000230)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_15		(RKISP1_CIF_ISP_BASE + 0x00000234)
> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_16		(RKISP1_CIF_ISP_BASE + 0x00000238)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_MODE_V10	(RKISP1_CIF_ISP_BASE + 0x000001F4)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_0_V10	(RKISP1_CIF_ISP_BASE + 0x000001F8)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_1_V10	(RKISP1_CIF_ISP_BASE + 0x000001FC)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_2_V10	(RKISP1_CIF_ISP_BASE + 0x00000200)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_3_V10	(RKISP1_CIF_ISP_BASE + 0x00000204)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_4_V10	(RKISP1_CIF_ISP_BASE + 0x00000208)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_5_V10	(RKISP1_CIF_ISP_BASE + 0x0000020C)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_6_V10	(RKISP1_CIF_ISP_BASE + 0x00000210)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_7_V10	(RKISP1_CIF_ISP_BASE + 0x00000214)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_8_V10	(RKISP1_CIF_ISP_BASE + 0x00000218)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_9_V10	(RKISP1_CIF_ISP_BASE + 0x0000021C)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_10_V10	(RKISP1_CIF_ISP_BASE + 0x00000220)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_11_V10	(RKISP1_CIF_ISP_BASE + 0x00000224)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_12_V10	(RKISP1_CIF_ISP_BASE + 0x00000228)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_13_V10	(RKISP1_CIF_ISP_BASE + 0x0000022C)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_14_V10	(RKISP1_CIF_ISP_BASE + 0x00000230)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_15_V10	(RKISP1_CIF_ISP_BASE + 0x00000234)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_16_V10	(RKISP1_CIF_ISP_BASE + 0x00000238)
>   #define RKISP1_CIF_ISP_ERR			(RKISP1_CIF_ISP_BASE + 0x0000023C)
>   #define RKISP1_CIF_ISP_ERR_CLR			(RKISP1_CIF_ISP_BASE + 0x00000240)
>   #define RKISP1_CIF_ISP_FRAME_COUNT		(RKISP1_CIF_ISP_BASE + 0x00000244)
>   #define RKISP1_CIF_ISP_CT_OFFSET_R		(RKISP1_CIF_ISP_BASE + 0x00000248)
>   #define RKISP1_CIF_ISP_CT_OFFSET_G		(RKISP1_CIF_ISP_BASE + 0x0000024C)
>   #define RKISP1_CIF_ISP_CT_OFFSET_B		(RKISP1_CIF_ISP_BASE + 0x00000250)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_MODE_V12	(RKISP1_CIF_ISP_BASE + 0x00000300)
> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_0_V12	(RKISP1_CIF_ISP_BASE + 0x00000304)
>   
>   #define RKISP1_CIF_ISP_FLASH_BASE		0x00000660
>   #define RKISP1_CIF_ISP_FLASH_CMD		(RKISP1_CIF_ISP_FLASH_BASE + 0x00000000)
> @@ -1004,36 +1131,35 @@
>   #define RKISP1_CIF_ISP_IS_H_SIZE_SHD		(RKISP1_CIF_ISP_IS_BASE + 0x0000002C)
>   #define RKISP1_CIF_ISP_IS_V_SIZE_SHD		(RKISP1_CIF_ISP_IS_BASE + 0x00000030)
>   
> -#define RKISP1_CIF_ISP_HIST_BASE		0x00002400
> -
> -#define RKISP1_CIF_ISP_HIST_PROP		(RKISP1_CIF_ISP_HIST_BASE + 0x00000000)
> -#define RKISP1_CIF_ISP_HIST_H_OFFS		(RKISP1_CIF_ISP_HIST_BASE + 0x00000004)
> -#define RKISP1_CIF_ISP_HIST_V_OFFS		(RKISP1_CIF_ISP_HIST_BASE + 0x00000008)
> -#define RKISP1_CIF_ISP_HIST_H_SIZE		(RKISP1_CIF_ISP_HIST_BASE + 0x0000000C)
> -#define RKISP1_CIF_ISP_HIST_V_SIZE		(RKISP1_CIF_ISP_HIST_BASE + 0x00000010)
> -#define RKISP1_CIF_ISP_HIST_BIN_0		(RKISP1_CIF_ISP_HIST_BASE + 0x00000014)
> -#define RKISP1_CIF_ISP_HIST_BIN_1		(RKISP1_CIF_ISP_HIST_BASE + 0x00000018)
> -#define RKISP1_CIF_ISP_HIST_BIN_2		(RKISP1_CIF_ISP_HIST_BASE + 0x0000001C)
> -#define RKISP1_CIF_ISP_HIST_BIN_3		(RKISP1_CIF_ISP_HIST_BASE + 0x00000020)
> -#define RKISP1_CIF_ISP_HIST_BIN_4		(RKISP1_CIF_ISP_HIST_BASE + 0x00000024)
> -#define RKISP1_CIF_ISP_HIST_BIN_5		(RKISP1_CIF_ISP_HIST_BASE + 0x00000028)
> -#define RKISP1_CIF_ISP_HIST_BIN_6		(RKISP1_CIF_ISP_HIST_BASE + 0x0000002C)
> -#define RKISP1_CIF_ISP_HIST_BIN_7		(RKISP1_CIF_ISP_HIST_BASE + 0x00000030)
> -#define RKISP1_CIF_ISP_HIST_BIN_8		(RKISP1_CIF_ISP_HIST_BASE + 0x00000034)
> -#define RKISP1_CIF_ISP_HIST_BIN_9		(RKISP1_CIF_ISP_HIST_BASE + 0x00000038)
> -#define RKISP1_CIF_ISP_HIST_BIN_10		(RKISP1_CIF_ISP_HIST_BASE + 0x0000003C)
> -#define RKISP1_CIF_ISP_HIST_BIN_11		(RKISP1_CIF_ISP_HIST_BASE + 0x00000040)
> -#define RKISP1_CIF_ISP_HIST_BIN_12		(RKISP1_CIF_ISP_HIST_BASE + 0x00000044)
> -#define RKISP1_CIF_ISP_HIST_BIN_13		(RKISP1_CIF_ISP_HIST_BASE + 0x00000048)
> -#define RKISP1_CIF_ISP_HIST_BIN_14		(RKISP1_CIF_ISP_HIST_BASE + 0x0000004C)
> -#define RKISP1_CIF_ISP_HIST_BIN_15		(RKISP1_CIF_ISP_HIST_BASE + 0x00000050)
> -#define RKISP1_CIF_ISP_HIST_WEIGHT_00TO30	(RKISP1_CIF_ISP_HIST_BASE + 0x00000054)
> -#define RKISP1_CIF_ISP_HIST_WEIGHT_40TO21	(RKISP1_CIF_ISP_HIST_BASE + 0x00000058)
> -#define RKISP1_CIF_ISP_HIST_WEIGHT_31TO12	(RKISP1_CIF_ISP_HIST_BASE + 0x0000005C)
> -#define RKISP1_CIF_ISP_HIST_WEIGHT_22TO03	(RKISP1_CIF_ISP_HIST_BASE + 0x00000060)
> -#define RKISP1_CIF_ISP_HIST_WEIGHT_13TO43	(RKISP1_CIF_ISP_HIST_BASE + 0x00000064)
> -#define RKISP1_CIF_ISP_HIST_WEIGHT_04TO34	(RKISP1_CIF_ISP_HIST_BASE + 0x00000068)
> -#define RKISP1_CIF_ISP_HIST_WEIGHT_44		(RKISP1_CIF_ISP_HIST_BASE + 0x0000006C)
> +#define RKISP1_CIF_ISP_HIST_BASE_V10		0x00002400
> +#define RKISP1_CIF_ISP_HIST_PROP_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000000)
> +#define RKISP1_CIF_ISP_HIST_H_OFFS_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000004)
> +#define RKISP1_CIF_ISP_HIST_V_OFFS_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000008)
> +#define RKISP1_CIF_ISP_HIST_H_SIZE_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000000C)
> +#define RKISP1_CIF_ISP_HIST_V_SIZE_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000010)
> +#define RKISP1_CIF_ISP_HIST_BIN_0_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000014)
> +#define RKISP1_CIF_ISP_HIST_BIN_1_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000018)
> +#define RKISP1_CIF_ISP_HIST_BIN_2_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000001C)
> +#define RKISP1_CIF_ISP_HIST_BIN_3_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000020)
> +#define RKISP1_CIF_ISP_HIST_BIN_4_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000024)
> +#define RKISP1_CIF_ISP_HIST_BIN_5_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000028)
> +#define RKISP1_CIF_ISP_HIST_BIN_6_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000002C)
> +#define RKISP1_CIF_ISP_HIST_BIN_7_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000030)
> +#define RKISP1_CIF_ISP_HIST_BIN_8_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000034)
> +#define RKISP1_CIF_ISP_HIST_BIN_9_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000038)
> +#define RKISP1_CIF_ISP_HIST_BIN_10_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000003C)
> +#define RKISP1_CIF_ISP_HIST_BIN_11_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000040)
> +#define RKISP1_CIF_ISP_HIST_BIN_12_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000044)
> +#define RKISP1_CIF_ISP_HIST_BIN_13_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000048)
> +#define RKISP1_CIF_ISP_HIST_BIN_14_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000004C)
> +#define RKISP1_CIF_ISP_HIST_BIN_15_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000050)
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_00TO30_V10	(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000054)
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_40TO21_V10	(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000058)
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_31TO12_V10	(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000005C)
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_22TO03_V10	(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000060)
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_13TO43_V10	(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000064)
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_04TO34_V10	(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000068)
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_44_V10	(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000006C)
>   
>   #define RKISP1_CIF_ISP_FILT_BASE		0x00002500
>   #define RKISP1_CIF_ISP_FILT_MODE		(RKISP1_CIF_ISP_FILT_BASE + 0x00000000)
> @@ -1059,35 +1185,38 @@
>   
>   #define RKISP1_CIF_ISP_EXP_BASE			0x00002600
>   #define RKISP1_CIF_ISP_EXP_CTRL			(RKISP1_CIF_ISP_EXP_BASE + 0x00000000)
> -#define RKISP1_CIF_ISP_EXP_H_OFFSET		(RKISP1_CIF_ISP_EXP_BASE + 0x00000004)
> -#define RKISP1_CIF_ISP_EXP_V_OFFSET		(RKISP1_CIF_ISP_EXP_BASE + 0x00000008)
> -#define RKISP1_CIF_ISP_EXP_H_SIZE		(RKISP1_CIF_ISP_EXP_BASE + 0x0000000C)
> -#define RKISP1_CIF_ISP_EXP_V_SIZE		(RKISP1_CIF_ISP_EXP_BASE + 0x00000010)
> -#define RKISP1_CIF_ISP_EXP_MEAN_00		(RKISP1_CIF_ISP_EXP_BASE + 0x00000014)
> -#define RKISP1_CIF_ISP_EXP_MEAN_10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000018)
> -#define RKISP1_CIF_ISP_EXP_MEAN_20		(RKISP1_CIF_ISP_EXP_BASE + 0x0000001c)
> -#define RKISP1_CIF_ISP_EXP_MEAN_30		(RKISP1_CIF_ISP_EXP_BASE + 0x00000020)
> -#define RKISP1_CIF_ISP_EXP_MEAN_40		(RKISP1_CIF_ISP_EXP_BASE + 0x00000024)
> -#define RKISP1_CIF_ISP_EXP_MEAN_01		(RKISP1_CIF_ISP_EXP_BASE + 0x00000028)
> -#define RKISP1_CIF_ISP_EXP_MEAN_11		(RKISP1_CIF_ISP_EXP_BASE + 0x0000002c)
> -#define RKISP1_CIF_ISP_EXP_MEAN_21		(RKISP1_CIF_ISP_EXP_BASE + 0x00000030)
> -#define RKISP1_CIF_ISP_EXP_MEAN_31		(RKISP1_CIF_ISP_EXP_BASE + 0x00000034)
> -#define RKISP1_CIF_ISP_EXP_MEAN_41		(RKISP1_CIF_ISP_EXP_BASE + 0x00000038)
> -#define RKISP1_CIF_ISP_EXP_MEAN_02		(RKISP1_CIF_ISP_EXP_BASE + 0x0000003c)
> -#define RKISP1_CIF_ISP_EXP_MEAN_12		(RKISP1_CIF_ISP_EXP_BASE + 0x00000040)
> -#define RKISP1_CIF_ISP_EXP_MEAN_22		(RKISP1_CIF_ISP_EXP_BASE + 0x00000044)
> -#define RKISP1_CIF_ISP_EXP_MEAN_32		(RKISP1_CIF_ISP_EXP_BASE + 0x00000048)
> -#define RKISP1_CIF_ISP_EXP_MEAN_42		(RKISP1_CIF_ISP_EXP_BASE + 0x0000004c)
> -#define RKISP1_CIF_ISP_EXP_MEAN_03		(RKISP1_CIF_ISP_EXP_BASE + 0x00000050)
> -#define RKISP1_CIF_ISP_EXP_MEAN_13		(RKISP1_CIF_ISP_EXP_BASE + 0x00000054)
> -#define RKISP1_CIF_ISP_EXP_MEAN_23		(RKISP1_CIF_ISP_EXP_BASE + 0x00000058)
> -#define RKISP1_CIF_ISP_EXP_MEAN_33		(RKISP1_CIF_ISP_EXP_BASE + 0x0000005c)
> -#define RKISP1_CIF_ISP_EXP_MEAN_43		(RKISP1_CIF_ISP_EXP_BASE + 0x00000060)
> -#define RKISP1_CIF_ISP_EXP_MEAN_04		(RKISP1_CIF_ISP_EXP_BASE + 0x00000064)
> -#define RKISP1_CIF_ISP_EXP_MEAN_14		(RKISP1_CIF_ISP_EXP_BASE + 0x00000068)
> -#define RKISP1_CIF_ISP_EXP_MEAN_24		(RKISP1_CIF_ISP_EXP_BASE + 0x0000006c)
> -#define RKISP1_CIF_ISP_EXP_MEAN_34		(RKISP1_CIF_ISP_EXP_BASE + 0x00000070)
> -#define RKISP1_CIF_ISP_EXP_MEAN_44		(RKISP1_CIF_ISP_EXP_BASE + 0x00000074)
> +#define RKISP1_CIF_ISP_EXP_H_OFFSET_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000004)
> +#define RKISP1_CIF_ISP_EXP_V_OFFSET_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000008)
> +#define RKISP1_CIF_ISP_EXP_H_SIZE_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x0000000C)
> +#define RKISP1_CIF_ISP_EXP_V_SIZE_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000010)
> +#define RKISP1_CIF_ISP_EXP_MEAN_00_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000014)
> +#define RKISP1_CIF_ISP_EXP_MEAN_10_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000018)
> +#define RKISP1_CIF_ISP_EXP_MEAN_20_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x0000001c)
> +#define RKISP1_CIF_ISP_EXP_MEAN_30_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000020)
> +#define RKISP1_CIF_ISP_EXP_MEAN_40_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000024)
> +#define RKISP1_CIF_ISP_EXP_MEAN_01_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000028)
> +#define RKISP1_CIF_ISP_EXP_MEAN_11_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x0000002c)
> +#define RKISP1_CIF_ISP_EXP_MEAN_21_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000030)
> +#define RKISP1_CIF_ISP_EXP_MEAN_31_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000034)
> +#define RKISP1_CIF_ISP_EXP_MEAN_41_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000038)
> +#define RKISP1_CIF_ISP_EXP_MEAN_02_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x0000003c)
> +#define RKISP1_CIF_ISP_EXP_MEAN_12_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000040)
> +#define RKISP1_CIF_ISP_EXP_MEAN_22_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000044)
> +#define RKISP1_CIF_ISP_EXP_MEAN_32_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000048)
> +#define RKISP1_CIF_ISP_EXP_MEAN_42_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x0000004c)
> +#define RKISP1_CIF_ISP_EXP_MEAN_03_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000050)
> +#define RKISP1_CIF_ISP_EXP_MEAN_13_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000054)
> +#define RKISP1_CIF_ISP_EXP_MEAN_23_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000058)
> +#define RKISP1_CIF_ISP_EXP_MEAN_33_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x0000005c)
> +#define RKISP1_CIF_ISP_EXP_MEAN_43_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000060)
> +#define RKISP1_CIF_ISP_EXP_MEAN_04_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000064)
> +#define RKISP1_CIF_ISP_EXP_MEAN_14_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000068)
> +#define RKISP1_CIF_ISP_EXP_MEAN_24_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x0000006c)
> +#define RKISP1_CIF_ISP_EXP_MEAN_34_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000070)
> +#define RKISP1_CIF_ISP_EXP_MEAN_44_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000074)
> +#define RKISP1_CIF_ISP_EXP_SIZE_V12		(RKISP1_CIF_ISP_EXP_BASE + 0x00000004)
> +#define RKISP1_CIF_ISP_EXP_OFFS_V12		(RKISP1_CIF_ISP_EXP_BASE + 0x00000008)
> +#define RKISP1_CIF_ISP_EXP_MEAN_V12		(RKISP1_CIF_ISP_EXP_BASE + 0x0000000c)
>   
>   #define RKISP1_CIF_ISP_BLS_BASE			0x00002700
>   #define RKISP1_CIF_ISP_BLS_CTRL			(RKISP1_CIF_ISP_BLS_BASE + 0x00000000)
> @@ -1248,6 +1377,16 @@
>   #define RKISP1_CIF_ISP_WDR_TONECURVE_YM_31_SHD	(RKISP1_CIF_ISP_WDR_BASE + 0x0000012C)
>   #define RKISP1_CIF_ISP_WDR_TONECURVE_YM_32_SHD	(RKISP1_CIF_ISP_WDR_BASE + 0x00000130)
>   
> +#define RKISP1_CIF_ISP_HIST_BASE_V12		0x00002C00
> +#define RKISP1_CIF_ISP_HIST_CTRL_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x00000000)
> +#define RKISP1_CIF_ISP_HIST_SIZE_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x00000004)
> +#define RKISP1_CIF_ISP_HIST_OFFS_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x00000008)
> +#define RKISP1_CIF_ISP_HIST_DBG1_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x0000000C)
> +#define RKISP1_CIF_ISP_HIST_DBG2_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x0000001C)
> +#define RKISP1_CIF_ISP_HIST_DBG3_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x0000002C)
> +#define RKISP1_CIF_ISP_HIST_WEIGHT_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x0000003C)
> +#define RKISP1_CIF_ISP_HIST_BIN_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x00000120)
> +
>   #define RKISP1_CIF_ISP_VSM_BASE			0x00002F00
>   #define RKISP1_CIF_ISP_VSM_MODE			(RKISP1_CIF_ISP_VSM_BASE + 0x00000000)
>   #define RKISP1_CIF_ISP_VSM_H_OFFS		(RKISP1_CIF_ISP_VSM_BASE + 0x00000004)
> @@ -1259,4 +1398,7 @@
>   #define RKISP1_CIF_ISP_VSM_DELTA_H		(RKISP1_CIF_ISP_VSM_BASE + 0x0000001C)
>   #define RKISP1_CIF_ISP_VSM_DELTA_V		(RKISP1_CIF_ISP_VSM_BASE + 0x00000020)
>   
> +#define RKISP1_CIF_ISP_CSI0_BASE		0x00007000
> +#define RKISP1_CIF_ISP_CSI0_CTRL0		(RKISP1_CIF_ISP_CSI0_BASE + 0x00000000)
> +
>   #endif /* _RKISP1_REGS_H */
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c
> index 7136292039f6..5ce1a2974b55 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c
> @@ -175,18 +175,18 @@ rkisp1_stats_init_vb2_queue(struct vb2_queue *q, struct rkisp1_stats *stats)
>   	return vb2_queue_init(q);
>   }
>   
> -static void rkisp1_stats_get_awb_meas(struct rkisp1_stats *stats,
> -				      struct rkisp1_stat_buffer *pbuf)
> +static void rkisp1_stats_get_awb_meas_v10(struct rkisp1_stats *stats,
> +					  struct rkisp1_stat_buffer *pbuf)
>   {
>   	/* Protect against concurrent access from ISR? */
>   	struct rkisp1_device *rkisp1 = stats->rkisp1;
>   	u32 reg_val;
>   
>   	pbuf->meas_type |= RKISP1_CIF_ISP_STAT_AWB;
> -	reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_WHITE_CNT);
> +	reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_WHITE_CNT_V10);
>   	pbuf->params.awb.awb_mean[0].cnt =
>   				RKISP1_CIF_ISP_AWB_GET_PIXEL_CNT(reg_val);
> -	reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_MEAN);
> +	reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_MEAN_V10);
>   
>   	pbuf->params.awb.awb_mean[0].mean_cr_or_r =
>   				RKISP1_CIF_ISP_AWB_GET_MEAN_CR_R(reg_val);
> @@ -196,8 +196,29 @@ static void rkisp1_stats_get_awb_meas(struct rkisp1_stats *stats,
>   				RKISP1_CIF_ISP_AWB_GET_MEAN_Y_G(reg_val);
>   }
>   
> -static void rkisp1_stats_get_aec_meas(struct rkisp1_stats *stats,
> -				      struct rkisp1_stat_buffer *pbuf)
> +static void rkisp1_stats_get_awb_meas_v12(struct rkisp1_stats *stats,
> +					  struct rkisp1_stat_buffer *pbuf)
> +{
> +	/* Protect against concurrent access from ISR? */
> +	struct rkisp1_device *rkisp1 = stats->rkisp1;
> +	u32 reg_val;
> +
> +	pbuf->meas_type |= RKISP1_CIF_ISP_STAT_AWB;
> +	reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_WHITE_CNT_V12);
> +	pbuf->params.awb.awb_mean[0].cnt =
> +				RKISP1_CIF_ISP_AWB_GET_PIXEL_CNT(reg_val);
> +	reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_MEAN_V12);
> +
> +	pbuf->params.awb.awb_mean[0].mean_cr_or_r =
> +				RKISP1_CIF_ISP_AWB_GET_MEAN_CR_R(reg_val);
> +	pbuf->params.awb.awb_mean[0].mean_cb_or_b =
> +				RKISP1_CIF_ISP_AWB_GET_MEAN_CB_B(reg_val);
> +	pbuf->params.awb.awb_mean[0].mean_y_or_g =
> +				RKISP1_CIF_ISP_AWB_GET_MEAN_Y_G(reg_val);
> +}
> +
> +static void rkisp1_stats_get_aec_meas_v10(struct rkisp1_stats *stats,
> +					  struct rkisp1_stat_buffer *pbuf)
>   {
>   	struct rkisp1_device *rkisp1 = stats->rkisp1;
>   	unsigned int i;
> @@ -206,7 +227,31 @@ static void rkisp1_stats_get_aec_meas(struct rkisp1_stats *stats,
>   	for (i = 0; i < stats->config->ae_mean_max; i++)
>   		pbuf->params.ae.exp_mean[i] =
>   			(u8)rkisp1_read(rkisp1,
> -					RKISP1_CIF_ISP_EXP_MEAN_00 + i * 4);
> +					RKISP1_CIF_ISP_EXP_MEAN_00_V10 + i * 4);
> +}
> +
> +static void rkisp1_stats_get_aec_meas_v12(struct rkisp1_stats *stats,
> +					  struct rkisp1_stat_buffer *pbuf)
> +{
> +	struct rkisp1_device *rkisp1 = stats->rkisp1;
> +	u32 value;
> +	int i;
> +
> +	pbuf->meas_type |= RKISP1_CIF_ISP_STAT_AUTOEXP;
> +	for (i = 0; i < stats->config->ae_mean_max / 4; i++) {
> +		value = rkisp1_read(rkisp1, RKISP1_CIF_ISP_EXP_MEAN_V12 + i * 4);
> +		pbuf->params.ae.exp_mean[4 * i + 0] =
> +				RKISP1_CIF_ISP_EXP_GET_MEAN_xy0_V12(value);
> +		pbuf->params.ae.exp_mean[4 * i + 1] =
> +				RKISP1_CIF_ISP_EXP_GET_MEAN_xy1_V12(value);
> +		pbuf->params.ae.exp_mean[4 * i + 2] =
> +				RKISP1_CIF_ISP_EXP_GET_MEAN_xy2_V12(value);
> +		pbuf->params.ae.exp_mean[4 * i + 3] =
> +				RKISP1_CIF_ISP_EXP_GET_MEAN_xy3_V12(value);
> +	}
> +
> +	value = rkisp1_read(rkisp1, RKISP1_CIF_ISP_EXP_MEAN_V12 + i * 4);
> +	pbuf->params.ae.exp_mean[4 * i + 0] = RKISP1_CIF_ISP_EXP_GET_MEAN_xy0_V12(value);
>   }
>   
>   static void rkisp1_stats_get_afc_meas(struct rkisp1_stats *stats,
> @@ -226,8 +271,8 @@ static void rkisp1_stats_get_afc_meas(struct rkisp1_stats *stats,
>   	af->window[2].lum = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AFM_LUM_C);
>   }
>   
> -static void rkisp1_stats_get_hst_meas(struct rkisp1_stats *stats,
> -				      struct rkisp1_stat_buffer *pbuf)
> +static void rkisp1_stats_get_hst_meas_v10(struct rkisp1_stats *stats,
> +					  struct rkisp1_stat_buffer *pbuf)
>   {
>   	struct rkisp1_device *rkisp1 = stats->rkisp1;
>   	unsigned int i;
> @@ -236,7 +281,24 @@ static void rkisp1_stats_get_hst_meas(struct rkisp1_stats *stats,
>   	for (i = 0; i < stats->config->hist_bin_n_max; i++)
>   		pbuf->params.hist.hist_bins[i] =
>   			(u8)rkisp1_read(rkisp1,
> -					RKISP1_CIF_ISP_HIST_BIN_0 + i * 4);
> +					RKISP1_CIF_ISP_HIST_BIN_0_V10 + i * 4);
> +}
> +
> +static void rkisp1_stats_get_hst_meas_v12(struct rkisp1_stats *stats,
> +					  struct rkisp1_stat_buffer *pbuf)
> +{
> +	struct rkisp1_device *rkisp1 = stats->rkisp1;
> +	u32 value;
> +	int i;
> +
> +	pbuf->meas_type |= RKISP1_CIF_ISP_STAT_HIST;
> +	for (i = 0; i < stats->config->hist_bin_n_max / 2; i++) {
> +		value = rkisp1_read(rkisp1, RKISP1_CIF_ISP_HIST_BIN_V12 + i * 4);
> +		pbuf->params.hist.hist_bins[2 * i] =
> +					RKISP1_CIF_ISP_HIST_GET_BIN0_V12(value);
> +		pbuf->params.hist.hist_bins[2 * i + 1] =
> +					RKISP1_CIF_ISP_HIST_GET_BIN1_V12(value);
> +	}
>   }
>   
>   static void rkisp1_stats_get_bls_meas(struct rkisp1_stats *stats,
> @@ -286,17 +348,28 @@ static void rkisp1_stats_get_bls_meas(struct rkisp1_stats *stats,
>   	}
>   }
>   
> -static struct rkisp1_stats_ops rkisp1_stats_ops = {
> -	.get_awb_meas = rkisp1_stats_get_awb_meas,
> -	.get_aec_meas = rkisp1_stats_get_aec_meas,
> -	.get_hst_meas = rkisp1_stats_get_hst_meas,
> +static struct rkisp1_stats_ops rkisp1_v10_stats_ops = {
> +	.get_awb_meas = rkisp1_stats_get_awb_meas_v10,
> +	.get_aec_meas = rkisp1_stats_get_aec_meas_v10,
> +	.get_hst_meas = rkisp1_stats_get_hst_meas_v10,
>   };
>   
> -static struct rkisp1_stats_config rkisp1_stats_config = {
> +static struct rkisp1_stats_config rkisp1_v10_stats_config = {
>   	.ae_mean_max = 25,
>   	.hist_bin_n_max = 16,
>   };
>   

Same as I commented regarding the config field in 'params',
it seems that also in 'stats' the field is not needed.

Thanks,
Dafna

> +static struct rkisp1_stats_ops rkisp1_v12_stats_ops = {
> +	.get_awb_meas = rkisp1_stats_get_awb_meas_v12,
> +	.get_aec_meas = rkisp1_stats_get_aec_meas_v12,
> +	.get_hst_meas = rkisp1_stats_get_hst_meas_v12,
> +};
> +
> +static struct rkisp1_stats_config rkisp1_v12_stats_config = {
> +	.ae_mean_max = 81,
> +	.hist_bin_n_max = 32,
> +};
> +
>   static void
>   rkisp1_stats_send_measurement(struct rkisp1_stats *stats, u32 isp_ris)
>   {
> @@ -365,8 +438,13 @@ static void rkisp1_init_stats(struct rkisp1_stats *stats)
>   	stats->vdev_fmt.fmt.meta.buffersize =
>   		sizeof(struct rkisp1_stat_buffer);
>   
> -	stats->ops = &rkisp1_stats_ops;
> -	stats->config = &rkisp1_stats_config;
> +	if (stats->rkisp1->isp_ver == RKISP1_V12) {
> +		stats->ops = &rkisp1_v12_stats_ops;
> +		stats->config = &rkisp1_v12_stats_config;
> +	} else {
> +		stats->ops = &rkisp1_v10_stats_ops;
> +		stats->config = &rkisp1_v10_stats_config;
> +	}
>   }
>   
>   int rkisp1_stats_register(struct rkisp1_device *rkisp1)
> 

Re: [PATCH RFC 10/11] media: rockchip: rkisp1: add support for v12 isp variants

[Dafna Hirschfeld]

Am 18.01.21 um 19:06 schrieb Helen Koike:
> Hi Heiko,
> 
> On 1/8/21 4:33 PM, Heiko Stuebner wrote:
>> From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
>>
>> The rkisp1 evolved over soc generations and the rk3326/px30 introduced
>> the so called v12 - probably meaning v1.2.
>>
>> Add the changed register definitions.
>>
>> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
>> ---
>>   .../platform/rockchip/rkisp1/rkisp1-common.h  |   1 +
>>   .../platform/rockchip/rkisp1/rkisp1-isp.c     |  13 +
>>   .../platform/rockchip/rkisp1/rkisp1-params.c  | 535 +++++++++++++++---
>>   .../platform/rockchip/rkisp1/rkisp1-regs.h    | 404 ++++++++-----
>>   .../platform/rockchip/rkisp1/rkisp1-stats.c   | 112 +++-
>>   5 files changed, 824 insertions(+), 241 deletions(-)
>>
>> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
>> index be0ae02165c9..9deb1ef1aa8b 100644
>> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
>> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
>> @@ -61,6 +61,7 @@
>>   
>>   enum rkisp1_isp_ver {
>>   	RKISP1_V10 = 0,
>> +	RKISP1_V12,
>>   };
>>   
>>   /* enum for the resizer pads */
>> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
>> index 84440aa71210..306cc96f8230 100644
>> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
>> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
>> @@ -408,6 +408,10 @@ static int rkisp1_config_mipi(struct rkisp1_device *rkisp1)
>>   
>>   	rkisp1_write(rkisp1, mipi_ctrl, RKISP1_CIF_MIPI_CTRL);
>>   
>> +	/* V12 could also use a newer csi2-host, but we don't want that yet */
>> +	if (rkisp1->isp_ver == RKISP1_V12)
>> +		rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_CSI0_CTRL0);
>> +
>>   	/* Configure Data Type and Virtual Channel */
>>   	rkisp1_write(rkisp1,
>>   		     RKISP1_CIF_MIPI_DATA_SEL_DT(sink_fmt->mipi_dt) |
>> @@ -527,6 +531,15 @@ static void rkisp1_config_clk(struct rkisp1_device *rkisp1)
>>   		  RKISP1_CIF_ICCL_DCROP_CLK;
>>   
>>   	rkisp1_write(rkisp1, val, RKISP1_CIF_ICCL);
>> +
>> +	/* ensure sp and mp can run at the same time in V12 */
>> +	if (rkisp1->isp_ver == RKISP1_V12) {
>> +		val = RKISP1_CIF_CLK_CTRL_MI_Y12 | RKISP1_CIF_CLK_CTRL_MI_SP |
>> +		      RKISP1_CIF_CLK_CTRL_MI_RAW0 | RKISP1_CIF_CLK_CTRL_MI_RAW1 |
>> +		      RKISP1_CIF_CLK_CTRL_MI_READ | RKISP1_CIF_CLK_CTRL_MI_RAWRD |
>> +		      RKISP1_CIF_CLK_CTRL_CP | RKISP1_CIF_CLK_CTRL_IE;
>> +		rkisp1_write(rkisp1, val, RKISP1_CIF_VI_ISP_CLK_CTRL_V12);
>> +	}
>>   }
>>   
>>   static void rkisp1_isp_start(struct rkisp1_device *rkisp1)
>> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
>> index 008584caaad0..408fa33bdc30 100644
>> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
>> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
>> @@ -185,8 +185,8 @@ static void rkisp1_bls_config(struct rkisp1_params *params,
>>   
>>   /* ISP LS correction interface function */
>>   static void
>> -rkisp1_lsc_matrix_config(struct rkisp1_params *params,
>> -			 const struct rkisp1_cif_isp_lsc_config *pconfig)
>> +rkisp1_lsc_matrix_config_v10(struct rkisp1_params *params,
>> +			     const struct rkisp1_cif_isp_lsc_config *pconfig)
>>   {
>>   	unsigned int isp_lsc_status, sram_addr, isp_lsc_table_sel, i, j, data;
>>   
>> @@ -212,39 +212,111 @@ rkisp1_lsc_matrix_config(struct rkisp1_params *params,
>>   		 * DWORDs (2nd value of last DWORD unused)
>>   		 */
>>   		for (j = 0; j < RKISP1_CIF_ISP_LSC_SAMPLES_MAX - 1; j += 2) {
>> -			data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->r_data_tbl[i][j],
>> -							     pconfig->r_data_tbl[i][j + 1]);
>> +			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->r_data_tbl[i][j],
>> +								 pconfig->r_data_tbl[i][j + 1]);
>>   			rkisp1_write(params->rkisp1, data,
>>   				     RKISP1_CIF_ISP_LSC_R_TABLE_DATA);
>>   
>> -			data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->gr_data_tbl[i][j],
>> -							     pconfig->gr_data_tbl[i][j + 1]);
>> +			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->gr_data_tbl[i][j],
>> +								 pconfig->gr_data_tbl[i][j + 1]);
>>   			rkisp1_write(params->rkisp1, data,
>>   				     RKISP1_CIF_ISP_LSC_GR_TABLE_DATA);
>>   
>> -			data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->gb_data_tbl[i][j],
>> -							     pconfig->gb_data_tbl[i][j + 1]);
>> +			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->gb_data_tbl[i][j],
>> +								 pconfig->gb_data_tbl[i][j + 1]);
>>   			rkisp1_write(params->rkisp1, data,
>>   				     RKISP1_CIF_ISP_LSC_GB_TABLE_DATA);
>>   
>> -			data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->b_data_tbl[i][j],
>> -							     pconfig->b_data_tbl[i][j + 1]);
>> +			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->b_data_tbl[i][j],
>> +								 pconfig->b_data_tbl[i][j + 1]);
>>   			rkisp1_write(params->rkisp1, data,
>>   				     RKISP1_CIF_ISP_LSC_B_TABLE_DATA);
>>   		}
>> -		data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->r_data_tbl[i][j], 0);
>> +		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->r_data_tbl[i][j], 0);
>>   		rkisp1_write(params->rkisp1, data,
>>   			     RKISP1_CIF_ISP_LSC_R_TABLE_DATA);
>>   
>> -		data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->gr_data_tbl[i][j], 0);
>> +		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->gr_data_tbl[i][j], 0);
>>   		rkisp1_write(params->rkisp1, data,
>>   			     RKISP1_CIF_ISP_LSC_GR_TABLE_DATA);
>>   
>> -		data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->gb_data_tbl[i][j], 0);
>> +		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->gb_data_tbl[i][j], 0);
>>   		rkisp1_write(params->rkisp1, data,
>>   			     RKISP1_CIF_ISP_LSC_GB_TABLE_DATA);
>>   
>> -		data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->b_data_tbl[i][j], 0);
>> +		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->b_data_tbl[i][j], 0);
>> +		rkisp1_write(params->rkisp1, data,
>> +			     RKISP1_CIF_ISP_LSC_B_TABLE_DATA);
> 
> I understand this patch shouldn't change v10 behaviour, shouldn't this write be in a
> separate patch?
> 

Helen, this code is not a new code in V10 but part of the function rkisp1_lsc_matrix_config_v12
just that the diff is a bit confusing. The two function rkisp1_lsc_matrix_config_*
are identical except of those macro operations.

Heiko, maybe you can separate the patch to two patches, one patch only do the renaming
of adding _v10 to all the needed functions and macros, and then a diffrent patch
that adds the _v12 versions? That will be easyer to review,

Thanks,
Dafna

>> +	}
>> +	isp_lsc_table_sel = (isp_lsc_status & RKISP1_CIF_ISP_LSC_ACTIVE_TABLE) ?
>> +			    RKISP1_CIF_ISP_LSC_TABLE_0 :
>> +			    RKISP1_CIF_ISP_LSC_TABLE_1;
>> +	rkisp1_write(params->rkisp1, isp_lsc_table_sel,
>> +		     RKISP1_CIF_ISP_LSC_TABLE_SEL);
> 
> Same here.
> 
>> +}
>> +
>> +static void
>> +rkisp1_lsc_matrix_config_v12(struct rkisp1_params *params,
>> +			     const struct rkisp1_cif_isp_lsc_config *pconfig)
>> +{
>> +	unsigned int isp_lsc_status, sram_addr, isp_lsc_table_sel, i, j, data;
>> +
>> +	isp_lsc_status = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_LSC_STATUS);
>> +
>> +	/* RKISP1_CIF_ISP_LSC_TABLE_ADDRESS_153 = ( 17 * 18 ) >> 1 */
>> +	sram_addr = (isp_lsc_status & RKISP1_CIF_ISP_LSC_ACTIVE_TABLE) ?
>> +		     RKISP1_CIF_ISP_LSC_TABLE_ADDRESS_0 :
>> +		     RKISP1_CIF_ISP_LSC_TABLE_ADDRESS_153;
>> +	rkisp1_write(params->rkisp1, sram_addr, RKISP1_CIF_ISP_LSC_R_TABLE_ADDR);
>> +	rkisp1_write(params->rkisp1, sram_addr, RKISP1_CIF_ISP_LSC_GR_TABLE_ADDR);
>> +	rkisp1_write(params->rkisp1, sram_addr, RKISP1_CIF_ISP_LSC_GB_TABLE_ADDR);
>> +	rkisp1_write(params->rkisp1, sram_addr, RKISP1_CIF_ISP_LSC_B_TABLE_ADDR);
>> +
>> +	/* program data tables (table size is 9 * 17 = 153) */
>> +	for (i = 0; i < RKISP1_CIF_ISP_LSC_SAMPLES_MAX; i++) {
>> +		/*
>> +		 * 17 sectors with 2 values in one DWORD = 9
>> +		 * DWORDs (2nd value of last DWORD unused)
>> +		 */
>> +		for (j = 0; j < RKISP1_CIF_ISP_LSC_SAMPLES_MAX - 1; j += 2) {
>> +			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(
>> +					pconfig->r_data_tbl[i][j],
>> +					pconfig->r_data_tbl[i][j + 1]);
>> +			rkisp1_write(params->rkisp1, data,
>> +				     RKISP1_CIF_ISP_LSC_R_TABLE_DATA);
>> +
>> +			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(
>> +					pconfig->gr_data_tbl[i][j],
>> +					pconfig->gr_data_tbl[i][j + 1]);
>> +			rkisp1_write(params->rkisp1, data,
>> +				     RKISP1_CIF_ISP_LSC_GR_TABLE_DATA);
>> +
>> +			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(
>> +					pconfig->gb_data_tbl[i][j],
>> +					pconfig->gb_data_tbl[i][j + 1]);
>> +			rkisp1_write(params->rkisp1, data,
>> +				     RKISP1_CIF_ISP_LSC_GB_TABLE_DATA);
>> +
>> +			data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(
>> +					pconfig->b_data_tbl[i][j],
>> +					pconfig->b_data_tbl[i][j + 1]);
>> +			rkisp1_write(params->rkisp1, data,
>> +				     RKISP1_CIF_ISP_LSC_B_TABLE_DATA);
>> +		}
>> +
>> +		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(pconfig->r_data_tbl[i][j], 0);
>> +		rkisp1_write(params->rkisp1, data,
>> +			     RKISP1_CIF_ISP_LSC_R_TABLE_DATA);
>> +
>> +		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(pconfig->gr_data_tbl[i][j], 0);
>> +		rkisp1_write(params->rkisp1, data,
>> +			     RKISP1_CIF_ISP_LSC_GR_TABLE_DATA);
>> +
>> +		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(pconfig->gb_data_tbl[i][j], 0);
>> +		rkisp1_write(params->rkisp1, data,
>> +			     RKISP1_CIF_ISP_LSC_GB_TABLE_DATA);
>> +
>> +		data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(pconfig->b_data_tbl[i][j], 0);
>>   		rkisp1_write(params->rkisp1, data,
>>   			     RKISP1_CIF_ISP_LSC_B_TABLE_DATA);
>>   	}
>> @@ -382,18 +454,37 @@ static void rkisp1_sdg_config(struct rkisp1_params *params,
>>   }
>>   
>>   /* ISP GAMMA correction interface function */
>> -static void rkisp1_goc_config(struct rkisp1_params *params,
>> -			      const struct rkisp1_cif_isp_goc_config *arg)
>> +static void rkisp1_goc_config_v10(struct rkisp1_params *params,
>> +				  const struct rkisp1_cif_isp_goc_config *arg)
>>   {
>>   	unsigned int i;
>>   
>>   	rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_CTRL,
>>   				RKISP1_CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA);
>> -	rkisp1_write(params->rkisp1, arg->mode, RKISP1_CIF_ISP_GAMMA_OUT_MODE);
>> +	rkisp1_write(params->rkisp1, arg->mode, RKISP1_CIF_ISP_GAMMA_OUT_MODE_V10);
>>   
>>   	for (i = 0; i < params->config->gamma_out_max_samples; i++)
>>   		rkisp1_write(params->rkisp1, arg->gamma_y[i],
>> -			     RKISP1_CIF_ISP_GAMMA_OUT_Y_0 + i * 4);
>> +			     RKISP1_CIF_ISP_GAMMA_OUT_Y_0_V10 + i * 4);
>> +}
>> +
>> +static void rkisp1_goc_config_v12(struct rkisp1_params *params,
>> +				  const struct rkisp1_cif_isp_goc_config *arg)
>> +{
>> +	int i;
> 
> unsigned int
> 
>> +	u32 value;
>> +
>> +	rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_CTRL,
>> +				RKISP1_CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA);
>> +	rkisp1_write(params->rkisp1, arg->mode, RKISP1_CIF_ISP_GAMMA_OUT_MODE_V12);
>> +
>> +	for (i = 0; i < params->config->gamma_out_max_samples / 2; i++) {
>> +		value = RKISP1_CIF_ISP_GAMMA_VALUE_V12(
>> +			arg->gamma_y[2 * i + 1],
>> +			arg->gamma_y[2 * i]);
>> +		rkisp1_write(params->rkisp1, value,
>> +			     RKISP1_CIF_ISP_GAMMA_OUT_Y_0_V12 + i * 4);
>> +	}
>>   }
>>   
>>   /* ISP Cross Talk */
>> @@ -433,8 +524,8 @@ static void rkisp1_ctk_enable(struct rkisp1_params *params, bool en)
>>   }
>>   
>>   /* ISP White Balance Mode */
>> -static void rkisp1_awb_meas_config(struct rkisp1_params *params,
>> -				   const struct rkisp1_cif_isp_awb_meas_config *arg)
>> +static void rkisp1_awb_meas_config_v10(struct rkisp1_params *params,
>> +				       const struct rkisp1_cif_isp_awb_meas_config *arg)
>>   {
>>   	u32 reg_val = 0;
>>   	/* based on the mode,configure the awb module */
>> @@ -442,43 +533,82 @@ static void rkisp1_awb_meas_config(struct rkisp1_params *params,
>>   		/* Reference Cb and Cr */
>>   		rkisp1_write(params->rkisp1,
>>   			     RKISP1_CIF_ISP_AWB_REF_CR_SET(arg->awb_ref_cr) |
>> -			     arg->awb_ref_cb, RKISP1_CIF_ISP_AWB_REF);
>> +			     arg->awb_ref_cb, RKISP1_CIF_ISP_AWB_REF_V10);
>>   		/* Yc Threshold */
>>   		rkisp1_write(params->rkisp1,
>>   			     RKISP1_CIF_ISP_AWB_MAX_Y_SET(arg->max_y) |
>>   			     RKISP1_CIF_ISP_AWB_MIN_Y_SET(arg->min_y) |
>>   			     RKISP1_CIF_ISP_AWB_MAX_CS_SET(arg->max_csum) |
>> -			     arg->min_c, RKISP1_CIF_ISP_AWB_THRESH);
>> +			     arg->min_c, RKISP1_CIF_ISP_AWB_THRESH_V10);
>>   	}
>>   
>> -	reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP);
>> +	reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP_V10);
>>   	if (arg->enable_ymax_cmp)
>>   		reg_val |= RKISP1_CIF_ISP_AWB_YMAX_CMP_EN;
>>   	else
>>   		reg_val &= ~RKISP1_CIF_ISP_AWB_YMAX_CMP_EN;
>> -	rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP);
>> +	rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP_V10);
>>   
>>   	/* window offset */
>>   	rkisp1_write(params->rkisp1,
>> -		     arg->awb_wnd.v_offs, RKISP1_CIF_ISP_AWB_WND_V_OFFS);
>> +		     arg->awb_wnd.v_offs, RKISP1_CIF_ISP_AWB_WND_V_OFFS_V10);
>>   	rkisp1_write(params->rkisp1,
>> -		     arg->awb_wnd.h_offs, RKISP1_CIF_ISP_AWB_WND_H_OFFS);
>> +		     arg->awb_wnd.h_offs, RKISP1_CIF_ISP_AWB_WND_H_OFFS_V10);
>>   	/* AWB window size */
>>   	rkisp1_write(params->rkisp1,
>> -		     arg->awb_wnd.v_size, RKISP1_CIF_ISP_AWB_WND_V_SIZE);
>> +		     arg->awb_wnd.v_size, RKISP1_CIF_ISP_AWB_WND_V_SIZE_V10);
>>   	rkisp1_write(params->rkisp1,
>> -		     arg->awb_wnd.h_size, RKISP1_CIF_ISP_AWB_WND_H_SIZE);
>> +		     arg->awb_wnd.h_size, RKISP1_CIF_ISP_AWB_WND_H_SIZE_V10);
>>   	/* Number of frames */
>>   	rkisp1_write(params->rkisp1,
>> -		     arg->frames, RKISP1_CIF_ISP_AWB_FRAMES);
>> +		     arg->frames, RKISP1_CIF_ISP_AWB_FRAMES_V10);
>> +}
>> +
>> +static void rkisp1_awb_meas_config_v12(struct rkisp1_params *params,
>> +				       const struct rkisp1_cif_isp_awb_meas_config *arg)
>> +{
>> +	u32 reg_val = 0;> +	/* based on the mode,configure the awb module */
>> +	if (arg->awb_mode == RKISP1_CIF_ISP_AWB_MODE_YCBCR) {
>> +		/* Reference Cb and Cr */
>> +		rkisp1_write(params->rkisp1,
>> +			     RKISP1_CIF_ISP_AWB_REF_CR_SET(arg->awb_ref_cr) |
>> +			     arg->awb_ref_cb, RKISP1_CIF_ISP_AWB_REF_V12);
>> +		/* Yc Threshold */
>> +		rkisp1_write(params->rkisp1,
>> +			     RKISP1_CIF_ISP_AWB_MAX_Y_SET(arg->max_y) |
>> +			     RKISP1_CIF_ISP_AWB_MIN_Y_SET(arg->min_y) |
>> +			     RKISP1_CIF_ISP_AWB_MAX_CS_SET(arg->max_csum) |
>> +			     arg->min_c, RKISP1_CIF_ISP_AWB_THRESH_V12);
>> +	}
>> +
>> +	reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP_V12);
>> +	if (arg->enable_ymax_cmp)
>> +		reg_val |= RKISP1_CIF_ISP_AWB_YMAX_CMP_EN;
>> +	else
>> +		reg_val &= ~RKISP1_CIF_ISP_AWB_YMAX_CMP_EN;
>> +	reg_val &= ~RKISP1_CIF_ISP_AWB_SET_FRAMES_MASK_V12;
>> +	reg_val |= RKISP1_CIF_ISP_AWB_SET_FRAMES_V12(arg->frames);
>> +	rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP_V12);
>> +
>> +	/* window offset */
>> +	rkisp1_write(params->rkisp1,
>> +		     arg->awb_wnd.v_offs << 16 |
>> +		     arg->awb_wnd.h_offs,
>> +		     RKISP1_CIF_ISP_AWB_OFFS_V12);
>> +	/* AWB window size */
>> +	rkisp1_write(params->rkisp1,
>> +		     arg->awb_wnd.v_size << 16 |
>> +		     arg->awb_wnd.h_size,
>> +		     RKISP1_CIF_ISP_AWB_SIZE_V12);
>>   }
>>   
>>   static void
>> -rkisp1_awb_meas_enable(struct rkisp1_params *params,
>> -		       const struct rkisp1_cif_isp_awb_meas_config *arg,
>> -		       bool en)
>> +rkisp1_awb_meas_enable_v10(struct rkisp1_params *params,
>> +			   const struct rkisp1_cif_isp_awb_meas_config *arg,
>> +			   bool en)
>>   {
>> -	u32 reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP);
>> +	u32 reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP_V10);
>>   
>>   	/* switch off */
>>   	reg_val &= RKISP1_CIF_ISP_AWB_MODE_MASK_NONE;
>> @@ -489,34 +619,76 @@ rkisp1_awb_meas_enable(struct rkisp1_params *params,
>>   		else
>>   			reg_val |= RKISP1_CIF_ISP_AWB_MODE_YCBCR_EN;
>>   
>> -		rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP);
>> +		rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP_V10);
>>   
>>   		/* Measurements require AWB block be active. */
>>   		rkisp1_param_set_bits(params, RKISP1_CIF_ISP_CTRL,
>>   				      RKISP1_CIF_ISP_CTRL_ISP_AWB_ENA);
>>   	} else {
>>   		rkisp1_write(params->rkisp1,
>> -			     reg_val, RKISP1_CIF_ISP_AWB_PROP);
>> +			     reg_val, RKISP1_CIF_ISP_AWB_PROP_V10);
>>   		rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_CTRL,
>>   					RKISP1_CIF_ISP_CTRL_ISP_AWB_ENA);
>>   	}
>>   }
>>   
>>   static void
>> -rkisp1_awb_gain_config(struct rkisp1_params *params,
>> -		       const struct rkisp1_cif_isp_awb_gain_config *arg)
>> +rkisp1_awb_meas_enable_v12(struct rkisp1_params *params,
>> +			   const struct rkisp1_cif_isp_awb_meas_config *arg,
>> +			   bool en)
>> +{
>> +	u32 reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP_V12);
>> +
>> +	/* switch off */
>> +	reg_val &= RKISP1_CIF_ISP_AWB_MODE_MASK_NONE;
>> +
>> +	if (en) {
>> +		if (arg->awb_mode == RKISP1_CIF_ISP_AWB_MODE_RGB)
>> +			reg_val |= RKISP1_CIF_ISP_AWB_MODE_RGB_EN;
>> +		else
>> +			reg_val |= RKISP1_CIF_ISP_AWB_MODE_YCBCR_EN;
>> +
>> +		rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP_V12);
>> +
>> +		/* Measurements require AWB block be active. */
>> +		rkisp1_param_set_bits(params, RKISP1_CIF_ISP_CTRL,
>> +				      RKISP1_CIF_ISP_CTRL_ISP_AWB_ENA);
>> +	} else {
>> +		rkisp1_write(params->rkisp1,
>> +			     reg_val, RKISP1_CIF_ISP_AWB_PROP_V12);
>> +		rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_CTRL,
>> +					RKISP1_CIF_ISP_CTRL_ISP_AWB_ENA);
>> +	}
>> +}
>> +
>> +static void
>> +rkisp1_awb_gain_config_v10(struct rkisp1_params *params,
>> +			   const struct rkisp1_cif_isp_awb_gain_config *arg)
>> +{
>> +	rkisp1_write(params->rkisp1,
>> +		     RKISP1_CIF_ISP_AWB_GAIN_R_SET(arg->gain_green_r) |
>> +		     arg->gain_green_b, RKISP1_CIF_ISP_AWB_GAIN_G_V10);
>> +
>> +	rkisp1_write(params->rkisp1,
>> +		     RKISP1_CIF_ISP_AWB_GAIN_R_SET(arg->gain_red) |
>> +		     arg->gain_blue, RKISP1_CIF_ISP_AWB_GAIN_RB_V10);
>> +}
>> +
>> +static void
>> +rkisp1_awb_gain_config_v12(struct rkisp1_params *params,
>> +			   const struct rkisp1_cif_isp_awb_gain_config *arg)
>>   {
>>   	rkisp1_write(params->rkisp1,
>>   		     RKISP1_CIF_ISP_AWB_GAIN_R_SET(arg->gain_green_r) |
>> -		     arg->gain_green_b, RKISP1_CIF_ISP_AWB_GAIN_G);
>> +		     arg->gain_green_b, RKISP1_CIF_ISP_AWB_GAIN_G_V12);
>>   
>>   	rkisp1_write(params->rkisp1,
>>   		     RKISP1_CIF_ISP_AWB_GAIN_R_SET(arg->gain_red) |
>> -		     arg->gain_blue, RKISP1_CIF_ISP_AWB_GAIN_RB);
>> +		     arg->gain_blue, RKISP1_CIF_ISP_AWB_GAIN_RB_V12);
>>   }
>>   
>> -static void rkisp1_aec_config(struct rkisp1_params *params,
>> -			      const struct rkisp1_cif_isp_aec_config *arg)
>> +static void rkisp1_aec_config_v10(struct rkisp1_params *params,
>> +				  const struct rkisp1_cif_isp_aec_config *arg)
>>   {
>>   	unsigned int block_hsize, block_vsize;
>>   	u32 exp_ctrl;
>> @@ -531,21 +703,55 @@ static void rkisp1_aec_config(struct rkisp1_params *params,
>>   	rkisp1_write(params->rkisp1, exp_ctrl, RKISP1_CIF_ISP_EXP_CTRL);
>>   
>>   	rkisp1_write(params->rkisp1,
>> -		     arg->meas_window.h_offs, RKISP1_CIF_ISP_EXP_H_OFFSET);
>> +		     arg->meas_window.h_offs, RKISP1_CIF_ISP_EXP_H_OFFSET_V10);
>>   	rkisp1_write(params->rkisp1,
>> -		     arg->meas_window.v_offs, RKISP1_CIF_ISP_EXP_V_OFFSET);
>> +		     arg->meas_window.v_offs, RKISP1_CIF_ISP_EXP_V_OFFSET_V10);
>>   
>>   	block_hsize = arg->meas_window.h_size /
>> -		      RKISP1_CIF_ISP_EXP_COLUMN_NUM - 1;
>> +		      RKISP1_CIF_ISP_EXP_COLUMN_NUM_V10 - 1;
>>   	block_vsize = arg->meas_window.v_size /
>> -		      RKISP1_CIF_ISP_EXP_ROW_NUM - 1;
>> +		      RKISP1_CIF_ISP_EXP_ROW_NUM_V10 - 1;
>> +
>> +	rkisp1_write(params->rkisp1,
>> +		     RKISP1_CIF_ISP_EXP_H_SIZE_SET_V10(block_hsize),
>> +		     RKISP1_CIF_ISP_EXP_H_SIZE_V10);
>> +	rkisp1_write(params->rkisp1,
>> +		     RKISP1_CIF_ISP_EXP_V_SIZE_SET_V10(block_vsize),
>> +		     RKISP1_CIF_ISP_EXP_V_SIZE_V10);
>> +}
>> +
>> +static void rkisp1_aec_config_v12(struct rkisp1_params *params,
>> +			       const struct rkisp1_cif_isp_aec_config *arg)
>> +{
>> +	u32 exp_ctrl;
>> +	u32 block_hsize, block_vsize;
>> +	u32 wnd_num_idx = 1;
>> +	const u32 ae_wnd_num[] = {
>> +		5, 9, 15, 15
>> +	};
> 
> I think it would be better to declare in the same line.
> 
>> +
>> +	/* avoid to override the old enable value */
>> +	exp_ctrl = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_EXP_CTRL);
>> +	exp_ctrl &= RKISP1_CIF_ISP_EXP_ENA;
>> +	if (arg->autostop)
>> +		exp_ctrl |= RKISP1_CIF_ISP_EXP_CTRL_AUTOSTOP;
>> +	if (arg->mode == RKISP1_CIF_ISP_EXP_MEASURING_MODE_1)
>> +		exp_ctrl |= RKISP1_CIF_ISP_EXP_CTRL_MEASMODE_1;
>> +	exp_ctrl |= RKISP1_CIF_ISP_EXP_CTRL_WNDNUM_SET_V12(wnd_num_idx);
>> +	rkisp1_write(params->rkisp1, exp_ctrl, RKISP1_CIF_ISP_EXP_CTRL);
>>   
>>   	rkisp1_write(params->rkisp1,
>> -		     RKISP1_CIF_ISP_EXP_H_SIZE_SET(block_hsize),
>> -		     RKISP1_CIF_ISP_EXP_H_SIZE);
>> +		     RKISP1_CIF_ISP_EXP_V_OFFSET_SET_V12(arg->meas_window.v_offs) |
>> +		     RKISP1_CIF_ISP_EXP_H_OFFSET_SET_V12(arg->meas_window.h_offs),
>> +		     RKISP1_CIF_ISP_EXP_OFFS_V12);
>> +
>> +	block_hsize = arg->meas_window.h_size / ae_wnd_num[wnd_num_idx] - 1;
>> +	block_vsize = arg->meas_window.v_size / ae_wnd_num[wnd_num_idx] - 1;
>> +
>>   	rkisp1_write(params->rkisp1,
>> -		     RKISP1_CIF_ISP_EXP_V_SIZE_SET(block_vsize),
>> -		     RKISP1_CIF_ISP_EXP_V_SIZE);
>> +		     RKISP1_CIF_ISP_EXP_V_SIZE_SET_V12(block_vsize) |
>> +		     RKISP1_CIF_ISP_EXP_H_SIZE_SET_V12(block_hsize),
>> +		     RKISP1_CIF_ISP_EXP_SIZE_V12);
>>   }
>>   
>>   static void rkisp1_cproc_config(struct rkisp1_params *params,
>> @@ -578,72 +784,154 @@ static void rkisp1_cproc_config(struct rkisp1_params *params,
>>   	}
>>   }
>>   
>> -static void rkisp1_hst_config(struct rkisp1_params *params,
>> -			      const struct rkisp1_cif_isp_hst_config *arg)
>> +static void rkisp1_hst_config_v10(struct rkisp1_params *params,
>> +				  const struct rkisp1_cif_isp_hst_config *arg)
>>   {
>>   	unsigned int block_hsize, block_vsize;
>>   	static const u32 hist_weight_regs[] = {
>> -		RKISP1_CIF_ISP_HIST_WEIGHT_00TO30,
>> -		RKISP1_CIF_ISP_HIST_WEIGHT_40TO21,
>> -		RKISP1_CIF_ISP_HIST_WEIGHT_31TO12,
>> -		RKISP1_CIF_ISP_HIST_WEIGHT_22TO03,
>> -		RKISP1_CIF_ISP_HIST_WEIGHT_13TO43,
>> -		RKISP1_CIF_ISP_HIST_WEIGHT_04TO34,
>> -		RKISP1_CIF_ISP_HIST_WEIGHT_44,
>> +		RKISP1_CIF_ISP_HIST_WEIGHT_00TO30_V10,
>> +		RKISP1_CIF_ISP_HIST_WEIGHT_40TO21_V10,
>> +		RKISP1_CIF_ISP_HIST_WEIGHT_31TO12_V10,
>> +		RKISP1_CIF_ISP_HIST_WEIGHT_22TO03_V10,
>> +		RKISP1_CIF_ISP_HIST_WEIGHT_13TO43_V10,
>> +		RKISP1_CIF_ISP_HIST_WEIGHT_04TO34_V10,
>> +		RKISP1_CIF_ISP_HIST_WEIGHT_44_V10,
>>   	};
>>   	const u8 *weight;
>>   	unsigned int i;
>>   	u32 hist_prop;
>>   
>>   	/* avoid to override the old enable value */
>> -	hist_prop = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_HIST_PROP);
>> -	hist_prop &= RKISP1_CIF_ISP_HIST_PROP_MODE_MASK;
>> -	hist_prop |= RKISP1_CIF_ISP_HIST_PREDIV_SET(arg->histogram_predivider);
>> -	rkisp1_write(params->rkisp1, hist_prop, RKISP1_CIF_ISP_HIST_PROP);
>> +	hist_prop = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_HIST_PROP_V10);
>> +	hist_prop &= RKISP1_CIF_ISP_HIST_PROP_MODE_MASK_V10;
>> +	hist_prop |= RKISP1_CIF_ISP_HIST_PREDIV_SET_V10(arg->histogram_predivider);
>> +	rkisp1_write(params->rkisp1, hist_prop, RKISP1_CIF_ISP_HIST_PROP_V10);
>>   	rkisp1_write(params->rkisp1,
>>   		     arg->meas_window.h_offs,
>> -		     RKISP1_CIF_ISP_HIST_H_OFFS);
>> +		     RKISP1_CIF_ISP_HIST_H_OFFS_V10);
>>   	rkisp1_write(params->rkisp1,
>>   		     arg->meas_window.v_offs,
>> -		     RKISP1_CIF_ISP_HIST_V_OFFS);
>> +		     RKISP1_CIF_ISP_HIST_V_OFFS_V10);
>>   
>>   	block_hsize = arg->meas_window.h_size /
>> -		      RKISP1_CIF_ISP_HIST_COLUMN_NUM - 1;
>> -	block_vsize = arg->meas_window.v_size / RKISP1_CIF_ISP_HIST_ROW_NUM - 1;
>> +		      RKISP1_CIF_ISP_HIST_COLUMN_NUM_V10 - 1;
>> +	block_vsize = arg->meas_window.v_size / RKISP1_CIF_ISP_HIST_ROW_NUM_V10 - 1;
>>   
>> -	rkisp1_write(params->rkisp1, block_hsize, RKISP1_CIF_ISP_HIST_H_SIZE);
>> -	rkisp1_write(params->rkisp1, block_vsize, RKISP1_CIF_ISP_HIST_V_SIZE);
>> +	rkisp1_write(params->rkisp1, block_hsize, RKISP1_CIF_ISP_HIST_H_SIZE_V10);
>> +	rkisp1_write(params->rkisp1, block_vsize, RKISP1_CIF_ISP_HIST_V_SIZE_V10);
>>   
>>   	weight = arg->hist_weight;
>>   	for (i = 0; i < ARRAY_SIZE(hist_weight_regs); ++i, weight += 4)
>>   		rkisp1_write(params->rkisp1,
>> -			     RKISP1_CIF_ISP_HIST_WEIGHT_SET(weight[0],
>> +			     RKISP1_CIF_ISP_HIST_WEIGHT_SET_V10(weight[0],
>>   							    weight[1],
>>   							    weight[2],
>>   							    weight[3]),
>>   				 hist_weight_regs[i]);
>>   }
>>   
>> +static void rkisp1_hst_config_v12(struct rkisp1_params *params,
>> +				  const struct rkisp1_cif_isp_hst_config *arg)
>> +{
>> +	u32 i, j;
> 
> unsigned int
> 
>> +	u32 value;
>> +	u32 hist_ctrl;
>> +	u32 block_hsize, block_vsize;
>> +	u32 wnd_num_idx, hist_weight_num;
> 
> Maybe organize those in the same line.
> 
>> +	u8 weight15x15[RKISP1_CIF_ISP_HIST_WEIGHT_REG_SIZE_V12];
>> +	const u32 hist_wnd_num[] = {
>> +		5, 9, 15, 15
>> +	};
>> +
>> +	/* now we just support 9x9 window */
>> +	wnd_num_idx = 1;
>> +	memset(weight15x15, 0x00, sizeof(weight15x15));
>> +	/* avoid to override the old enable value */
>> +	hist_ctrl = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_HIST_CTRL_V12);
>> +	hist_ctrl &= RKISP1_CIF_ISP_HIST_CTRL_MODE_MASK_V12 |
>> +		     RKISP1_CIF_ISP_HIST_CTRL_EN_MASK_V12;
>> +	hist_ctrl = hist_ctrl |
>> +		    RKISP1_CIF_ISP_HIST_CTRL_INTRSEL_SET_V12(1) |
>> +		    RKISP1_CIF_ISP_HIST_CTRL_DATASEL_SET_V12(0) |
>> +		    RKISP1_CIF_ISP_HIST_CTRL_WATERLINE_SET_V12(0) |
>> +		    RKISP1_CIF_ISP_HIST_CTRL_AUTOSTOP_SET_V12(0) |
>> +		    RKISP1_CIF_ISP_HIST_CTRL_WNDNUM_SET_V12(1) |
>> +		    RKISP1_CIF_ISP_HIST_CTRL_STEPSIZE_SET_V12(arg->histogram_predivider);
>> +	rkisp1_write(params->rkisp1, hist_ctrl, RKISP1_CIF_ISP_HIST_CTRL_V12);
>> +
>> +	rkisp1_write(params->rkisp1,
>> +		     RKISP1_CIF_ISP_HIST_OFFS_SET_V12(arg->meas_window.h_offs,
>> +						      arg->meas_window.v_offs),
>> +		     RKISP1_CIF_ISP_HIST_OFFS_V12);
>> +
>> +	block_hsize = arg->meas_window.h_size / hist_wnd_num[wnd_num_idx] - 1;
>> +	block_vsize = arg->meas_window.v_size / hist_wnd_num[wnd_num_idx] - 1;
>> +	rkisp1_write(params->rkisp1,
>> +		     RKISP1_CIF_ISP_HIST_SIZE_SET_V12(block_hsize, block_vsize),
>> +		     RKISP1_CIF_ISP_HIST_SIZE_V12);
>> +
>> +	for (i = 0; i < hist_wnd_num[wnd_num_idx]; i++) {
>> +		for (j = 0; j < hist_wnd_num[wnd_num_idx]; j++) {
>> +			weight15x15[i * RKISP1_CIF_ISP_HIST_ROW_NUM_V12 + j] =
>> +				arg->hist_weight[i * hist_wnd_num[wnd_num_idx] + j];
>> +		}
>> +	}
>> +
>> +	hist_weight_num = RKISP1_CIF_ISP_HIST_WEIGHT_REG_SIZE_V12;
>> +	for (i = 0; i < (hist_weight_num / 4); i++) {
>> +		value = RKISP1_CIF_ISP_HIST_WEIGHT_SET_V12(
>> +				 weight15x15[4 * i + 0],
>> +				 weight15x15[4 * i + 1],
>> +				 weight15x15[4 * i + 2],
>> +				 weight15x15[4 * i + 3]);
>> +		rkisp1_write(params->rkisp1, value,
>> +				 RKISP1_CIF_ISP_HIST_WEIGHT_V12 + 4 * i);
>> +	}
>> +	value = RKISP1_CIF_ISP_HIST_WEIGHT_SET_V12(weight15x15[4 * i + 0], 0, 0, 0);
>> +	rkisp1_write(params->rkisp1, value,
>> +				 RKISP1_CIF_ISP_HIST_WEIGHT_V12 + 4 * i);
>> +}
>> +
>>   static void
>> -rkisp1_hst_enable(struct rkisp1_params *params,
>> -		  const struct rkisp1_cif_isp_hst_config *arg, bool en)
>> +rkisp1_hst_enable_v10(struct rkisp1_params *params,
>> +		      const struct rkisp1_cif_isp_hst_config *arg, bool en)
>>   {
>>   	if (en)	{
>>   		u32 hist_prop = rkisp1_read(params->rkisp1,
>> -					    RKISP1_CIF_ISP_HIST_PROP);
>> +					    RKISP1_CIF_ISP_HIST_PROP_V10);
>>   
>> -		hist_prop &= ~RKISP1_CIF_ISP_HIST_PROP_MODE_MASK;
>> +		hist_prop &= ~RKISP1_CIF_ISP_HIST_PROP_MODE_MASK_V10;
>>   		hist_prop |= arg->mode;
>> -		rkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_PROP,
>> +		rkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_PROP_V10,
>>   				      hist_prop);
>>   	} else {
>> -		rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_HIST_PROP,
>> -					RKISP1_CIF_ISP_HIST_PROP_MODE_MASK);
>> +		rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_HIST_PROP_V10,
>> +					RKISP1_CIF_ISP_HIST_PROP_MODE_MASK_V10);
>> +	}
>> +}
>> +
>> +static void
>> +rkisp1_hst_enable_v12(struct rkisp1_params *params,
>> +		      const struct rkisp1_cif_isp_hst_config *arg, bool en)
>> +{
>> +	if (en) {
>> +		u32 hist_ctrl = rkisp1_read(params->rkisp1,
>> +					    RKISP1_CIF_ISP_HIST_CTRL_V12);
>> +
>> +		hist_ctrl &= ~RKISP1_CIF_ISP_HIST_CTRL_MODE_MASK_V12;
>> +		hist_ctrl |= RKISP1_CIF_ISP_HIST_CTRL_MODE_SET_V12(arg->mode);
>> +		hist_ctrl |= RKISP1_CIF_ISP_HIST_CTRL_EN_SET_V12(1);
>> +		rkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_CTRL_V12,
>> +				      hist_ctrl);
>> +	} else {
>> +		rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_HIST_CTRL_V12,
>> +					RKISP1_CIF_ISP_HIST_CTRL_MODE_MASK_V12 |
>> +					RKISP1_CIF_ISP_HIST_CTRL_EN_MASK_V12);
>>   	}
>>   }
>>   
>> -static void rkisp1_afm_config(struct rkisp1_params *params,
>> -			      const struct rkisp1_cif_isp_afc_config *arg)
>> +static void rkisp1_afm_config_v10(struct rkisp1_params *params,
>> +				  const struct rkisp1_cif_isp_afc_config *arg)
>>   {
>>   	size_t num_of_win = min_t(size_t, ARRAY_SIZE(arg->afm_win),
>>   				  arg->num_afm_win);
>> @@ -673,6 +961,45 @@ static void rkisp1_afm_config(struct rkisp1_params *params,
>>   	rkisp1_write(params->rkisp1, afm_ctrl, RKISP1_CIF_ISP_AFM_CTRL);
>>   }
>>   
>> +static void rkisp1_afm_config_v12(struct rkisp1_params *params,
>> +				  const struct rkisp1_cif_isp_afc_config *arg)
>> +{
>> +	size_t num_of_win = min_t(size_t, ARRAY_SIZE(arg->afm_win),
>> +				  arg->num_afm_win);
>> +	u32 afm_ctrl = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AFM_CTRL);
>> +	u32 lum_var_shift, afm_var_shift;
>> +	unsigned int i;
>> +
>> +	/* Switch off to configure. */
>> +	rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_AFM_CTRL,
>> +				RKISP1_CIF_ISP_AFM_ENA);
>> +
>> +	for (i = 0; i < num_of_win; i++) {
>> +		rkisp1_write(params->rkisp1,
>> +			     RKISP1_CIF_ISP_AFM_WINDOW_X(arg->afm_win[i].h_offs) |
>> +			     RKISP1_CIF_ISP_AFM_WINDOW_Y(arg->afm_win[i].v_offs),
>> +			     RKISP1_CIF_ISP_AFM_LT_A + i * 8);
>> +		rkisp1_write(params->rkisp1,
>> +			     RKISP1_CIF_ISP_AFM_WINDOW_X(arg->afm_win[i].h_size +
>> +							 arg->afm_win[i].h_offs) |
>> +			     RKISP1_CIF_ISP_AFM_WINDOW_Y(arg->afm_win[i].v_size +
>> +							 arg->afm_win[i].v_offs),
>> +			     RKISP1_CIF_ISP_AFM_RB_A + i * 8);
>> +	}
>> +	rkisp1_write(params->rkisp1, arg->thres, RKISP1_CIF_ISP_AFM_THRES);
>> +
>> +	lum_var_shift = RKISP1_CIF_ISP_AFM_GET_LUM_SHIFT_a_V12(arg->var_shift);
>> +	afm_var_shift = RKISP1_CIF_ISP_AFM_GET_AFM_SHIFT_a_V12(arg->var_shift);
>> +	rkisp1_write(params->rkisp1,
>> +		     RKISP1_CIF_ISP_AFM_SET_SHIFT_a_V12(lum_var_shift, afm_var_shift) |
>> +		     RKISP1_CIF_ISP_AFM_SET_SHIFT_b_V12(lum_var_shift, afm_var_shift) |
>> +		     RKISP1_CIF_ISP_AFM_SET_SHIFT_c_V12(lum_var_shift, afm_var_shift),
>> +		     RKISP1_CIF_ISP_AFM_VAR_SHIFT);
>> +
>> +	/* restore afm status */
>> +	rkisp1_write(params->rkisp1, afm_ctrl, RKISP1_CIF_ISP_AFM_CTRL);
>> +}
>> +
>>   static void rkisp1_ie_config(struct rkisp1_params *params,
>>   			     const struct rkisp1_cif_isp_ie_config *arg)
>>   {
>> @@ -1286,8 +1613,8 @@ static void rkisp1_params_config_parameter(struct rkisp1_params *params)
>>   
>>   	memset(hst.hist_weight, 0x01, sizeof(hst.hist_weight));
>>   	params->ops->hst_config(params, &hst);
>> -	rkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_PROP,
>> -			      ~RKISP1_CIF_ISP_HIST_PROP_MODE_MASK |
>> +	rkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_PROP_V10,
>> +			      ~RKISP1_CIF_ISP_HIST_PROP_MODE_MASK_V10 |
>>   			      rkisp1_hst_params_default_config.mode);
>>   
>>   	/* set the  range */
>> @@ -1346,22 +1673,38 @@ void rkisp1_params_disable(struct rkisp1_params *params)
>>   				RKISP1_CIF_ISP_DPF_MODE_EN);
>>   }
>>   
>> -static struct rkisp1_params_ops rkisp1_params_ops = {
>> -	.lsc_matrix_config = rkisp1_lsc_matrix_config,
>> -	.goc_config = rkisp1_goc_config,
>> -	.awb_meas_config = rkisp1_awb_meas_config,
>> -	.awb_meas_enable = rkisp1_awb_meas_enable,
>> -	.awb_gain_config = rkisp1_awb_gain_config,
>> -	.aec_config = rkisp1_aec_config,
>> -	.hst_config = rkisp1_hst_config,
>> -	.hst_enable = rkisp1_hst_enable,
>> -	.afm_config = rkisp1_afm_config,
>> +static struct rkisp1_params_ops rkisp1_v10_params_ops = {
>> +	.lsc_matrix_config = rkisp1_lsc_matrix_config_v10,
>> +	.goc_config = rkisp1_goc_config_v10,
>> +	.awb_meas_config = rkisp1_awb_meas_config_v10,
>> +	.awb_meas_enable = rkisp1_awb_meas_enable_v10,
>> +	.awb_gain_config = rkisp1_awb_gain_config_v10,
>> +	.aec_config = rkisp1_aec_config_v10,
>> +	.hst_config = rkisp1_hst_config_v10,
>> +	.hst_enable = rkisp1_hst_enable_v10,
>> +	.afm_config = rkisp1_afm_config_v10,
>>   };
>>   
>> -static struct rkisp1_params_config rkisp1_params_config = {
>> +static struct rkisp1_params_config rkisp1_v10_params_config = {
>>   	.gamma_out_max_samples = 17,
>>   };
>>   
>> +static struct rkisp1_params_ops rkisp1_v12_params_ops = {
>> +	.lsc_matrix_config = rkisp1_lsc_matrix_config_v12,
>> +	.goc_config = rkisp1_goc_config_v12,
>> +	.awb_meas_config = rkisp1_awb_meas_config_v12,
>> +	.awb_meas_enable = rkisp1_awb_meas_enable_v12,
>> +	.awb_gain_config = rkisp1_awb_gain_config_v12,
>> +	.aec_config = rkisp1_aec_config_v12,
>> +	.hst_config = rkisp1_hst_config_v12,
>> +	.hst_enable = rkisp1_hst_enable_v12,
>> +	.afm_config = rkisp1_afm_config_v12,
>> +};
>> +
>> +static struct rkisp1_params_config rkisp1_v12_params_config = {
>> +	.gamma_out_max_samples = 34,
>> +};
>> +
>>   static int rkisp1_params_enum_fmt_meta_out(struct file *file, void *priv,
>>   					   struct v4l2_fmtdesc *f)
>>   {
>> @@ -1528,8 +1871,14 @@ static void rkisp1_init_params(struct rkisp1_params *params)
>>   		V4L2_META_FMT_RK_ISP1_PARAMS;
>>   	params->vdev_fmt.fmt.meta.buffersize =
>>   		sizeof(struct rkisp1_params_cfg);
>> -	params->ops = &rkisp1_params_ops;
>> -	params->config = &rkisp1_params_config;
>> +
>> +	if (params->rkisp1->isp_ver == RKISP1_V12) {
>> +		params->ops = &rkisp1_v12_params_ops;
>> +		params->config = &rkisp1_v12_params_config;
>> +	} else {
>> +		params->ops = &rkisp1_v10_params_ops;
>> +		params->config = &rkisp1_v10_params_config;
>> +	}
>>   }
>>   
>>   int rkisp1_params_register(struct rkisp1_device *rkisp1)
>> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
>> index 8a8d960a679c..388adee3beff 100644
>> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
>> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
>> @@ -212,6 +212,35 @@
>>   
>>   /* CCL */
>>   #define RKISP1_CIF_CCL_CIF_CLK_DIS			BIT(2)
>> +/* VI_ISP_CLK_CTRL */
>> +#define RKISP1_CIF_CLK_CTRL_ISP_RAW			BIT(0)
>> +#define RKISP1_CIF_CLK_CTRL_ISP_RGB			BIT(1)
>> +#define RKISP1_CIF_CLK_CTRL_ISP_YUV			BIT(2)
>> +#define RKISP1_CIF_CLK_CTRL_ISP_3A			BIT(3)
>> +#define RKISP1_CIF_CLK_CTRL_MIPI_RAW			BIT(4)
>> +#define RKISP1_CIF_CLK_CTRL_ISP_IE			BIT(5)
>> +#define RKISP1_CIF_CLK_CTRL_RSZ_RAM			BIT(6)
>> +#define RKISP1_CIF_CLK_CTRL_JPEG_RAM			BIT(7)
>> +#define RKISP1_CIF_CLK_CTRL_ACLK_ISP			BIT(8)
>> +#define RKISP1_CIF_CLK_CTRL_MI_IDC			BIT(9)
>> +#define RKISP1_CIF_CLK_CTRL_MI_MP			BIT(10)
>> +#define RKISP1_CIF_CLK_CTRL_MI_JPEG			BIT(11)
>> +#define RKISP1_CIF_CLK_CTRL_MI_DP			BIT(12)
>> +#define RKISP1_CIF_CLK_CTRL_MI_Y12			BIT(13)
>> +#define RKISP1_CIF_CLK_CTRL_MI_SP			BIT(14)
>> +#define RKISP1_CIF_CLK_CTRL_MI_RAW0			BIT(15)
>> +#define RKISP1_CIF_CLK_CTRL_MI_RAW1			BIT(16)
>> +#define RKISP1_CIF_CLK_CTRL_MI_READ			BIT(17)
>> +#define RKISP1_CIF_CLK_CTRL_MI_RAWRD			BIT(18)
>> +#define RKISP1_CIF_CLK_CTRL_CP				BIT(19)
>> +#define RKISP1_CIF_CLK_CTRL_IE				BIT(20)
>> +#define RKISP1_CIF_CLK_CTRL_SI				BIT(21)
>> +#define RKISP1_CIF_CLK_CTRL_RSZM			BIT(22)
>> +#define RKISP1_CIF_CLK_CTRL_DPMUX			BIT(23)
>> +#define RKISP1_CIF_CLK_CTRL_JPEG			BIT(24)
>> +#define RKISP1_CIF_CLK_CTRL_RSZS			BIT(25)
>> +#define RKISP1_CIF_CLK_CTRL_MIPI			BIT(26)
>> +#define RKISP1_CIF_CLK_CTRL_MARVINMI			BIT(27)
>>   /* ICCL */
>>   #define RKISP1_CIF_ICCL_ISP_CLK				BIT(0)
>>   #define RKISP1_CIF_ICCL_CP_CLK				BIT(1)
>> @@ -346,25 +375,57 @@
>>   #define RKISP1_CIF_SUPER_IMP_CTRL_TRANSP_DIS		BIT(2)
>>   
>>   /* ISP HISTOGRAM CALCULATION : ISP_HIST_PROP */
>> -#define RKISP1_CIF_ISP_HIST_PROP_MODE_DIS		(0 << 0)
>> -#define RKISP1_CIF_ISP_HIST_PROP_MODE_RGB		BIT(0)
>> -#define RKISP1_CIF_ISP_HIST_PROP_MODE_RED		(2 << 0)
>> -#define RKISP1_CIF_ISP_HIST_PROP_MODE_GREEN		(3 << 0)
>> -#define RKISP1_CIF_ISP_HIST_PROP_MODE_BLUE		(4 << 0)
>> -#define RKISP1_CIF_ISP_HIST_PROP_MODE_LUM		(5 << 0)
>> -#define RKISP1_CIF_ISP_HIST_PROP_MODE_MASK		0x7
>> -#define RKISP1_CIF_ISP_HIST_PREDIV_SET(x)		(((x) & 0x7F) << 3)
>> -#define RKISP1_CIF_ISP_HIST_WEIGHT_SET(v0, v1, v2, v3)	\
>> +#define RKISP1_CIF_ISP_HIST_PROP_MODE_DIS_V10		(0 << 0)
>> +#define RKISP1_CIF_ISP_HIST_PROP_MODE_RGB_V10		BIT(0)
>> +#define RKISP1_CIF_ISP_HIST_PROP_MODE_RED_V10		(2 << 0)
>> +#define RKISP1_CIF_ISP_HIST_PROP_MODE_GREEN_V10		(3 << 0)
>> +#define RKISP1_CIF_ISP_HIST_PROP_MODE_BLUE_V10		(4 << 0)
>> +#define RKISP1_CIF_ISP_HIST_PROP_MODE_LUM_V10		(5 << 0)
>> +#define RKISP1_CIF_ISP_HIST_PROP_MODE_MASK_V10		0x7
>> +#define RKISP1_CIF_ISP_HIST_PREDIV_SET_V10(x)		(((x) & 0x7F) << 3)
>> +#define RKISP1_CIF_ISP_HIST_WEIGHT_SET_V10(v0, v1, v2, v3)	\
>>   				     (((v0) & 0x1F) | (((v1) & 0x1F) << 8)  |\
>>   				     (((v2) & 0x1F) << 16) | \
>>   				     (((v3) & 0x1F) << 24))
>>   
>> -#define RKISP1_CIF_ISP_HIST_WINDOW_OFFSET_RESERVED	0xFFFFF000
>> -#define RKISP1_CIF_ISP_HIST_WINDOW_SIZE_RESERVED	0xFFFFF800
>> -#define RKISP1_CIF_ISP_HIST_WEIGHT_RESERVED		0xE0E0E0E0
>> -#define RKISP1_CIF_ISP_MAX_HIST_PREDIVIDER		0x0000007F
>> -#define RKISP1_CIF_ISP_HIST_ROW_NUM			5
>> -#define RKISP1_CIF_ISP_HIST_COLUMN_NUM			5
>> +#define RKISP1_CIF_ISP_HIST_WINDOW_OFFSET_RESERVED_V10	0xFFFFF000
>> +#define RKISP1_CIF_ISP_HIST_WINDOW_SIZE_RESERVED_V10	0xFFFFF800
>> +#define RKISP1_CIF_ISP_HIST_WEIGHT_RESERVED_V10		0xE0E0E0E0
>> +#define RKISP1_CIF_ISP_MAX_HIST_PREDIVIDER_V10		0x0000007F
>> +#define RKISP1_CIF_ISP_HIST_ROW_NUM_V10			5
>> +#define RKISP1_CIF_ISP_HIST_COLUMN_NUM_V10		5
>> +
>> +/* ISP HISTOGRAM CALCULATION : CIF_ISP_HIST */
>> +#define RKISP1_CIF_ISP_HIST_CTRL_EN_SET_V12(x)		(((x) & 0x01) << 0)
>> +#define RKISP1_CIF_ISP_HIST_CTRL_EN_MASK_V12		RKISP1_CIF_ISP_HIST_CTRL_EN_SET_V12(0x01)
>> +#define RKISP1_CIF_ISP_HIST_CTRL_STEPSIZE_SET_V12(x)	(((x) & 0x7F) << 1)
>> +#define RKISP1_CIF_ISP_HIST_CTRL_MODE_SET_V12(x)	(((x) & 0x07) << 8)
>> +#define RKISP1_CIF_ISP_HIST_CTRL_MODE_MASK_V12		RKISP1_CIF_ISP_HIST_CTRL_MODE_SET_V12(0x07)
>> +#define RKISP1_CIF_ISP_HIST_CTRL_AUTOSTOP_SET_V12(x)	(((x) & 0x01) << 11)
>> +#define RKISP1_CIF_ISP_HIST_CTRL_WATERLINE_SET_V12(x)	(((x) & 0xFFF) << 12)
>> +#define RKISP1_CIF_ISP_HIST_CTRL_DATASEL_SET_V12(x)	(((x) & 0x07) << 24)
>> +#define RKISP1_CIF_ISP_HIST_CTRL_INTRSEL_SET_V12(x)	(((x) & 0x01) << 27)
>> +#define RKISP1_CIF_ISP_HIST_CTRL_WNDNUM_SET_V12(x)	(((x) & 0x03) << 28)
>> +#define RKISP1_CIF_ISP_HIST_CTRL_DBGEN_SET_V12(x)	(((x) & 0x01) << 30)
>> +#define RKISP1_CIF_ISP_HIST_ROW_NUM_V12		15
>> +#define RKISP1_CIF_ISP_HIST_COLUMN_NUM_V12		15
>> +#define RKISP1_CIF_ISP_HIST_WEIGHT_REG_SIZE_V12	\
>> +				(RKISP1_CIF_ISP_HIST_ROW_NUM_V12 * RKISP1_CIF_ISP_HIST_COLUMN_NUM_V12)
>> +
>> +#define RKISP1_CIF_ISP_HIST_WEIGHT_SET_V12(v0, v1, v2, v3)	\
>> +				(((v0) & 0x3F) | (((v1) & 0x3F) << 8) |\
>> +				(((v2) & 0x3F) << 16) |\
>> +				(((v3) & 0x3F) << 24))
>> +
>> +#define RKISP1_CIF_ISP_HIST_OFFS_SET_V12(v0, v1)	\
>> +				(((v0) & 0x1FFF) | (((v1) & 0x1FFF) << 16))
>> +#define RKISP1_CIF_ISP_HIST_SIZE_SET_V12(v0, v1)	\
>> +				(((v0) & 0x7FF) | (((v1) & 0x7FF) << 16))
>> +
>> +#define RKISP1_CIF_ISP_HIST_GET_BIN0_V12(x)	\
>> +				((x) & 0xFFFF)
>> +#define RKISP1_CIF_ISP_HIST_GET_BIN1_V12(x)	\
>> +				(((x) >> 16) & 0xFFFF)
>>   
>>   /* AUTO FOCUS MEASUREMENT:  ISP_AFM_CTRL */
>>   #define RKISP1_ISP_AFM_CTRL_ENABLE			BIT(0)
>> @@ -400,6 +461,8 @@
>>   #define RKISP1_CIF_ISP_AWB_MODE_YCBCR_EN		((0 << 31) | (0x2 << 0))
>>   #define RKISP1_CIF_ISP_AWB_MODE_MASK_NONE		0xFFFFFFFC
>>   #define RKISP1_CIF_ISP_AWB_MODE_READ(x)			((x) & 3)
>> +#define RKISP1_CIF_ISP_AWB_SET_FRAMES_V12(x)		(((x) & 0x07) << 28)
>> +#define RKISP1_CIF_ISP_AWB_SET_FRAMES_MASK_V12		RKISP1_CIF_ISP_AWB_SET_FRAMES_V12(0x07)
>>   /* ISP_AWB_GAIN_RB, ISP_AWB_GAIN_G  */
>>   #define RKISP1_CIF_ISP_AWB_GAIN_R_SET(x)		(((x) & 0x3FF) << 16)
>>   #define RKISP1_CIF_ISP_AWB_GAIN_R_READ(x)		(((x) >> 16) & 0x3FF)
>> @@ -434,6 +497,7 @@
>>   /* ISP_EXP_CTRL */
>>   #define RKISP1_CIF_ISP_EXP_ENA				BIT(0)
>>   #define RKISP1_CIF_ISP_EXP_CTRL_AUTOSTOP		BIT(1)
>> +#define RKISP1_CIF_ISP_EXP_CTRL_WNDNUM_SET_V12(x)	(((x) & 0x03) << 2)
>>   /*
>>    *'1' luminance calculation according to  Y=(R+G+B) x 0.332 (85/256)
>>    *'0' luminance calculation according to Y=16+0.25R+0.5G+0.1094B
>> @@ -441,42 +505,76 @@
>>   #define RKISP1_CIF_ISP_EXP_CTRL_MEASMODE_1		BIT(31)
>>   
>>   /* ISP_EXP_H_SIZE */
>> -#define RKISP1_CIF_ISP_EXP_H_SIZE_SET(x)		((x) & 0x7FF)
>> -#define RKISP1_CIF_ISP_EXP_HEIGHT_MASK			0x000007FF
>> +#define RKISP1_CIF_ISP_EXP_H_SIZE_SET_V10(x)		((x) & 0x7FF)
>> +#define RKISP1_CIF_ISP_EXP_HEIGHT_MASK_V10			0x000007FF
>> +#define RKISP1_CIF_ISP_EXP_H_SIZE_SET_V12(x)		((x) & 0x7FF)
>> +#define RKISP1_CIF_ISP_EXP_HEIGHT_MASK_V12		0x000007FF
>>   /* ISP_EXP_V_SIZE : vertical size must be a multiple of 2). */
>> -#define RKISP1_CIF_ISP_EXP_V_SIZE_SET(x)		((x) & 0x7FE)
>> +#define RKISP1_CIF_ISP_EXP_V_SIZE_SET_V10(x)		((x) & 0x7FE)
>> +#define RKISP1_CIF_ISP_EXP_V_SIZE_SET_V12(x)		(((x) & 0x7FE) << 16)
>>   
>>   /* ISP_EXP_H_OFFSET */
>> -#define RKISP1_CIF_ISP_EXP_H_OFFSET_SET(x)		((x) & 0x1FFF)
>> -#define RKISP1_CIF_ISP_EXP_MAX_HOFFS			2424
>> +#define RKISP1_CIF_ISP_EXP_H_OFFSET_SET_V10(x)		((x) & 0x1FFF)
>> +#define RKISP1_CIF_ISP_EXP_MAX_HOFFS_V10		2424
>> +#define RKISP1_CIF_ISP_EXP_H_OFFSET_SET_V12(x)		((x) & 0x1FFF)
>> +#define RKISP1_CIF_ISP_EXP_MAX_HOFFS_V12		0x1FFF
>>   /* ISP_EXP_V_OFFSET */
>> -#define RKISP1_CIF_ISP_EXP_V_OFFSET_SET(x)		((x) & 0x1FFF)
>> -#define RKISP1_CIF_ISP_EXP_MAX_VOFFS			1806
>> -
>> -#define RKISP1_CIF_ISP_EXP_ROW_NUM			5
>> -#define RKISP1_CIF_ISP_EXP_COLUMN_NUM			5
>> -#define RKISP1_CIF_ISP_EXP_NUM_LUMA_REGS \
>> -	(RKISP1_CIF_ISP_EXP_ROW_NUM * RKISP1_CIF_ISP_EXP_COLUMN_NUM)
>> -#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE		516
>> -#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE		35
>> -#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE		390
>> -#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE		28
>> -#define RKISP1_CIF_ISP_EXP_MAX_HSIZE	\
>> -	(RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE * RKISP1_CIF_ISP_EXP_COLUMN_NUM + 1)
>> -#define RKISP1_CIF_ISP_EXP_MIN_HSIZE	\
>> -	(RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE * RKISP1_CIF_ISP_EXP_COLUMN_NUM + 1)
>> -#define RKISP1_CIF_ISP_EXP_MAX_VSIZE	\
>> -	(RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE * RKISP1_CIF_ISP_EXP_ROW_NUM + 1)
>> -#define RKISP1_CIF_ISP_EXP_MIN_VSIZE	\
>> -	(RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE * RKISP1_CIF_ISP_EXP_ROW_NUM + 1)
>> +#define RKISP1_CIF_ISP_EXP_V_OFFSET_SET_V10(x)		((x) & 0x1FFF)
>> +#define RKISP1_CIF_ISP_EXP_MAX_VOFFS_V10		1806
>> +#define RKISP1_CIF_ISP_EXP_V_OFFSET_SET_V12(x)		(((x) & 0x1FFF) << 16)
>> +#define RKISP1_CIF_ISP_EXP_MAX_VOFFS_V12		0x1FFF
>> +
>> +#define RKISP1_CIF_ISP_EXP_ROW_NUM_V10			5
>> +#define RKISP1_CIF_ISP_EXP_COLUMN_NUM_V10			5
>> +#define RKISP1_CIF_ISP_EXP_NUM_LUMA_REGS_V10 \
>> +	(RKISP1_CIF_ISP_EXP_ROW_NUM_V10 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V10)
>> +#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE_V10		516
>> +#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE_V10		35
>> +#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE_V10		390
>> +#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE_V10		28
>> +#define RKISP1_CIF_ISP_EXP_MAX_HSIZE_V10	\
>> +	(RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE_V10 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V10 + 1)
>> +#define RKISP1_CIF_ISP_EXP_MIN_HSIZE_V10	\
>> +	(RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE_V10 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V10 + 1)
>> +#define RKISP1_CIF_ISP_EXP_MAX_VSIZE_V10	\
>> +	(RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE_V10 * RKISP1_CIF_ISP_EXP_ROW_NUM_V10 + 1)
>> +#define RKISP1_CIF_ISP_EXP_MIN_VSIZE_V10	\
>> +	(RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE_V10 * RKISP1_CIF_ISP_EXP_ROW_NUM_V10 + 1)
>> +
>> +#define RKISP1_CIF_ISP_EXP_ROW_NUM_V12			15
>> +#define RKISP1_CIF_ISP_EXP_COLUMN_NUM_V12		15
>> +#define RKISP1_CIF_ISP_EXP_NUM_LUMA_REGS_V12 \
>> +	(RKISP1_CIF_ISP_EXP_ROW_NUM_V12 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V12)
>> +
>> +#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE_V12		0x7FF
>> +#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE_V12		0xE
>> +#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE_V12		0x7FE
>> +#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE_V12		0xE
>> +#define RKISP1_CIF_ISP_EXP_MAX_HSIZE_V12	\
>> +	(RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE_V12 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V12 + 1)
>> +#define RKISP1_CIF_ISP_EXP_MIN_HSIZE_V12	\
>> +	(RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE_V12 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V12 + 1)
>> +#define RKISP1_CIF_ISP_EXP_MAX_VSIZE_V12	\
>> +	(RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE_V12 * RKISP1_CIF_ISP_EXP_ROW_NUM_V12 + 1)
>> +#define RKISP1_CIF_ISP_EXP_MIN_VSIZE_V12	\
>> +	(RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE_V12 * RKISP1_CIF_ISP_EXP_ROW_NUM_V12 + 1)
>> +
>> +#define RKISP1_CIF_ISP_EXP_GET_MEAN_xy0_V12(x)		((x) & 0xFF)
>> +#define RKISP1_CIF_ISP_EXP_GET_MEAN_xy1_V12(x)		(((x) >> 8) & 0xFF)
>> +#define RKISP1_CIF_ISP_EXP_GET_MEAN_xy2_V12(x)		(((x) >> 16) & 0xFF)
>> +#define RKISP1_CIF_ISP_EXP_GET_MEAN_xy3_V12(x)		(((x) >> 24) & 0xFF)
>>   
>>   /* LSC: ISP_LSC_CTRL */
>>   #define RKISP1_CIF_ISP_LSC_CTRL_ENA			BIT(0)
>>   #define RKISP1_CIF_ISP_LSC_SECT_SIZE_RESERVED		0xFC00FC00
>> -#define RKISP1_CIF_ISP_LSC_GRAD_RESERVED		0xF000F000
>> -#define RKISP1_CIF_ISP_LSC_SAMPLE_RESERVED		0xF000F000
>> -#define RKISP1_CIF_ISP_LSC_TABLE_DATA(v0, v1)     \
>> +#define RKISP1_CIF_ISP_LSC_GRAD_RESERVED_V10		0xF000F000
>> +#define RKISP1_CIF_ISP_LSC_SAMPLE_RESERVED_V10		0xF000F000
>> +#define RKISP1_CIF_ISP_LSC_GRAD_RESERVED_V12		0xE000E000
>> +#define RKISP1_CIF_ISP_LSC_SAMPLE_RESERVED_V12		0xE000E000
>> +#define RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(v0, v1)     \
>>   	(((v0) & 0xFFF) | (((v1) & 0xFFF) << 12))
>> +#define RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(v0, v1)     \
>> +	(((v0) & 0x1FFF) | (((v1) & 0x1FFF) << 13))
>>   #define RKISP1_CIF_ISP_LSC_SECT_SIZE(v0, v1)      \
>>   	(((v0) & 0xFFF) | (((v1) & 0xFFF) << 16))
>>   #define RKISP1_CIF_ISP_LSC_GRAD_SIZE(v0, v1)      \
>> @@ -549,6 +647,10 @@
>>   	(1 << 15) | (1 << 11) | (1 << 7) | (1 << 3))
>>   #define RKISP1_CIFISP_DEGAMMA_Y_RESERVED		0xFFFFF000
>>   
>> +/* GAMMA-OUT */
>> +#define RKISP1_CIF_ISP_GAMMA_VALUE_V12(x, y)	\
>> +	(((x) & 0xFFF) << 16 | ((y) & 0xFFF) << 0)
>> +
>>   /* AFM */
>>   #define RKISP1_CIF_ISP_AFM_ENA				BIT(0)
>>   #define RKISP1_CIF_ISP_AFM_THRES_RESERVED		0xFFFF0000
>> @@ -559,6 +661,11 @@
>>   #define RKISP1_CIF_ISP_AFM_WINDOW_Y_MIN			0x2
>>   #define RKISP1_CIF_ISP_AFM_WINDOW_X(x)			(((x) & 0x1FFF) << 16)
>>   #define RKISP1_CIF_ISP_AFM_WINDOW_Y(x)			((x) & 0x1FFF)
>> +#define RKISP1_CIF_ISP_AFM_SET_SHIFT_a_V12(x, y)	(((x) & 0x7) << 16 | ((y) & 0x7) << 0)
>> +#define RKISP1_CIF_ISP_AFM_SET_SHIFT_b_V12(x, y)	(((x) & 0x7) << 20 | ((y) & 0x7) << 4)
>> +#define RKISP1_CIF_ISP_AFM_SET_SHIFT_c_V12(x, y)	(((x) & 0x7) << 24 | ((y) & 0x7) << 8)
>> +#define RKISP1_CIF_ISP_AFM_GET_LUM_SHIFT_a_V12(x)	(((x) & 0x70000) >> 16)
>> +#define RKISP1_CIF_ISP_AFM_GET_AFM_SHIFT_a_V12(x)	((x) & 0x7)
>>   
>>   /* DPF */
>>   #define RKISP1_CIF_ISP_DPF_MODE_EN			BIT(0)
>> @@ -581,6 +688,7 @@
>>   #define RKISP1_CIF_CTRL_BASE			0x00000000
>>   #define RKISP1_CIF_CCL				(RKISP1_CIF_CTRL_BASE + 0x00000000)
>>   #define RKISP1_CIF_VI_ID			(RKISP1_CIF_CTRL_BASE + 0x00000008)
>> +#define RKISP1_CIF_VI_ISP_CLK_CTRL_V12		(RKISP1_CIF_CTRL_BASE + 0x0000000C)
>>   #define RKISP1_CIF_ICCL				(RKISP1_CIF_CTRL_BASE + 0x00000010)
>>   #define RKISP1_CIF_IRCL				(RKISP1_CIF_CTRL_BASE + 0x00000014)
>>   #define RKISP1_CIF_VI_DPCL			(RKISP1_CIF_CTRL_BASE + 0x00000018)
>> @@ -666,18 +774,35 @@
>>   #define RKISP1_CIF_ISP_GAMMA_B_Y14		(RKISP1_CIF_ISP_BASE + 0x000000E4)
>>   #define RKISP1_CIF_ISP_GAMMA_B_Y15		(RKISP1_CIF_ISP_BASE + 0x000000E8)
>>   #define RKISP1_CIF_ISP_GAMMA_B_Y16		(RKISP1_CIF_ISP_BASE + 0x000000EC)
>> -#define RKISP1_CIF_ISP_AWB_PROP			(RKISP1_CIF_ISP_BASE + 0x00000110)
>> -#define RKISP1_CIF_ISP_AWB_WND_H_OFFS		(RKISP1_CIF_ISP_BASE + 0x00000114)
>> -#define RKISP1_CIF_ISP_AWB_WND_V_OFFS		(RKISP1_CIF_ISP_BASE + 0x00000118)
>> -#define RKISP1_CIF_ISP_AWB_WND_H_SIZE		(RKISP1_CIF_ISP_BASE + 0x0000011C)
>> -#define RKISP1_CIF_ISP_AWB_WND_V_SIZE		(RKISP1_CIF_ISP_BASE + 0x00000120)
>> -#define RKISP1_CIF_ISP_AWB_FRAMES		(RKISP1_CIF_ISP_BASE + 0x00000124)
>> -#define RKISP1_CIF_ISP_AWB_REF			(RKISP1_CIF_ISP_BASE + 0x00000128)
>> -#define RKISP1_CIF_ISP_AWB_THRESH		(RKISP1_CIF_ISP_BASE + 0x0000012C)
>> -#define RKISP1_CIF_ISP_AWB_GAIN_G		(RKISP1_CIF_ISP_BASE + 0x00000138)
>> -#define RKISP1_CIF_ISP_AWB_GAIN_RB		(RKISP1_CIF_ISP_BASE + 0x0000013C)
>> -#define RKISP1_CIF_ISP_AWB_WHITE_CNT		(RKISP1_CIF_ISP_BASE + 0x00000140)
>> -#define RKISP1_CIF_ISP_AWB_MEAN			(RKISP1_CIF_ISP_BASE + 0x00000144)
>> +#define RKISP1_CIF_ISP_AWB_PROP_V10		(RKISP1_CIF_ISP_BASE + 0x00000110)
>> +#define RKISP1_CIF_ISP_AWB_WND_H_OFFS_V10	(RKISP1_CIF_ISP_BASE + 0x00000114)
>> +#define RKISP1_CIF_ISP_AWB_WND_V_OFFS_V10	(RKISP1_CIF_ISP_BASE + 0x00000118)
>> +#define RKISP1_CIF_ISP_AWB_WND_H_SIZE_V10	(RKISP1_CIF_ISP_BASE + 0x0000011C)
>> +#define RKISP1_CIF_ISP_AWB_WND_V_SIZE_V10	(RKISP1_CIF_ISP_BASE + 0x00000120)
>> +#define RKISP1_CIF_ISP_AWB_FRAMES_V10		(RKISP1_CIF_ISP_BASE + 0x00000124)
>> +#define RKISP1_CIF_ISP_AWB_REF_V10		(RKISP1_CIF_ISP_BASE + 0x00000128)
>> +#define RKISP1_CIF_ISP_AWB_THRESH_V10		(RKISP1_CIF_ISP_BASE + 0x0000012C)
>> +#define RKISP1_CIF_ISP_AWB_GAIN_G_V10		(RKISP1_CIF_ISP_BASE + 0x00000138)
>> +#define RKISP1_CIF_ISP_AWB_GAIN_RB_V10		(RKISP1_CIF_ISP_BASE + 0x0000013C)
>> +#define RKISP1_CIF_ISP_AWB_WHITE_CNT_V10	(RKISP1_CIF_ISP_BASE + 0x00000140)
>> +#define RKISP1_CIF_ISP_AWB_MEAN_V10		(RKISP1_CIF_ISP_BASE + 0x00000144)
>> +#define RKISP1_CIF_ISP_AWB_PROP_V12		(RKISP1_CIF_ISP_BASE + 0x00000110)
>> +#define RKISP1_CIF_ISP_AWB_SIZE_V12		(RKISP1_CIF_ISP_BASE + 0x00000114)
>> +#define RKISP1_CIF_ISP_AWB_OFFS_V12		(RKISP1_CIF_ISP_BASE + 0x00000118)
>> +#define RKISP1_CIF_ISP_AWB_REF_V12		(RKISP1_CIF_ISP_BASE + 0x0000011C)
>> +#define RKISP1_CIF_ISP_AWB_THRESH_V12		(RKISP1_CIF_ISP_BASE + 0x00000120)
>> +#define RKISP1_CIF_ISP_X_COOR12_V12		(RKISP1_CIF_ISP_BASE + 0x00000124)
>> +#define RKISP1_CIF_ISP_X_COOR34_V12		(RKISP1_CIF_ISP_BASE + 0x00000128)
>> +#define RKISP1_CIF_ISP_AWB_WHITE_CNT_V12	(RKISP1_CIF_ISP_BASE + 0x0000012C)
>> +#define RKISP1_CIF_ISP_AWB_MEAN_V12		(RKISP1_CIF_ISP_BASE + 0x00000130)
>> +#define RKISP1_CIF_ISP_DEGAIN_V12		(RKISP1_CIF_ISP_BASE + 0x00000134)
>> +#define RKISP1_CIF_ISP_AWB_GAIN_G_V12		(RKISP1_CIF_ISP_BASE + 0x00000138)
>> +#define RKISP1_CIF_ISP_AWB_GAIN_RB_V12		(RKISP1_CIF_ISP_BASE + 0x0000013C)
>> +#define RKISP1_CIF_ISP_REGION_LINE_V12		(RKISP1_CIF_ISP_BASE + 0x00000140)
>> +#define RKISP1_CIF_ISP_WP_CNT_REGION0_V12	(RKISP1_CIF_ISP_BASE + 0x00000160)
>> +#define RKISP1_CIF_ISP_WP_CNT_REGION1_V12	(RKISP1_CIF_ISP_BASE + 0x00000164)
>> +#define RKISP1_CIF_ISP_WP_CNT_REGION2_V12	(RKISP1_CIF_ISP_BASE + 0x00000168)
>> +#define RKISP1_CIF_ISP_WP_CNT_REGION3_V12	(RKISP1_CIF_ISP_BASE + 0x0000016C)
>>   #define RKISP1_CIF_ISP_CC_COEFF_0		(RKISP1_CIF_ISP_BASE + 0x00000170)
>>   #define RKISP1_CIF_ISP_CC_COEFF_1		(RKISP1_CIF_ISP_BASE + 0x00000174)
>>   #define RKISP1_CIF_ISP_CC_COEFF_2		(RKISP1_CIF_ISP_BASE + 0x00000178)
>> @@ -711,30 +836,32 @@
>>   #define RKISP1_CIF_ISP_CT_COEFF_6		(RKISP1_CIF_ISP_BASE + 0x000001E8)
>>   #define RKISP1_CIF_ISP_CT_COEFF_7		(RKISP1_CIF_ISP_BASE + 0x000001EC)
>>   #define RKISP1_CIF_ISP_CT_COEFF_8		(RKISP1_CIF_ISP_BASE + 0x000001F0)
>> -#define RKISP1_CIF_ISP_GAMMA_OUT_MODE		(RKISP1_CIF_ISP_BASE + 0x000001F4)
>> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_0		(RKISP1_CIF_ISP_BASE + 0x000001F8)
>> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_1		(RKISP1_CIF_ISP_BASE + 0x000001FC)
>> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_2		(RKISP1_CIF_ISP_BASE + 0x00000200)
>> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_3		(RKISP1_CIF_ISP_BASE + 0x00000204)
>> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_4		(RKISP1_CIF_ISP_BASE + 0x00000208)
>> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_5		(RKISP1_CIF_ISP_BASE + 0x0000020C)
>> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_6		(RKISP1_CIF_ISP_BASE + 0x00000210)
>> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_7		(RKISP1_CIF_ISP_BASE + 0x00000214)
>> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_8		(RKISP1_CIF_ISP_BASE + 0x00000218)
>> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_9		(RKISP1_CIF_ISP_BASE + 0x0000021C)
>> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_10		(RKISP1_CIF_ISP_BASE + 0x00000220)
>> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_11		(RKISP1_CIF_ISP_BASE + 0x00000224)
>> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_12		(RKISP1_CIF_ISP_BASE + 0x00000228)
>> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_13		(RKISP1_CIF_ISP_BASE + 0x0000022C)
>> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_14		(RKISP1_CIF_ISP_BASE + 0x00000230)
>> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_15		(RKISP1_CIF_ISP_BASE + 0x00000234)
>> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_16		(RKISP1_CIF_ISP_BASE + 0x00000238)
>> +#define RKISP1_CIF_ISP_GAMMA_OUT_MODE_V10	(RKISP1_CIF_ISP_BASE + 0x000001F4)
>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_0_V10	(RKISP1_CIF_ISP_BASE + 0x000001F8)
>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_1_V10	(RKISP1_CIF_ISP_BASE + 0x000001FC)
>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_2_V10	(RKISP1_CIF_ISP_BASE + 0x00000200)
>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_3_V10	(RKISP1_CIF_ISP_BASE + 0x00000204)
>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_4_V10	(RKISP1_CIF_ISP_BASE + 0x00000208)
>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_5_V10	(RKISP1_CIF_ISP_BASE + 0x0000020C)
>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_6_V10	(RKISP1_CIF_ISP_BASE + 0x00000210)
>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_7_V10	(RKISP1_CIF_ISP_BASE + 0x00000214)
>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_8_V10	(RKISP1_CIF_ISP_BASE + 0x00000218)
>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_9_V10	(RKISP1_CIF_ISP_BASE + 0x0000021C)
>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_10_V10	(RKISP1_CIF_ISP_BASE + 0x00000220)
>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_11_V10	(RKISP1_CIF_ISP_BASE + 0x00000224)
>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_12_V10	(RKISP1_CIF_ISP_BASE + 0x00000228)
>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_13_V10	(RKISP1_CIF_ISP_BASE + 0x0000022C)
>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_14_V10	(RKISP1_CIF_ISP_BASE + 0x00000230)
>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_15_V10	(RKISP1_CIF_ISP_BASE + 0x00000234)
>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_16_V10	(RKISP1_CIF_ISP_BASE + 0x00000238)
>>   #define RKISP1_CIF_ISP_ERR			(RKISP1_CIF_ISP_BASE + 0x0000023C)
>>   #define RKISP1_CIF_ISP_ERR_CLR			(RKISP1_CIF_ISP_BASE + 0x00000240)
>>   #define RKISP1_CIF_ISP_FRAME_COUNT		(RKISP1_CIF_ISP_BASE + 0x00000244)
>>   #define RKISP1_CIF_ISP_CT_OFFSET_R		(RKISP1_CIF_ISP_BASE + 0x00000248)
>>   #define RKISP1_CIF_ISP_CT_OFFSET_G		(RKISP1_CIF_ISP_BASE + 0x0000024C)
>>   #define RKISP1_CIF_ISP_CT_OFFSET_B		(RKISP1_CIF_ISP_BASE + 0x00000250)
>> +#define RKISP1_CIF_ISP_GAMMA_OUT_MODE_V12	(RKISP1_CIF_ISP_BASE + 0x00000300)
>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_0_V12	(RKISP1_CIF_ISP_BASE + 0x00000304)
>>   
>>   #define RKISP1_CIF_ISP_FLASH_BASE		0x00000660
>>   #define RKISP1_CIF_ISP_FLASH_CMD		(RKISP1_CIF_ISP_FLASH_BASE + 0x00000000)
>> @@ -1004,36 +1131,35 @@
>>   #define RKISP1_CIF_ISP_IS_H_SIZE_SHD		(RKISP1_CIF_ISP_IS_BASE + 0x0000002C)
>>   #define RKISP1_CIF_ISP_IS_V_SIZE_SHD		(RKISP1_CIF_ISP_IS_BASE + 0x00000030)
>>   
>> -#define RKISP1_CIF_ISP_HIST_BASE		0x00002400
>> -
>> -#define RKISP1_CIF_ISP_HIST_PROP		(RKISP1_CIF_ISP_HIST_BASE + 0x00000000)
>> -#define RKISP1_CIF_ISP_HIST_H_OFFS		(RKISP1_CIF_ISP_HIST_BASE + 0x00000004)
>> -#define RKISP1_CIF_ISP_HIST_V_OFFS		(RKISP1_CIF_ISP_HIST_BASE + 0x00000008)
>> -#define RKISP1_CIF_ISP_HIST_H_SIZE		(RKISP1_CIF_ISP_HIST_BASE + 0x0000000C)
>> -#define RKISP1_CIF_ISP_HIST_V_SIZE		(RKISP1_CIF_ISP_HIST_BASE + 0x00000010)
>> -#define RKISP1_CIF_ISP_HIST_BIN_0		(RKISP1_CIF_ISP_HIST_BASE + 0x00000014)
>> -#define RKISP1_CIF_ISP_HIST_BIN_1		(RKISP1_CIF_ISP_HIST_BASE + 0x00000018)
>> -#define RKISP1_CIF_ISP_HIST_BIN_2		(RKISP1_CIF_ISP_HIST_BASE + 0x0000001C)
>> -#define RKISP1_CIF_ISP_HIST_BIN_3		(RKISP1_CIF_ISP_HIST_BASE + 0x00000020)
>> -#define RKISP1_CIF_ISP_HIST_BIN_4		(RKISP1_CIF_ISP_HIST_BASE + 0x00000024)
>> -#define RKISP1_CIF_ISP_HIST_BIN_5		(RKISP1_CIF_ISP_HIST_BASE + 0x00000028)
>> -#define RKISP1_CIF_ISP_HIST_BIN_6		(RKISP1_CIF_ISP_HIST_BASE + 0x0000002C)
>> -#define RKISP1_CIF_ISP_HIST_BIN_7		(RKISP1_CIF_ISP_HIST_BASE + 0x00000030)
>> -#define RKISP1_CIF_ISP_HIST_BIN_8		(RKISP1_CIF_ISP_HIST_BASE + 0x00000034)
>> -#define RKISP1_CIF_ISP_HIST_BIN_9		(RKISP1_CIF_ISP_HIST_BASE + 0x00000038)
>> -#define RKISP1_CIF_ISP_HIST_BIN_10		(RKISP1_CIF_ISP_HIST_BASE + 0x0000003C)
>> -#define RKISP1_CIF_ISP_HIST_BIN_11		(RKISP1_CIF_ISP_HIST_BASE + 0x00000040)
>> -#define RKISP1_CIF_ISP_HIST_BIN_12		(RKISP1_CIF_ISP_HIST_BASE + 0x00000044)
>> -#define RKISP1_CIF_ISP_HIST_BIN_13		(RKISP1_CIF_ISP_HIST_BASE + 0x00000048)
>> -#define RKISP1_CIF_ISP_HIST_BIN_14		(RKISP1_CIF_ISP_HIST_BASE + 0x0000004C)
>> -#define RKISP1_CIF_ISP_HIST_BIN_15		(RKISP1_CIF_ISP_HIST_BASE + 0x00000050)
>> -#define RKISP1_CIF_ISP_HIST_WEIGHT_00TO30	(RKISP1_CIF_ISP_HIST_BASE + 0x00000054)
>> -#define RKISP1_CIF_ISP_HIST_WEIGHT_40TO21	(RKISP1_CIF_ISP_HIST_BASE + 0x00000058)
>> -#define RKISP1_CIF_ISP_HIST_WEIGHT_31TO12	(RKISP1_CIF_ISP_HIST_BASE + 0x0000005C)
>> -#define RKISP1_CIF_ISP_HIST_WEIGHT_22TO03	(RKISP1_CIF_ISP_HIST_BASE + 0x00000060)
>> -#define RKISP1_CIF_ISP_HIST_WEIGHT_13TO43	(RKISP1_CIF_ISP_HIST_BASE + 0x00000064)
>> -#define RKISP1_CIF_ISP_HIST_WEIGHT_04TO34	(RKISP1_CIF_ISP_HIST_BASE + 0x00000068)
>> -#define RKISP1_CIF_ISP_HIST_WEIGHT_44		(RKISP1_CIF_ISP_HIST_BASE + 0x0000006C)
>> +#define RKISP1_CIF_ISP_HIST_BASE_V10		0x00002400
>> +#define RKISP1_CIF_ISP_HIST_PROP_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000000)
>> +#define RKISP1_CIF_ISP_HIST_H_OFFS_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000004)
>> +#define RKISP1_CIF_ISP_HIST_V_OFFS_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000008)
>> +#define RKISP1_CIF_ISP_HIST_H_SIZE_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000000C)
>> +#define RKISP1_CIF_ISP_HIST_V_SIZE_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000010)
>> +#define RKISP1_CIF_ISP_HIST_BIN_0_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000014)
>> +#define RKISP1_CIF_ISP_HIST_BIN_1_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000018)
>> +#define RKISP1_CIF_ISP_HIST_BIN_2_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000001C)
>> +#define RKISP1_CIF_ISP_HIST_BIN_3_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000020)
>> +#define RKISP1_CIF_ISP_HIST_BIN_4_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000024)
>> +#define RKISP1_CIF_ISP_HIST_BIN_5_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000028)
>> +#define RKISP1_CIF_ISP_HIST_BIN_6_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000002C)
>> +#define RKISP1_CIF_ISP_HIST_BIN_7_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000030)
>> +#define RKISP1_CIF_ISP_HIST_BIN_8_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000034)
>> +#define RKISP1_CIF_ISP_HIST_BIN_9_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000038)
>> +#define RKISP1_CIF_ISP_HIST_BIN_10_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000003C)
>> +#define RKISP1_CIF_ISP_HIST_BIN_11_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000040)
>> +#define RKISP1_CIF_ISP_HIST_BIN_12_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000044)
>> +#define RKISP1_CIF_ISP_HIST_BIN_13_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000048)
>> +#define RKISP1_CIF_ISP_HIST_BIN_14_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000004C)
>> +#define RKISP1_CIF_ISP_HIST_BIN_15_V10		(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000050)
>> +#define RKISP1_CIF_ISP_HIST_WEIGHT_00TO30_V10	(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000054)
>> +#define RKISP1_CIF_ISP_HIST_WEIGHT_40TO21_V10	(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000058)
>> +#define RKISP1_CIF_ISP_HIST_WEIGHT_31TO12_V10	(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000005C)
>> +#define RKISP1_CIF_ISP_HIST_WEIGHT_22TO03_V10	(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000060)
>> +#define RKISP1_CIF_ISP_HIST_WEIGHT_13TO43_V10	(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000064)
>> +#define RKISP1_CIF_ISP_HIST_WEIGHT_04TO34_V10	(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000068)
>> +#define RKISP1_CIF_ISP_HIST_WEIGHT_44_V10	(RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000006C)
>>   
>>   #define RKISP1_CIF_ISP_FILT_BASE		0x00002500
>>   #define RKISP1_CIF_ISP_FILT_MODE		(RKISP1_CIF_ISP_FILT_BASE + 0x00000000)
>> @@ -1059,35 +1185,38 @@
>>   
>>   #define RKISP1_CIF_ISP_EXP_BASE			0x00002600
>>   #define RKISP1_CIF_ISP_EXP_CTRL			(RKISP1_CIF_ISP_EXP_BASE + 0x00000000)
>> -#define RKISP1_CIF_ISP_EXP_H_OFFSET		(RKISP1_CIF_ISP_EXP_BASE + 0x00000004)
>> -#define RKISP1_CIF_ISP_EXP_V_OFFSET		(RKISP1_CIF_ISP_EXP_BASE + 0x00000008)
>> -#define RKISP1_CIF_ISP_EXP_H_SIZE		(RKISP1_CIF_ISP_EXP_BASE + 0x0000000C)
>> -#define RKISP1_CIF_ISP_EXP_V_SIZE		(RKISP1_CIF_ISP_EXP_BASE + 0x00000010)
>> -#define RKISP1_CIF_ISP_EXP_MEAN_00		(RKISP1_CIF_ISP_EXP_BASE + 0x00000014)
>> -#define RKISP1_CIF_ISP_EXP_MEAN_10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000018)
>> -#define RKISP1_CIF_ISP_EXP_MEAN_20		(RKISP1_CIF_ISP_EXP_BASE + 0x0000001c)
>> -#define RKISP1_CIF_ISP_EXP_MEAN_30		(RKISP1_CIF_ISP_EXP_BASE + 0x00000020)
>> -#define RKISP1_CIF_ISP_EXP_MEAN_40		(RKISP1_CIF_ISP_EXP_BASE + 0x00000024)
>> -#define RKISP1_CIF_ISP_EXP_MEAN_01		(RKISP1_CIF_ISP_EXP_BASE + 0x00000028)
>> -#define RKISP1_CIF_ISP_EXP_MEAN_11		(RKISP1_CIF_ISP_EXP_BASE + 0x0000002c)
>> -#define RKISP1_CIF_ISP_EXP_MEAN_21		(RKISP1_CIF_ISP_EXP_BASE + 0x00000030)
>> -#define RKISP1_CIF_ISP_EXP_MEAN_31		(RKISP1_CIF_ISP_EXP_BASE + 0x00000034)
>> -#define RKISP1_CIF_ISP_EXP_MEAN_41		(RKISP1_CIF_ISP_EXP_BASE + 0x00000038)
>> -#define RKISP1_CIF_ISP_EXP_MEAN_02		(RKISP1_CIF_ISP_EXP_BASE + 0x0000003c)
>> -#define RKISP1_CIF_ISP_EXP_MEAN_12		(RKISP1_CIF_ISP_EXP_BASE + 0x00000040)
>> -#define RKISP1_CIF_ISP_EXP_MEAN_22		(RKISP1_CIF_ISP_EXP_BASE + 0x00000044)
>> -#define RKISP1_CIF_ISP_EXP_MEAN_32		(RKISP1_CIF_ISP_EXP_BASE + 0x00000048)
>> -#define RKISP1_CIF_ISP_EXP_MEAN_42		(RKISP1_CIF_ISP_EXP_BASE + 0x0000004c)
>> -#define RKISP1_CIF_ISP_EXP_MEAN_03		(RKISP1_CIF_ISP_EXP_BASE + 0x00000050)
>> -#define RKISP1_CIF_ISP_EXP_MEAN_13		(RKISP1_CIF_ISP_EXP_BASE + 0x00000054)
>> -#define RKISP1_CIF_ISP_EXP_MEAN_23		(RKISP1_CIF_ISP_EXP_BASE + 0x00000058)
>> -#define RKISP1_CIF_ISP_EXP_MEAN_33		(RKISP1_CIF_ISP_EXP_BASE + 0x0000005c)
>> -#define RKISP1_CIF_ISP_EXP_MEAN_43		(RKISP1_CIF_ISP_EXP_BASE + 0x00000060)
>> -#define RKISP1_CIF_ISP_EXP_MEAN_04		(RKISP1_CIF_ISP_EXP_BASE + 0x00000064)
>> -#define RKISP1_CIF_ISP_EXP_MEAN_14		(RKISP1_CIF_ISP_EXP_BASE + 0x00000068)
>> -#define RKISP1_CIF_ISP_EXP_MEAN_24		(RKISP1_CIF_ISP_EXP_BASE + 0x0000006c)
>> -#define RKISP1_CIF_ISP_EXP_MEAN_34		(RKISP1_CIF_ISP_EXP_BASE + 0x00000070)
>> -#define RKISP1_CIF_ISP_EXP_MEAN_44		(RKISP1_CIF_ISP_EXP_BASE + 0x00000074)
>> +#define RKISP1_CIF_ISP_EXP_H_OFFSET_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000004)
>> +#define RKISP1_CIF_ISP_EXP_V_OFFSET_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000008)
>> +#define RKISP1_CIF_ISP_EXP_H_SIZE_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x0000000C)
>> +#define RKISP1_CIF_ISP_EXP_V_SIZE_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000010)
>> +#define RKISP1_CIF_ISP_EXP_MEAN_00_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000014)
>> +#define RKISP1_CIF_ISP_EXP_MEAN_10_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000018)
>> +#define RKISP1_CIF_ISP_EXP_MEAN_20_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x0000001c)
>> +#define RKISP1_CIF_ISP_EXP_MEAN_30_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000020)
>> +#define RKISP1_CIF_ISP_EXP_MEAN_40_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000024)
>> +#define RKISP1_CIF_ISP_EXP_MEAN_01_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000028)
>> +#define RKISP1_CIF_ISP_EXP_MEAN_11_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x0000002c)
>> +#define RKISP1_CIF_ISP_EXP_MEAN_21_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000030)
>> +#define RKISP1_CIF_ISP_EXP_MEAN_31_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000034)
>> +#define RKISP1_CIF_ISP_EXP_MEAN_41_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000038)
>> +#define RKISP1_CIF_ISP_EXP_MEAN_02_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x0000003c)
>> +#define RKISP1_CIF_ISP_EXP_MEAN_12_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000040)
>> +#define RKISP1_CIF_ISP_EXP_MEAN_22_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000044)
>> +#define RKISP1_CIF_ISP_EXP_MEAN_32_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000048)
>> +#define RKISP1_CIF_ISP_EXP_MEAN_42_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x0000004c)
>> +#define RKISP1_CIF_ISP_EXP_MEAN_03_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000050)
>> +#define RKISP1_CIF_ISP_EXP_MEAN_13_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000054)
>> +#define RKISP1_CIF_ISP_EXP_MEAN_23_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000058)
>> +#define RKISP1_CIF_ISP_EXP_MEAN_33_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x0000005c)
>> +#define RKISP1_CIF_ISP_EXP_MEAN_43_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000060)
>> +#define RKISP1_CIF_ISP_EXP_MEAN_04_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000064)
>> +#define RKISP1_CIF_ISP_EXP_MEAN_14_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000068)
>> +#define RKISP1_CIF_ISP_EXP_MEAN_24_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x0000006c)
>> +#define RKISP1_CIF_ISP_EXP_MEAN_34_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000070)
>> +#define RKISP1_CIF_ISP_EXP_MEAN_44_V10		(RKISP1_CIF_ISP_EXP_BASE + 0x00000074)
>> +#define RKISP1_CIF_ISP_EXP_SIZE_V12		(RKISP1_CIF_ISP_EXP_BASE + 0x00000004)
>> +#define RKISP1_CIF_ISP_EXP_OFFS_V12		(RKISP1_CIF_ISP_EXP_BASE + 0x00000008)
>> +#define RKISP1_CIF_ISP_EXP_MEAN_V12		(RKISP1_CIF_ISP_EXP_BASE + 0x0000000c)
>>   
>>   #define RKISP1_CIF_ISP_BLS_BASE			0x00002700
>>   #define RKISP1_CIF_ISP_BLS_CTRL			(RKISP1_CIF_ISP_BLS_BASE + 0x00000000)
>> @@ -1248,6 +1377,16 @@
>>   #define RKISP1_CIF_ISP_WDR_TONECURVE_YM_31_SHD	(RKISP1_CIF_ISP_WDR_BASE + 0x0000012C)
>>   #define RKISP1_CIF_ISP_WDR_TONECURVE_YM_32_SHD	(RKISP1_CIF_ISP_WDR_BASE + 0x00000130)
>>   
>> +#define RKISP1_CIF_ISP_HIST_BASE_V12		0x00002C00
>> +#define RKISP1_CIF_ISP_HIST_CTRL_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x00000000)
>> +#define RKISP1_CIF_ISP_HIST_SIZE_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x00000004)
>> +#define RKISP1_CIF_ISP_HIST_OFFS_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x00000008)
>> +#define RKISP1_CIF_ISP_HIST_DBG1_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x0000000C)
>> +#define RKISP1_CIF_ISP_HIST_DBG2_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x0000001C)
>> +#define RKISP1_CIF_ISP_HIST_DBG3_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x0000002C)
>> +#define RKISP1_CIF_ISP_HIST_WEIGHT_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x0000003C)
>> +#define RKISP1_CIF_ISP_HIST_BIN_V12		(RKISP1_CIF_ISP_HIST_BASE_V12 + 0x00000120)
>> +
>>   #define RKISP1_CIF_ISP_VSM_BASE			0x00002F00
>>   #define RKISP1_CIF_ISP_VSM_MODE			(RKISP1_CIF_ISP_VSM_BASE + 0x00000000)
>>   #define RKISP1_CIF_ISP_VSM_H_OFFS		(RKISP1_CIF_ISP_VSM_BASE + 0x00000004)
>> @@ -1259,4 +1398,7 @@
>>   #define RKISP1_CIF_ISP_VSM_DELTA_H		(RKISP1_CIF_ISP_VSM_BASE + 0x0000001C)
>>   #define RKISP1_CIF_ISP_VSM_DELTA_V		(RKISP1_CIF_ISP_VSM_BASE + 0x00000020)
>>   
>> +#define RKISP1_CIF_ISP_CSI0_BASE		0x00007000
>> +#define RKISP1_CIF_ISP_CSI0_CTRL0		(RKISP1_CIF_ISP_CSI0_BASE + 0x00000000)
>> +
>>   #endif /* _RKISP1_REGS_H */
>> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c
>> index 7136292039f6..5ce1a2974b55 100644
>> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c
>> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c
>> @@ -175,18 +175,18 @@ rkisp1_stats_init_vb2_queue(struct vb2_queue *q, struct rkisp1_stats *stats)
>>   	return vb2_queue_init(q);
>>   }
>>   
>> -static void rkisp1_stats_get_awb_meas(struct rkisp1_stats *stats,
>> -				      struct rkisp1_stat_buffer *pbuf)
>> +static void rkisp1_stats_get_awb_meas_v10(struct rkisp1_stats *stats,
>> +					  struct rkisp1_stat_buffer *pbuf)
>>   {
>>   	/* Protect against concurrent access from ISR? */
>>   	struct rkisp1_device *rkisp1 = stats->rkisp1;
>>   	u32 reg_val;
>>   
>>   	pbuf->meas_type |= RKISP1_CIF_ISP_STAT_AWB;
>> -	reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_WHITE_CNT);
>> +	reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_WHITE_CNT_V10);
>>   	pbuf->params.awb.awb_mean[0].cnt =
>>   				RKISP1_CIF_ISP_AWB_GET_PIXEL_CNT(reg_val);
>> -	reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_MEAN);
>> +	reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_MEAN_V10);
>>   
>>   	pbuf->params.awb.awb_mean[0].mean_cr_or_r =
>>   				RKISP1_CIF_ISP_AWB_GET_MEAN_CR_R(reg_val);
>> @@ -196,8 +196,29 @@ static void rkisp1_stats_get_awb_meas(struct rkisp1_stats *stats,
>>   				RKISP1_CIF_ISP_AWB_GET_MEAN_Y_G(reg_val);
>>   }
>>   
>> -static void rkisp1_stats_get_aec_meas(struct rkisp1_stats *stats,
>> -				      struct rkisp1_stat_buffer *pbuf)
>> +static void rkisp1_stats_get_awb_meas_v12(struct rkisp1_stats *stats,
>> +					  struct rkisp1_stat_buffer *pbuf)
>> +{
>> +	/* Protect against concurrent access from ISR? */
>> +	struct rkisp1_device *rkisp1 = stats->rkisp1;
>> +	u32 reg_val;
>> +
>> +	pbuf->meas_type |= RKISP1_CIF_ISP_STAT_AWB;
>> +	reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_WHITE_CNT_V12);
>> +	pbuf->params.awb.awb_mean[0].cnt =
>> +				RKISP1_CIF_ISP_AWB_GET_PIXEL_CNT(reg_val);
>> +	reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_MEAN_V12);
>> +
>> +	pbuf->params.awb.awb_mean[0].mean_cr_or_r =
>> +				RKISP1_CIF_ISP_AWB_GET_MEAN_CR_R(reg_val);
>> +	pbuf->params.awb.awb_mean[0].mean_cb_or_b =
>> +				RKISP1_CIF_ISP_AWB_GET_MEAN_CB_B(reg_val);
>> +	pbuf->params.awb.awb_mean[0].mean_y_or_g =
>> +				RKISP1_CIF_ISP_AWB_GET_MEAN_Y_G(reg_val);
>> +}
>> +
>> +static void rkisp1_stats_get_aec_meas_v10(struct rkisp1_stats *stats,
>> +					  struct rkisp1_stat_buffer *pbuf)
>>   {
>>   	struct rkisp1_device *rkisp1 = stats->rkisp1;
>>   	unsigned int i;
>> @@ -206,7 +227,31 @@ static void rkisp1_stats_get_aec_meas(struct rkisp1_stats *stats,
>>   	for (i = 0; i < stats->config->ae_mean_max; i++)
>>   		pbuf->params.ae.exp_mean[i] =
>>   			(u8)rkisp1_read(rkisp1,
>> -					RKISP1_CIF_ISP_EXP_MEAN_00 + i * 4);
>> +					RKISP1_CIF_ISP_EXP_MEAN_00_V10 + i * 4);
>> +}
>> +
>> +static void rkisp1_stats_get_aec_meas_v12(struct rkisp1_stats *stats,
>> +					  struct rkisp1_stat_buffer *pbuf)
>> +{
>> +	struct rkisp1_device *rkisp1 = stats->rkisp1;
>> +	u32 value;
>> +	int i;
>> +
>> +	pbuf->meas_type |= RKISP1_CIF_ISP_STAT_AUTOEXP;
>> +	for (i = 0; i < stats->config->ae_mean_max / 4; i++) {
>> +		value = rkisp1_read(rkisp1, RKISP1_CIF_ISP_EXP_MEAN_V12 + i * 4);
>> +		pbuf->params.ae.exp_mean[4 * i + 0] =
>> +				RKISP1_CIF_ISP_EXP_GET_MEAN_xy0_V12(value);
>> +		pbuf->params.ae.exp_mean[4 * i + 1] =
>> +				RKISP1_CIF_ISP_EXP_GET_MEAN_xy1_V12(value);
>> +		pbuf->params.ae.exp_mean[4 * i + 2] =
>> +				RKISP1_CIF_ISP_EXP_GET_MEAN_xy2_V12(value);
>> +		pbuf->params.ae.exp_mean[4 * i + 3] =
>> +				RKISP1_CIF_ISP_EXP_GET_MEAN_xy3_V12(value);
>> +	}
>> +
>> +	value = rkisp1_read(rkisp1, RKISP1_CIF_ISP_EXP_MEAN_V12 + i * 4);
>> +	pbuf->params.ae.exp_mean[4 * i + 0] = RKISP1_CIF_ISP_EXP_GET_MEAN_xy0_V12(value);
>>   }
>>   
>>   static void rkisp1_stats_get_afc_meas(struct rkisp1_stats *stats,
>> @@ -226,8 +271,8 @@ static void rkisp1_stats_get_afc_meas(struct rkisp1_stats *stats,
>>   	af->window[2].lum = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AFM_LUM_C);
>>   }
>>   
>> -static void rkisp1_stats_get_hst_meas(struct rkisp1_stats *stats,
>> -				      struct rkisp1_stat_buffer *pbuf)
>> +static void rkisp1_stats_get_hst_meas_v10(struct rkisp1_stats *stats,
>> +					  struct rkisp1_stat_buffer *pbuf)
>>   {
>>   	struct rkisp1_device *rkisp1 = stats->rkisp1;
>>   	unsigned int i;
>> @@ -236,7 +281,24 @@ static void rkisp1_stats_get_hst_meas(struct rkisp1_stats *stats,
>>   	for (i = 0; i < stats->config->hist_bin_n_max; i++)
>>   		pbuf->params.hist.hist_bins[i] =
>>   			(u8)rkisp1_read(rkisp1,
>> -					RKISP1_CIF_ISP_HIST_BIN_0 + i * 4);
>> +					RKISP1_CIF_ISP_HIST_BIN_0_V10 + i * 4);
>> +}
>> +
>> +static void rkisp1_stats_get_hst_meas_v12(struct rkisp1_stats *stats,
>> +					  struct rkisp1_stat_buffer *pbuf)
>> +{
>> +	struct rkisp1_device *rkisp1 = stats->rkisp1;
>> +	u32 value;
>> +	int i;
>> +
>> +	pbuf->meas_type |= RKISP1_CIF_ISP_STAT_HIST;
>> +	for (i = 0; i < stats->config->hist_bin_n_max / 2; i++) {
>> +		value = rkisp1_read(rkisp1, RKISP1_CIF_ISP_HIST_BIN_V12 + i * 4);
>> +		pbuf->params.hist.hist_bins[2 * i] =
>> +					RKISP1_CIF_ISP_HIST_GET_BIN0_V12(value);
>> +		pbuf->params.hist.hist_bins[2 * i + 1] =
>> +					RKISP1_CIF_ISP_HIST_GET_BIN1_V12(value);
>> +	}
>>   }
>>   
>>   static void rkisp1_stats_get_bls_meas(struct rkisp1_stats *stats,
>> @@ -286,17 +348,28 @@ static void rkisp1_stats_get_bls_meas(struct rkisp1_stats *stats,
>>   	}
>>   }
>>   
>> -static struct rkisp1_stats_ops rkisp1_stats_ops = {
>> -	.get_awb_meas = rkisp1_stats_get_awb_meas,
>> -	.get_aec_meas = rkisp1_stats_get_aec_meas,
>> -	.get_hst_meas = rkisp1_stats_get_hst_meas,
>> +static struct rkisp1_stats_ops rkisp1_v10_stats_ops = {
>> +	.get_awb_meas = rkisp1_stats_get_awb_meas_v10,
>> +	.get_aec_meas = rkisp1_stats_get_aec_meas_v10,
>> +	.get_hst_meas = rkisp1_stats_get_hst_meas_v10,
>>   };
>>   
>> -static struct rkisp1_stats_config rkisp1_stats_config = {
>> +static struct rkisp1_stats_config rkisp1_v10_stats_config = {
>>   	.ae_mean_max = 25,
>>   	.hist_bin_n_max = 16,
>>   };
>>   
>> +static struct rkisp1_stats_ops rkisp1_v12_stats_ops = {
>> +	.get_awb_meas = rkisp1_stats_get_awb_meas_v12,
>> +	.get_aec_meas = rkisp1_stats_get_aec_meas_v12,
>> +	.get_hst_meas = rkisp1_stats_get_hst_meas_v12,
>> +};
>> +
>> +static struct rkisp1_stats_config rkisp1_v12_stats_config = {
>> +	.ae_mean_max = 81,
>> +	.hist_bin_n_max = 32,
>> +};
>> +
>>   static void
>>   rkisp1_stats_send_measurement(struct rkisp1_stats *stats, u32 isp_ris)
>>   {
>> @@ -365,8 +438,13 @@ static void rkisp1_init_stats(struct rkisp1_stats *stats)
>>   	stats->vdev_fmt.fmt.meta.buffersize =
>>   		sizeof(struct rkisp1_stat_buffer);
>>   
>> -	stats->ops = &rkisp1_stats_ops;
>> -	stats->config = &rkisp1_stats_config;
>> +	if (stats->rkisp1->isp_ver == RKISP1_V12) {
>> +		stats->ops = &rkisp1_v12_stats_ops;
>> +		stats->config = &rkisp1_v12_stats_config;
>> +	} else {
>> +		stats->ops = &rkisp1_v10_stats_ops;
>> +		stats->config = &rkisp1_v10_stats_config;
>> +	}
>>   }
>>   
>>   int rkisp1_stats_register(struct rkisp1_device *rkisp1)
>>

Re: [PATCH RFC 10/11] media: rockchip: rkisp1: add support for v12 isp variants

[Helen Koike]

On 2/5/21 4:23 PM, Dafna Hirschfeld wrote:
> 
> 
> Am 18.01.21 um 19:06 schrieb Helen Koike:
>> Hi Heiko,
>>
>> On 1/8/21 4:33 PM, Heiko Stuebner wrote:
>>> From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
>>>
>>> The rkisp1 evolved over soc generations and the rk3326/px30 introduced
>>> the so called v12 - probably meaning v1.2.
>>>
>>> Add the changed register definitions.
>>>
>>> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
>>> ---
>>>   .../platform/rockchip/rkisp1/rkisp1-common.h  |   1 +
>>>   .../platform/rockchip/rkisp1/rkisp1-isp.c     |  13 +
>>>   .../platform/rockchip/rkisp1/rkisp1-params.c  | 535 +++++++++++++++---
>>>   .../platform/rockchip/rkisp1/rkisp1-regs.h    | 404 ++++++++-----
>>>   .../platform/rockchip/rkisp1/rkisp1-stats.c   | 112 +++-
>>>   5 files changed, 824 insertions(+), 241 deletions(-)
>>>
>>> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
>>> index be0ae02165c9..9deb1ef1aa8b 100644
>>> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
>>> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
>>> @@ -61,6 +61,7 @@
>>>     enum rkisp1_isp_ver {
>>>       RKISP1_V10 = 0,
>>> +    RKISP1_V12,
>>>   };
>>>     /* enum for the resizer pads */
>>> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
>>> index 84440aa71210..306cc96f8230 100644
>>> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
>>> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
>>> @@ -408,6 +408,10 @@ static int rkisp1_config_mipi(struct rkisp1_device *rkisp1)
>>>         rkisp1_write(rkisp1, mipi_ctrl, RKISP1_CIF_MIPI_CTRL);
>>>   +    /* V12 could also use a newer csi2-host, but we don't want that yet */
>>> +    if (rkisp1->isp_ver == RKISP1_V12)
>>> +        rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_CSI0_CTRL0);
>>> +
>>>       /* Configure Data Type and Virtual Channel */
>>>       rkisp1_write(rkisp1,
>>>                RKISP1_CIF_MIPI_DATA_SEL_DT(sink_fmt->mipi_dt) |
>>> @@ -527,6 +531,15 @@ static void rkisp1_config_clk(struct rkisp1_device *rkisp1)
>>>             RKISP1_CIF_ICCL_DCROP_CLK;
>>>         rkisp1_write(rkisp1, val, RKISP1_CIF_ICCL);
>>> +
>>> +    /* ensure sp and mp can run at the same time in V12 */
>>> +    if (rkisp1->isp_ver == RKISP1_V12) {
>>> +        val = RKISP1_CIF_CLK_CTRL_MI_Y12 | RKISP1_CIF_CLK_CTRL_MI_SP |
>>> +              RKISP1_CIF_CLK_CTRL_MI_RAW0 | RKISP1_CIF_CLK_CTRL_MI_RAW1 |
>>> +              RKISP1_CIF_CLK_CTRL_MI_READ | RKISP1_CIF_CLK_CTRL_MI_RAWRD |
>>> +              RKISP1_CIF_CLK_CTRL_CP | RKISP1_CIF_CLK_CTRL_IE;
>>> +        rkisp1_write(rkisp1, val, RKISP1_CIF_VI_ISP_CLK_CTRL_V12);
>>> +    }
>>>   }
>>>     static void rkisp1_isp_start(struct rkisp1_device *rkisp1)
>>> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
>>> index 008584caaad0..408fa33bdc30 100644
>>> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
>>> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
>>> @@ -185,8 +185,8 @@ static void rkisp1_bls_config(struct rkisp1_params *params,
>>>     /* ISP LS correction interface function */
>>>   static void
>>> -rkisp1_lsc_matrix_config(struct rkisp1_params *params,
>>> -             const struct rkisp1_cif_isp_lsc_config *pconfig)
>>> +rkisp1_lsc_matrix_config_v10(struct rkisp1_params *params,
>>> +                 const struct rkisp1_cif_isp_lsc_config *pconfig)
>>>   {
>>>       unsigned int isp_lsc_status, sram_addr, isp_lsc_table_sel, i, j, data;
>>>   @@ -212,39 +212,111 @@ rkisp1_lsc_matrix_config(struct rkisp1_params *params,
>>>            * DWORDs (2nd value of last DWORD unused)
>>>            */
>>>           for (j = 0; j < RKISP1_CIF_ISP_LSC_SAMPLES_MAX - 1; j += 2) {
>>> -            data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->r_data_tbl[i][j],
>>> -                                 pconfig->r_data_tbl[i][j + 1]);
>>> +            data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->r_data_tbl[i][j],
>>> +                                 pconfig->r_data_tbl[i][j + 1]);
>>>               rkisp1_write(params->rkisp1, data,
>>>                        RKISP1_CIF_ISP_LSC_R_TABLE_DATA);
>>>   -            data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->gr_data_tbl[i][j],
>>> -                                 pconfig->gr_data_tbl[i][j + 1]);
>>> +            data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->gr_data_tbl[i][j],
>>> +                                 pconfig->gr_data_tbl[i][j + 1]);
>>>               rkisp1_write(params->rkisp1, data,
>>>                        RKISP1_CIF_ISP_LSC_GR_TABLE_DATA);
>>>   -            data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->gb_data_tbl[i][j],
>>> -                                 pconfig->gb_data_tbl[i][j + 1]);
>>> +            data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->gb_data_tbl[i][j],
>>> +                                 pconfig->gb_data_tbl[i][j + 1]);
>>>               rkisp1_write(params->rkisp1, data,
>>>                        RKISP1_CIF_ISP_LSC_GB_TABLE_DATA);
>>>   -            data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->b_data_tbl[i][j],
>>> -                                 pconfig->b_data_tbl[i][j + 1]);
>>> +            data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->b_data_tbl[i][j],
>>> +                                 pconfig->b_data_tbl[i][j + 1]);
>>>               rkisp1_write(params->rkisp1, data,
>>>                        RKISP1_CIF_ISP_LSC_B_TABLE_DATA);
>>>           }
>>> -        data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->r_data_tbl[i][j], 0);
>>> +        data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->r_data_tbl[i][j], 0);
>>>           rkisp1_write(params->rkisp1, data,
>>>                    RKISP1_CIF_ISP_LSC_R_TABLE_DATA);
>>>   -        data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->gr_data_tbl[i][j], 0);
>>> +        data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->gr_data_tbl[i][j], 0);
>>>           rkisp1_write(params->rkisp1, data,
>>>                    RKISP1_CIF_ISP_LSC_GR_TABLE_DATA);
>>>   -        data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->gb_data_tbl[i][j], 0);
>>> +        data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->gb_data_tbl[i][j], 0);
>>>           rkisp1_write(params->rkisp1, data,
>>>                    RKISP1_CIF_ISP_LSC_GB_TABLE_DATA);
>>>   -        data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->b_data_tbl[i][j], 0);
>>> +        data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(pconfig->b_data_tbl[i][j], 0);
>>> +        rkisp1_write(params->rkisp1, data,
>>> +                 RKISP1_CIF_ISP_LSC_B_TABLE_DATA);
>>
>> I understand this patch shouldn't change v10 behaviour, shouldn't this write be in a
>> separate patch?
>>
> 
> Helen, this code is not a new code in V10 but part of the function rkisp1_lsc_matrix_config_v12
> just that the diff is a bit confusing. The two function rkisp1_lsc_matrix_config_*
> are identical except of those macro operations.

You are right, please ignore my comment regarding it.

Thanks
Helen

> 
> Heiko, maybe you can separate the patch to two patches, one patch only do the renaming
> of adding _v10 to all the needed functions and macros, and then a diffrent patch
> that adds the _v12 versions? That will be easyer to review,
> 
> Thanks,
> Dafna
> 
>>> +    }
>>> +    isp_lsc_table_sel = (isp_lsc_status & RKISP1_CIF_ISP_LSC_ACTIVE_TABLE) ?
>>> +                RKISP1_CIF_ISP_LSC_TABLE_0 :
>>> +                RKISP1_CIF_ISP_LSC_TABLE_1;
>>> +    rkisp1_write(params->rkisp1, isp_lsc_table_sel,
>>> +             RKISP1_CIF_ISP_LSC_TABLE_SEL);
>>
>> Same here.
>>
>>> +}
>>> +
>>> +static void
>>> +rkisp1_lsc_matrix_config_v12(struct rkisp1_params *params,
>>> +                 const struct rkisp1_cif_isp_lsc_config *pconfig)
>>> +{
>>> +    unsigned int isp_lsc_status, sram_addr, isp_lsc_table_sel, i, j, data;
>>> +
>>> +    isp_lsc_status = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_LSC_STATUS);
>>> +
>>> +    /* RKISP1_CIF_ISP_LSC_TABLE_ADDRESS_153 = ( 17 * 18 ) >> 1 */
>>> +    sram_addr = (isp_lsc_status & RKISP1_CIF_ISP_LSC_ACTIVE_TABLE) ?
>>> +             RKISP1_CIF_ISP_LSC_TABLE_ADDRESS_0 :
>>> +             RKISP1_CIF_ISP_LSC_TABLE_ADDRESS_153;
>>> +    rkisp1_write(params->rkisp1, sram_addr, RKISP1_CIF_ISP_LSC_R_TABLE_ADDR);
>>> +    rkisp1_write(params->rkisp1, sram_addr, RKISP1_CIF_ISP_LSC_GR_TABLE_ADDR);
>>> +    rkisp1_write(params->rkisp1, sram_addr, RKISP1_CIF_ISP_LSC_GB_TABLE_ADDR);
>>> +    rkisp1_write(params->rkisp1, sram_addr, RKISP1_CIF_ISP_LSC_B_TABLE_ADDR);
>>> +
>>> +    /* program data tables (table size is 9 * 17 = 153) */
>>> +    for (i = 0; i < RKISP1_CIF_ISP_LSC_SAMPLES_MAX; i++) {
>>> +        /*
>>> +         * 17 sectors with 2 values in one DWORD = 9
>>> +         * DWORDs (2nd value of last DWORD unused)
>>> +         */
>>> +        for (j = 0; j < RKISP1_CIF_ISP_LSC_SAMPLES_MAX - 1; j += 2) {
>>> +            data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(
>>> +                    pconfig->r_data_tbl[i][j],
>>> +                    pconfig->r_data_tbl[i][j + 1]);
>>> +            rkisp1_write(params->rkisp1, data,
>>> +                     RKISP1_CIF_ISP_LSC_R_TABLE_DATA);
>>> +
>>> +            data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(
>>> +                    pconfig->gr_data_tbl[i][j],
>>> +                    pconfig->gr_data_tbl[i][j + 1]);
>>> +            rkisp1_write(params->rkisp1, data,
>>> +                     RKISP1_CIF_ISP_LSC_GR_TABLE_DATA);
>>> +
>>> +            data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(
>>> +                    pconfig->gb_data_tbl[i][j],
>>> +                    pconfig->gb_data_tbl[i][j + 1]);
>>> +            rkisp1_write(params->rkisp1, data,
>>> +                     RKISP1_CIF_ISP_LSC_GB_TABLE_DATA);
>>> +
>>> +            data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(
>>> +                    pconfig->b_data_tbl[i][j],
>>> +                    pconfig->b_data_tbl[i][j + 1]);
>>> +            rkisp1_write(params->rkisp1, data,
>>> +                     RKISP1_CIF_ISP_LSC_B_TABLE_DATA);
>>> +        }
>>> +
>>> +        data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(pconfig->r_data_tbl[i][j], 0);
>>> +        rkisp1_write(params->rkisp1, data,
>>> +                 RKISP1_CIF_ISP_LSC_R_TABLE_DATA);
>>> +
>>> +        data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(pconfig->gr_data_tbl[i][j], 0);
>>> +        rkisp1_write(params->rkisp1, data,
>>> +                 RKISP1_CIF_ISP_LSC_GR_TABLE_DATA);
>>> +
>>> +        data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(pconfig->gb_data_tbl[i][j], 0);
>>> +        rkisp1_write(params->rkisp1, data,
>>> +                 RKISP1_CIF_ISP_LSC_GB_TABLE_DATA);
>>> +
>>> +        data = RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(pconfig->b_data_tbl[i][j], 0);
>>>           rkisp1_write(params->rkisp1, data,
>>>                    RKISP1_CIF_ISP_LSC_B_TABLE_DATA);
>>>       }
>>> @@ -382,18 +454,37 @@ static void rkisp1_sdg_config(struct rkisp1_params *params,
>>>   }
>>>     /* ISP GAMMA correction interface function */
>>> -static void rkisp1_goc_config(struct rkisp1_params *params,
>>> -                  const struct rkisp1_cif_isp_goc_config *arg)
>>> +static void rkisp1_goc_config_v10(struct rkisp1_params *params,
>>> +                  const struct rkisp1_cif_isp_goc_config *arg)
>>>   {
>>>       unsigned int i;
>>>         rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_CTRL,
>>>                   RKISP1_CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA);
>>> -    rkisp1_write(params->rkisp1, arg->mode, RKISP1_CIF_ISP_GAMMA_OUT_MODE);
>>> +    rkisp1_write(params->rkisp1, arg->mode, RKISP1_CIF_ISP_GAMMA_OUT_MODE_V10);
>>>         for (i = 0; i < params->config->gamma_out_max_samples; i++)
>>>           rkisp1_write(params->rkisp1, arg->gamma_y[i],
>>> -                 RKISP1_CIF_ISP_GAMMA_OUT_Y_0 + i * 4);
>>> +                 RKISP1_CIF_ISP_GAMMA_OUT_Y_0_V10 + i * 4);
>>> +}
>>> +
>>> +static void rkisp1_goc_config_v12(struct rkisp1_params *params,
>>> +                  const struct rkisp1_cif_isp_goc_config *arg)
>>> +{
>>> +    int i;
>>
>> unsigned int
>>
>>> +    u32 value;
>>> +
>>> +    rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_CTRL,
>>> +                RKISP1_CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA);
>>> +    rkisp1_write(params->rkisp1, arg->mode, RKISP1_CIF_ISP_GAMMA_OUT_MODE_V12);
>>> +
>>> +    for (i = 0; i < params->config->gamma_out_max_samples / 2; i++) {
>>> +        value = RKISP1_CIF_ISP_GAMMA_VALUE_V12(
>>> +            arg->gamma_y[2 * i + 1],
>>> +            arg->gamma_y[2 * i]);
>>> +        rkisp1_write(params->rkisp1, value,
>>> +                 RKISP1_CIF_ISP_GAMMA_OUT_Y_0_V12 + i * 4);
>>> +    }
>>>   }
>>>     /* ISP Cross Talk */
>>> @@ -433,8 +524,8 @@ static void rkisp1_ctk_enable(struct rkisp1_params *params, bool en)
>>>   }
>>>     /* ISP White Balance Mode */
>>> -static void rkisp1_awb_meas_config(struct rkisp1_params *params,
>>> -                   const struct rkisp1_cif_isp_awb_meas_config *arg)
>>> +static void rkisp1_awb_meas_config_v10(struct rkisp1_params *params,
>>> +                       const struct rkisp1_cif_isp_awb_meas_config *arg)
>>>   {
>>>       u32 reg_val = 0;
>>>       /* based on the mode,configure the awb module */
>>> @@ -442,43 +533,82 @@ static void rkisp1_awb_meas_config(struct rkisp1_params *params,
>>>           /* Reference Cb and Cr */
>>>           rkisp1_write(params->rkisp1,
>>>                    RKISP1_CIF_ISP_AWB_REF_CR_SET(arg->awb_ref_cr) |
>>> -                 arg->awb_ref_cb, RKISP1_CIF_ISP_AWB_REF);
>>> +                 arg->awb_ref_cb, RKISP1_CIF_ISP_AWB_REF_V10);
>>>           /* Yc Threshold */
>>>           rkisp1_write(params->rkisp1,
>>>                    RKISP1_CIF_ISP_AWB_MAX_Y_SET(arg->max_y) |
>>>                    RKISP1_CIF_ISP_AWB_MIN_Y_SET(arg->min_y) |
>>>                    RKISP1_CIF_ISP_AWB_MAX_CS_SET(arg->max_csum) |
>>> -                 arg->min_c, RKISP1_CIF_ISP_AWB_THRESH);
>>> +                 arg->min_c, RKISP1_CIF_ISP_AWB_THRESH_V10);
>>>       }
>>>   -    reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP);
>>> +    reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP_V10);
>>>       if (arg->enable_ymax_cmp)
>>>           reg_val |= RKISP1_CIF_ISP_AWB_YMAX_CMP_EN;
>>>       else
>>>           reg_val &= ~RKISP1_CIF_ISP_AWB_YMAX_CMP_EN;
>>> -    rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP);
>>> +    rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP_V10);
>>>         /* window offset */
>>>       rkisp1_write(params->rkisp1,
>>> -             arg->awb_wnd.v_offs, RKISP1_CIF_ISP_AWB_WND_V_OFFS);
>>> +             arg->awb_wnd.v_offs, RKISP1_CIF_ISP_AWB_WND_V_OFFS_V10);
>>>       rkisp1_write(params->rkisp1,
>>> -             arg->awb_wnd.h_offs, RKISP1_CIF_ISP_AWB_WND_H_OFFS);
>>> +             arg->awb_wnd.h_offs, RKISP1_CIF_ISP_AWB_WND_H_OFFS_V10);
>>>       /* AWB window size */
>>>       rkisp1_write(params->rkisp1,
>>> -             arg->awb_wnd.v_size, RKISP1_CIF_ISP_AWB_WND_V_SIZE);
>>> +             arg->awb_wnd.v_size, RKISP1_CIF_ISP_AWB_WND_V_SIZE_V10);
>>>       rkisp1_write(params->rkisp1,
>>> -             arg->awb_wnd.h_size, RKISP1_CIF_ISP_AWB_WND_H_SIZE);
>>> +             arg->awb_wnd.h_size, RKISP1_CIF_ISP_AWB_WND_H_SIZE_V10);
>>>       /* Number of frames */
>>>       rkisp1_write(params->rkisp1,
>>> -             arg->frames, RKISP1_CIF_ISP_AWB_FRAMES);
>>> +             arg->frames, RKISP1_CIF_ISP_AWB_FRAMES_V10);
>>> +}
>>> +
>>> +static void rkisp1_awb_meas_config_v12(struct rkisp1_params *params,
>>> +                       const struct rkisp1_cif_isp_awb_meas_config *arg)
>>> +{
>>> +    u32 reg_val = 0;> +    /* based on the mode,configure the awb module */
>>> +    if (arg->awb_mode == RKISP1_CIF_ISP_AWB_MODE_YCBCR) {
>>> +        /* Reference Cb and Cr */
>>> +        rkisp1_write(params->rkisp1,
>>> +                 RKISP1_CIF_ISP_AWB_REF_CR_SET(arg->awb_ref_cr) |
>>> +                 arg->awb_ref_cb, RKISP1_CIF_ISP_AWB_REF_V12);
>>> +        /* Yc Threshold */
>>> +        rkisp1_write(params->rkisp1,
>>> +                 RKISP1_CIF_ISP_AWB_MAX_Y_SET(arg->max_y) |
>>> +                 RKISP1_CIF_ISP_AWB_MIN_Y_SET(arg->min_y) |
>>> +                 RKISP1_CIF_ISP_AWB_MAX_CS_SET(arg->max_csum) |
>>> +                 arg->min_c, RKISP1_CIF_ISP_AWB_THRESH_V12);
>>> +    }
>>> +
>>> +    reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP_V12);
>>> +    if (arg->enable_ymax_cmp)
>>> +        reg_val |= RKISP1_CIF_ISP_AWB_YMAX_CMP_EN;
>>> +    else
>>> +        reg_val &= ~RKISP1_CIF_ISP_AWB_YMAX_CMP_EN;
>>> +    reg_val &= ~RKISP1_CIF_ISP_AWB_SET_FRAMES_MASK_V12;
>>> +    reg_val |= RKISP1_CIF_ISP_AWB_SET_FRAMES_V12(arg->frames);
>>> +    rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP_V12);
>>> +
>>> +    /* window offset */
>>> +    rkisp1_write(params->rkisp1,
>>> +             arg->awb_wnd.v_offs << 16 |
>>> +             arg->awb_wnd.h_offs,
>>> +             RKISP1_CIF_ISP_AWB_OFFS_V12);
>>> +    /* AWB window size */
>>> +    rkisp1_write(params->rkisp1,
>>> +             arg->awb_wnd.v_size << 16 |
>>> +             arg->awb_wnd.h_size,
>>> +             RKISP1_CIF_ISP_AWB_SIZE_V12);
>>>   }
>>>     static void
>>> -rkisp1_awb_meas_enable(struct rkisp1_params *params,
>>> -               const struct rkisp1_cif_isp_awb_meas_config *arg,
>>> -               bool en)
>>> +rkisp1_awb_meas_enable_v10(struct rkisp1_params *params,
>>> +               const struct rkisp1_cif_isp_awb_meas_config *arg,
>>> +               bool en)
>>>   {
>>> -    u32 reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP);
>>> +    u32 reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP_V10);
>>>         /* switch off */
>>>       reg_val &= RKISP1_CIF_ISP_AWB_MODE_MASK_NONE;
>>> @@ -489,34 +619,76 @@ rkisp1_awb_meas_enable(struct rkisp1_params *params,
>>>           else
>>>               reg_val |= RKISP1_CIF_ISP_AWB_MODE_YCBCR_EN;
>>>   -        rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP);
>>> +        rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP_V10);
>>>             /* Measurements require AWB block be active. */
>>>           rkisp1_param_set_bits(params, RKISP1_CIF_ISP_CTRL,
>>>                         RKISP1_CIF_ISP_CTRL_ISP_AWB_ENA);
>>>       } else {
>>>           rkisp1_write(params->rkisp1,
>>> -                 reg_val, RKISP1_CIF_ISP_AWB_PROP);
>>> +                 reg_val, RKISP1_CIF_ISP_AWB_PROP_V10);
>>>           rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_CTRL,
>>>                       RKISP1_CIF_ISP_CTRL_ISP_AWB_ENA);
>>>       }
>>>   }
>>>     static void
>>> -rkisp1_awb_gain_config(struct rkisp1_params *params,
>>> -               const struct rkisp1_cif_isp_awb_gain_config *arg)
>>> +rkisp1_awb_meas_enable_v12(struct rkisp1_params *params,
>>> +               const struct rkisp1_cif_isp_awb_meas_config *arg,
>>> +               bool en)
>>> +{
>>> +    u32 reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP_V12);
>>> +
>>> +    /* switch off */
>>> +    reg_val &= RKISP1_CIF_ISP_AWB_MODE_MASK_NONE;
>>> +
>>> +    if (en) {
>>> +        if (arg->awb_mode == RKISP1_CIF_ISP_AWB_MODE_RGB)
>>> +            reg_val |= RKISP1_CIF_ISP_AWB_MODE_RGB_EN;
>>> +        else
>>> +            reg_val |= RKISP1_CIF_ISP_AWB_MODE_YCBCR_EN;
>>> +
>>> +        rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP_V12);
>>> +
>>> +        /* Measurements require AWB block be active. */
>>> +        rkisp1_param_set_bits(params, RKISP1_CIF_ISP_CTRL,
>>> +                      RKISP1_CIF_ISP_CTRL_ISP_AWB_ENA);
>>> +    } else {
>>> +        rkisp1_write(params->rkisp1,
>>> +                 reg_val, RKISP1_CIF_ISP_AWB_PROP_V12);
>>> +        rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_CTRL,
>>> +                    RKISP1_CIF_ISP_CTRL_ISP_AWB_ENA);
>>> +    }
>>> +}
>>> +
>>> +static void
>>> +rkisp1_awb_gain_config_v10(struct rkisp1_params *params,
>>> +               const struct rkisp1_cif_isp_awb_gain_config *arg)
>>> +{
>>> +    rkisp1_write(params->rkisp1,
>>> +             RKISP1_CIF_ISP_AWB_GAIN_R_SET(arg->gain_green_r) |
>>> +             arg->gain_green_b, RKISP1_CIF_ISP_AWB_GAIN_G_V10);
>>> +
>>> +    rkisp1_write(params->rkisp1,
>>> +             RKISP1_CIF_ISP_AWB_GAIN_R_SET(arg->gain_red) |
>>> +             arg->gain_blue, RKISP1_CIF_ISP_AWB_GAIN_RB_V10);
>>> +}
>>> +
>>> +static void
>>> +rkisp1_awb_gain_config_v12(struct rkisp1_params *params,
>>> +               const struct rkisp1_cif_isp_awb_gain_config *arg)
>>>   {
>>>       rkisp1_write(params->rkisp1,
>>>                RKISP1_CIF_ISP_AWB_GAIN_R_SET(arg->gain_green_r) |
>>> -             arg->gain_green_b, RKISP1_CIF_ISP_AWB_GAIN_G);
>>> +             arg->gain_green_b, RKISP1_CIF_ISP_AWB_GAIN_G_V12);
>>>         rkisp1_write(params->rkisp1,
>>>                RKISP1_CIF_ISP_AWB_GAIN_R_SET(arg->gain_red) |
>>> -             arg->gain_blue, RKISP1_CIF_ISP_AWB_GAIN_RB);
>>> +             arg->gain_blue, RKISP1_CIF_ISP_AWB_GAIN_RB_V12);
>>>   }
>>>   -static void rkisp1_aec_config(struct rkisp1_params *params,
>>> -                  const struct rkisp1_cif_isp_aec_config *arg)
>>> +static void rkisp1_aec_config_v10(struct rkisp1_params *params,
>>> +                  const struct rkisp1_cif_isp_aec_config *arg)
>>>   {
>>>       unsigned int block_hsize, block_vsize;
>>>       u32 exp_ctrl;
>>> @@ -531,21 +703,55 @@ static void rkisp1_aec_config(struct rkisp1_params *params,
>>>       rkisp1_write(params->rkisp1, exp_ctrl, RKISP1_CIF_ISP_EXP_CTRL);
>>>         rkisp1_write(params->rkisp1,
>>> -             arg->meas_window.h_offs, RKISP1_CIF_ISP_EXP_H_OFFSET);
>>> +             arg->meas_window.h_offs, RKISP1_CIF_ISP_EXP_H_OFFSET_V10);
>>>       rkisp1_write(params->rkisp1,
>>> -             arg->meas_window.v_offs, RKISP1_CIF_ISP_EXP_V_OFFSET);
>>> +             arg->meas_window.v_offs, RKISP1_CIF_ISP_EXP_V_OFFSET_V10);
>>>         block_hsize = arg->meas_window.h_size /
>>> -              RKISP1_CIF_ISP_EXP_COLUMN_NUM - 1;
>>> +              RKISP1_CIF_ISP_EXP_COLUMN_NUM_V10 - 1;
>>>       block_vsize = arg->meas_window.v_size /
>>> -              RKISP1_CIF_ISP_EXP_ROW_NUM - 1;
>>> +              RKISP1_CIF_ISP_EXP_ROW_NUM_V10 - 1;
>>> +
>>> +    rkisp1_write(params->rkisp1,
>>> +             RKISP1_CIF_ISP_EXP_H_SIZE_SET_V10(block_hsize),
>>> +             RKISP1_CIF_ISP_EXP_H_SIZE_V10);
>>> +    rkisp1_write(params->rkisp1,
>>> +             RKISP1_CIF_ISP_EXP_V_SIZE_SET_V10(block_vsize),
>>> +             RKISP1_CIF_ISP_EXP_V_SIZE_V10);
>>> +}
>>> +
>>> +static void rkisp1_aec_config_v12(struct rkisp1_params *params,
>>> +                   const struct rkisp1_cif_isp_aec_config *arg)
>>> +{
>>> +    u32 exp_ctrl;
>>> +    u32 block_hsize, block_vsize;
>>> +    u32 wnd_num_idx = 1;
>>> +    const u32 ae_wnd_num[] = {
>>> +        5, 9, 15, 15
>>> +    };
>>
>> I think it would be better to declare in the same line.
>>
>>> +
>>> +    /* avoid to override the old enable value */
>>> +    exp_ctrl = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_EXP_CTRL);
>>> +    exp_ctrl &= RKISP1_CIF_ISP_EXP_ENA;
>>> +    if (arg->autostop)
>>> +        exp_ctrl |= RKISP1_CIF_ISP_EXP_CTRL_AUTOSTOP;
>>> +    if (arg->mode == RKISP1_CIF_ISP_EXP_MEASURING_MODE_1)
>>> +        exp_ctrl |= RKISP1_CIF_ISP_EXP_CTRL_MEASMODE_1;
>>> +    exp_ctrl |= RKISP1_CIF_ISP_EXP_CTRL_WNDNUM_SET_V12(wnd_num_idx);
>>> +    rkisp1_write(params->rkisp1, exp_ctrl, RKISP1_CIF_ISP_EXP_CTRL);
>>>         rkisp1_write(params->rkisp1,
>>> -             RKISP1_CIF_ISP_EXP_H_SIZE_SET(block_hsize),
>>> -             RKISP1_CIF_ISP_EXP_H_SIZE);
>>> +             RKISP1_CIF_ISP_EXP_V_OFFSET_SET_V12(arg->meas_window.v_offs) |
>>> +             RKISP1_CIF_ISP_EXP_H_OFFSET_SET_V12(arg->meas_window.h_offs),
>>> +             RKISP1_CIF_ISP_EXP_OFFS_V12);
>>> +
>>> +    block_hsize = arg->meas_window.h_size / ae_wnd_num[wnd_num_idx] - 1;
>>> +    block_vsize = arg->meas_window.v_size / ae_wnd_num[wnd_num_idx] - 1;
>>> +
>>>       rkisp1_write(params->rkisp1,
>>> -             RKISP1_CIF_ISP_EXP_V_SIZE_SET(block_vsize),
>>> -             RKISP1_CIF_ISP_EXP_V_SIZE);
>>> +             RKISP1_CIF_ISP_EXP_V_SIZE_SET_V12(block_vsize) |
>>> +             RKISP1_CIF_ISP_EXP_H_SIZE_SET_V12(block_hsize),
>>> +             RKISP1_CIF_ISP_EXP_SIZE_V12);
>>>   }
>>>     static void rkisp1_cproc_config(struct rkisp1_params *params,
>>> @@ -578,72 +784,154 @@ static void rkisp1_cproc_config(struct rkisp1_params *params,
>>>       }
>>>   }
>>>   -static void rkisp1_hst_config(struct rkisp1_params *params,
>>> -                  const struct rkisp1_cif_isp_hst_config *arg)
>>> +static void rkisp1_hst_config_v10(struct rkisp1_params *params,
>>> +                  const struct rkisp1_cif_isp_hst_config *arg)
>>>   {
>>>       unsigned int block_hsize, block_vsize;
>>>       static const u32 hist_weight_regs[] = {
>>> -        RKISP1_CIF_ISP_HIST_WEIGHT_00TO30,
>>> -        RKISP1_CIF_ISP_HIST_WEIGHT_40TO21,
>>> -        RKISP1_CIF_ISP_HIST_WEIGHT_31TO12,
>>> -        RKISP1_CIF_ISP_HIST_WEIGHT_22TO03,
>>> -        RKISP1_CIF_ISP_HIST_WEIGHT_13TO43,
>>> -        RKISP1_CIF_ISP_HIST_WEIGHT_04TO34,
>>> -        RKISP1_CIF_ISP_HIST_WEIGHT_44,
>>> +        RKISP1_CIF_ISP_HIST_WEIGHT_00TO30_V10,
>>> +        RKISP1_CIF_ISP_HIST_WEIGHT_40TO21_V10,
>>> +        RKISP1_CIF_ISP_HIST_WEIGHT_31TO12_V10,
>>> +        RKISP1_CIF_ISP_HIST_WEIGHT_22TO03_V10,
>>> +        RKISP1_CIF_ISP_HIST_WEIGHT_13TO43_V10,
>>> +        RKISP1_CIF_ISP_HIST_WEIGHT_04TO34_V10,
>>> +        RKISP1_CIF_ISP_HIST_WEIGHT_44_V10,
>>>       };
>>>       const u8 *weight;
>>>       unsigned int i;
>>>       u32 hist_prop;
>>>         /* avoid to override the old enable value */
>>> -    hist_prop = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_HIST_PROP);
>>> -    hist_prop &= RKISP1_CIF_ISP_HIST_PROP_MODE_MASK;
>>> -    hist_prop |= RKISP1_CIF_ISP_HIST_PREDIV_SET(arg->histogram_predivider);
>>> -    rkisp1_write(params->rkisp1, hist_prop, RKISP1_CIF_ISP_HIST_PROP);
>>> +    hist_prop = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_HIST_PROP_V10);
>>> +    hist_prop &= RKISP1_CIF_ISP_HIST_PROP_MODE_MASK_V10;
>>> +    hist_prop |= RKISP1_CIF_ISP_HIST_PREDIV_SET_V10(arg->histogram_predivider);
>>> +    rkisp1_write(params->rkisp1, hist_prop, RKISP1_CIF_ISP_HIST_PROP_V10);
>>>       rkisp1_write(params->rkisp1,
>>>                arg->meas_window.h_offs,
>>> -             RKISP1_CIF_ISP_HIST_H_OFFS);
>>> +             RKISP1_CIF_ISP_HIST_H_OFFS_V10);
>>>       rkisp1_write(params->rkisp1,
>>>                arg->meas_window.v_offs,
>>> -             RKISP1_CIF_ISP_HIST_V_OFFS);
>>> +             RKISP1_CIF_ISP_HIST_V_OFFS_V10);
>>>         block_hsize = arg->meas_window.h_size /
>>> -              RKISP1_CIF_ISP_HIST_COLUMN_NUM - 1;
>>> -    block_vsize = arg->meas_window.v_size / RKISP1_CIF_ISP_HIST_ROW_NUM - 1;
>>> +              RKISP1_CIF_ISP_HIST_COLUMN_NUM_V10 - 1;
>>> +    block_vsize = arg->meas_window.v_size / RKISP1_CIF_ISP_HIST_ROW_NUM_V10 - 1;
>>>   -    rkisp1_write(params->rkisp1, block_hsize, RKISP1_CIF_ISP_HIST_H_SIZE);
>>> -    rkisp1_write(params->rkisp1, block_vsize, RKISP1_CIF_ISP_HIST_V_SIZE);
>>> +    rkisp1_write(params->rkisp1, block_hsize, RKISP1_CIF_ISP_HIST_H_SIZE_V10);
>>> +    rkisp1_write(params->rkisp1, block_vsize, RKISP1_CIF_ISP_HIST_V_SIZE_V10);
>>>         weight = arg->hist_weight;
>>>       for (i = 0; i < ARRAY_SIZE(hist_weight_regs); ++i, weight += 4)
>>>           rkisp1_write(params->rkisp1,
>>> -                 RKISP1_CIF_ISP_HIST_WEIGHT_SET(weight[0],
>>> +                 RKISP1_CIF_ISP_HIST_WEIGHT_SET_V10(weight[0],
>>>                                   weight[1],
>>>                                   weight[2],
>>>                                   weight[3]),
>>>                    hist_weight_regs[i]);
>>>   }
>>>   +static void rkisp1_hst_config_v12(struct rkisp1_params *params,
>>> +                  const struct rkisp1_cif_isp_hst_config *arg)
>>> +{
>>> +    u32 i, j;
>>
>> unsigned int
>>
>>> +    u32 value;
>>> +    u32 hist_ctrl;
>>> +    u32 block_hsize, block_vsize;
>>> +    u32 wnd_num_idx, hist_weight_num;
>>
>> Maybe organize those in the same line.
>>
>>> +    u8 weight15x15[RKISP1_CIF_ISP_HIST_WEIGHT_REG_SIZE_V12];
>>> +    const u32 hist_wnd_num[] = {
>>> +        5, 9, 15, 15
>>> +    };
>>> +
>>> +    /* now we just support 9x9 window */
>>> +    wnd_num_idx = 1;
>>> +    memset(weight15x15, 0x00, sizeof(weight15x15));
>>> +    /* avoid to override the old enable value */
>>> +    hist_ctrl = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_HIST_CTRL_V12);
>>> +    hist_ctrl &= RKISP1_CIF_ISP_HIST_CTRL_MODE_MASK_V12 |
>>> +             RKISP1_CIF_ISP_HIST_CTRL_EN_MASK_V12;
>>> +    hist_ctrl = hist_ctrl |
>>> +            RKISP1_CIF_ISP_HIST_CTRL_INTRSEL_SET_V12(1) |
>>> +            RKISP1_CIF_ISP_HIST_CTRL_DATASEL_SET_V12(0) |
>>> +            RKISP1_CIF_ISP_HIST_CTRL_WATERLINE_SET_V12(0) |
>>> +            RKISP1_CIF_ISP_HIST_CTRL_AUTOSTOP_SET_V12(0) |
>>> +            RKISP1_CIF_ISP_HIST_CTRL_WNDNUM_SET_V12(1) |
>>> +            RKISP1_CIF_ISP_HIST_CTRL_STEPSIZE_SET_V12(arg->histogram_predivider);
>>> +    rkisp1_write(params->rkisp1, hist_ctrl, RKISP1_CIF_ISP_HIST_CTRL_V12);
>>> +
>>> +    rkisp1_write(params->rkisp1,
>>> +             RKISP1_CIF_ISP_HIST_OFFS_SET_V12(arg->meas_window.h_offs,
>>> +                              arg->meas_window.v_offs),
>>> +             RKISP1_CIF_ISP_HIST_OFFS_V12);
>>> +
>>> +    block_hsize = arg->meas_window.h_size / hist_wnd_num[wnd_num_idx] - 1;
>>> +    block_vsize = arg->meas_window.v_size / hist_wnd_num[wnd_num_idx] - 1;
>>> +    rkisp1_write(params->rkisp1,
>>> +             RKISP1_CIF_ISP_HIST_SIZE_SET_V12(block_hsize, block_vsize),
>>> +             RKISP1_CIF_ISP_HIST_SIZE_V12);
>>> +
>>> +    for (i = 0; i < hist_wnd_num[wnd_num_idx]; i++) {
>>> +        for (j = 0; j < hist_wnd_num[wnd_num_idx]; j++) {
>>> +            weight15x15[i * RKISP1_CIF_ISP_HIST_ROW_NUM_V12 + j] =
>>> +                arg->hist_weight[i * hist_wnd_num[wnd_num_idx] + j];
>>> +        }
>>> +    }
>>> +
>>> +    hist_weight_num = RKISP1_CIF_ISP_HIST_WEIGHT_REG_SIZE_V12;
>>> +    for (i = 0; i < (hist_weight_num / 4); i++) {
>>> +        value = RKISP1_CIF_ISP_HIST_WEIGHT_SET_V12(
>>> +                 weight15x15[4 * i + 0],
>>> +                 weight15x15[4 * i + 1],
>>> +                 weight15x15[4 * i + 2],
>>> +                 weight15x15[4 * i + 3]);
>>> +        rkisp1_write(params->rkisp1, value,
>>> +                 RKISP1_CIF_ISP_HIST_WEIGHT_V12 + 4 * i);
>>> +    }
>>> +    value = RKISP1_CIF_ISP_HIST_WEIGHT_SET_V12(weight15x15[4 * i + 0], 0, 0, 0);
>>> +    rkisp1_write(params->rkisp1, value,
>>> +                 RKISP1_CIF_ISP_HIST_WEIGHT_V12 + 4 * i);
>>> +}
>>> +
>>>   static void
>>> -rkisp1_hst_enable(struct rkisp1_params *params,
>>> -          const struct rkisp1_cif_isp_hst_config *arg, bool en)
>>> +rkisp1_hst_enable_v10(struct rkisp1_params *params,
>>> +              const struct rkisp1_cif_isp_hst_config *arg, bool en)
>>>   {
>>>       if (en)    {
>>>           u32 hist_prop = rkisp1_read(params->rkisp1,
>>> -                        RKISP1_CIF_ISP_HIST_PROP);
>>> +                        RKISP1_CIF_ISP_HIST_PROP_V10);
>>>   -        hist_prop &= ~RKISP1_CIF_ISP_HIST_PROP_MODE_MASK;
>>> +        hist_prop &= ~RKISP1_CIF_ISP_HIST_PROP_MODE_MASK_V10;
>>>           hist_prop |= arg->mode;
>>> -        rkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_PROP,
>>> +        rkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_PROP_V10,
>>>                         hist_prop);
>>>       } else {
>>> -        rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_HIST_PROP,
>>> -                    RKISP1_CIF_ISP_HIST_PROP_MODE_MASK);
>>> +        rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_HIST_PROP_V10,
>>> +                    RKISP1_CIF_ISP_HIST_PROP_MODE_MASK_V10);
>>> +    }
>>> +}
>>> +
>>> +static void
>>> +rkisp1_hst_enable_v12(struct rkisp1_params *params,
>>> +              const struct rkisp1_cif_isp_hst_config *arg, bool en)
>>> +{
>>> +    if (en) {
>>> +        u32 hist_ctrl = rkisp1_read(params->rkisp1,
>>> +                        RKISP1_CIF_ISP_HIST_CTRL_V12);
>>> +
>>> +        hist_ctrl &= ~RKISP1_CIF_ISP_HIST_CTRL_MODE_MASK_V12;
>>> +        hist_ctrl |= RKISP1_CIF_ISP_HIST_CTRL_MODE_SET_V12(arg->mode);
>>> +        hist_ctrl |= RKISP1_CIF_ISP_HIST_CTRL_EN_SET_V12(1);
>>> +        rkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_CTRL_V12,
>>> +                      hist_ctrl);
>>> +    } else {
>>> +        rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_HIST_CTRL_V12,
>>> +                    RKISP1_CIF_ISP_HIST_CTRL_MODE_MASK_V12 |
>>> +                    RKISP1_CIF_ISP_HIST_CTRL_EN_MASK_V12);
>>>       }
>>>   }
>>>   -static void rkisp1_afm_config(struct rkisp1_params *params,
>>> -                  const struct rkisp1_cif_isp_afc_config *arg)
>>> +static void rkisp1_afm_config_v10(struct rkisp1_params *params,
>>> +                  const struct rkisp1_cif_isp_afc_config *arg)
>>>   {
>>>       size_t num_of_win = min_t(size_t, ARRAY_SIZE(arg->afm_win),
>>>                     arg->num_afm_win);
>>> @@ -673,6 +961,45 @@ static void rkisp1_afm_config(struct rkisp1_params *params,
>>>       rkisp1_write(params->rkisp1, afm_ctrl, RKISP1_CIF_ISP_AFM_CTRL);
>>>   }
>>>   +static void rkisp1_afm_config_v12(struct rkisp1_params *params,
>>> +                  const struct rkisp1_cif_isp_afc_config *arg)
>>> +{
>>> +    size_t num_of_win = min_t(size_t, ARRAY_SIZE(arg->afm_win),
>>> +                  arg->num_afm_win);
>>> +    u32 afm_ctrl = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AFM_CTRL);
>>> +    u32 lum_var_shift, afm_var_shift;
>>> +    unsigned int i;
>>> +
>>> +    /* Switch off to configure. */
>>> +    rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_AFM_CTRL,
>>> +                RKISP1_CIF_ISP_AFM_ENA);
>>> +
>>> +    for (i = 0; i < num_of_win; i++) {
>>> +        rkisp1_write(params->rkisp1,
>>> +                 RKISP1_CIF_ISP_AFM_WINDOW_X(arg->afm_win[i].h_offs) |
>>> +                 RKISP1_CIF_ISP_AFM_WINDOW_Y(arg->afm_win[i].v_offs),
>>> +                 RKISP1_CIF_ISP_AFM_LT_A + i * 8);
>>> +        rkisp1_write(params->rkisp1,
>>> +                 RKISP1_CIF_ISP_AFM_WINDOW_X(arg->afm_win[i].h_size +
>>> +                             arg->afm_win[i].h_offs) |
>>> +                 RKISP1_CIF_ISP_AFM_WINDOW_Y(arg->afm_win[i].v_size +
>>> +                             arg->afm_win[i].v_offs),
>>> +                 RKISP1_CIF_ISP_AFM_RB_A + i * 8);
>>> +    }
>>> +    rkisp1_write(params->rkisp1, arg->thres, RKISP1_CIF_ISP_AFM_THRES);
>>> +
>>> +    lum_var_shift = RKISP1_CIF_ISP_AFM_GET_LUM_SHIFT_a_V12(arg->var_shift);
>>> +    afm_var_shift = RKISP1_CIF_ISP_AFM_GET_AFM_SHIFT_a_V12(arg->var_shift);
>>> +    rkisp1_write(params->rkisp1,
>>> +             RKISP1_CIF_ISP_AFM_SET_SHIFT_a_V12(lum_var_shift, afm_var_shift) |
>>> +             RKISP1_CIF_ISP_AFM_SET_SHIFT_b_V12(lum_var_shift, afm_var_shift) |
>>> +             RKISP1_CIF_ISP_AFM_SET_SHIFT_c_V12(lum_var_shift, afm_var_shift),
>>> +             RKISP1_CIF_ISP_AFM_VAR_SHIFT);
>>> +
>>> +    /* restore afm status */
>>> +    rkisp1_write(params->rkisp1, afm_ctrl, RKISP1_CIF_ISP_AFM_CTRL);
>>> +}
>>> +
>>>   static void rkisp1_ie_config(struct rkisp1_params *params,
>>>                    const struct rkisp1_cif_isp_ie_config *arg)
>>>   {
>>> @@ -1286,8 +1613,8 @@ static void rkisp1_params_config_parameter(struct rkisp1_params *params)
>>>         memset(hst.hist_weight, 0x01, sizeof(hst.hist_weight));
>>>       params->ops->hst_config(params, &hst);
>>> -    rkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_PROP,
>>> -                  ~RKISP1_CIF_ISP_HIST_PROP_MODE_MASK |
>>> +    rkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_PROP_V10,
>>> +                  ~RKISP1_CIF_ISP_HIST_PROP_MODE_MASK_V10 |
>>>                     rkisp1_hst_params_default_config.mode);
>>>         /* set the  range */
>>> @@ -1346,22 +1673,38 @@ void rkisp1_params_disable(struct rkisp1_params *params)
>>>                   RKISP1_CIF_ISP_DPF_MODE_EN);
>>>   }
>>>   -static struct rkisp1_params_ops rkisp1_params_ops = {
>>> -    .lsc_matrix_config = rkisp1_lsc_matrix_config,
>>> -    .goc_config = rkisp1_goc_config,
>>> -    .awb_meas_config = rkisp1_awb_meas_config,
>>> -    .awb_meas_enable = rkisp1_awb_meas_enable,
>>> -    .awb_gain_config = rkisp1_awb_gain_config,
>>> -    .aec_config = rkisp1_aec_config,
>>> -    .hst_config = rkisp1_hst_config,
>>> -    .hst_enable = rkisp1_hst_enable,
>>> -    .afm_config = rkisp1_afm_config,
>>> +static struct rkisp1_params_ops rkisp1_v10_params_ops = {
>>> +    .lsc_matrix_config = rkisp1_lsc_matrix_config_v10,
>>> +    .goc_config = rkisp1_goc_config_v10,
>>> +    .awb_meas_config = rkisp1_awb_meas_config_v10,
>>> +    .awb_meas_enable = rkisp1_awb_meas_enable_v10,
>>> +    .awb_gain_config = rkisp1_awb_gain_config_v10,
>>> +    .aec_config = rkisp1_aec_config_v10,
>>> +    .hst_config = rkisp1_hst_config_v10,
>>> +    .hst_enable = rkisp1_hst_enable_v10,
>>> +    .afm_config = rkisp1_afm_config_v10,
>>>   };
>>>   -static struct rkisp1_params_config rkisp1_params_config = {
>>> +static struct rkisp1_params_config rkisp1_v10_params_config = {
>>>       .gamma_out_max_samples = 17,
>>>   };
>>>   +static struct rkisp1_params_ops rkisp1_v12_params_ops = {
>>> +    .lsc_matrix_config = rkisp1_lsc_matrix_config_v12,
>>> +    .goc_config = rkisp1_goc_config_v12,
>>> +    .awb_meas_config = rkisp1_awb_meas_config_v12,
>>> +    .awb_meas_enable = rkisp1_awb_meas_enable_v12,
>>> +    .awb_gain_config = rkisp1_awb_gain_config_v12,
>>> +    .aec_config = rkisp1_aec_config_v12,
>>> +    .hst_config = rkisp1_hst_config_v12,
>>> +    .hst_enable = rkisp1_hst_enable_v12,
>>> +    .afm_config = rkisp1_afm_config_v12,
>>> +};
>>> +
>>> +static struct rkisp1_params_config rkisp1_v12_params_config = {
>>> +    .gamma_out_max_samples = 34,
>>> +};
>>> +
>>>   static int rkisp1_params_enum_fmt_meta_out(struct file *file, void *priv,
>>>                          struct v4l2_fmtdesc *f)
>>>   {
>>> @@ -1528,8 +1871,14 @@ static void rkisp1_init_params(struct rkisp1_params *params)
>>>           V4L2_META_FMT_RK_ISP1_PARAMS;
>>>       params->vdev_fmt.fmt.meta.buffersize =
>>>           sizeof(struct rkisp1_params_cfg);
>>> -    params->ops = &rkisp1_params_ops;
>>> -    params->config = &rkisp1_params_config;
>>> +
>>> +    if (params->rkisp1->isp_ver == RKISP1_V12) {
>>> +        params->ops = &rkisp1_v12_params_ops;
>>> +        params->config = &rkisp1_v12_params_config;
>>> +    } else {
>>> +        params->ops = &rkisp1_v10_params_ops;
>>> +        params->config = &rkisp1_v10_params_config;
>>> +    }
>>>   }
>>>     int rkisp1_params_register(struct rkisp1_device *rkisp1)
>>> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
>>> index 8a8d960a679c..388adee3beff 100644
>>> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
>>> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
>>> @@ -212,6 +212,35 @@
>>>     /* CCL */
>>>   #define RKISP1_CIF_CCL_CIF_CLK_DIS            BIT(2)
>>> +/* VI_ISP_CLK_CTRL */
>>> +#define RKISP1_CIF_CLK_CTRL_ISP_RAW            BIT(0)
>>> +#define RKISP1_CIF_CLK_CTRL_ISP_RGB            BIT(1)
>>> +#define RKISP1_CIF_CLK_CTRL_ISP_YUV            BIT(2)
>>> +#define RKISP1_CIF_CLK_CTRL_ISP_3A            BIT(3)
>>> +#define RKISP1_CIF_CLK_CTRL_MIPI_RAW            BIT(4)
>>> +#define RKISP1_CIF_CLK_CTRL_ISP_IE            BIT(5)
>>> +#define RKISP1_CIF_CLK_CTRL_RSZ_RAM            BIT(6)
>>> +#define RKISP1_CIF_CLK_CTRL_JPEG_RAM            BIT(7)
>>> +#define RKISP1_CIF_CLK_CTRL_ACLK_ISP            BIT(8)
>>> +#define RKISP1_CIF_CLK_CTRL_MI_IDC            BIT(9)
>>> +#define RKISP1_CIF_CLK_CTRL_MI_MP            BIT(10)
>>> +#define RKISP1_CIF_CLK_CTRL_MI_JPEG            BIT(11)
>>> +#define RKISP1_CIF_CLK_CTRL_MI_DP            BIT(12)
>>> +#define RKISP1_CIF_CLK_CTRL_MI_Y12            BIT(13)
>>> +#define RKISP1_CIF_CLK_CTRL_MI_SP            BIT(14)
>>> +#define RKISP1_CIF_CLK_CTRL_MI_RAW0            BIT(15)
>>> +#define RKISP1_CIF_CLK_CTRL_MI_RAW1            BIT(16)
>>> +#define RKISP1_CIF_CLK_CTRL_MI_READ            BIT(17)
>>> +#define RKISP1_CIF_CLK_CTRL_MI_RAWRD            BIT(18)
>>> +#define RKISP1_CIF_CLK_CTRL_CP                BIT(19)
>>> +#define RKISP1_CIF_CLK_CTRL_IE                BIT(20)
>>> +#define RKISP1_CIF_CLK_CTRL_SI                BIT(21)
>>> +#define RKISP1_CIF_CLK_CTRL_RSZM            BIT(22)
>>> +#define RKISP1_CIF_CLK_CTRL_DPMUX            BIT(23)
>>> +#define RKISP1_CIF_CLK_CTRL_JPEG            BIT(24)
>>> +#define RKISP1_CIF_CLK_CTRL_RSZS            BIT(25)
>>> +#define RKISP1_CIF_CLK_CTRL_MIPI            BIT(26)
>>> +#define RKISP1_CIF_CLK_CTRL_MARVINMI            BIT(27)
>>>   /* ICCL */
>>>   #define RKISP1_CIF_ICCL_ISP_CLK                BIT(0)
>>>   #define RKISP1_CIF_ICCL_CP_CLK                BIT(1)
>>> @@ -346,25 +375,57 @@
>>>   #define RKISP1_CIF_SUPER_IMP_CTRL_TRANSP_DIS        BIT(2)
>>>     /* ISP HISTOGRAM CALCULATION : ISP_HIST_PROP */
>>> -#define RKISP1_CIF_ISP_HIST_PROP_MODE_DIS        (0 << 0)
>>> -#define RKISP1_CIF_ISP_HIST_PROP_MODE_RGB        BIT(0)
>>> -#define RKISP1_CIF_ISP_HIST_PROP_MODE_RED        (2 << 0)
>>> -#define RKISP1_CIF_ISP_HIST_PROP_MODE_GREEN        (3 << 0)
>>> -#define RKISP1_CIF_ISP_HIST_PROP_MODE_BLUE        (4 << 0)
>>> -#define RKISP1_CIF_ISP_HIST_PROP_MODE_LUM        (5 << 0)
>>> -#define RKISP1_CIF_ISP_HIST_PROP_MODE_MASK        0x7
>>> -#define RKISP1_CIF_ISP_HIST_PREDIV_SET(x)        (((x) & 0x7F) << 3)
>>> -#define RKISP1_CIF_ISP_HIST_WEIGHT_SET(v0, v1, v2, v3)    \
>>> +#define RKISP1_CIF_ISP_HIST_PROP_MODE_DIS_V10        (0 << 0)
>>> +#define RKISP1_CIF_ISP_HIST_PROP_MODE_RGB_V10        BIT(0)
>>> +#define RKISP1_CIF_ISP_HIST_PROP_MODE_RED_V10        (2 << 0)
>>> +#define RKISP1_CIF_ISP_HIST_PROP_MODE_GREEN_V10        (3 << 0)
>>> +#define RKISP1_CIF_ISP_HIST_PROP_MODE_BLUE_V10        (4 << 0)
>>> +#define RKISP1_CIF_ISP_HIST_PROP_MODE_LUM_V10        (5 << 0)
>>> +#define RKISP1_CIF_ISP_HIST_PROP_MODE_MASK_V10        0x7
>>> +#define RKISP1_CIF_ISP_HIST_PREDIV_SET_V10(x)        (((x) & 0x7F) << 3)
>>> +#define RKISP1_CIF_ISP_HIST_WEIGHT_SET_V10(v0, v1, v2, v3)    \
>>>                        (((v0) & 0x1F) | (((v1) & 0x1F) << 8)  |\
>>>                        (((v2) & 0x1F) << 16) | \
>>>                        (((v3) & 0x1F) << 24))
>>>   -#define RKISP1_CIF_ISP_HIST_WINDOW_OFFSET_RESERVED    0xFFFFF000
>>> -#define RKISP1_CIF_ISP_HIST_WINDOW_SIZE_RESERVED    0xFFFFF800
>>> -#define RKISP1_CIF_ISP_HIST_WEIGHT_RESERVED        0xE0E0E0E0
>>> -#define RKISP1_CIF_ISP_MAX_HIST_PREDIVIDER        0x0000007F
>>> -#define RKISP1_CIF_ISP_HIST_ROW_NUM            5
>>> -#define RKISP1_CIF_ISP_HIST_COLUMN_NUM            5
>>> +#define RKISP1_CIF_ISP_HIST_WINDOW_OFFSET_RESERVED_V10    0xFFFFF000
>>> +#define RKISP1_CIF_ISP_HIST_WINDOW_SIZE_RESERVED_V10    0xFFFFF800
>>> +#define RKISP1_CIF_ISP_HIST_WEIGHT_RESERVED_V10        0xE0E0E0E0
>>> +#define RKISP1_CIF_ISP_MAX_HIST_PREDIVIDER_V10        0x0000007F
>>> +#define RKISP1_CIF_ISP_HIST_ROW_NUM_V10            5
>>> +#define RKISP1_CIF_ISP_HIST_COLUMN_NUM_V10        5
>>> +
>>> +/* ISP HISTOGRAM CALCULATION : CIF_ISP_HIST */
>>> +#define RKISP1_CIF_ISP_HIST_CTRL_EN_SET_V12(x)        (((x) & 0x01) << 0)
>>> +#define RKISP1_CIF_ISP_HIST_CTRL_EN_MASK_V12        RKISP1_CIF_ISP_HIST_CTRL_EN_SET_V12(0x01)
>>> +#define RKISP1_CIF_ISP_HIST_CTRL_STEPSIZE_SET_V12(x)    (((x) & 0x7F) << 1)
>>> +#define RKISP1_CIF_ISP_HIST_CTRL_MODE_SET_V12(x)    (((x) & 0x07) << 8)
>>> +#define RKISP1_CIF_ISP_HIST_CTRL_MODE_MASK_V12        RKISP1_CIF_ISP_HIST_CTRL_MODE_SET_V12(0x07)
>>> +#define RKISP1_CIF_ISP_HIST_CTRL_AUTOSTOP_SET_V12(x)    (((x) & 0x01) << 11)
>>> +#define RKISP1_CIF_ISP_HIST_CTRL_WATERLINE_SET_V12(x)    (((x) & 0xFFF) << 12)
>>> +#define RKISP1_CIF_ISP_HIST_CTRL_DATASEL_SET_V12(x)    (((x) & 0x07) << 24)
>>> +#define RKISP1_CIF_ISP_HIST_CTRL_INTRSEL_SET_V12(x)    (((x) & 0x01) << 27)
>>> +#define RKISP1_CIF_ISP_HIST_CTRL_WNDNUM_SET_V12(x)    (((x) & 0x03) << 28)
>>> +#define RKISP1_CIF_ISP_HIST_CTRL_DBGEN_SET_V12(x)    (((x) & 0x01) << 30)
>>> +#define RKISP1_CIF_ISP_HIST_ROW_NUM_V12        15
>>> +#define RKISP1_CIF_ISP_HIST_COLUMN_NUM_V12        15
>>> +#define RKISP1_CIF_ISP_HIST_WEIGHT_REG_SIZE_V12    \
>>> +                (RKISP1_CIF_ISP_HIST_ROW_NUM_V12 * RKISP1_CIF_ISP_HIST_COLUMN_NUM_V12)
>>> +
>>> +#define RKISP1_CIF_ISP_HIST_WEIGHT_SET_V12(v0, v1, v2, v3)    \
>>> +                (((v0) & 0x3F) | (((v1) & 0x3F) << 8) |\
>>> +                (((v2) & 0x3F) << 16) |\
>>> +                (((v3) & 0x3F) << 24))
>>> +
>>> +#define RKISP1_CIF_ISP_HIST_OFFS_SET_V12(v0, v1)    \
>>> +                (((v0) & 0x1FFF) | (((v1) & 0x1FFF) << 16))
>>> +#define RKISP1_CIF_ISP_HIST_SIZE_SET_V12(v0, v1)    \
>>> +                (((v0) & 0x7FF) | (((v1) & 0x7FF) << 16))
>>> +
>>> +#define RKISP1_CIF_ISP_HIST_GET_BIN0_V12(x)    \
>>> +                ((x) & 0xFFFF)
>>> +#define RKISP1_CIF_ISP_HIST_GET_BIN1_V12(x)    \
>>> +                (((x) >> 16) & 0xFFFF)
>>>     /* AUTO FOCUS MEASUREMENT:  ISP_AFM_CTRL */
>>>   #define RKISP1_ISP_AFM_CTRL_ENABLE            BIT(0)
>>> @@ -400,6 +461,8 @@
>>>   #define RKISP1_CIF_ISP_AWB_MODE_YCBCR_EN        ((0 << 31) | (0x2 << 0))
>>>   #define RKISP1_CIF_ISP_AWB_MODE_MASK_NONE        0xFFFFFFFC
>>>   #define RKISP1_CIF_ISP_AWB_MODE_READ(x)            ((x) & 3)
>>> +#define RKISP1_CIF_ISP_AWB_SET_FRAMES_V12(x)        (((x) & 0x07) << 28)
>>> +#define RKISP1_CIF_ISP_AWB_SET_FRAMES_MASK_V12        RKISP1_CIF_ISP_AWB_SET_FRAMES_V12(0x07)
>>>   /* ISP_AWB_GAIN_RB, ISP_AWB_GAIN_G  */
>>>   #define RKISP1_CIF_ISP_AWB_GAIN_R_SET(x)        (((x) & 0x3FF) << 16)
>>>   #define RKISP1_CIF_ISP_AWB_GAIN_R_READ(x)        (((x) >> 16) & 0x3FF)
>>> @@ -434,6 +497,7 @@
>>>   /* ISP_EXP_CTRL */
>>>   #define RKISP1_CIF_ISP_EXP_ENA                BIT(0)
>>>   #define RKISP1_CIF_ISP_EXP_CTRL_AUTOSTOP        BIT(1)
>>> +#define RKISP1_CIF_ISP_EXP_CTRL_WNDNUM_SET_V12(x)    (((x) & 0x03) << 2)
>>>   /*
>>>    *'1' luminance calculation according to  Y=(R+G+B) x 0.332 (85/256)
>>>    *'0' luminance calculation according to Y=16+0.25R+0.5G+0.1094B
>>> @@ -441,42 +505,76 @@
>>>   #define RKISP1_CIF_ISP_EXP_CTRL_MEASMODE_1        BIT(31)
>>>     /* ISP_EXP_H_SIZE */
>>> -#define RKISP1_CIF_ISP_EXP_H_SIZE_SET(x)        ((x) & 0x7FF)
>>> -#define RKISP1_CIF_ISP_EXP_HEIGHT_MASK            0x000007FF
>>> +#define RKISP1_CIF_ISP_EXP_H_SIZE_SET_V10(x)        ((x) & 0x7FF)
>>> +#define RKISP1_CIF_ISP_EXP_HEIGHT_MASK_V10            0x000007FF
>>> +#define RKISP1_CIF_ISP_EXP_H_SIZE_SET_V12(x)        ((x) & 0x7FF)
>>> +#define RKISP1_CIF_ISP_EXP_HEIGHT_MASK_V12        0x000007FF
>>>   /* ISP_EXP_V_SIZE : vertical size must be a multiple of 2). */
>>> -#define RKISP1_CIF_ISP_EXP_V_SIZE_SET(x)        ((x) & 0x7FE)
>>> +#define RKISP1_CIF_ISP_EXP_V_SIZE_SET_V10(x)        ((x) & 0x7FE)
>>> +#define RKISP1_CIF_ISP_EXP_V_SIZE_SET_V12(x)        (((x) & 0x7FE) << 16)
>>>     /* ISP_EXP_H_OFFSET */
>>> -#define RKISP1_CIF_ISP_EXP_H_OFFSET_SET(x)        ((x) & 0x1FFF)
>>> -#define RKISP1_CIF_ISP_EXP_MAX_HOFFS            2424
>>> +#define RKISP1_CIF_ISP_EXP_H_OFFSET_SET_V10(x)        ((x) & 0x1FFF)
>>> +#define RKISP1_CIF_ISP_EXP_MAX_HOFFS_V10        2424
>>> +#define RKISP1_CIF_ISP_EXP_H_OFFSET_SET_V12(x)        ((x) & 0x1FFF)
>>> +#define RKISP1_CIF_ISP_EXP_MAX_HOFFS_V12        0x1FFF
>>>   /* ISP_EXP_V_OFFSET */
>>> -#define RKISP1_CIF_ISP_EXP_V_OFFSET_SET(x)        ((x) & 0x1FFF)
>>> -#define RKISP1_CIF_ISP_EXP_MAX_VOFFS            1806
>>> -
>>> -#define RKISP1_CIF_ISP_EXP_ROW_NUM            5
>>> -#define RKISP1_CIF_ISP_EXP_COLUMN_NUM            5
>>> -#define RKISP1_CIF_ISP_EXP_NUM_LUMA_REGS \
>>> -    (RKISP1_CIF_ISP_EXP_ROW_NUM * RKISP1_CIF_ISP_EXP_COLUMN_NUM)
>>> -#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE        516
>>> -#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE        35
>>> -#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE        390
>>> -#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE        28
>>> -#define RKISP1_CIF_ISP_EXP_MAX_HSIZE    \
>>> -    (RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE * RKISP1_CIF_ISP_EXP_COLUMN_NUM + 1)
>>> -#define RKISP1_CIF_ISP_EXP_MIN_HSIZE    \
>>> -    (RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE * RKISP1_CIF_ISP_EXP_COLUMN_NUM + 1)
>>> -#define RKISP1_CIF_ISP_EXP_MAX_VSIZE    \
>>> -    (RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE * RKISP1_CIF_ISP_EXP_ROW_NUM + 1)
>>> -#define RKISP1_CIF_ISP_EXP_MIN_VSIZE    \
>>> -    (RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE * RKISP1_CIF_ISP_EXP_ROW_NUM + 1)
>>> +#define RKISP1_CIF_ISP_EXP_V_OFFSET_SET_V10(x)        ((x) & 0x1FFF)
>>> +#define RKISP1_CIF_ISP_EXP_MAX_VOFFS_V10        1806
>>> +#define RKISP1_CIF_ISP_EXP_V_OFFSET_SET_V12(x)        (((x) & 0x1FFF) << 16)
>>> +#define RKISP1_CIF_ISP_EXP_MAX_VOFFS_V12        0x1FFF
>>> +
>>> +#define RKISP1_CIF_ISP_EXP_ROW_NUM_V10            5
>>> +#define RKISP1_CIF_ISP_EXP_COLUMN_NUM_V10            5
>>> +#define RKISP1_CIF_ISP_EXP_NUM_LUMA_REGS_V10 \
>>> +    (RKISP1_CIF_ISP_EXP_ROW_NUM_V10 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V10)
>>> +#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE_V10        516
>>> +#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE_V10        35
>>> +#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE_V10        390
>>> +#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE_V10        28
>>> +#define RKISP1_CIF_ISP_EXP_MAX_HSIZE_V10    \
>>> +    (RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE_V10 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V10 + 1)
>>> +#define RKISP1_CIF_ISP_EXP_MIN_HSIZE_V10    \
>>> +    (RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE_V10 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V10 + 1)
>>> +#define RKISP1_CIF_ISP_EXP_MAX_VSIZE_V10    \
>>> +    (RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE_V10 * RKISP1_CIF_ISP_EXP_ROW_NUM_V10 + 1)
>>> +#define RKISP1_CIF_ISP_EXP_MIN_VSIZE_V10    \
>>> +    (RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE_V10 * RKISP1_CIF_ISP_EXP_ROW_NUM_V10 + 1)
>>> +
>>> +#define RKISP1_CIF_ISP_EXP_ROW_NUM_V12            15
>>> +#define RKISP1_CIF_ISP_EXP_COLUMN_NUM_V12        15
>>> +#define RKISP1_CIF_ISP_EXP_NUM_LUMA_REGS_V12 \
>>> +    (RKISP1_CIF_ISP_EXP_ROW_NUM_V12 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V12)
>>> +
>>> +#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE_V12        0x7FF
>>> +#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE_V12        0xE
>>> +#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE_V12        0x7FE
>>> +#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE_V12        0xE
>>> +#define RKISP1_CIF_ISP_EXP_MAX_HSIZE_V12    \
>>> +    (RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE_V12 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V12 + 1)
>>> +#define RKISP1_CIF_ISP_EXP_MIN_HSIZE_V12    \
>>> +    (RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE_V12 * RKISP1_CIF_ISP_EXP_COLUMN_NUM_V12 + 1)
>>> +#define RKISP1_CIF_ISP_EXP_MAX_VSIZE_V12    \
>>> +    (RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE_V12 * RKISP1_CIF_ISP_EXP_ROW_NUM_V12 + 1)
>>> +#define RKISP1_CIF_ISP_EXP_MIN_VSIZE_V12    \
>>> +    (RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE_V12 * RKISP1_CIF_ISP_EXP_ROW_NUM_V12 + 1)
>>> +
>>> +#define RKISP1_CIF_ISP_EXP_GET_MEAN_xy0_V12(x)        ((x) & 0xFF)
>>> +#define RKISP1_CIF_ISP_EXP_GET_MEAN_xy1_V12(x)        (((x) >> 8) & 0xFF)
>>> +#define RKISP1_CIF_ISP_EXP_GET_MEAN_xy2_V12(x)        (((x) >> 16) & 0xFF)
>>> +#define RKISP1_CIF_ISP_EXP_GET_MEAN_xy3_V12(x)        (((x) >> 24) & 0xFF)
>>>     /* LSC: ISP_LSC_CTRL */
>>>   #define RKISP1_CIF_ISP_LSC_CTRL_ENA            BIT(0)
>>>   #define RKISP1_CIF_ISP_LSC_SECT_SIZE_RESERVED        0xFC00FC00
>>> -#define RKISP1_CIF_ISP_LSC_GRAD_RESERVED        0xF000F000
>>> -#define RKISP1_CIF_ISP_LSC_SAMPLE_RESERVED        0xF000F000
>>> -#define RKISP1_CIF_ISP_LSC_TABLE_DATA(v0, v1)     \
>>> +#define RKISP1_CIF_ISP_LSC_GRAD_RESERVED_V10        0xF000F000
>>> +#define RKISP1_CIF_ISP_LSC_SAMPLE_RESERVED_V10        0xF000F000
>>> +#define RKISP1_CIF_ISP_LSC_GRAD_RESERVED_V12        0xE000E000
>>> +#define RKISP1_CIF_ISP_LSC_SAMPLE_RESERVED_V12        0xE000E000
>>> +#define RKISP1_CIF_ISP_LSC_TABLE_DATA_V10(v0, v1)     \
>>>       (((v0) & 0xFFF) | (((v1) & 0xFFF) << 12))
>>> +#define RKISP1_CIF_ISP_LSC_TABLE_DATA_V12(v0, v1)     \
>>> +    (((v0) & 0x1FFF) | (((v1) & 0x1FFF) << 13))
>>>   #define RKISP1_CIF_ISP_LSC_SECT_SIZE(v0, v1)      \
>>>       (((v0) & 0xFFF) | (((v1) & 0xFFF) << 16))
>>>   #define RKISP1_CIF_ISP_LSC_GRAD_SIZE(v0, v1)      \
>>> @@ -549,6 +647,10 @@
>>>       (1 << 15) | (1 << 11) | (1 << 7) | (1 << 3))
>>>   #define RKISP1_CIFISP_DEGAMMA_Y_RESERVED        0xFFFFF000
>>>   +/* GAMMA-OUT */
>>> +#define RKISP1_CIF_ISP_GAMMA_VALUE_V12(x, y)    \
>>> +    (((x) & 0xFFF) << 16 | ((y) & 0xFFF) << 0)
>>> +
>>>   /* AFM */
>>>   #define RKISP1_CIF_ISP_AFM_ENA                BIT(0)
>>>   #define RKISP1_CIF_ISP_AFM_THRES_RESERVED        0xFFFF0000
>>> @@ -559,6 +661,11 @@
>>>   #define RKISP1_CIF_ISP_AFM_WINDOW_Y_MIN            0x2
>>>   #define RKISP1_CIF_ISP_AFM_WINDOW_X(x)            (((x) & 0x1FFF) << 16)
>>>   #define RKISP1_CIF_ISP_AFM_WINDOW_Y(x)            ((x) & 0x1FFF)
>>> +#define RKISP1_CIF_ISP_AFM_SET_SHIFT_a_V12(x, y)    (((x) & 0x7) << 16 | ((y) & 0x7) << 0)
>>> +#define RKISP1_CIF_ISP_AFM_SET_SHIFT_b_V12(x, y)    (((x) & 0x7) << 20 | ((y) & 0x7) << 4)
>>> +#define RKISP1_CIF_ISP_AFM_SET_SHIFT_c_V12(x, y)    (((x) & 0x7) << 24 | ((y) & 0x7) << 8)
>>> +#define RKISP1_CIF_ISP_AFM_GET_LUM_SHIFT_a_V12(x)    (((x) & 0x70000) >> 16)
>>> +#define RKISP1_CIF_ISP_AFM_GET_AFM_SHIFT_a_V12(x)    ((x) & 0x7)
>>>     /* DPF */
>>>   #define RKISP1_CIF_ISP_DPF_MODE_EN            BIT(0)
>>> @@ -581,6 +688,7 @@
>>>   #define RKISP1_CIF_CTRL_BASE            0x00000000
>>>   #define RKISP1_CIF_CCL                (RKISP1_CIF_CTRL_BASE + 0x00000000)
>>>   #define RKISP1_CIF_VI_ID            (RKISP1_CIF_CTRL_BASE + 0x00000008)
>>> +#define RKISP1_CIF_VI_ISP_CLK_CTRL_V12        (RKISP1_CIF_CTRL_BASE + 0x0000000C)
>>>   #define RKISP1_CIF_ICCL                (RKISP1_CIF_CTRL_BASE + 0x00000010)
>>>   #define RKISP1_CIF_IRCL                (RKISP1_CIF_CTRL_BASE + 0x00000014)
>>>   #define RKISP1_CIF_VI_DPCL            (RKISP1_CIF_CTRL_BASE + 0x00000018)
>>> @@ -666,18 +774,35 @@
>>>   #define RKISP1_CIF_ISP_GAMMA_B_Y14        (RKISP1_CIF_ISP_BASE + 0x000000E4)
>>>   #define RKISP1_CIF_ISP_GAMMA_B_Y15        (RKISP1_CIF_ISP_BASE + 0x000000E8)
>>>   #define RKISP1_CIF_ISP_GAMMA_B_Y16        (RKISP1_CIF_ISP_BASE + 0x000000EC)
>>> -#define RKISP1_CIF_ISP_AWB_PROP            (RKISP1_CIF_ISP_BASE + 0x00000110)
>>> -#define RKISP1_CIF_ISP_AWB_WND_H_OFFS        (RKISP1_CIF_ISP_BASE + 0x00000114)
>>> -#define RKISP1_CIF_ISP_AWB_WND_V_OFFS        (RKISP1_CIF_ISP_BASE + 0x00000118)
>>> -#define RKISP1_CIF_ISP_AWB_WND_H_SIZE        (RKISP1_CIF_ISP_BASE + 0x0000011C)
>>> -#define RKISP1_CIF_ISP_AWB_WND_V_SIZE        (RKISP1_CIF_ISP_BASE + 0x00000120)
>>> -#define RKISP1_CIF_ISP_AWB_FRAMES        (RKISP1_CIF_ISP_BASE + 0x00000124)
>>> -#define RKISP1_CIF_ISP_AWB_REF            (RKISP1_CIF_ISP_BASE + 0x00000128)
>>> -#define RKISP1_CIF_ISP_AWB_THRESH        (RKISP1_CIF_ISP_BASE + 0x0000012C)
>>> -#define RKISP1_CIF_ISP_AWB_GAIN_G        (RKISP1_CIF_ISP_BASE + 0x00000138)
>>> -#define RKISP1_CIF_ISP_AWB_GAIN_RB        (RKISP1_CIF_ISP_BASE + 0x0000013C)
>>> -#define RKISP1_CIF_ISP_AWB_WHITE_CNT        (RKISP1_CIF_ISP_BASE + 0x00000140)
>>> -#define RKISP1_CIF_ISP_AWB_MEAN            (RKISP1_CIF_ISP_BASE + 0x00000144)
>>> +#define RKISP1_CIF_ISP_AWB_PROP_V10        (RKISP1_CIF_ISP_BASE + 0x00000110)
>>> +#define RKISP1_CIF_ISP_AWB_WND_H_OFFS_V10    (RKISP1_CIF_ISP_BASE + 0x00000114)
>>> +#define RKISP1_CIF_ISP_AWB_WND_V_OFFS_V10    (RKISP1_CIF_ISP_BASE + 0x00000118)
>>> +#define RKISP1_CIF_ISP_AWB_WND_H_SIZE_V10    (RKISP1_CIF_ISP_BASE + 0x0000011C)
>>> +#define RKISP1_CIF_ISP_AWB_WND_V_SIZE_V10    (RKISP1_CIF_ISP_BASE + 0x00000120)
>>> +#define RKISP1_CIF_ISP_AWB_FRAMES_V10        (RKISP1_CIF_ISP_BASE + 0x00000124)
>>> +#define RKISP1_CIF_ISP_AWB_REF_V10        (RKISP1_CIF_ISP_BASE + 0x00000128)
>>> +#define RKISP1_CIF_ISP_AWB_THRESH_V10        (RKISP1_CIF_ISP_BASE + 0x0000012C)
>>> +#define RKISP1_CIF_ISP_AWB_GAIN_G_V10        (RKISP1_CIF_ISP_BASE + 0x00000138)
>>> +#define RKISP1_CIF_ISP_AWB_GAIN_RB_V10        (RKISP1_CIF_ISP_BASE + 0x0000013C)
>>> +#define RKISP1_CIF_ISP_AWB_WHITE_CNT_V10    (RKISP1_CIF_ISP_BASE + 0x00000140)
>>> +#define RKISP1_CIF_ISP_AWB_MEAN_V10        (RKISP1_CIF_ISP_BASE + 0x00000144)
>>> +#define RKISP1_CIF_ISP_AWB_PROP_V12        (RKISP1_CIF_ISP_BASE + 0x00000110)
>>> +#define RKISP1_CIF_ISP_AWB_SIZE_V12        (RKISP1_CIF_ISP_BASE + 0x00000114)
>>> +#define RKISP1_CIF_ISP_AWB_OFFS_V12        (RKISP1_CIF_ISP_BASE + 0x00000118)
>>> +#define RKISP1_CIF_ISP_AWB_REF_V12        (RKISP1_CIF_ISP_BASE + 0x0000011C)
>>> +#define RKISP1_CIF_ISP_AWB_THRESH_V12        (RKISP1_CIF_ISP_BASE + 0x00000120)
>>> +#define RKISP1_CIF_ISP_X_COOR12_V12        (RKISP1_CIF_ISP_BASE + 0x00000124)
>>> +#define RKISP1_CIF_ISP_X_COOR34_V12        (RKISP1_CIF_ISP_BASE + 0x00000128)
>>> +#define RKISP1_CIF_ISP_AWB_WHITE_CNT_V12    (RKISP1_CIF_ISP_BASE + 0x0000012C)
>>> +#define RKISP1_CIF_ISP_AWB_MEAN_V12        (RKISP1_CIF_ISP_BASE + 0x00000130)
>>> +#define RKISP1_CIF_ISP_DEGAIN_V12        (RKISP1_CIF_ISP_BASE + 0x00000134)
>>> +#define RKISP1_CIF_ISP_AWB_GAIN_G_V12        (RKISP1_CIF_ISP_BASE + 0x00000138)
>>> +#define RKISP1_CIF_ISP_AWB_GAIN_RB_V12        (RKISP1_CIF_ISP_BASE + 0x0000013C)
>>> +#define RKISP1_CIF_ISP_REGION_LINE_V12        (RKISP1_CIF_ISP_BASE + 0x00000140)
>>> +#define RKISP1_CIF_ISP_WP_CNT_REGION0_V12    (RKISP1_CIF_ISP_BASE + 0x00000160)
>>> +#define RKISP1_CIF_ISP_WP_CNT_REGION1_V12    (RKISP1_CIF_ISP_BASE + 0x00000164)
>>> +#define RKISP1_CIF_ISP_WP_CNT_REGION2_V12    (RKISP1_CIF_ISP_BASE + 0x00000168)
>>> +#define RKISP1_CIF_ISP_WP_CNT_REGION3_V12    (RKISP1_CIF_ISP_BASE + 0x0000016C)
>>>   #define RKISP1_CIF_ISP_CC_COEFF_0        (RKISP1_CIF_ISP_BASE + 0x00000170)
>>>   #define RKISP1_CIF_ISP_CC_COEFF_1        (RKISP1_CIF_ISP_BASE + 0x00000174)
>>>   #define RKISP1_CIF_ISP_CC_COEFF_2        (RKISP1_CIF_ISP_BASE + 0x00000178)
>>> @@ -711,30 +836,32 @@
>>>   #define RKISP1_CIF_ISP_CT_COEFF_6        (RKISP1_CIF_ISP_BASE + 0x000001E8)
>>>   #define RKISP1_CIF_ISP_CT_COEFF_7        (RKISP1_CIF_ISP_BASE + 0x000001EC)
>>>   #define RKISP1_CIF_ISP_CT_COEFF_8        (RKISP1_CIF_ISP_BASE + 0x000001F0)
>>> -#define RKISP1_CIF_ISP_GAMMA_OUT_MODE        (RKISP1_CIF_ISP_BASE + 0x000001F4)
>>> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_0        (RKISP1_CIF_ISP_BASE + 0x000001F8)
>>> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_1        (RKISP1_CIF_ISP_BASE + 0x000001FC)
>>> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_2        (RKISP1_CIF_ISP_BASE + 0x00000200)
>>> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_3        (RKISP1_CIF_ISP_BASE + 0x00000204)
>>> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_4        (RKISP1_CIF_ISP_BASE + 0x00000208)
>>> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_5        (RKISP1_CIF_ISP_BASE + 0x0000020C)
>>> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_6        (RKISP1_CIF_ISP_BASE + 0x00000210)
>>> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_7        (RKISP1_CIF_ISP_BASE + 0x00000214)
>>> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_8        (RKISP1_CIF_ISP_BASE + 0x00000218)
>>> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_9        (RKISP1_CIF_ISP_BASE + 0x0000021C)
>>> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_10        (RKISP1_CIF_ISP_BASE + 0x00000220)
>>> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_11        (RKISP1_CIF_ISP_BASE + 0x00000224)
>>> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_12        (RKISP1_CIF_ISP_BASE + 0x00000228)
>>> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_13        (RKISP1_CIF_ISP_BASE + 0x0000022C)
>>> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_14        (RKISP1_CIF_ISP_BASE + 0x00000230)
>>> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_15        (RKISP1_CIF_ISP_BASE + 0x00000234)
>>> -#define RKISP1_CIF_ISP_GAMMA_OUT_Y_16        (RKISP1_CIF_ISP_BASE + 0x00000238)
>>> +#define RKISP1_CIF_ISP_GAMMA_OUT_MODE_V10    (RKISP1_CIF_ISP_BASE + 0x000001F4)
>>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_0_V10    (RKISP1_CIF_ISP_BASE + 0x000001F8)
>>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_1_V10    (RKISP1_CIF_ISP_BASE + 0x000001FC)
>>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_2_V10    (RKISP1_CIF_ISP_BASE + 0x00000200)
>>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_3_V10    (RKISP1_CIF_ISP_BASE + 0x00000204)
>>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_4_V10    (RKISP1_CIF_ISP_BASE + 0x00000208)
>>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_5_V10    (RKISP1_CIF_ISP_BASE + 0x0000020C)
>>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_6_V10    (RKISP1_CIF_ISP_BASE + 0x00000210)
>>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_7_V10    (RKISP1_CIF_ISP_BASE + 0x00000214)
>>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_8_V10    (RKISP1_CIF_ISP_BASE + 0x00000218)
>>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_9_V10    (RKISP1_CIF_ISP_BASE + 0x0000021C)
>>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_10_V10    (RKISP1_CIF_ISP_BASE + 0x00000220)
>>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_11_V10    (RKISP1_CIF_ISP_BASE + 0x00000224)
>>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_12_V10    (RKISP1_CIF_ISP_BASE + 0x00000228)
>>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_13_V10    (RKISP1_CIF_ISP_BASE + 0x0000022C)
>>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_14_V10    (RKISP1_CIF_ISP_BASE + 0x00000230)
>>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_15_V10    (RKISP1_CIF_ISP_BASE + 0x00000234)
>>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_16_V10    (RKISP1_CIF_ISP_BASE + 0x00000238)
>>>   #define RKISP1_CIF_ISP_ERR            (RKISP1_CIF_ISP_BASE + 0x0000023C)
>>>   #define RKISP1_CIF_ISP_ERR_CLR            (RKISP1_CIF_ISP_BASE + 0x00000240)
>>>   #define RKISP1_CIF_ISP_FRAME_COUNT        (RKISP1_CIF_ISP_BASE + 0x00000244)
>>>   #define RKISP1_CIF_ISP_CT_OFFSET_R        (RKISP1_CIF_ISP_BASE + 0x00000248)
>>>   #define RKISP1_CIF_ISP_CT_OFFSET_G        (RKISP1_CIF_ISP_BASE + 0x0000024C)
>>>   #define RKISP1_CIF_ISP_CT_OFFSET_B        (RKISP1_CIF_ISP_BASE + 0x00000250)
>>> +#define RKISP1_CIF_ISP_GAMMA_OUT_MODE_V12    (RKISP1_CIF_ISP_BASE + 0x00000300)
>>> +#define RKISP1_CIF_ISP_GAMMA_OUT_Y_0_V12    (RKISP1_CIF_ISP_BASE + 0x00000304)
>>>     #define RKISP1_CIF_ISP_FLASH_BASE        0x00000660
>>>   #define RKISP1_CIF_ISP_FLASH_CMD        (RKISP1_CIF_ISP_FLASH_BASE + 0x00000000)
>>> @@ -1004,36 +1131,35 @@
>>>   #define RKISP1_CIF_ISP_IS_H_SIZE_SHD        (RKISP1_CIF_ISP_IS_BASE + 0x0000002C)
>>>   #define RKISP1_CIF_ISP_IS_V_SIZE_SHD        (RKISP1_CIF_ISP_IS_BASE + 0x00000030)
>>>   -#define RKISP1_CIF_ISP_HIST_BASE        0x00002400
>>> -
>>> -#define RKISP1_CIF_ISP_HIST_PROP        (RKISP1_CIF_ISP_HIST_BASE + 0x00000000)
>>> -#define RKISP1_CIF_ISP_HIST_H_OFFS        (RKISP1_CIF_ISP_HIST_BASE + 0x00000004)
>>> -#define RKISP1_CIF_ISP_HIST_V_OFFS        (RKISP1_CIF_ISP_HIST_BASE + 0x00000008)
>>> -#define RKISP1_CIF_ISP_HIST_H_SIZE        (RKISP1_CIF_ISP_HIST_BASE + 0x0000000C)
>>> -#define RKISP1_CIF_ISP_HIST_V_SIZE        (RKISP1_CIF_ISP_HIST_BASE + 0x00000010)
>>> -#define RKISP1_CIF_ISP_HIST_BIN_0        (RKISP1_CIF_ISP_HIST_BASE + 0x00000014)
>>> -#define RKISP1_CIF_ISP_HIST_BIN_1        (RKISP1_CIF_ISP_HIST_BASE + 0x00000018)
>>> -#define RKISP1_CIF_ISP_HIST_BIN_2        (RKISP1_CIF_ISP_HIST_BASE + 0x0000001C)
>>> -#define RKISP1_CIF_ISP_HIST_BIN_3        (RKISP1_CIF_ISP_HIST_BASE + 0x00000020)
>>> -#define RKISP1_CIF_ISP_HIST_BIN_4        (RKISP1_CIF_ISP_HIST_BASE + 0x00000024)
>>> -#define RKISP1_CIF_ISP_HIST_BIN_5        (RKISP1_CIF_ISP_HIST_BASE + 0x00000028)
>>> -#define RKISP1_CIF_ISP_HIST_BIN_6        (RKISP1_CIF_ISP_HIST_BASE + 0x0000002C)
>>> -#define RKISP1_CIF_ISP_HIST_BIN_7        (RKISP1_CIF_ISP_HIST_BASE + 0x00000030)
>>> -#define RKISP1_CIF_ISP_HIST_BIN_8        (RKISP1_CIF_ISP_HIST_BASE + 0x00000034)
>>> -#define RKISP1_CIF_ISP_HIST_BIN_9        (RKISP1_CIF_ISP_HIST_BASE + 0x00000038)
>>> -#define RKISP1_CIF_ISP_HIST_BIN_10        (RKISP1_CIF_ISP_HIST_BASE + 0x0000003C)
>>> -#define RKISP1_CIF_ISP_HIST_BIN_11        (RKISP1_CIF_ISP_HIST_BASE + 0x00000040)
>>> -#define RKISP1_CIF_ISP_HIST_BIN_12        (RKISP1_CIF_ISP_HIST_BASE + 0x00000044)
>>> -#define RKISP1_CIF_ISP_HIST_BIN_13        (RKISP1_CIF_ISP_HIST_BASE + 0x00000048)
>>> -#define RKISP1_CIF_ISP_HIST_BIN_14        (RKISP1_CIF_ISP_HIST_BASE + 0x0000004C)
>>> -#define RKISP1_CIF_ISP_HIST_BIN_15        (RKISP1_CIF_ISP_HIST_BASE + 0x00000050)
>>> -#define RKISP1_CIF_ISP_HIST_WEIGHT_00TO30    (RKISP1_CIF_ISP_HIST_BASE + 0x00000054)
>>> -#define RKISP1_CIF_ISP_HIST_WEIGHT_40TO21    (RKISP1_CIF_ISP_HIST_BASE + 0x00000058)
>>> -#define RKISP1_CIF_ISP_HIST_WEIGHT_31TO12    (RKISP1_CIF_ISP_HIST_BASE + 0x0000005C)
>>> -#define RKISP1_CIF_ISP_HIST_WEIGHT_22TO03    (RKISP1_CIF_ISP_HIST_BASE + 0x00000060)
>>> -#define RKISP1_CIF_ISP_HIST_WEIGHT_13TO43    (RKISP1_CIF_ISP_HIST_BASE + 0x00000064)
>>> -#define RKISP1_CIF_ISP_HIST_WEIGHT_04TO34    (RKISP1_CIF_ISP_HIST_BASE + 0x00000068)
>>> -#define RKISP1_CIF_ISP_HIST_WEIGHT_44        (RKISP1_CIF_ISP_HIST_BASE + 0x0000006C)
>>> +#define RKISP1_CIF_ISP_HIST_BASE_V10        0x00002400
>>> +#define RKISP1_CIF_ISP_HIST_PROP_V10        (RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000000)
>>> +#define RKISP1_CIF_ISP_HIST_H_OFFS_V10        (RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000004)
>>> +#define RKISP1_CIF_ISP_HIST_V_OFFS_V10        (RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000008)
>>> +#define RKISP1_CIF_ISP_HIST_H_SIZE_V10        (RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000000C)
>>> +#define RKISP1_CIF_ISP_HIST_V_SIZE_V10        (RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000010)
>>> +#define RKISP1_CIF_ISP_HIST_BIN_0_V10        (RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000014)
>>> +#define RKISP1_CIF_ISP_HIST_BIN_1_V10        (RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000018)
>>> +#define RKISP1_CIF_ISP_HIST_BIN_2_V10        (RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000001C)
>>> +#define RKISP1_CIF_ISP_HIST_BIN_3_V10        (RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000020)
>>> +#define RKISP1_CIF_ISP_HIST_BIN_4_V10        (RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000024)
>>> +#define RKISP1_CIF_ISP_HIST_BIN_5_V10        (RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000028)
>>> +#define RKISP1_CIF_ISP_HIST_BIN_6_V10        (RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000002C)
>>> +#define RKISP1_CIF_ISP_HIST_BIN_7_V10        (RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000030)
>>> +#define RKISP1_CIF_ISP_HIST_BIN_8_V10        (RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000034)
>>> +#define RKISP1_CIF_ISP_HIST_BIN_9_V10        (RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000038)
>>> +#define RKISP1_CIF_ISP_HIST_BIN_10_V10        (RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000003C)
>>> +#define RKISP1_CIF_ISP_HIST_BIN_11_V10        (RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000040)
>>> +#define RKISP1_CIF_ISP_HIST_BIN_12_V10        (RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000044)
>>> +#define RKISP1_CIF_ISP_HIST_BIN_13_V10        (RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000048)
>>> +#define RKISP1_CIF_ISP_HIST_BIN_14_V10        (RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000004C)
>>> +#define RKISP1_CIF_ISP_HIST_BIN_15_V10        (RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000050)
>>> +#define RKISP1_CIF_ISP_HIST_WEIGHT_00TO30_V10    (RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000054)
>>> +#define RKISP1_CIF_ISP_HIST_WEIGHT_40TO21_V10    (RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000058)
>>> +#define RKISP1_CIF_ISP_HIST_WEIGHT_31TO12_V10    (RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000005C)
>>> +#define RKISP1_CIF_ISP_HIST_WEIGHT_22TO03_V10    (RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000060)
>>> +#define RKISP1_CIF_ISP_HIST_WEIGHT_13TO43_V10    (RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000064)
>>> +#define RKISP1_CIF_ISP_HIST_WEIGHT_04TO34_V10    (RKISP1_CIF_ISP_HIST_BASE_V10 + 0x00000068)
>>> +#define RKISP1_CIF_ISP_HIST_WEIGHT_44_V10    (RKISP1_CIF_ISP_HIST_BASE_V10 + 0x0000006C)
>>>     #define RKISP1_CIF_ISP_FILT_BASE        0x00002500
>>>   #define RKISP1_CIF_ISP_FILT_MODE        (RKISP1_CIF_ISP_FILT_BASE + 0x00000000)
>>> @@ -1059,35 +1185,38 @@
>>>     #define RKISP1_CIF_ISP_EXP_BASE            0x00002600
>>>   #define RKISP1_CIF_ISP_EXP_CTRL            (RKISP1_CIF_ISP_EXP_BASE + 0x00000000)
>>> -#define RKISP1_CIF_ISP_EXP_H_OFFSET        (RKISP1_CIF_ISP_EXP_BASE + 0x00000004)
>>> -#define RKISP1_CIF_ISP_EXP_V_OFFSET        (RKISP1_CIF_ISP_EXP_BASE + 0x00000008)
>>> -#define RKISP1_CIF_ISP_EXP_H_SIZE        (RKISP1_CIF_ISP_EXP_BASE + 0x0000000C)
>>> -#define RKISP1_CIF_ISP_EXP_V_SIZE        (RKISP1_CIF_ISP_EXP_BASE + 0x00000010)
>>> -#define RKISP1_CIF_ISP_EXP_MEAN_00        (RKISP1_CIF_ISP_EXP_BASE + 0x00000014)
>>> -#define RKISP1_CIF_ISP_EXP_MEAN_10        (RKISP1_CIF_ISP_EXP_BASE + 0x00000018)
>>> -#define RKISP1_CIF_ISP_EXP_MEAN_20        (RKISP1_CIF_ISP_EXP_BASE + 0x0000001c)
>>> -#define RKISP1_CIF_ISP_EXP_MEAN_30        (RKISP1_CIF_ISP_EXP_BASE + 0x00000020)
>>> -#define RKISP1_CIF_ISP_EXP_MEAN_40        (RKISP1_CIF_ISP_EXP_BASE + 0x00000024)
>>> -#define RKISP1_CIF_ISP_EXP_MEAN_01        (RKISP1_CIF_ISP_EXP_BASE + 0x00000028)
>>> -#define RKISP1_CIF_ISP_EXP_MEAN_11        (RKISP1_CIF_ISP_EXP_BASE + 0x0000002c)
>>> -#define RKISP1_CIF_ISP_EXP_MEAN_21        (RKISP1_CIF_ISP_EXP_BASE + 0x00000030)
>>> -#define RKISP1_CIF_ISP_EXP_MEAN_31        (RKISP1_CIF_ISP_EXP_BASE + 0x00000034)
>>> -#define RKISP1_CIF_ISP_EXP_MEAN_41        (RKISP1_CIF_ISP_EXP_BASE + 0x00000038)
>>> -#define RKISP1_CIF_ISP_EXP_MEAN_02        (RKISP1_CIF_ISP_EXP_BASE + 0x0000003c)
>>> -#define RKISP1_CIF_ISP_EXP_MEAN_12        (RKISP1_CIF_ISP_EXP_BASE + 0x00000040)
>>> -#define RKISP1_CIF_ISP_EXP_MEAN_22        (RKISP1_CIF_ISP_EXP_BASE + 0x00000044)
>>> -#define RKISP1_CIF_ISP_EXP_MEAN_32        (RKISP1_CIF_ISP_EXP_BASE + 0x00000048)
>>> -#define RKISP1_CIF_ISP_EXP_MEAN_42        (RKISP1_CIF_ISP_EXP_BASE + 0x0000004c)
>>> -#define RKISP1_CIF_ISP_EXP_MEAN_03        (RKISP1_CIF_ISP_EXP_BASE + 0x00000050)
>>> -#define RKISP1_CIF_ISP_EXP_MEAN_13        (RKISP1_CIF_ISP_EXP_BASE + 0x00000054)
>>> -#define RKISP1_CIF_ISP_EXP_MEAN_23        (RKISP1_CIF_ISP_EXP_BASE + 0x00000058)
>>> -#define RKISP1_CIF_ISP_EXP_MEAN_33        (RKISP1_CIF_ISP_EXP_BASE + 0x0000005c)
>>> -#define RKISP1_CIF_ISP_EXP_MEAN_43        (RKISP1_CIF_ISP_EXP_BASE + 0x00000060)
>>> -#define RKISP1_CIF_ISP_EXP_MEAN_04        (RKISP1_CIF_ISP_EXP_BASE + 0x00000064)
>>> -#define RKISP1_CIF_ISP_EXP_MEAN_14        (RKISP1_CIF_ISP_EXP_BASE + 0x00000068)
>>> -#define RKISP1_CIF_ISP_EXP_MEAN_24        (RKISP1_CIF_ISP_EXP_BASE + 0x0000006c)
>>> -#define RKISP1_CIF_ISP_EXP_MEAN_34        (RKISP1_CIF_ISP_EXP_BASE + 0x00000070)
>>> -#define RKISP1_CIF_ISP_EXP_MEAN_44        (RKISP1_CIF_ISP_EXP_BASE + 0x00000074)
>>> +#define RKISP1_CIF_ISP_EXP_H_OFFSET_V10        (RKISP1_CIF_ISP_EXP_BASE + 0x00000004)
>>> +#define RKISP1_CIF_ISP_EXP_V_OFFSET_V10        (RKISP1_CIF_ISP_EXP_BASE + 0x00000008)
>>> +#define RKISP1_CIF_ISP_EXP_H_SIZE_V10        (RKISP1_CIF_ISP_EXP_BASE + 0x0000000C)
>>> +#define RKISP1_CIF_ISP_EXP_V_SIZE_V10        (RKISP1_CIF_ISP_EXP_BASE + 0x00000010)
>>> +#define RKISP1_CIF_ISP_EXP_MEAN_00_V10        (RKISP1_CIF_ISP_EXP_BASE + 0x00000014)
>>> +#define RKISP1_CIF_ISP_EXP_MEAN_10_V10        (RKISP1_CIF_ISP_EXP_BASE + 0x00000018)
>>> +#define RKISP1_CIF_ISP_EXP_MEAN_20_V10        (RKISP1_CIF_ISP_EXP_BASE + 0x0000001c)
>>> +#define RKISP1_CIF_ISP_EXP_MEAN_30_V10        (RKISP1_CIF_ISP_EXP_BASE + 0x00000020)
>>> +#define RKISP1_CIF_ISP_EXP_MEAN_40_V10        (RKISP1_CIF_ISP_EXP_BASE + 0x00000024)
>>> +#define RKISP1_CIF_ISP_EXP_MEAN_01_V10        (RKISP1_CIF_ISP_EXP_BASE + 0x00000028)
>>> +#define RKISP1_CIF_ISP_EXP_MEAN_11_V10        (RKISP1_CIF_ISP_EXP_BASE + 0x0000002c)
>>> +#define RKISP1_CIF_ISP_EXP_MEAN_21_V10        (RKISP1_CIF_ISP_EXP_BASE + 0x00000030)
>>> +#define RKISP1_CIF_ISP_EXP_MEAN_31_V10        (RKISP1_CIF_ISP_EXP_BASE + 0x00000034)
>>> +#define RKISP1_CIF_ISP_EXP_MEAN_41_V10        (RKISP1_CIF_ISP_EXP_BASE + 0x00000038)
>>> +#define RKISP1_CIF_ISP_EXP_MEAN_02_V10        (RKISP1_CIF_ISP_EXP_BASE + 0x0000003c)
>>> +#define RKISP1_CIF_ISP_EXP_MEAN_12_V10        (RKISP1_CIF_ISP_EXP_BASE + 0x00000040)
>>> +#define RKISP1_CIF_ISP_EXP_MEAN_22_V10        (RKISP1_CIF_ISP_EXP_BASE + 0x00000044)
>>> +#define RKISP1_CIF_ISP_EXP_MEAN_32_V10        (RKISP1_CIF_ISP_EXP_BASE + 0x00000048)
>>> +#define RKISP1_CIF_ISP_EXP_MEAN_42_V10        (RKISP1_CIF_ISP_EXP_BASE + 0x0000004c)
>>> +#define RKISP1_CIF_ISP_EXP_MEAN_03_V10        (RKISP1_CIF_ISP_EXP_BASE + 0x00000050)
>>> +#define RKISP1_CIF_ISP_EXP_MEAN_13_V10        (RKISP1_CIF_ISP_EXP_BASE + 0x00000054)
>>> +#define RKISP1_CIF_ISP_EXP_MEAN_23_V10        (RKISP1_CIF_ISP_EXP_BASE + 0x00000058)
>>> +#define RKISP1_CIF_ISP_EXP_MEAN_33_V10        (RKISP1_CIF_ISP_EXP_BASE + 0x0000005c)
>>> +#define RKISP1_CIF_ISP_EXP_MEAN_43_V10        (RKISP1_CIF_ISP_EXP_BASE + 0x00000060)
>>> +#define RKISP1_CIF_ISP_EXP_MEAN_04_V10        (RKISP1_CIF_ISP_EXP_BASE + 0x00000064)
>>> +#define RKISP1_CIF_ISP_EXP_MEAN_14_V10        (RKISP1_CIF_ISP_EXP_BASE + 0x00000068)
>>> +#define RKISP1_CIF_ISP_EXP_MEAN_24_V10        (RKISP1_CIF_ISP_EXP_BASE + 0x0000006c)
>>> +#define RKISP1_CIF_ISP_EXP_MEAN_34_V10        (RKISP1_CIF_ISP_EXP_BASE + 0x00000070)
>>> +#define RKISP1_CIF_ISP_EXP_MEAN_44_V10        (RKISP1_CIF_ISP_EXP_BASE + 0x00000074)
>>> +#define RKISP1_CIF_ISP_EXP_SIZE_V12        (RKISP1_CIF_ISP_EXP_BASE + 0x00000004)
>>> +#define RKISP1_CIF_ISP_EXP_OFFS_V12        (RKISP1_CIF_ISP_EXP_BASE + 0x00000008)
>>> +#define RKISP1_CIF_ISP_EXP_MEAN_V12        (RKISP1_CIF_ISP_EXP_BASE + 0x0000000c)
>>>     #define RKISP1_CIF_ISP_BLS_BASE            0x00002700
>>>   #define RKISP1_CIF_ISP_BLS_CTRL            (RKISP1_CIF_ISP_BLS_BASE + 0x00000000)
>>> @@ -1248,6 +1377,16 @@
>>>   #define RKISP1_CIF_ISP_WDR_TONECURVE_YM_31_SHD    (RKISP1_CIF_ISP_WDR_BASE + 0x0000012C)
>>>   #define RKISP1_CIF_ISP_WDR_TONECURVE_YM_32_SHD    (RKISP1_CIF_ISP_WDR_BASE + 0x00000130)
>>>   +#define RKISP1_CIF_ISP_HIST_BASE_V12        0x00002C00
>>> +#define RKISP1_CIF_ISP_HIST_CTRL_V12        (RKISP1_CIF_ISP_HIST_BASE_V12 + 0x00000000)
>>> +#define RKISP1_CIF_ISP_HIST_SIZE_V12        (RKISP1_CIF_ISP_HIST_BASE_V12 + 0x00000004)
>>> +#define RKISP1_CIF_ISP_HIST_OFFS_V12        (RKISP1_CIF_ISP_HIST_BASE_V12 + 0x00000008)
>>> +#define RKISP1_CIF_ISP_HIST_DBG1_V12        (RKISP1_CIF_ISP_HIST_BASE_V12 + 0x0000000C)
>>> +#define RKISP1_CIF_ISP_HIST_DBG2_V12        (RKISP1_CIF_ISP_HIST_BASE_V12 + 0x0000001C)
>>> +#define RKISP1_CIF_ISP_HIST_DBG3_V12        (RKISP1_CIF_ISP_HIST_BASE_V12 + 0x0000002C)
>>> +#define RKISP1_CIF_ISP_HIST_WEIGHT_V12        (RKISP1_CIF_ISP_HIST_BASE_V12 + 0x0000003C)
>>> +#define RKISP1_CIF_ISP_HIST_BIN_V12        (RKISP1_CIF_ISP_HIST_BASE_V12 + 0x00000120)
>>> +
>>>   #define RKISP1_CIF_ISP_VSM_BASE            0x00002F00
>>>   #define RKISP1_CIF_ISP_VSM_MODE            (RKISP1_CIF_ISP_VSM_BASE + 0x00000000)
>>>   #define RKISP1_CIF_ISP_VSM_H_OFFS        (RKISP1_CIF_ISP_VSM_BASE + 0x00000004)
>>> @@ -1259,4 +1398,7 @@
>>>   #define RKISP1_CIF_ISP_VSM_DELTA_H        (RKISP1_CIF_ISP_VSM_BASE + 0x0000001C)
>>>   #define RKISP1_CIF_ISP_VSM_DELTA_V        (RKISP1_CIF_ISP_VSM_BASE + 0x00000020)
>>>   +#define RKISP1_CIF_ISP_CSI0_BASE        0x00007000
>>> +#define RKISP1_CIF_ISP_CSI0_CTRL0        (RKISP1_CIF_ISP_CSI0_BASE + 0x00000000)
>>> +
>>>   #endif /* _RKISP1_REGS_H */
>>> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c
>>> index 7136292039f6..5ce1a2974b55 100644
>>> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c
>>> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c
>>> @@ -175,18 +175,18 @@ rkisp1_stats_init_vb2_queue(struct vb2_queue *q, struct rkisp1_stats *stats)
>>>       return vb2_queue_init(q);
>>>   }
>>>   -static void rkisp1_stats_get_awb_meas(struct rkisp1_stats *stats,
>>> -                      struct rkisp1_stat_buffer *pbuf)
>>> +static void rkisp1_stats_get_awb_meas_v10(struct rkisp1_stats *stats,
>>> +                      struct rkisp1_stat_buffer *pbuf)
>>>   {
>>>       /* Protect against concurrent access from ISR? */
>>>       struct rkisp1_device *rkisp1 = stats->rkisp1;
>>>       u32 reg_val;
>>>         pbuf->meas_type |= RKISP1_CIF_ISP_STAT_AWB;
>>> -    reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_WHITE_CNT);
>>> +    reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_WHITE_CNT_V10);
>>>       pbuf->params.awb.awb_mean[0].cnt =
>>>                   RKISP1_CIF_ISP_AWB_GET_PIXEL_CNT(reg_val);
>>> -    reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_MEAN);
>>> +    reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_MEAN_V10);
>>>         pbuf->params.awb.awb_mean[0].mean_cr_or_r =
>>>                   RKISP1_CIF_ISP_AWB_GET_MEAN_CR_R(reg_val);
>>> @@ -196,8 +196,29 @@ static void rkisp1_stats_get_awb_meas(struct rkisp1_stats *stats,
>>>                   RKISP1_CIF_ISP_AWB_GET_MEAN_Y_G(reg_val);
>>>   }
>>>   -static void rkisp1_stats_get_aec_meas(struct rkisp1_stats *stats,
>>> -                      struct rkisp1_stat_buffer *pbuf)
>>> +static void rkisp1_stats_get_awb_meas_v12(struct rkisp1_stats *stats,
>>> +                      struct rkisp1_stat_buffer *pbuf)
>>> +{
>>> +    /* Protect against concurrent access from ISR? */
>>> +    struct rkisp1_device *rkisp1 = stats->rkisp1;
>>> +    u32 reg_val;
>>> +
>>> +    pbuf->meas_type |= RKISP1_CIF_ISP_STAT_AWB;
>>> +    reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_WHITE_CNT_V12);
>>> +    pbuf->params.awb.awb_mean[0].cnt =
>>> +                RKISP1_CIF_ISP_AWB_GET_PIXEL_CNT(reg_val);
>>> +    reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_MEAN_V12);
>>> +
>>> +    pbuf->params.awb.awb_mean[0].mean_cr_or_r =
>>> +                RKISP1_CIF_ISP_AWB_GET_MEAN_CR_R(reg_val);
>>> +    pbuf->params.awb.awb_mean[0].mean_cb_or_b =
>>> +                RKISP1_CIF_ISP_AWB_GET_MEAN_CB_B(reg_val);
>>> +    pbuf->params.awb.awb_mean[0].mean_y_or_g =
>>> +                RKISP1_CIF_ISP_AWB_GET_MEAN_Y_G(reg_val);
>>> +}
>>> +
>>> +static void rkisp1_stats_get_aec_meas_v10(struct rkisp1_stats *stats,
>>> +                      struct rkisp1_stat_buffer *pbuf)
>>>   {
>>>       struct rkisp1_device *rkisp1 = stats->rkisp1;
>>>       unsigned int i;
>>> @@ -206,7 +227,31 @@ static void rkisp1_stats_get_aec_meas(struct rkisp1_stats *stats,
>>>       for (i = 0; i < stats->config->ae_mean_max; i++)
>>>           pbuf->params.ae.exp_mean[i] =
>>>               (u8)rkisp1_read(rkisp1,
>>> -                    RKISP1_CIF_ISP_EXP_MEAN_00 + i * 4);
>>> +                    RKISP1_CIF_ISP_EXP_MEAN_00_V10 + i * 4);
>>> +}
>>> +
>>> +static void rkisp1_stats_get_aec_meas_v12(struct rkisp1_stats *stats,
>>> +                      struct rkisp1_stat_buffer *pbuf)
>>> +{
>>> +    struct rkisp1_device *rkisp1 = stats->rkisp1;
>>> +    u32 value;
>>> +    int i;
>>> +
>>> +    pbuf->meas_type |= RKISP1_CIF_ISP_STAT_AUTOEXP;
>>> +    for (i = 0; i < stats->config->ae_mean_max / 4; i++) {
>>> +        value = rkisp1_read(rkisp1, RKISP1_CIF_ISP_EXP_MEAN_V12 + i * 4);
>>> +        pbuf->params.ae.exp_mean[4 * i + 0] =
>>> +                RKISP1_CIF_ISP_EXP_GET_MEAN_xy0_V12(value);
>>> +        pbuf->params.ae.exp_mean[4 * i + 1] =
>>> +                RKISP1_CIF_ISP_EXP_GET_MEAN_xy1_V12(value);
>>> +        pbuf->params.ae.exp_mean[4 * i + 2] =
>>> +                RKISP1_CIF_ISP_EXP_GET_MEAN_xy2_V12(value);
>>> +        pbuf->params.ae.exp_mean[4 * i + 3] =
>>> +                RKISP1_CIF_ISP_EXP_GET_MEAN_xy3_V12(value);
>>> +    }
>>> +
>>> +    value = rkisp1_read(rkisp1, RKISP1_CIF_ISP_EXP_MEAN_V12 + i * 4);
>>> +    pbuf->params.ae.exp_mean[4 * i + 0] = RKISP1_CIF_ISP_EXP_GET_MEAN_xy0_V12(value);
>>>   }
>>>     static void rkisp1_stats_get_afc_meas(struct rkisp1_stats *stats,
>>> @@ -226,8 +271,8 @@ static void rkisp1_stats_get_afc_meas(struct rkisp1_stats *stats,
>>>       af->window[2].lum = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AFM_LUM_C);
>>>   }
>>>   -static void rkisp1_stats_get_hst_meas(struct rkisp1_stats *stats,
>>> -                      struct rkisp1_stat_buffer *pbuf)
>>> +static void rkisp1_stats_get_hst_meas_v10(struct rkisp1_stats *stats,
>>> +                      struct rkisp1_stat_buffer *pbuf)
>>>   {
>>>       struct rkisp1_device *rkisp1 = stats->rkisp1;
>>>       unsigned int i;
>>> @@ -236,7 +281,24 @@ static void rkisp1_stats_get_hst_meas(struct rkisp1_stats *stats,
>>>       for (i = 0; i < stats->config->hist_bin_n_max; i++)
>>>           pbuf->params.hist.hist_bins[i] =
>>>               (u8)rkisp1_read(rkisp1,
>>> -                    RKISP1_CIF_ISP_HIST_BIN_0 + i * 4);
>>> +                    RKISP1_CIF_ISP_HIST_BIN_0_V10 + i * 4);
>>> +}
>>> +
>>> +static void rkisp1_stats_get_hst_meas_v12(struct rkisp1_stats *stats,
>>> +                      struct rkisp1_stat_buffer *pbuf)
>>> +{
>>> +    struct rkisp1_device *rkisp1 = stats->rkisp1;
>>> +    u32 value;
>>> +    int i;
>>> +
>>> +    pbuf->meas_type |= RKISP1_CIF_ISP_STAT_HIST;
>>> +    for (i = 0; i < stats->config->hist_bin_n_max / 2; i++) {
>>> +        value = rkisp1_read(rkisp1, RKISP1_CIF_ISP_HIST_BIN_V12 + i * 4);
>>> +        pbuf->params.hist.hist_bins[2 * i] =
>>> +                    RKISP1_CIF_ISP_HIST_GET_BIN0_V12(value);
>>> +        pbuf->params.hist.hist_bins[2 * i + 1] =
>>> +                    RKISP1_CIF_ISP_HIST_GET_BIN1_V12(value);
>>> +    }
>>>   }
>>>     static void rkisp1_stats_get_bls_meas(struct rkisp1_stats *stats,
>>> @@ -286,17 +348,28 @@ static void rkisp1_stats_get_bls_meas(struct rkisp1_stats *stats,
>>>       }
>>>   }
>>>   -static struct rkisp1_stats_ops rkisp1_stats_ops = {
>>> -    .get_awb_meas = rkisp1_stats_get_awb_meas,
>>> -    .get_aec_meas = rkisp1_stats_get_aec_meas,
>>> -    .get_hst_meas = rkisp1_stats_get_hst_meas,
>>> +static struct rkisp1_stats_ops rkisp1_v10_stats_ops = {
>>> +    .get_awb_meas = rkisp1_stats_get_awb_meas_v10,
>>> +    .get_aec_meas = rkisp1_stats_get_aec_meas_v10,
>>> +    .get_hst_meas = rkisp1_stats_get_hst_meas_v10,
>>>   };
>>>   -static struct rkisp1_stats_config rkisp1_stats_config = {
>>> +static struct rkisp1_stats_config rkisp1_v10_stats_config = {
>>>       .ae_mean_max = 25,
>>>       .hist_bin_n_max = 16,
>>>   };
>>>   +static struct rkisp1_stats_ops rkisp1_v12_stats_ops = {
>>> +    .get_awb_meas = rkisp1_stats_get_awb_meas_v12,
>>> +    .get_aec_meas = rkisp1_stats_get_aec_meas_v12,
>>> +    .get_hst_meas = rkisp1_stats_get_hst_meas_v12,
>>> +};
>>> +
>>> +static struct rkisp1_stats_config rkisp1_v12_stats_config = {
>>> +    .ae_mean_max = 81,
>>> +    .hist_bin_n_max = 32,
>>> +};
>>> +
>>>   static void
>>>   rkisp1_stats_send_measurement(struct rkisp1_stats *stats, u32 isp_ris)
>>>   {
>>> @@ -365,8 +438,13 @@ static void rkisp1_init_stats(struct rkisp1_stats *stats)
>>>       stats->vdev_fmt.fmt.meta.buffersize =
>>>           sizeof(struct rkisp1_stat_buffer);
>>>   -    stats->ops = &rkisp1_stats_ops;
>>> -    stats->config = &rkisp1_stats_config;
>>> +    if (stats->rkisp1->isp_ver == RKISP1_V12) {
>>> +        stats->ops = &rkisp1_v12_stats_ops;
>>> +        stats->config = &rkisp1_v12_stats_config;
>>> +    } else {
>>> +        stats->ops = &rkisp1_v10_stats_ops;
>>> +        stats->config = &rkisp1_v10_stats_config;
>>> +    }
>>>   }
>>>     int rkisp1_stats_register(struct rkisp1_device *rkisp1)
>>>