[PATCH v2 0/3] media: rc: meson-ir: support MMIO regmaps to access registers

[PATCH v2 0/3] media: rc: meson-ir: support MMIO regmaps to access registers

[zelong dong]

From: Zelong Dong <zelong.dong@amlogic.com>

This patchset add MMIO regmaps to access register in Meson IR driver.
For defining clearly, sort/rename IR Controller register macros.

Changes since v1:
- move the cleanup/rename to a separate patch.
- use devm_platform_ioremap_resource() instead of platform_get_resource()
  and devm_ioremap_resource().

---
v1: https://lore.kernel.org/r/20230511034333.26800-1-zelong.dong@amlogic.com

Zelong Dong (3):
  media: rc: meson-ir: sort Meson IR Controller register macros
  media: rc: meson-ir: rename Meson IR Controller register macros
  media: rc: meson-ir: support MMIO regmaps to access registers

 drivers/media/rc/meson-ir.c | 125 ++++++++++++++++++------------------
 1 file changed, 64 insertions(+), 61 deletions(-)

-- 
2.35.1

[PATCH v2 1/3] media: rc: meson-ir: sort Meson IR Controller register macros

[zelong dong]

From: Zelong Dong <zelong.dong@amlogic.com>

There are more registers to come in the next Meson IR Controller.
For defining clearly, sort register macros and let address and bit
macros as a set.

Signed-off-by: Zelong Dong <zelong.dong@amlogic.com>
---
 drivers/media/rc/meson-ir.c | 35 +++++++++++++++++------------------
 1 file changed, 17 insertions(+), 18 deletions(-)

diff --git a/drivers/media/rc/meson-ir.c b/drivers/media/rc/meson-ir.c
index 4b769111f78e..a32d034b33aa 100644
--- a/drivers/media/rc/meson-ir.c
+++ b/drivers/media/rc/meson-ir.c
@@ -19,44 +19,43 @@
 
 #define DRIVER_NAME		"meson-ir"
 
-/* valid on all Meson platforms */
 #define IR_DEC_LDR_ACTIVE	0x00
+
 #define IR_DEC_LDR_IDLE		0x04
+
 #define IR_DEC_LDR_REPEAT	0x08
+
 #define IR_DEC_BIT_0		0x0c
-#define IR_DEC_REG0		0x10
-#define IR_DEC_FRAME		0x14
-#define IR_DEC_STATUS		0x18
-#define IR_DEC_REG1		0x1c
-/* only available on Meson 8b and newer */
-#define IR_DEC_REG2		0x20
 
+#define IR_DEC_REG0		0x10
 #define REG0_RATE_MASK		GENMASK(11, 0)
 
-#define DECODE_MODE_NEC		0x0
-#define DECODE_MODE_RAW		0x2
+#define IR_DEC_FRAME		0x14
+
+#define IR_DEC_STATUS		0x18
+#define STATUS_IR_DEC_IN	BIT(8)
 
-/* Meson 6b uses REG1 to configure the mode */
+#define IR_DEC_REG1		0x1c
+#define REG1_TIME_IV_MASK	GENMASK(28, 16)
+#define REG1_ENABLE		BIT(15)
 #define REG1_MODE_MASK		GENMASK(8, 7)
 #define REG1_MODE_SHIFT		7
+#define REG1_IRQSEL_MASK	GENMASK(3, 2)
+#define REG1_RESET		BIT(0)
 
-/* Meson 8b / GXBB use REG2 to configure the mode */
+/* The following regs are only available on Meson 8b and newer */
+#define IR_DEC_REG2		0x20
 #define REG2_MODE_MASK		GENMASK(3, 0)
 #define REG2_MODE_SHIFT		0
 
-#define REG1_TIME_IV_MASK	GENMASK(28, 16)
+#define DECODE_MODE_NEC		0x0
+#define DECODE_MODE_RAW		0x2
 
-#define REG1_IRQSEL_MASK	GENMASK(3, 2)
 #define REG1_IRQSEL_NEC_MODE	0
 #define REG1_IRQSEL_RISE_FALL	1
 #define REG1_IRQSEL_FALL	2
 #define REG1_IRQSEL_RISE	3
 
-#define REG1_RESET		BIT(0)
-#define REG1_ENABLE		BIT(15)
-
-#define STATUS_IR_DEC_IN	BIT(8)
-
 #define MESON_TRATE		10	/* us */
 
 struct meson_ir {
-- 
2.35.1

Re: [PATCH v2 1/3] media: rc: meson-ir: sort Meson IR Controller register macros

[Neil Armstrong]

On 17/05/2023 13:56, zelong dong wrote:
> From: Zelong Dong <zelong.dong@amlogic.com>
> 
> There are more registers to come in the next Meson IR Controller.
> For defining clearly, sort register macros and let address and bit
> macros as a set.
> 
> Signed-off-by: Zelong Dong <zelong.dong@amlogic.com>
> ---
>   drivers/media/rc/meson-ir.c | 35 +++++++++++++++++------------------
>   1 file changed, 17 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/media/rc/meson-ir.c b/drivers/media/rc/meson-ir.c
> index 4b769111f78e..a32d034b33aa 100644
> --- a/drivers/media/rc/meson-ir.c
> +++ b/drivers/media/rc/meson-ir.c
> @@ -19,44 +19,43 @@
>   
>   #define DRIVER_NAME		"meson-ir"
>   
> -/* valid on all Meson platforms */
>   #define IR_DEC_LDR_ACTIVE	0x00
> +
>   #define IR_DEC_LDR_IDLE		0x04
> +
>   #define IR_DEC_LDR_REPEAT	0x08
> +

You add those blank lines here, but remove them on next patch.

>   #define IR_DEC_BIT_0		0x0c
> -#define IR_DEC_REG0		0x10
> -#define IR_DEC_FRAME		0x14
> -#define IR_DEC_STATUS		0x18
> -#define IR_DEC_REG1		0x1c
> -/* only available on Meson 8b and newer */
> -#define IR_DEC_REG2		0x20
>   
> +#define IR_DEC_REG0		0x10
>   #define REG0_RATE_MASK		GENMASK(11, 0)
>   
> -#define DECODE_MODE_NEC		0x0
> -#define DECODE_MODE_RAW		0x2
> +#define IR_DEC_FRAME		0x14
> +
> +#define IR_DEC_STATUS		0x18
> +#define STATUS_IR_DEC_IN	BIT(8)
>   
> -/* Meson 6b uses REG1 to configure the mode */
> +#define IR_DEC_REG1		0x1c
> +#define REG1_TIME_IV_MASK	GENMASK(28, 16)
> +#define REG1_ENABLE		BIT(15)
>   #define REG1_MODE_MASK		GENMASK(8, 7)
>   #define REG1_MODE_SHIFT		7
> +#define REG1_IRQSEL_MASK	GENMASK(3, 2)
> +#define REG1_RESET		BIT(0)
>   
> -/* Meson 8b / GXBB use REG2 to configure the mode */
> +/* The following regs are only available on Meson 8b and newer */
> +#define IR_DEC_REG2		0x20
>   #define REG2_MODE_MASK		GENMASK(3, 0)
>   #define REG2_MODE_SHIFT		0
>   
> -#define REG1_TIME_IV_MASK	GENMASK(28, 16)
> +#define DECODE_MODE_NEC		0x0
> +#define DECODE_MODE_RAW		0x2
>   
> -#define REG1_IRQSEL_MASK	GENMASK(3, 2)
>   #define REG1_IRQSEL_NEC_MODE	0
>   #define REG1_IRQSEL_RISE_FALL	1
>   #define REG1_IRQSEL_FALL	2
>   #define REG1_IRQSEL_RISE	3
>   
> -#define REG1_RESET		BIT(0)
> -#define REG1_ENABLE		BIT(15)
> -
> -#define STATUS_IR_DEC_IN	BIT(8)
> -
>   #define MESON_TRATE		10	/* us */
>   
>   struct meson_ir {

Without the blank lines:

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

[PATCH v2 2/3] media: rc: meson-ir: rename Meson IR Controller register macros

[zelong dong]

From: Zelong Dong <zelong.dong@amlogic.com>

There are more registers to come in the next Meson IR Controller.
For defining clearly, rename register macros.

Signed-off-by: Zelong Dong <zelong.dong@amlogic.com>
---
 drivers/media/rc/meson-ir.c | 80 ++++++++++++++++++-------------------
 1 file changed, 40 insertions(+), 40 deletions(-)

diff --git a/drivers/media/rc/meson-ir.c b/drivers/media/rc/meson-ir.c
index a32d034b33aa..7ab6304f7184 100644
--- a/drivers/media/rc/meson-ir.c
+++ b/drivers/media/rc/meson-ir.c
@@ -20,43 +20,39 @@
 #define DRIVER_NAME		"meson-ir"
 
 #define IR_DEC_LDR_ACTIVE	0x00
-
 #define IR_DEC_LDR_IDLE		0x04
-
 #define IR_DEC_LDR_REPEAT	0x08
-
 #define IR_DEC_BIT_0		0x0c
 
 #define IR_DEC_REG0		0x10
-#define REG0_RATE_MASK		GENMASK(11, 0)
+#define IR_DEC_REG0_BASE_TIME	GENMASK(11, 0)
 
 #define IR_DEC_FRAME		0x14
 
 #define IR_DEC_STATUS		0x18
-#define STATUS_IR_DEC_IN	BIT(8)
+#define IR_DEC_STATUS_PULSE	BIT(8)
 
 #define IR_DEC_REG1		0x1c
-#define REG1_TIME_IV_MASK	GENMASK(28, 16)
-#define REG1_ENABLE		BIT(15)
-#define REG1_MODE_MASK		GENMASK(8, 7)
-#define REG1_MODE_SHIFT		7
-#define REG1_IRQSEL_MASK	GENMASK(3, 2)
-#define REG1_RESET		BIT(0)
+#define IR_DEC_REG1_TIME_IV	GENMASK(28, 16)
+#define IR_DEC_REG1_ENABLE	BIT(15)
+#define IR_DEC_REG1_MODE	GENMASK(8, 7)
+#define IR_DEC_REG1_IRQSEL	GENMASK(3, 2)
+#define IR_DEC_REG1_RESET	BIT(0)
 
 /* The following regs are only available on Meson 8b and newer */
 #define IR_DEC_REG2		0x20
-#define REG2_MODE_MASK		GENMASK(3, 0)
-#define REG2_MODE_SHIFT		0
+#define IR_DEC_REG2_MODE	GENMASK(3, 0)
 
-#define DECODE_MODE_NEC		0x0
-#define DECODE_MODE_RAW		0x2
+#define DEC_MODE_NEC		0x0
+#define DEC_MODE_RAW		0x2
 
-#define REG1_IRQSEL_NEC_MODE	0
-#define REG1_IRQSEL_RISE_FALL	1
-#define REG1_IRQSEL_FALL	2
-#define REG1_IRQSEL_RISE	3
+#define IRQSEL_NEC_MODE		0
+#define IRQSEL_RISE_FALL	1
+#define IRQSEL_FALL		2
+#define IRQSEL_RISE		3
 
-#define MESON_TRATE		10	/* us */
+#define MESON_RAW_TRATE		10	/* us */
+#define MESON_HW_TRATE		20	/* us */
 
 struct meson_ir {
 	void __iomem	*reg;
@@ -84,11 +80,11 @@ static irqreturn_t meson_ir_irq(int irqno, void *dev_id)
 	spin_lock(&ir->lock);
 
 	duration = readl_relaxed(ir->reg + IR_DEC_REG1);
-	duration = FIELD_GET(REG1_TIME_IV_MASK, duration);
-	rawir.duration = duration * MESON_TRATE;
+	duration = FIELD_GET(IR_DEC_REG1_TIME_IV, duration);
+	rawir.duration = duration * MESON_RAW_TRATE;
 
 	status = readl_relaxed(ir->reg + IR_DEC_STATUS);
-	rawir.pulse = !!(status & STATUS_IR_DEC_IN);
+	rawir.pulse = !!(status & IR_DEC_STATUS_PULSE);
 
 	ir_raw_event_store_with_timeout(ir->rc, &rawir);
 
@@ -130,7 +126,7 @@ static int meson_ir_probe(struct platform_device *pdev)
 	map_name = of_get_property(node, "linux,rc-map-name", NULL);
 	ir->rc->map_name = map_name ? map_name : RC_MAP_EMPTY;
 	ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
-	ir->rc->rx_resolution = MESON_TRATE;
+	ir->rc->rx_resolution = MESON_RAW_TRATE;
 	ir->rc->min_timeout = 1;
 	ir->rc->timeout = IR_DEFAULT_TIMEOUT;
 	ir->rc->max_timeout = 10 * IR_DEFAULT_TIMEOUT;
@@ -152,24 +148,27 @@ static int meson_ir_probe(struct platform_device *pdev)
 	}
 
 	/* Reset the decoder */
-	meson_ir_set_mask(ir, IR_DEC_REG1, REG1_RESET, REG1_RESET);
-	meson_ir_set_mask(ir, IR_DEC_REG1, REG1_RESET, 0);
+	meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_RESET,
+			  IR_DEC_REG1_RESET);
+	meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_RESET, 0);
 
 	/* Set general operation mode (= raw/software decoding) */
 	if (of_device_is_compatible(node, "amlogic,meson6-ir"))
-		meson_ir_set_mask(ir, IR_DEC_REG1, REG1_MODE_MASK,
-				  FIELD_PREP(REG1_MODE_MASK, DECODE_MODE_RAW));
+		meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_MODE,
+				  FIELD_PREP(IR_DEC_REG1_MODE, DEC_MODE_RAW));
 	else
-		meson_ir_set_mask(ir, IR_DEC_REG2, REG2_MODE_MASK,
-				  FIELD_PREP(REG2_MODE_MASK, DECODE_MODE_RAW));
+		meson_ir_set_mask(ir, IR_DEC_REG2, IR_DEC_REG2_MODE,
+				  FIELD_PREP(IR_DEC_REG2_MODE, DEC_MODE_RAW));
 
 	/* Set rate */
-	meson_ir_set_mask(ir, IR_DEC_REG0, REG0_RATE_MASK, MESON_TRATE - 1);
+	meson_ir_set_mask(ir, IR_DEC_REG0, IR_DEC_REG0_BASE_TIME,
+			  MESON_RAW_TRATE - 1);
 	/* IRQ on rising and falling edges */
-	meson_ir_set_mask(ir, IR_DEC_REG1, REG1_IRQSEL_MASK,
-			  FIELD_PREP(REG1_IRQSEL_MASK, REG1_IRQSEL_RISE_FALL));
+	meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_IRQSEL,
+			  FIELD_PREP(IR_DEC_REG1_IRQSEL, IRQSEL_RISE_FALL));
 	/* Enable the decoder */
-	meson_ir_set_mask(ir, IR_DEC_REG1, REG1_ENABLE, REG1_ENABLE);
+	meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_ENABLE,
+			  IR_DEC_REG1_ENABLE);
 
 	dev_info(dev, "receiver initialized\n");
 
@@ -183,7 +182,7 @@ static int meson_ir_remove(struct platform_device *pdev)
 
 	/* Disable the decoder */
 	spin_lock_irqsave(&ir->lock, flags);
-	meson_ir_set_mask(ir, IR_DEC_REG1, REG1_ENABLE, 0);
+	meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_ENABLE, 0);
 	spin_unlock_irqrestore(&ir->lock, flags);
 
 	return 0;
@@ -203,14 +202,15 @@ static void meson_ir_shutdown(struct platform_device *pdev)
 	 * bootloader a chance to power the system back on
 	 */
 	if (of_device_is_compatible(node, "amlogic,meson6-ir"))
-		meson_ir_set_mask(ir, IR_DEC_REG1, REG1_MODE_MASK,
-				  DECODE_MODE_NEC << REG1_MODE_SHIFT);
+		meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_MODE,
+				  FIELD_PREP(IR_DEC_REG1_MODE, DEC_MODE_NEC));
 	else
-		meson_ir_set_mask(ir, IR_DEC_REG2, REG2_MODE_MASK,
-				  DECODE_MODE_NEC << REG2_MODE_SHIFT);
+		meson_ir_set_mask(ir, IR_DEC_REG2, IR_DEC_REG2_MODE,
+				  FIELD_PREP(IR_DEC_REG2_MODE, DEC_MODE_NEC));
 
 	/* Set rate to default value */
-	meson_ir_set_mask(ir, IR_DEC_REG0, REG0_RATE_MASK, 0x13);
+	meson_ir_set_mask(ir, IR_DEC_REG0, IR_DEC_REG0_BASE_TIME,
+			  MESON_HW_TRATE - 1);
 
 	spin_unlock_irqrestore(&ir->lock, flags);
 }
-- 
2.35.1

Re: [PATCH v2 2/3] media: rc: meson-ir: rename Meson IR Controller register macros

[Neil Armstrong]

On 17/05/2023 13:56, zelong dong wrote:
> From: Zelong Dong <zelong.dong@amlogic.com>
> 
> There are more registers to come in the next Meson IR Controller.
> For defining clearly, rename register macros.
> 
> Signed-off-by: Zelong Dong <zelong.dong@amlogic.com>
> ---
>   drivers/media/rc/meson-ir.c | 80 ++++++++++++++++++-------------------
>   1 file changed, 40 insertions(+), 40 deletions(-)
> 
> diff --git a/drivers/media/rc/meson-ir.c b/drivers/media/rc/meson-ir.c
> index a32d034b33aa..7ab6304f7184 100644
> --- a/drivers/media/rc/meson-ir.c
> +++ b/drivers/media/rc/meson-ir.c
> @@ -20,43 +20,39 @@
>   #define DRIVER_NAME		"meson-ir"
>   
>   #define IR_DEC_LDR_ACTIVE	0x00
> -
>   #define IR_DEC_LDR_IDLE		0x04
> -
>   #define IR_DEC_LDR_REPEAT	0x08
> -
>   #define IR_DEC_BIT_0		0x0c
>   
>   #define IR_DEC_REG0		0x10
> -#define REG0_RATE_MASK		GENMASK(11, 0)
> +#define IR_DEC_REG0_BASE_TIME	GENMASK(11, 0)
>   
>   #define IR_DEC_FRAME		0x14
>   
>   #define IR_DEC_STATUS		0x18
> -#define STATUS_IR_DEC_IN	BIT(8)
> +#define IR_DEC_STATUS_PULSE	BIT(8)
>   
>   #define IR_DEC_REG1		0x1c
> -#define REG1_TIME_IV_MASK	GENMASK(28, 16)
> -#define REG1_ENABLE		BIT(15)
> -#define REG1_MODE_MASK		GENMASK(8, 7)
> -#define REG1_MODE_SHIFT		7
> -#define REG1_IRQSEL_MASK	GENMASK(3, 2)
> -#define REG1_RESET		BIT(0)
> +#define IR_DEC_REG1_TIME_IV	GENMASK(28, 16)
> +#define IR_DEC_REG1_ENABLE	BIT(15)
> +#define IR_DEC_REG1_MODE	GENMASK(8, 7)
> +#define IR_DEC_REG1_IRQSEL	GENMASK(3, 2)
> +#define IR_DEC_REG1_RESET	BIT(0)
>   
>   /* The following regs are only available on Meson 8b and newer */
>   #define IR_DEC_REG2		0x20
> -#define REG2_MODE_MASK		GENMASK(3, 0)
> -#define REG2_MODE_SHIFT		0
> +#define IR_DEC_REG2_MODE	GENMASK(3, 0)
>   
> -#define DECODE_MODE_NEC		0x0
> -#define DECODE_MODE_RAW		0x2
> +#define DEC_MODE_NEC		0x0
> +#define DEC_MODE_RAW		0x2
>   
> -#define REG1_IRQSEL_NEC_MODE	0
> -#define REG1_IRQSEL_RISE_FALL	1
> -#define REG1_IRQSEL_FALL	2
> -#define REG1_IRQSEL_RISE	3
> +#define IRQSEL_NEC_MODE		0
> +#define IRQSEL_RISE_FALL	1
> +#define IRQSEL_FALL		2
> +#define IRQSEL_RISE		3
>   
> -#define MESON_TRATE		10	/* us */
> +#define MESON_RAW_TRATE		10	/* us */
> +#define MESON_HW_TRATE		20	/* us */
>   
>   struct meson_ir {
>   	void __iomem	*reg;
> @@ -84,11 +80,11 @@ static irqreturn_t meson_ir_irq(int irqno, void *dev_id)
>   	spin_lock(&ir->lock);
>   
>   	duration = readl_relaxed(ir->reg + IR_DEC_REG1);
> -	duration = FIELD_GET(REG1_TIME_IV_MASK, duration);
> -	rawir.duration = duration * MESON_TRATE;
> +	duration = FIELD_GET(IR_DEC_REG1_TIME_IV, duration);
> +	rawir.duration = duration * MESON_RAW_TRATE;
>   
>   	status = readl_relaxed(ir->reg + IR_DEC_STATUS);
> -	rawir.pulse = !!(status & STATUS_IR_DEC_IN);
> +	rawir.pulse = !!(status & IR_DEC_STATUS_PULSE);
>   
>   	ir_raw_event_store_with_timeout(ir->rc, &rawir);
>   
> @@ -130,7 +126,7 @@ static int meson_ir_probe(struct platform_device *pdev)
>   	map_name = of_get_property(node, "linux,rc-map-name", NULL);
>   	ir->rc->map_name = map_name ? map_name : RC_MAP_EMPTY;
>   	ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
> -	ir->rc->rx_resolution = MESON_TRATE;
> +	ir->rc->rx_resolution = MESON_RAW_TRATE;
>   	ir->rc->min_timeout = 1;
>   	ir->rc->timeout = IR_DEFAULT_TIMEOUT;
>   	ir->rc->max_timeout = 10 * IR_DEFAULT_TIMEOUT;
> @@ -152,24 +148,27 @@ static int meson_ir_probe(struct platform_device *pdev)
>   	}
>   
>   	/* Reset the decoder */
> -	meson_ir_set_mask(ir, IR_DEC_REG1, REG1_RESET, REG1_RESET);
> -	meson_ir_set_mask(ir, IR_DEC_REG1, REG1_RESET, 0);
> +	meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_RESET,
> +			  IR_DEC_REG1_RESET);
> +	meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_RESET, 0);
>   
>   	/* Set general operation mode (= raw/software decoding) */
>   	if (of_device_is_compatible(node, "amlogic,meson6-ir"))
> -		meson_ir_set_mask(ir, IR_DEC_REG1, REG1_MODE_MASK,
> -				  FIELD_PREP(REG1_MODE_MASK, DECODE_MODE_RAW));
> +		meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_MODE,
> +				  FIELD_PREP(IR_DEC_REG1_MODE, DEC_MODE_RAW));
>   	else
> -		meson_ir_set_mask(ir, IR_DEC_REG2, REG2_MODE_MASK,
> -				  FIELD_PREP(REG2_MODE_MASK, DECODE_MODE_RAW));
> +		meson_ir_set_mask(ir, IR_DEC_REG2, IR_DEC_REG2_MODE,
> +				  FIELD_PREP(IR_DEC_REG2_MODE, DEC_MODE_RAW));
>   
>   	/* Set rate */
> -	meson_ir_set_mask(ir, IR_DEC_REG0, REG0_RATE_MASK, MESON_TRATE - 1);
> +	meson_ir_set_mask(ir, IR_DEC_REG0, IR_DEC_REG0_BASE_TIME,
> +			  MESON_RAW_TRATE - 1);
>   	/* IRQ on rising and falling edges */
> -	meson_ir_set_mask(ir, IR_DEC_REG1, REG1_IRQSEL_MASK,
> -			  FIELD_PREP(REG1_IRQSEL_MASK, REG1_IRQSEL_RISE_FALL));
> +	meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_IRQSEL,
> +			  FIELD_PREP(IR_DEC_REG1_IRQSEL, IRQSEL_RISE_FALL));
>   	/* Enable the decoder */
> -	meson_ir_set_mask(ir, IR_DEC_REG1, REG1_ENABLE, REG1_ENABLE);
> +	meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_ENABLE,
> +			  IR_DEC_REG1_ENABLE);
>   
>   	dev_info(dev, "receiver initialized\n");
>   
> @@ -183,7 +182,7 @@ static int meson_ir_remove(struct platform_device *pdev)
>   
>   	/* Disable the decoder */
>   	spin_lock_irqsave(&ir->lock, flags);
> -	meson_ir_set_mask(ir, IR_DEC_REG1, REG1_ENABLE, 0);
> +	meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_ENABLE, 0);
>   	spin_unlock_irqrestore(&ir->lock, flags);
>   
>   	return 0;
> @@ -203,14 +202,15 @@ static void meson_ir_shutdown(struct platform_device *pdev)
>   	 * bootloader a chance to power the system back on
>   	 */
>   	if (of_device_is_compatible(node, "amlogic,meson6-ir"))
> -		meson_ir_set_mask(ir, IR_DEC_REG1, REG1_MODE_MASK,
> -				  DECODE_MODE_NEC << REG1_MODE_SHIFT);
> +		meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_MODE,
> +				  FIELD_PREP(IR_DEC_REG1_MODE, DEC_MODE_NEC));
>   	else
> -		meson_ir_set_mask(ir, IR_DEC_REG2, REG2_MODE_MASK,
> -				  DECODE_MODE_NEC << REG2_MODE_SHIFT);
> +		meson_ir_set_mask(ir, IR_DEC_REG2, IR_DEC_REG2_MODE,
> +				  FIELD_PREP(IR_DEC_REG2_MODE, DEC_MODE_NEC));
>   
>   	/* Set rate to default value */
> -	meson_ir_set_mask(ir, IR_DEC_REG0, REG0_RATE_MASK, 0x13);
> +	meson_ir_set_mask(ir, IR_DEC_REG0, IR_DEC_REG0_BASE_TIME,
> +			  MESON_HW_TRATE - 1);
>   
>   	spin_unlock_irqrestore(&ir->lock, flags);
>   }

Without the unneded removed blank lines:

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

[PATCH v2 3/3] media: rc: meson-ir: support MMIO regmaps to access registers

[zelong dong]

From: Zelong Dong <zelong.dong@amlogic.com>

Supports MMIO regmaps to access controller registers in Meson IR driver.

Signed-off-by: Zelong Dong <zelong.dong@amlogic.com>
---
 drivers/media/rc/meson-ir.c | 72 +++++++++++++++++++------------------
 1 file changed, 38 insertions(+), 34 deletions(-)

diff --git a/drivers/media/rc/meson-ir.c b/drivers/media/rc/meson-ir.c
index 7ab6304f7184..ac4ebaa3904c 100644
--- a/drivers/media/rc/meson-ir.c
+++ b/drivers/media/rc/meson-ir.c
@@ -14,6 +14,7 @@
 #include <linux/platform_device.h>
 #include <linux/spinlock.h>
 #include <linux/bitfield.h>
+#include <linux/regmap.h>
 
 #include <media/rc-core.h>
 
@@ -55,21 +56,16 @@
 #define MESON_HW_TRATE		20	/* us */
 
 struct meson_ir {
-	void __iomem	*reg;
+	struct regmap	*reg;
 	struct rc_dev	*rc;
 	spinlock_t	lock;
 };
 
-static void meson_ir_set_mask(struct meson_ir *ir, unsigned int reg,
-			      u32 mask, u32 value)
-{
-	u32 data;
-
-	data = readl(ir->reg + reg);
-	data &= ~mask;
-	data |= (value & mask);
-	writel(data, ir->reg + reg);
-}
+static struct regmap_config meson_ir_regmap_config = {
+	.reg_bits = 32,
+	.val_bits = 32,
+	.reg_stride = 4,
+};
 
 static irqreturn_t meson_ir_irq(int irqno, void *dev_id)
 {
@@ -79,11 +75,11 @@ static irqreturn_t meson_ir_irq(int irqno, void *dev_id)
 
 	spin_lock(&ir->lock);
 
-	duration = readl_relaxed(ir->reg + IR_DEC_REG1);
+	regmap_read(ir->reg, IR_DEC_REG1, &duration);
 	duration = FIELD_GET(IR_DEC_REG1_TIME_IV, duration);
 	rawir.duration = duration * MESON_RAW_TRATE;
 
-	status = readl_relaxed(ir->reg + IR_DEC_STATUS);
+	regmap_read(ir->reg, IR_DEC_STATUS, &status);
 	rawir.pulse = !!(status & IR_DEC_STATUS_PULSE);
 
 	ir_raw_event_store_with_timeout(ir->rc, &rawir);
@@ -97,6 +93,7 @@ static int meson_ir_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct device_node *node = dev->of_node;
+	void __iomem *res_start;
 	const char *map_name;
 	struct meson_ir *ir;
 	int irq, ret;
@@ -105,7 +102,12 @@ static int meson_ir_probe(struct platform_device *pdev)
 	if (!ir)
 		return -ENOMEM;
 
-	ir->reg = devm_platform_ioremap_resource(pdev, 0);
+	res_start = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(res_start))
+		return PTR_ERR(res_start);
+
+	ir->reg = devm_regmap_init_mmio(&pdev->dev, res_start,
+					&meson_ir_regmap_config);
 	if (IS_ERR(ir->reg))
 		return PTR_ERR(ir->reg);
 
@@ -148,27 +150,28 @@ static int meson_ir_probe(struct platform_device *pdev)
 	}
 
 	/* Reset the decoder */
-	meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_RESET,
-			  IR_DEC_REG1_RESET);
-	meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_RESET, 0);
+	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET,
+			   IR_DEC_REG1_RESET);
+	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET, 0);
 
 	/* Set general operation mode (= raw/software decoding) */
 	if (of_device_is_compatible(node, "amlogic,meson6-ir"))
-		meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_MODE,
-				  FIELD_PREP(IR_DEC_REG1_MODE, DEC_MODE_RAW));
+		regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_MODE,
+				   FIELD_PREP(IR_DEC_REG1_MODE, DEC_MODE_RAW));
 	else
-		meson_ir_set_mask(ir, IR_DEC_REG2, IR_DEC_REG2_MODE,
-				  FIELD_PREP(IR_DEC_REG2_MODE, DEC_MODE_RAW));
+		regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_MODE,
+				   FIELD_PREP(IR_DEC_REG2_MODE, DEC_MODE_RAW));
 
 	/* Set rate */
-	meson_ir_set_mask(ir, IR_DEC_REG0, IR_DEC_REG0_BASE_TIME,
-			  MESON_RAW_TRATE - 1);
+	regmap_update_bits(ir->reg, IR_DEC_REG0, IR_DEC_REG0_BASE_TIME,
+			   FIELD_PREP(IR_DEC_REG0_BASE_TIME,
+				      MESON_RAW_TRATE - 1));
 	/* IRQ on rising and falling edges */
-	meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_IRQSEL,
-			  FIELD_PREP(IR_DEC_REG1_IRQSEL, IRQSEL_RISE_FALL));
+	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_IRQSEL,
+			   FIELD_PREP(IR_DEC_REG1_IRQSEL, IRQSEL_RISE_FALL));
 	/* Enable the decoder */
-	meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_ENABLE,
-			  IR_DEC_REG1_ENABLE);
+	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE,
+			   IR_DEC_REG1_ENABLE);
 
 	dev_info(dev, "receiver initialized\n");
 
@@ -182,7 +185,7 @@ static int meson_ir_remove(struct platform_device *pdev)
 
 	/* Disable the decoder */
 	spin_lock_irqsave(&ir->lock, flags);
-	meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_ENABLE, 0);
+	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE, 0);
 	spin_unlock_irqrestore(&ir->lock, flags);
 
 	return 0;
@@ -202,15 +205,16 @@ static void meson_ir_shutdown(struct platform_device *pdev)
 	 * bootloader a chance to power the system back on
 	 */
 	if (of_device_is_compatible(node, "amlogic,meson6-ir"))
-		meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_MODE,
-				  FIELD_PREP(IR_DEC_REG1_MODE, DEC_MODE_NEC));
+		regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_MODE,
+				   FIELD_PREP(IR_DEC_REG1_MODE, DEC_MODE_NEC));
 	else
-		meson_ir_set_mask(ir, IR_DEC_REG2, IR_DEC_REG2_MODE,
-				  FIELD_PREP(IR_DEC_REG2_MODE, DEC_MODE_NEC));
+		regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_MODE,
+				   FIELD_PREP(IR_DEC_REG2_MODE, DEC_MODE_NEC));
 
 	/* Set rate to default value */
-	meson_ir_set_mask(ir, IR_DEC_REG0, IR_DEC_REG0_BASE_TIME,
-			  MESON_HW_TRATE - 1);
+	regmap_update_bits(ir->reg, IR_DEC_REG0, IR_DEC_REG0_BASE_TIME,
+			   FIELD_PREP(IR_DEC_REG0_BASE_TIME,
+				      MESON_HW_TRATE - 1));
 
 	spin_unlock_irqrestore(&ir->lock, flags);
 }
-- 
2.35.1

Re: [PATCH v2 3/3] media: rc: meson-ir: support MMIO regmaps to access registers

[Martin Blumenstingl]

Hello,

On Wed, May 17, 2023 at 1:56 PM zelong dong <zelong.dong@amlogic.com> wrote:
>
> From: Zelong Dong <zelong.dong@amlogic.com>
>
> Supports MMIO regmaps to access controller registers in Meson IR driver.
>
> Signed-off-by: Zelong Dong <zelong.dong@amlogic.com>
> ---
>  drivers/media/rc/meson-ir.c | 72 +++++++++++++++++++------------------
Kconfig also has to be updated with:
  select REGMAP_MMIO

Otherwise you can end up with a compile error: undefined reference to
`__devm_regmap_init_mmio_clk`
See a recent patch on this: [0]


Best regards,
Martin


[0] https://lore.kernel.org/lkml/20230228043423.19335-1-xry111@xry111.site/

Re: [PATCH v2 0/3] media: rc: meson-ir: support MMIO regmaps to access registers

[Neil Armstrong]

Hi,

On 17/05/2023 13:56, zelong dong wrote:
> From: Zelong Dong <zelong.dong@amlogic.com>
> 
> This patchset add MMIO regmaps to access register in Meson IR driver.
> For defining clearly, sort/rename IR Controller register macros.
> 
> Changes since v1:
> - move the cleanup/rename to a separate patch.
> - use devm_platform_ioremap_resource() instead of platform_get_resource()
>    and devm_ioremap_resource().
> 
> ---
> v1: https://lore.kernel.org/r/20230511034333.26800-1-zelong.dong@amlogic.com
> 
> Zelong Dong (3):
>    media: rc: meson-ir: sort Meson IR Controller register macros
>    media: rc: meson-ir: rename Meson IR Controller register macros
>    media: rc: meson-ir: support MMIO regmaps to access registers
> 
>   drivers/media/rc/meson-ir.c | 125 ++++++++++++++++++------------------
>   1 file changed, 64 insertions(+), 61 deletions(-)
> 

Patch 2 & 3 doesn't apply cleanly on v6.4-rc1, please rebase on the latest -rc1 kernel.

Neil